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1/*
2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Authors: Rusty Russell <rusty@rustcorp.com.au>
4 * Christoffer Dall <c.dall@virtualopensystems.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, version 2, as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 */
19#include <linux/mm.h>
20#include <linux/kvm_host.h>
21#include <linux/uaccess.h>
22#include <asm/kvm_arm.h>
23#include <asm/kvm_host.h>
24#include <asm/kvm_emulate.h>
25#include <asm/kvm_coproc.h>
26#include <asm/kvm_mmu.h>
27#include <asm/cacheflush.h>
28#include <asm/cputype.h>
29#include <trace/events/kvm.h>
30#include <asm/vfp.h>
31#include "../vfp/vfpinstr.h"
32
33#include "trace.h"
34#include "coproc.h"
35
36
37/******************************************************************************
38 * Co-processor emulation
39 *****************************************************************************/
40
41/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
42static u32 cache_levels;
43
44/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
45#define CSSELR_MAX 12
46
47int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run)
48{
49 kvm_inject_undefined(vcpu);
50 return 1;
51}
52
53int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
54{
55 /*
56 * We can get here, if the host has been built without VFPv3 support,
57 * but the guest attempted a floating point operation.
58 */
59 kvm_inject_undefined(vcpu);
60 return 1;
61}
62
63int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
64{
65 kvm_inject_undefined(vcpu);
66 return 1;
67}
68
69int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
70{
71 kvm_inject_undefined(vcpu);
72 return 1;
73}
74
75static void reset_mpidr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
76{
77 /*
78 * Compute guest MPIDR. We build a virtual cluster out of the
79 * vcpu_id, but we read the 'U' bit from the underlying
80 * hardware directly.
81 */
82 vcpu->arch.cp15[c0_MPIDR] = ((read_cpuid_mpidr() & MPIDR_SMP_BITMASK) |
83 ((vcpu->vcpu_id >> 2) << MPIDR_LEVEL_BITS) |
84 (vcpu->vcpu_id & 3));
85}
86
87/* TRM entries A7:4.3.31 A15:4.3.28 - RO WI */
88static bool access_actlr(struct kvm_vcpu *vcpu,
89 const struct coproc_params *p,
90 const struct coproc_reg *r)
91{
92 if (p->is_write)
93 return ignore_write(vcpu, p);
94
95 *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[c1_ACTLR];
96 return true;
97}
98
99/* TRM entries A7:4.3.56, A15:4.3.60 - R/O. */
100static bool access_cbar(struct kvm_vcpu *vcpu,
101 const struct coproc_params *p,
102 const struct coproc_reg *r)
103{
104 if (p->is_write)
105 return write_to_read_only(vcpu, p);
106 return read_zero(vcpu, p);
107}
108
109/* TRM entries A7:4.3.49, A15:4.3.48 - R/O WI */
110static bool access_l2ctlr(struct kvm_vcpu *vcpu,
111 const struct coproc_params *p,
112 const struct coproc_reg *r)
113{
114 if (p->is_write)
115 return ignore_write(vcpu, p);
116
117 *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[c9_L2CTLR];
118 return true;
119}
120
121static void reset_l2ctlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
122{
123 u32 l2ctlr, ncores;
124
125 asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
126 l2ctlr &= ~(3 << 24);
127 ncores = atomic_read(&vcpu->kvm->online_vcpus) - 1;
128 /* How many cores in the current cluster and the next ones */
129 ncores -= (vcpu->vcpu_id & ~3);
130 /* Cap it to the maximum number of cores in a single cluster */
131 ncores = min(ncores, 3U);
132 l2ctlr |= (ncores & 3) << 24;
133
134 vcpu->arch.cp15[c9_L2CTLR] = l2ctlr;
135}
136
137static void reset_actlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
138{
139 u32 actlr;
140
141 /* ACTLR contains SMP bit: make sure you create all cpus first! */
142 asm volatile("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));
143 /* Make the SMP bit consistent with the guest configuration */
144 if (atomic_read(&vcpu->kvm->online_vcpus) > 1)
145 actlr |= 1U << 6;
146 else
147 actlr &= ~(1U << 6);
148
149 vcpu->arch.cp15[c1_ACTLR] = actlr;
150}
151
152/*
153 * TRM entries: A7:4.3.50, A15:4.3.49
154 * R/O WI (even if NSACR.NS_L2ERR, a write of 1 is ignored).
155 */
156static bool access_l2ectlr(struct kvm_vcpu *vcpu,
157 const struct coproc_params *p,
158 const struct coproc_reg *r)
159{
160 if (p->is_write)
161 return ignore_write(vcpu, p);
162
163 *vcpu_reg(vcpu, p->Rt1) = 0;
164 return true;
165}
166
167/* See note at ARM ARM B1.14.4 */
168static bool access_dcsw(struct kvm_vcpu *vcpu,
169 const struct coproc_params *p,
170 const struct coproc_reg *r)
171{
172 unsigned long val;
173 int cpu;
174
175 if (!p->is_write)
176 return read_from_write_only(vcpu, p);
177
178 cpu = get_cpu();
179
180 cpumask_setall(&vcpu->arch.require_dcache_flush);
181 cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
182
183 /* If we were already preempted, take the long way around */
184 if (cpu != vcpu->arch.last_pcpu) {
185 flush_cache_all();
186 goto done;
187 }
188
189 val = *vcpu_reg(vcpu, p->Rt1);
190
191 switch (p->CRm) {
192 case 6: /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
193 case 14: /* DCCISW */
194 asm volatile("mcr p15, 0, %0, c7, c14, 2" : : "r" (val));
195 break;
196
197 case 10: /* DCCSW */
198 asm volatile("mcr p15, 0, %0, c7, c10, 2" : : "r" (val));
199 break;
200 }
201
202done:
203 put_cpu();
204
205 return true;
206}
207
208/*
209 * Generic accessor for VM registers. Only called as long as HCR_TVM
210 * is set.
211 */
212static bool access_vm_reg(struct kvm_vcpu *vcpu,
213 const struct coproc_params *p,
214 const struct coproc_reg *r)
215{
216 BUG_ON(!p->is_write);
217
218 vcpu->arch.cp15[r->reg] = *vcpu_reg(vcpu, p->Rt1);
219 if (p->is_64bit)
220 vcpu->arch.cp15[r->reg + 1] = *vcpu_reg(vcpu, p->Rt2);
221
222 return true;
223}
224
225/*
226 * SCTLR accessor. Only called as long as HCR_TVM is set. If the
227 * guest enables the MMU, we stop trapping the VM sys_regs and leave
228 * it in complete control of the caches.
229 *
230 * Used by the cpu-specific code.
231 */
232bool access_sctlr(struct kvm_vcpu *vcpu,
233 const struct coproc_params *p,
234 const struct coproc_reg *r)
235{
236 access_vm_reg(vcpu, p, r);
237
238 if (vcpu_has_cache_enabled(vcpu)) { /* MMU+Caches enabled? */
239 vcpu->arch.hcr &= ~HCR_TVM;
240 stage2_flush_vm(vcpu->kvm);
241 }
242
243 return true;
244}
245
246/*
247 * We could trap ID_DFR0 and tell the guest we don't support performance
248 * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was
249 * NAKed, so it will read the PMCR anyway.
250 *
251 * Therefore we tell the guest we have 0 counters. Unfortunately, we
252 * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
253 * all PM registers, which doesn't crash the guest kernel at least.
254 */
255static bool pm_fake(struct kvm_vcpu *vcpu,
256 const struct coproc_params *p,
257 const struct coproc_reg *r)
258{
259 if (p->is_write)
260 return ignore_write(vcpu, p);
261 else
262 return read_zero(vcpu, p);
263}
264
265#define access_pmcr pm_fake
266#define access_pmcntenset pm_fake
267#define access_pmcntenclr pm_fake
268#define access_pmovsr pm_fake
269#define access_pmselr pm_fake
270#define access_pmceid0 pm_fake
271#define access_pmceid1 pm_fake
272#define access_pmccntr pm_fake
273#define access_pmxevtyper pm_fake
274#define access_pmxevcntr pm_fake
275#define access_pmuserenr pm_fake
276#define access_pmintenset pm_fake
277#define access_pmintenclr pm_fake
278
279/* Architected CP15 registers.
280 * CRn denotes the primary register number, but is copied to the CRm in the
281 * user space API for 64-bit register access in line with the terminology used
282 * in the ARM ARM.
283 * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
284 * registers preceding 32-bit ones.
285 */
286static const struct coproc_reg cp15_regs[] = {
287 /* MPIDR: we use VMPIDR for guest access. */
288 { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32,
289 NULL, reset_mpidr, c0_MPIDR },
290
291 /* CSSELR: swapped by interrupt.S. */
292 { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
293 NULL, reset_unknown, c0_CSSELR },
294
295 /* ACTLR: trapped by HCR.TAC bit. */
296 { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32,
297 access_actlr, reset_actlr, c1_ACTLR },
298
299 /* CPACR: swapped by interrupt.S. */
300 { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32,
301 NULL, reset_val, c1_CPACR, 0x00000000 },
302
303 /* TTBR0/TTBR1/TTBCR: swapped by interrupt.S. */
304 { CRm64( 2), Op1( 0), is64, access_vm_reg, reset_unknown64, c2_TTBR0 },
305 { CRn(2), CRm( 0), Op1( 0), Op2( 0), is32,
306 access_vm_reg, reset_unknown, c2_TTBR0 },
307 { CRn(2), CRm( 0), Op1( 0), Op2( 1), is32,
308 access_vm_reg, reset_unknown, c2_TTBR1 },
309 { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
310 access_vm_reg, reset_val, c2_TTBCR, 0x00000000 },
311 { CRm64( 2), Op1( 1), is64, access_vm_reg, reset_unknown64, c2_TTBR1 },
312
313
314 /* DACR: swapped by interrupt.S. */
315 { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
316 access_vm_reg, reset_unknown, c3_DACR },
317
318 /* DFSR/IFSR/ADFSR/AIFSR: swapped by interrupt.S. */
319 { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
320 access_vm_reg, reset_unknown, c5_DFSR },
321 { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
322 access_vm_reg, reset_unknown, c5_IFSR },
323 { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32,
324 access_vm_reg, reset_unknown, c5_ADFSR },
325 { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32,
326 access_vm_reg, reset_unknown, c5_AIFSR },
327
328 /* DFAR/IFAR: swapped by interrupt.S. */
329 { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32,
330 access_vm_reg, reset_unknown, c6_DFAR },
331 { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32,
332 access_vm_reg, reset_unknown, c6_IFAR },
333
334 /* PAR swapped by interrupt.S */
335 { CRm64( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
336
337 /*
338 * DC{C,I,CI}SW operations:
339 */
340 { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, access_dcsw},
341 { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw},
342 { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw},
343 /*
344 * L2CTLR access (guest wants to know #CPUs).
345 */
346 { CRn( 9), CRm( 0), Op1( 1), Op2( 2), is32,
347 access_l2ctlr, reset_l2ctlr, c9_L2CTLR },
348 { CRn( 9), CRm( 0), Op1( 1), Op2( 3), is32, access_l2ectlr},
349
350 /*
351 * Dummy performance monitor implementation.
352 */
353 { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr},
354 { CRn( 9), CRm(12), Op1( 0), Op2( 1), is32, access_pmcntenset},
355 { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, access_pmcntenclr},
356 { CRn( 9), CRm(12), Op1( 0), Op2( 3), is32, access_pmovsr},
357 { CRn( 9), CRm(12), Op1( 0), Op2( 5), is32, access_pmselr},
358 { CRn( 9), CRm(12), Op1( 0), Op2( 6), is32, access_pmceid0},
359 { CRn( 9), CRm(12), Op1( 0), Op2( 7), is32, access_pmceid1},
360 { CRn( 9), CRm(13), Op1( 0), Op2( 0), is32, access_pmccntr},
361 { CRn( 9), CRm(13), Op1( 0), Op2( 1), is32, access_pmxevtyper},
362 { CRn( 9), CRm(13), Op1( 0), Op2( 2), is32, access_pmxevcntr},
363 { CRn( 9), CRm(14), Op1( 0), Op2( 0), is32, access_pmuserenr},
364 { CRn( 9), CRm(14), Op1( 0), Op2( 1), is32, access_pmintenset},
365 { CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, access_pmintenclr},
366
367 /* PRRR/NMRR (aka MAIR0/MAIR1): swapped by interrupt.S. */
368 { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32,
369 access_vm_reg, reset_unknown, c10_PRRR},
370 { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32,
371 access_vm_reg, reset_unknown, c10_NMRR},
372
373 /* AMAIR0/AMAIR1: swapped by interrupt.S. */
374 { CRn(10), CRm( 3), Op1( 0), Op2( 0), is32,
375 access_vm_reg, reset_unknown, c10_AMAIR0},
376 { CRn(10), CRm( 3), Op1( 0), Op2( 1), is32,
377 access_vm_reg, reset_unknown, c10_AMAIR1},
378
379 /* VBAR: swapped by interrupt.S. */
380 { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32,
381 NULL, reset_val, c12_VBAR, 0x00000000 },
382
383 /* CONTEXTIDR/TPIDRURW/TPIDRURO/TPIDRPRW: swapped by interrupt.S. */
384 { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32,
385 access_vm_reg, reset_val, c13_CID, 0x00000000 },
386 { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32,
387 NULL, reset_unknown, c13_TID_URW },
388 { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32,
389 NULL, reset_unknown, c13_TID_URO },
390 { CRn(13), CRm( 0), Op1( 0), Op2( 4), is32,
391 NULL, reset_unknown, c13_TID_PRIV },
392
393 /* CNTKCTL: swapped by interrupt.S. */
394 { CRn(14), CRm( 1), Op1( 0), Op2( 0), is32,
395 NULL, reset_val, c14_CNTKCTL, 0x00000000 },
396
397 /* The Configuration Base Address Register. */
398 { CRn(15), CRm( 0), Op1( 4), Op2( 0), is32, access_cbar},
399};
400
401/* Target specific emulation tables */
402static struct kvm_coproc_target_table *target_tables[KVM_ARM_NUM_TARGETS];
403
404void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table)
405{
406 unsigned int i;
407
408 for (i = 1; i < table->num; i++)
409 BUG_ON(cmp_reg(&table->table[i-1],
410 &table->table[i]) >= 0);
411
412 target_tables[table->target] = table;
413}
414
415/* Get specific register table for this target. */
416static const struct coproc_reg *get_target_table(unsigned target, size_t *num)
417{
418 struct kvm_coproc_target_table *table;
419
420 table = target_tables[target];
421 *num = table->num;
422 return table->table;
423}
424
425static const struct coproc_reg *find_reg(const struct coproc_params *params,
426 const struct coproc_reg table[],
427 unsigned int num)
428{
429 unsigned int i;
430
431 for (i = 0; i < num; i++) {
432 const struct coproc_reg *r = &table[i];
433
434 if (params->is_64bit != r->is_64)
435 continue;
436 if (params->CRn != r->CRn)
437 continue;
438 if (params->CRm != r->CRm)
439 continue;
440 if (params->Op1 != r->Op1)
441 continue;
442 if (params->Op2 != r->Op2)
443 continue;
444
445 return r;
446 }
447 return NULL;
448}
449
450static int emulate_cp15(struct kvm_vcpu *vcpu,
451 const struct coproc_params *params)
452{
453 size_t num;
454 const struct coproc_reg *table, *r;
455
456 trace_kvm_emulate_cp15_imp(params->Op1, params->Rt1, params->CRn,
457 params->CRm, params->Op2, params->is_write);
458
459 table = get_target_table(vcpu->arch.target, &num);
460
461 /* Search target-specific then generic table. */
462 r = find_reg(params, table, num);
463 if (!r)
464 r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs));
465
466 if (likely(r)) {
467 /* If we don't have an accessor, we should never get here! */
468 BUG_ON(!r->access);
469
470 if (likely(r->access(vcpu, params, r))) {
471 /* Skip instruction, since it was emulated */
472 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
473 return 1;
474 }
475 /* If access function fails, it should complain. */
476 } else {
477 kvm_err("Unsupported guest CP15 access at: %08lx\n",
478 *vcpu_pc(vcpu));
479 print_cp_instr(params);
480 }
481 kvm_inject_undefined(vcpu);
482 return 1;
483}
484
485/**
486 * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
487 * @vcpu: The VCPU pointer
488 * @run: The kvm_run struct
489 */
490int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
491{
492 struct coproc_params params;
493
494 params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
495 params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
496 params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
497 params.is_64bit = true;
498
499 params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 16) & 0xf;
500 params.Op2 = 0;
501 params.Rt2 = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
502 params.CRm = 0;
503
504 return emulate_cp15(vcpu, ¶ms);
505}
506
507static void reset_coproc_regs(struct kvm_vcpu *vcpu,
508 const struct coproc_reg *table, size_t num)
509{
510 unsigned long i;
511
512 for (i = 0; i < num; i++)
513 if (table[i].reset)
514 table[i].reset(vcpu, &table[i]);
515}
516
517/**
518 * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
519 * @vcpu: The VCPU pointer
520 * @run: The kvm_run struct
521 */
522int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
523{
524 struct coproc_params params;
525
526 params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
527 params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
528 params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
529 params.is_64bit = false;
530
531 params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
532 params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 14) & 0x7;
533 params.Op2 = (kvm_vcpu_get_hsr(vcpu) >> 17) & 0x7;
534 params.Rt2 = 0;
535
536 return emulate_cp15(vcpu, ¶ms);
537}
538
539/******************************************************************************
540 * Userspace API
541 *****************************************************************************/
542
543static bool index_to_params(u64 id, struct coproc_params *params)
544{
545 switch (id & KVM_REG_SIZE_MASK) {
546 case KVM_REG_SIZE_U32:
547 /* Any unused index bits means it's not valid. */
548 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
549 | KVM_REG_ARM_COPROC_MASK
550 | KVM_REG_ARM_32_CRN_MASK
551 | KVM_REG_ARM_CRM_MASK
552 | KVM_REG_ARM_OPC1_MASK
553 | KVM_REG_ARM_32_OPC2_MASK))
554 return false;
555
556 params->is_64bit = false;
557 params->CRn = ((id & KVM_REG_ARM_32_CRN_MASK)
558 >> KVM_REG_ARM_32_CRN_SHIFT);
559 params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
560 >> KVM_REG_ARM_CRM_SHIFT);
561 params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
562 >> KVM_REG_ARM_OPC1_SHIFT);
563 params->Op2 = ((id & KVM_REG_ARM_32_OPC2_MASK)
564 >> KVM_REG_ARM_32_OPC2_SHIFT);
565 return true;
566 case KVM_REG_SIZE_U64:
567 /* Any unused index bits means it's not valid. */
568 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
569 | KVM_REG_ARM_COPROC_MASK
570 | KVM_REG_ARM_CRM_MASK
571 | KVM_REG_ARM_OPC1_MASK))
572 return false;
573 params->is_64bit = true;
574 /* CRm to CRn: see cp15_to_index for details */
575 params->CRn = ((id & KVM_REG_ARM_CRM_MASK)
576 >> KVM_REG_ARM_CRM_SHIFT);
577 params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
578 >> KVM_REG_ARM_OPC1_SHIFT);
579 params->Op2 = 0;
580 params->CRm = 0;
581 return true;
582 default:
583 return false;
584 }
585}
586
587/* Decode an index value, and find the cp15 coproc_reg entry. */
588static const struct coproc_reg *index_to_coproc_reg(struct kvm_vcpu *vcpu,
589 u64 id)
590{
591 size_t num;
592 const struct coproc_reg *table, *r;
593 struct coproc_params params;
594
595 /* We only do cp15 for now. */
596 if ((id & KVM_REG_ARM_COPROC_MASK) >> KVM_REG_ARM_COPROC_SHIFT != 15)
597 return NULL;
598
599 if (!index_to_params(id, ¶ms))
600 return NULL;
601
602 table = get_target_table(vcpu->arch.target, &num);
603 r = find_reg(¶ms, table, num);
604 if (!r)
605 r = find_reg(¶ms, cp15_regs, ARRAY_SIZE(cp15_regs));
606
607 /* Not saved in the cp15 array? */
608 if (r && !r->reg)
609 r = NULL;
610
611 return r;
612}
613
614/*
615 * These are the invariant cp15 registers: we let the guest see the host
616 * versions of these, so they're part of the guest state.
617 *
618 * A future CPU may provide a mechanism to present different values to
619 * the guest, or a future kvm may trap them.
620 */
621/* Unfortunately, there's no register-argument for mrc, so generate. */
622#define FUNCTION_FOR32(crn, crm, op1, op2, name) \
623 static void get_##name(struct kvm_vcpu *v, \
624 const struct coproc_reg *r) \
625 { \
626 u32 val; \
627 \
628 asm volatile("mrc p15, " __stringify(op1) \
629 ", %0, c" __stringify(crn) \
630 ", c" __stringify(crm) \
631 ", " __stringify(op2) "\n" : "=r" (val)); \
632 ((struct coproc_reg *)r)->val = val; \
633 }
634
635FUNCTION_FOR32(0, 0, 0, 0, MIDR)
636FUNCTION_FOR32(0, 0, 0, 1, CTR)
637FUNCTION_FOR32(0, 0, 0, 2, TCMTR)
638FUNCTION_FOR32(0, 0, 0, 3, TLBTR)
639FUNCTION_FOR32(0, 0, 0, 6, REVIDR)
640FUNCTION_FOR32(0, 1, 0, 0, ID_PFR0)
641FUNCTION_FOR32(0, 1, 0, 1, ID_PFR1)
642FUNCTION_FOR32(0, 1, 0, 2, ID_DFR0)
643FUNCTION_FOR32(0, 1, 0, 3, ID_AFR0)
644FUNCTION_FOR32(0, 1, 0, 4, ID_MMFR0)
645FUNCTION_FOR32(0, 1, 0, 5, ID_MMFR1)
646FUNCTION_FOR32(0, 1, 0, 6, ID_MMFR2)
647FUNCTION_FOR32(0, 1, 0, 7, ID_MMFR3)
648FUNCTION_FOR32(0, 2, 0, 0, ID_ISAR0)
649FUNCTION_FOR32(0, 2, 0, 1, ID_ISAR1)
650FUNCTION_FOR32(0, 2, 0, 2, ID_ISAR2)
651FUNCTION_FOR32(0, 2, 0, 3, ID_ISAR3)
652FUNCTION_FOR32(0, 2, 0, 4, ID_ISAR4)
653FUNCTION_FOR32(0, 2, 0, 5, ID_ISAR5)
654FUNCTION_FOR32(0, 0, 1, 1, CLIDR)
655FUNCTION_FOR32(0, 0, 1, 7, AIDR)
656
657/* ->val is filled in by kvm_invariant_coproc_table_init() */
658static struct coproc_reg invariant_cp15[] = {
659 { CRn( 0), CRm( 0), Op1( 0), Op2( 0), is32, NULL, get_MIDR },
660 { CRn( 0), CRm( 0), Op1( 0), Op2( 1), is32, NULL, get_CTR },
661 { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, NULL, get_TCMTR },
662 { CRn( 0), CRm( 0), Op1( 0), Op2( 3), is32, NULL, get_TLBTR },
663 { CRn( 0), CRm( 0), Op1( 0), Op2( 6), is32, NULL, get_REVIDR },
664
665 { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, NULL, get_ID_PFR0 },
666 { CRn( 0), CRm( 1), Op1( 0), Op2( 1), is32, NULL, get_ID_PFR1 },
667 { CRn( 0), CRm( 1), Op1( 0), Op2( 2), is32, NULL, get_ID_DFR0 },
668 { CRn( 0), CRm( 1), Op1( 0), Op2( 3), is32, NULL, get_ID_AFR0 },
669 { CRn( 0), CRm( 1), Op1( 0), Op2( 4), is32, NULL, get_ID_MMFR0 },
670 { CRn( 0), CRm( 1), Op1( 0), Op2( 5), is32, NULL, get_ID_MMFR1 },
671 { CRn( 0), CRm( 1), Op1( 0), Op2( 6), is32, NULL, get_ID_MMFR2 },
672 { CRn( 0), CRm( 1), Op1( 0), Op2( 7), is32, NULL, get_ID_MMFR3 },
673
674 { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is32, NULL, get_ID_ISAR0 },
675 { CRn( 0), CRm( 2), Op1( 0), Op2( 1), is32, NULL, get_ID_ISAR1 },
676 { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, NULL, get_ID_ISAR2 },
677 { CRn( 0), CRm( 2), Op1( 0), Op2( 3), is32, NULL, get_ID_ISAR3 },
678 { CRn( 0), CRm( 2), Op1( 0), Op2( 4), is32, NULL, get_ID_ISAR4 },
679 { CRn( 0), CRm( 2), Op1( 0), Op2( 5), is32, NULL, get_ID_ISAR5 },
680
681 { CRn( 0), CRm( 0), Op1( 1), Op2( 1), is32, NULL, get_CLIDR },
682 { CRn( 0), CRm( 0), Op1( 1), Op2( 7), is32, NULL, get_AIDR },
683};
684
685static int reg_from_user(void *val, const void __user *uaddr, u64 id)
686{
687 /* This Just Works because we are little endian. */
688 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
689 return -EFAULT;
690 return 0;
691}
692
693static int reg_to_user(void __user *uaddr, const void *val, u64 id)
694{
695 /* This Just Works because we are little endian. */
696 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
697 return -EFAULT;
698 return 0;
699}
700
701static int get_invariant_cp15(u64 id, void __user *uaddr)
702{
703 struct coproc_params params;
704 const struct coproc_reg *r;
705
706 if (!index_to_params(id, ¶ms))
707 return -ENOENT;
708
709 r = find_reg(¶ms, invariant_cp15, ARRAY_SIZE(invariant_cp15));
710 if (!r)
711 return -ENOENT;
712
713 return reg_to_user(uaddr, &r->val, id);
714}
715
716static int set_invariant_cp15(u64 id, void __user *uaddr)
717{
718 struct coproc_params params;
719 const struct coproc_reg *r;
720 int err;
721 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
722
723 if (!index_to_params(id, ¶ms))
724 return -ENOENT;
725 r = find_reg(¶ms, invariant_cp15, ARRAY_SIZE(invariant_cp15));
726 if (!r)
727 return -ENOENT;
728
729 err = reg_from_user(&val, uaddr, id);
730 if (err)
731 return err;
732
733 /* This is what we mean by invariant: you can't change it. */
734 if (r->val != val)
735 return -EINVAL;
736
737 return 0;
738}
739
740static bool is_valid_cache(u32 val)
741{
742 u32 level, ctype;
743
744 if (val >= CSSELR_MAX)
745 return -ENOENT;
746
747 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
748 level = (val >> 1);
749 ctype = (cache_levels >> (level * 3)) & 7;
750
751 switch (ctype) {
752 case 0: /* No cache */
753 return false;
754 case 1: /* Instruction cache only */
755 return (val & 1);
756 case 2: /* Data cache only */
757 case 4: /* Unified cache */
758 return !(val & 1);
759 case 3: /* Separate instruction and data caches */
760 return true;
761 default: /* Reserved: we can't know instruction or data. */
762 return false;
763 }
764}
765
766/* Which cache CCSIDR represents depends on CSSELR value. */
767static u32 get_ccsidr(u32 csselr)
768{
769 u32 ccsidr;
770
771 /* Make sure noone else changes CSSELR during this! */
772 local_irq_disable();
773 /* Put value into CSSELR */
774 asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
775 isb();
776 /* Read result out of CCSIDR */
777 asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
778 local_irq_enable();
779
780 return ccsidr;
781}
782
783static int demux_c15_get(u64 id, void __user *uaddr)
784{
785 u32 val;
786 u32 __user *uval = uaddr;
787
788 /* Fail if we have unknown bits set. */
789 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
790 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
791 return -ENOENT;
792
793 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
794 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
795 if (KVM_REG_SIZE(id) != 4)
796 return -ENOENT;
797 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
798 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
799 if (!is_valid_cache(val))
800 return -ENOENT;
801
802 return put_user(get_ccsidr(val), uval);
803 default:
804 return -ENOENT;
805 }
806}
807
808static int demux_c15_set(u64 id, void __user *uaddr)
809{
810 u32 val, newval;
811 u32 __user *uval = uaddr;
812
813 /* Fail if we have unknown bits set. */
814 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
815 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
816 return -ENOENT;
817
818 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
819 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
820 if (KVM_REG_SIZE(id) != 4)
821 return -ENOENT;
822 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
823 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
824 if (!is_valid_cache(val))
825 return -ENOENT;
826
827 if (get_user(newval, uval))
828 return -EFAULT;
829
830 /* This is also invariant: you can't change it. */
831 if (newval != get_ccsidr(val))
832 return -EINVAL;
833 return 0;
834 default:
835 return -ENOENT;
836 }
837}
838
839#ifdef CONFIG_VFPv3
840static const int vfp_sysregs[] = { KVM_REG_ARM_VFP_FPEXC,
841 KVM_REG_ARM_VFP_FPSCR,
842 KVM_REG_ARM_VFP_FPINST,
843 KVM_REG_ARM_VFP_FPINST2,
844 KVM_REG_ARM_VFP_MVFR0,
845 KVM_REG_ARM_VFP_MVFR1,
846 KVM_REG_ARM_VFP_FPSID };
847
848static unsigned int num_fp_regs(void)
849{
850 if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK) >> MVFR0_A_SIMD_BIT) == 2)
851 return 32;
852 else
853 return 16;
854}
855
856static unsigned int num_vfp_regs(void)
857{
858 /* Normal FP regs + control regs. */
859 return num_fp_regs() + ARRAY_SIZE(vfp_sysregs);
860}
861
862static int copy_vfp_regids(u64 __user *uindices)
863{
864 unsigned int i;
865 const u64 u32reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP;
866 const u64 u64reg = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
867
868 for (i = 0; i < num_fp_regs(); i++) {
869 if (put_user((u64reg | KVM_REG_ARM_VFP_BASE_REG) + i,
870 uindices))
871 return -EFAULT;
872 uindices++;
873 }
874
875 for (i = 0; i < ARRAY_SIZE(vfp_sysregs); i++) {
876 if (put_user(u32reg | vfp_sysregs[i], uindices))
877 return -EFAULT;
878 uindices++;
879 }
880
881 return num_vfp_regs();
882}
883
884static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
885{
886 u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
887 u32 val;
888
889 /* Fail if we have unknown bits set. */
890 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
891 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
892 return -ENOENT;
893
894 if (vfpid < num_fp_regs()) {
895 if (KVM_REG_SIZE(id) != 8)
896 return -ENOENT;
897 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpregs[vfpid],
898 id);
899 }
900
901 /* FP control registers are all 32 bit. */
902 if (KVM_REG_SIZE(id) != 4)
903 return -ENOENT;
904
905 switch (vfpid) {
906 case KVM_REG_ARM_VFP_FPEXC:
907 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpexc, id);
908 case KVM_REG_ARM_VFP_FPSCR:
909 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpscr, id);
910 case KVM_REG_ARM_VFP_FPINST:
911 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpinst, id);
912 case KVM_REG_ARM_VFP_FPINST2:
913 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpinst2, id);
914 case KVM_REG_ARM_VFP_MVFR0:
915 val = fmrx(MVFR0);
916 return reg_to_user(uaddr, &val, id);
917 case KVM_REG_ARM_VFP_MVFR1:
918 val = fmrx(MVFR1);
919 return reg_to_user(uaddr, &val, id);
920 case KVM_REG_ARM_VFP_FPSID:
921 val = fmrx(FPSID);
922 return reg_to_user(uaddr, &val, id);
923 default:
924 return -ENOENT;
925 }
926}
927
928static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
929{
930 u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
931 u32 val;
932
933 /* Fail if we have unknown bits set. */
934 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
935 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
936 return -ENOENT;
937
938 if (vfpid < num_fp_regs()) {
939 if (KVM_REG_SIZE(id) != 8)
940 return -ENOENT;
941 return reg_from_user(&vcpu->arch.vfp_guest.fpregs[vfpid],
942 uaddr, id);
943 }
944
945 /* FP control registers are all 32 bit. */
946 if (KVM_REG_SIZE(id) != 4)
947 return -ENOENT;
948
949 switch (vfpid) {
950 case KVM_REG_ARM_VFP_FPEXC:
951 return reg_from_user(&vcpu->arch.vfp_guest.fpexc, uaddr, id);
952 case KVM_REG_ARM_VFP_FPSCR:
953 return reg_from_user(&vcpu->arch.vfp_guest.fpscr, uaddr, id);
954 case KVM_REG_ARM_VFP_FPINST:
955 return reg_from_user(&vcpu->arch.vfp_guest.fpinst, uaddr, id);
956 case KVM_REG_ARM_VFP_FPINST2:
957 return reg_from_user(&vcpu->arch.vfp_guest.fpinst2, uaddr, id);
958 /* These are invariant. */
959 case KVM_REG_ARM_VFP_MVFR0:
960 if (reg_from_user(&val, uaddr, id))
961 return -EFAULT;
962 if (val != fmrx(MVFR0))
963 return -EINVAL;
964 return 0;
965 case KVM_REG_ARM_VFP_MVFR1:
966 if (reg_from_user(&val, uaddr, id))
967 return -EFAULT;
968 if (val != fmrx(MVFR1))
969 return -EINVAL;
970 return 0;
971 case KVM_REG_ARM_VFP_FPSID:
972 if (reg_from_user(&val, uaddr, id))
973 return -EFAULT;
974 if (val != fmrx(FPSID))
975 return -EINVAL;
976 return 0;
977 default:
978 return -ENOENT;
979 }
980}
981#else /* !CONFIG_VFPv3 */
982static unsigned int num_vfp_regs(void)
983{
984 return 0;
985}
986
987static int copy_vfp_regids(u64 __user *uindices)
988{
989 return 0;
990}
991
992static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
993{
994 return -ENOENT;
995}
996
997static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
998{
999 return -ENOENT;
1000}
1001#endif /* !CONFIG_VFPv3 */
1002
1003int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1004{
1005 const struct coproc_reg *r;
1006 void __user *uaddr = (void __user *)(long)reg->addr;
1007
1008 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1009 return demux_c15_get(reg->id, uaddr);
1010
1011 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
1012 return vfp_get_reg(vcpu, reg->id, uaddr);
1013
1014 r = index_to_coproc_reg(vcpu, reg->id);
1015 if (!r)
1016 return get_invariant_cp15(reg->id, uaddr);
1017
1018 /* Note: copies two regs if size is 64 bit. */
1019 return reg_to_user(uaddr, &vcpu->arch.cp15[r->reg], reg->id);
1020}
1021
1022int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1023{
1024 const struct coproc_reg *r;
1025 void __user *uaddr = (void __user *)(long)reg->addr;
1026
1027 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1028 return demux_c15_set(reg->id, uaddr);
1029
1030 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
1031 return vfp_set_reg(vcpu, reg->id, uaddr);
1032
1033 r = index_to_coproc_reg(vcpu, reg->id);
1034 if (!r)
1035 return set_invariant_cp15(reg->id, uaddr);
1036
1037 /* Note: copies two regs if size is 64 bit */
1038 return reg_from_user(&vcpu->arch.cp15[r->reg], uaddr, reg->id);
1039}
1040
1041static unsigned int num_demux_regs(void)
1042{
1043 unsigned int i, count = 0;
1044
1045 for (i = 0; i < CSSELR_MAX; i++)
1046 if (is_valid_cache(i))
1047 count++;
1048
1049 return count;
1050}
1051
1052static int write_demux_regids(u64 __user *uindices)
1053{
1054 u64 val = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
1055 unsigned int i;
1056
1057 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
1058 for (i = 0; i < CSSELR_MAX; i++) {
1059 if (!is_valid_cache(i))
1060 continue;
1061 if (put_user(val | i, uindices))
1062 return -EFAULT;
1063 uindices++;
1064 }
1065 return 0;
1066}
1067
1068static u64 cp15_to_index(const struct coproc_reg *reg)
1069{
1070 u64 val = KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT);
1071 if (reg->is_64) {
1072 val |= KVM_REG_SIZE_U64;
1073 val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
1074 /*
1075 * CRn always denotes the primary coproc. reg. nr. for the
1076 * in-kernel representation, but the user space API uses the
1077 * CRm for the encoding, because it is modelled after the
1078 * MRRC/MCRR instructions: see the ARM ARM rev. c page
1079 * B3-1445
1080 */
1081 val |= (reg->CRn << KVM_REG_ARM_CRM_SHIFT);
1082 } else {
1083 val |= KVM_REG_SIZE_U32;
1084 val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
1085 val |= (reg->Op2 << KVM_REG_ARM_32_OPC2_SHIFT);
1086 val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
1087 val |= (reg->CRn << KVM_REG_ARM_32_CRN_SHIFT);
1088 }
1089 return val;
1090}
1091
1092static bool copy_reg_to_user(const struct coproc_reg *reg, u64 __user **uind)
1093{
1094 if (!*uind)
1095 return true;
1096
1097 if (put_user(cp15_to_index(reg), *uind))
1098 return false;
1099
1100 (*uind)++;
1101 return true;
1102}
1103
1104/* Assumed ordered tables, see kvm_coproc_table_init. */
1105static int walk_cp15(struct kvm_vcpu *vcpu, u64 __user *uind)
1106{
1107 const struct coproc_reg *i1, *i2, *end1, *end2;
1108 unsigned int total = 0;
1109 size_t num;
1110
1111 /* We check for duplicates here, to allow arch-specific overrides. */
1112 i1 = get_target_table(vcpu->arch.target, &num);
1113 end1 = i1 + num;
1114 i2 = cp15_regs;
1115 end2 = cp15_regs + ARRAY_SIZE(cp15_regs);
1116
1117 BUG_ON(i1 == end1 || i2 == end2);
1118
1119 /* Walk carefully, as both tables may refer to the same register. */
1120 while (i1 || i2) {
1121 int cmp = cmp_reg(i1, i2);
1122 /* target-specific overrides generic entry. */
1123 if (cmp <= 0) {
1124 /* Ignore registers we trap but don't save. */
1125 if (i1->reg) {
1126 if (!copy_reg_to_user(i1, &uind))
1127 return -EFAULT;
1128 total++;
1129 }
1130 } else {
1131 /* Ignore registers we trap but don't save. */
1132 if (i2->reg) {
1133 if (!copy_reg_to_user(i2, &uind))
1134 return -EFAULT;
1135 total++;
1136 }
1137 }
1138
1139 if (cmp <= 0 && ++i1 == end1)
1140 i1 = NULL;
1141 if (cmp >= 0 && ++i2 == end2)
1142 i2 = NULL;
1143 }
1144 return total;
1145}
1146
1147unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu)
1148{
1149 return ARRAY_SIZE(invariant_cp15)
1150 + num_demux_regs()
1151 + num_vfp_regs()
1152 + walk_cp15(vcpu, (u64 __user *)NULL);
1153}
1154
1155int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
1156{
1157 unsigned int i;
1158 int err;
1159
1160 /* Then give them all the invariant registers' indices. */
1161 for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++) {
1162 if (put_user(cp15_to_index(&invariant_cp15[i]), uindices))
1163 return -EFAULT;
1164 uindices++;
1165 }
1166
1167 err = walk_cp15(vcpu, uindices);
1168 if (err < 0)
1169 return err;
1170 uindices += err;
1171
1172 err = copy_vfp_regids(uindices);
1173 if (err < 0)
1174 return err;
1175 uindices += err;
1176
1177 return write_demux_regids(uindices);
1178}
1179
1180void kvm_coproc_table_init(void)
1181{
1182 unsigned int i;
1183
1184 /* Make sure tables are unique and in order. */
1185 for (i = 1; i < ARRAY_SIZE(cp15_regs); i++)
1186 BUG_ON(cmp_reg(&cp15_regs[i-1], &cp15_regs[i]) >= 0);
1187
1188 /* We abuse the reset function to overwrite the table itself. */
1189 for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++)
1190 invariant_cp15[i].reset(NULL, &invariant_cp15[i]);
1191
1192 /*
1193 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
1194 *
1195 * If software reads the Cache Type fields from Ctype1
1196 * upwards, once it has seen a value of 0b000, no caches
1197 * exist at further-out levels of the hierarchy. So, for
1198 * example, if Ctype3 is the first Cache Type field with a
1199 * value of 0b000, the values of Ctype4 to Ctype7 must be
1200 * ignored.
1201 */
1202 asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (cache_levels));
1203 for (i = 0; i < 7; i++)
1204 if (((cache_levels >> (i*3)) & 7) == 0)
1205 break;
1206 /* Clear all higher bits. */
1207 cache_levels &= (1 << (i*3))-1;
1208}
1209
1210/**
1211 * kvm_reset_coprocs - sets cp15 registers to reset value
1212 * @vcpu: The VCPU pointer
1213 *
1214 * This function finds the right table above and sets the registers on the
1215 * virtual CPU struct to their architecturally defined reset values.
1216 */
1217void kvm_reset_coprocs(struct kvm_vcpu *vcpu)
1218{
1219 size_t num;
1220 const struct coproc_reg *table;
1221
1222 /* Catch someone adding a register without putting in reset entry. */
1223 memset(vcpu->arch.cp15, 0x42, sizeof(vcpu->arch.cp15));
1224
1225 /* Generic chip reset first (so target could override). */
1226 reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
1227
1228 table = get_target_table(vcpu->arch.target, &num);
1229 reset_coproc_regs(vcpu, table, num);
1230
1231 for (num = 1; num < NR_CP15_REGS; num++)
1232 if (vcpu->arch.cp15[num] == 0x42424242)
1233 panic("Didn't reset vcpu->arch.cp15[%zi]", num);
1234}