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1// SPDX-License-Identifier: GPL-2.0
2/* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch
3 *
4 * This is a sparsely documented chip, the only viable documentation seems
5 * to be a patched up code drop from the vendor that appear in various
6 * GPL source trees.
7 *
8 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
9 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
10 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
11 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
12 * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com>
13 */
14
15#include <linux/bitops.h>
16#include <linux/etherdevice.h>
17#include <linux/interrupt.h>
18#include <linux/irqdomain.h>
19#include <linux/irqchip/chained_irq.h>
20#include <linux/of_irq.h>
21#include <linux/regmap.h>
22
23#include "realtek-smi-core.h"
24
25#define RTL8366RB_PORT_NUM_CPU 5
26#define RTL8366RB_NUM_PORTS 6
27#define RTL8366RB_PHY_NO_MAX 4
28#define RTL8366RB_PHY_ADDR_MAX 31
29
30/* Switch Global Configuration register */
31#define RTL8366RB_SGCR 0x0000
32#define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
33#define RTL8366RB_SGCR_MAX_LENGTH(a) ((a) << 4)
34#define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
35#define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
36#define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
37#define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
38#define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
39#define RTL8366RB_SGCR_EN_VLAN BIT(13)
40#define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
41
42/* Port Enable Control register */
43#define RTL8366RB_PECR 0x0001
44
45/* Switch Security Control registers */
46#define RTL8366RB_SSCR0 0x0002
47#define RTL8366RB_SSCR1 0x0003
48#define RTL8366RB_SSCR2 0x0004
49#define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
50
51/* Port Mode Control registers */
52#define RTL8366RB_PMC0 0x0005
53#define RTL8366RB_PMC0_SPI BIT(0)
54#define RTL8366RB_PMC0_EN_AUTOLOAD BIT(1)
55#define RTL8366RB_PMC0_PROBE BIT(2)
56#define RTL8366RB_PMC0_DIS_BISR BIT(3)
57#define RTL8366RB_PMC0_ADCTEST BIT(4)
58#define RTL8366RB_PMC0_SRAM_DIAG BIT(5)
59#define RTL8366RB_PMC0_EN_SCAN BIT(6)
60#define RTL8366RB_PMC0_P4_IOMODE_SHIFT 7
61#define RTL8366RB_PMC0_P4_IOMODE_MASK GENMASK(9, 7)
62#define RTL8366RB_PMC0_P5_IOMODE_SHIFT 10
63#define RTL8366RB_PMC0_P5_IOMODE_MASK GENMASK(12, 10)
64#define RTL8366RB_PMC0_SDSMODE_SHIFT 13
65#define RTL8366RB_PMC0_SDSMODE_MASK GENMASK(15, 13)
66#define RTL8366RB_PMC1 0x0006
67
68/* Port Mirror Control Register */
69#define RTL8366RB_PMCR 0x0007
70#define RTL8366RB_PMCR_SOURCE_PORT(a) (a)
71#define RTL8366RB_PMCR_SOURCE_PORT_MASK 0x000f
72#define RTL8366RB_PMCR_MONITOR_PORT(a) ((a) << 4)
73#define RTL8366RB_PMCR_MONITOR_PORT_MASK 0x00f0
74#define RTL8366RB_PMCR_MIRROR_RX BIT(8)
75#define RTL8366RB_PMCR_MIRROR_TX BIT(9)
76#define RTL8366RB_PMCR_MIRROR_SPC BIT(10)
77#define RTL8366RB_PMCR_MIRROR_ISO BIT(11)
78
79/* bits 0..7 = port 0, bits 8..15 = port 1 */
80#define RTL8366RB_PAACR0 0x0010
81/* bits 0..7 = port 2, bits 8..15 = port 3 */
82#define RTL8366RB_PAACR1 0x0011
83/* bits 0..7 = port 4, bits 8..15 = port 5 */
84#define RTL8366RB_PAACR2 0x0012
85#define RTL8366RB_PAACR_SPEED_10M 0
86#define RTL8366RB_PAACR_SPEED_100M 1
87#define RTL8366RB_PAACR_SPEED_1000M 2
88#define RTL8366RB_PAACR_FULL_DUPLEX BIT(2)
89#define RTL8366RB_PAACR_LINK_UP BIT(4)
90#define RTL8366RB_PAACR_TX_PAUSE BIT(5)
91#define RTL8366RB_PAACR_RX_PAUSE BIT(6)
92#define RTL8366RB_PAACR_AN BIT(7)
93
94#define RTL8366RB_PAACR_CPU_PORT (RTL8366RB_PAACR_SPEED_1000M | \
95 RTL8366RB_PAACR_FULL_DUPLEX | \
96 RTL8366RB_PAACR_LINK_UP | \
97 RTL8366RB_PAACR_TX_PAUSE | \
98 RTL8366RB_PAACR_RX_PAUSE)
99
100/* bits 0..7 = port 0, bits 8..15 = port 1 */
101#define RTL8366RB_PSTAT0 0x0014
102/* bits 0..7 = port 2, bits 8..15 = port 3 */
103#define RTL8366RB_PSTAT1 0x0015
104/* bits 0..7 = port 4, bits 8..15 = port 5 */
105#define RTL8366RB_PSTAT2 0x0016
106
107#define RTL8366RB_POWER_SAVING_REG 0x0021
108
109/* CPU port control reg */
110#define RTL8368RB_CPU_CTRL_REG 0x0061
111#define RTL8368RB_CPU_PORTS_MSK 0x00FF
112/* Disables inserting custom tag length/type 0x8899 */
113#define RTL8368RB_CPU_NO_TAG BIT(15)
114
115#define RTL8366RB_SMAR0 0x0070 /* bits 0..15 */
116#define RTL8366RB_SMAR1 0x0071 /* bits 16..31 */
117#define RTL8366RB_SMAR2 0x0072 /* bits 32..47 */
118
119#define RTL8366RB_RESET_CTRL_REG 0x0100
120#define RTL8366RB_CHIP_CTRL_RESET_HW BIT(0)
121#define RTL8366RB_CHIP_CTRL_RESET_SW BIT(1)
122
123#define RTL8366RB_CHIP_ID_REG 0x0509
124#define RTL8366RB_CHIP_ID_8366 0x5937
125#define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
126#define RTL8366RB_CHIP_VERSION_MASK 0xf
127
128/* PHY registers control */
129#define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
130#define RTL8366RB_PHY_CTRL_READ BIT(0)
131#define RTL8366RB_PHY_CTRL_WRITE 0
132#define RTL8366RB_PHY_ACCESS_BUSY_REG 0x8001
133#define RTL8366RB_PHY_INT_BUSY BIT(0)
134#define RTL8366RB_PHY_EXT_BUSY BIT(4)
135#define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
136#define RTL8366RB_PHY_EXT_CTRL_REG 0x8010
137#define RTL8366RB_PHY_EXT_WRDATA_REG 0x8011
138#define RTL8366RB_PHY_EXT_RDDATA_REG 0x8012
139
140#define RTL8366RB_PHY_REG_MASK 0x1f
141#define RTL8366RB_PHY_PAGE_OFFSET 5
142#define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
143#define RTL8366RB_PHY_NO_OFFSET 9
144#define RTL8366RB_PHY_NO_MASK (0x1f << 9)
145
146#define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
147
148/* LED control registers */
149#define RTL8366RB_LED_BLINKRATE_REG 0x0430
150#define RTL8366RB_LED_BLINKRATE_MASK 0x0007
151#define RTL8366RB_LED_BLINKRATE_28MS 0x0000
152#define RTL8366RB_LED_BLINKRATE_56MS 0x0001
153#define RTL8366RB_LED_BLINKRATE_84MS 0x0002
154#define RTL8366RB_LED_BLINKRATE_111MS 0x0003
155#define RTL8366RB_LED_BLINKRATE_222MS 0x0004
156#define RTL8366RB_LED_BLINKRATE_446MS 0x0005
157
158#define RTL8366RB_LED_CTRL_REG 0x0431
159#define RTL8366RB_LED_OFF 0x0
160#define RTL8366RB_LED_DUP_COL 0x1
161#define RTL8366RB_LED_LINK_ACT 0x2
162#define RTL8366RB_LED_SPD1000 0x3
163#define RTL8366RB_LED_SPD100 0x4
164#define RTL8366RB_LED_SPD10 0x5
165#define RTL8366RB_LED_SPD1000_ACT 0x6
166#define RTL8366RB_LED_SPD100_ACT 0x7
167#define RTL8366RB_LED_SPD10_ACT 0x8
168#define RTL8366RB_LED_SPD100_10_ACT 0x9
169#define RTL8366RB_LED_FIBER 0xa
170#define RTL8366RB_LED_AN_FAULT 0xb
171#define RTL8366RB_LED_LINK_RX 0xc
172#define RTL8366RB_LED_LINK_TX 0xd
173#define RTL8366RB_LED_MASTER 0xe
174#define RTL8366RB_LED_FORCE 0xf
175#define RTL8366RB_LED_0_1_CTRL_REG 0x0432
176#define RTL8366RB_LED_1_OFFSET 6
177#define RTL8366RB_LED_2_3_CTRL_REG 0x0433
178#define RTL8366RB_LED_3_OFFSET 6
179
180#define RTL8366RB_MIB_COUNT 33
181#define RTL8366RB_GLOBAL_MIB_COUNT 1
182#define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
183#define RTL8366RB_MIB_COUNTER_BASE 0x1000
184#define RTL8366RB_MIB_CTRL_REG 0x13F0
185#define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
186#define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
187#define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
188#define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
189#define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
190
191#define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
192#define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
193 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
194#define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
195#define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
196
197#define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
198#define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
199
200#define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
201#define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
202#define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
203
204#define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
205
206#define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
207#define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
208#define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
209#define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
210#define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
211#define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
212#define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
213
214#define RTL8366RB_NUM_VLANS 16
215#define RTL8366RB_NUM_LEDGROUPS 4
216#define RTL8366RB_NUM_VIDS 4096
217#define RTL8366RB_PRIORITYMAX 7
218#define RTL8366RB_FIDMAX 7
219
220#define RTL8366RB_PORT_1 BIT(0) /* In userspace port 0 */
221#define RTL8366RB_PORT_2 BIT(1) /* In userspace port 1 */
222#define RTL8366RB_PORT_3 BIT(2) /* In userspace port 2 */
223#define RTL8366RB_PORT_4 BIT(3) /* In userspace port 3 */
224#define RTL8366RB_PORT_5 BIT(4) /* In userspace port 4 */
225
226#define RTL8366RB_PORT_CPU BIT(5) /* CPU port */
227
228#define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
229 RTL8366RB_PORT_2 | \
230 RTL8366RB_PORT_3 | \
231 RTL8366RB_PORT_4 | \
232 RTL8366RB_PORT_5 | \
233 RTL8366RB_PORT_CPU)
234
235#define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
236 RTL8366RB_PORT_2 | \
237 RTL8366RB_PORT_3 | \
238 RTL8366RB_PORT_4 | \
239 RTL8366RB_PORT_5)
240
241#define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
242 RTL8366RB_PORT_2 | \
243 RTL8366RB_PORT_3 | \
244 RTL8366RB_PORT_4)
245
246#define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
247
248/* First configuration word per member config, VID and prio */
249#define RTL8366RB_VLAN_VID_MASK 0xfff
250#define RTL8366RB_VLAN_PRIORITY_SHIFT 12
251#define RTL8366RB_VLAN_PRIORITY_MASK 0x7
252/* Second configuration word per member config, member and untagged */
253#define RTL8366RB_VLAN_UNTAG_SHIFT 8
254#define RTL8366RB_VLAN_UNTAG_MASK 0xff
255#define RTL8366RB_VLAN_MEMBER_MASK 0xff
256/* Third config word per member config, STAG currently unused */
257#define RTL8366RB_VLAN_STAG_MBR_MASK 0xff
258#define RTL8366RB_VLAN_STAG_MBR_SHIFT 8
259#define RTL8366RB_VLAN_STAG_IDX_MASK 0x7
260#define RTL8366RB_VLAN_STAG_IDX_SHIFT 5
261#define RTL8366RB_VLAN_FID_MASK 0x7
262
263/* Port ingress bandwidth control */
264#define RTL8366RB_IB_BASE 0x0200
265#define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + (pnum))
266#define RTL8366RB_IB_BDTH_MASK 0x3fff
267#define RTL8366RB_IB_PREIFG BIT(14)
268
269/* Port egress bandwidth control */
270#define RTL8366RB_EB_BASE 0x02d1
271#define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + (pnum))
272#define RTL8366RB_EB_BDTH_MASK 0x3fff
273#define RTL8366RB_EB_PREIFG_REG 0x02f8
274#define RTL8366RB_EB_PREIFG BIT(9)
275
276#define RTL8366RB_BDTH_SW_MAX 1048512 /* 1048576? */
277#define RTL8366RB_BDTH_UNIT 64
278#define RTL8366RB_BDTH_REG_DEFAULT 16383
279
280/* QOS */
281#define RTL8366RB_QOS BIT(15)
282/* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
283#define RTL8366RB_QOS_DEFAULT_PREIFG 1
284
285/* Interrupt handling */
286#define RTL8366RB_INTERRUPT_CONTROL_REG 0x0440
287#define RTL8366RB_INTERRUPT_POLARITY BIT(0)
288#define RTL8366RB_P4_RGMII_LED BIT(2)
289#define RTL8366RB_INTERRUPT_MASK_REG 0x0441
290#define RTL8366RB_INTERRUPT_LINK_CHGALL GENMASK(11, 0)
291#define RTL8366RB_INTERRUPT_ACLEXCEED BIT(8)
292#define RTL8366RB_INTERRUPT_STORMEXCEED BIT(9)
293#define RTL8366RB_INTERRUPT_P4_FIBER BIT(12)
294#define RTL8366RB_INTERRUPT_P4_UTP BIT(13)
295#define RTL8366RB_INTERRUPT_VALID (RTL8366RB_INTERRUPT_LINK_CHGALL | \
296 RTL8366RB_INTERRUPT_ACLEXCEED | \
297 RTL8366RB_INTERRUPT_STORMEXCEED | \
298 RTL8366RB_INTERRUPT_P4_FIBER | \
299 RTL8366RB_INTERRUPT_P4_UTP)
300#define RTL8366RB_INTERRUPT_STATUS_REG 0x0442
301#define RTL8366RB_NUM_INTERRUPT 14 /* 0..13 */
302
303/* bits 0..5 enable force when cleared */
304#define RTL8366RB_MAC_FORCE_CTRL_REG 0x0F11
305
306#define RTL8366RB_OAM_PARSER_REG 0x0F14
307#define RTL8366RB_OAM_MULTIPLEXER_REG 0x0F15
308
309#define RTL8366RB_GREEN_FEATURE_REG 0x0F51
310#define RTL8366RB_GREEN_FEATURE_MSK 0x0007
311#define RTL8366RB_GREEN_FEATURE_TX BIT(0)
312#define RTL8366RB_GREEN_FEATURE_RX BIT(2)
313
314static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
315 { 0, 0, 4, "IfInOctets" },
316 { 0, 4, 4, "EtherStatsOctets" },
317 { 0, 8, 2, "EtherStatsUnderSizePkts" },
318 { 0, 10, 2, "EtherFragments" },
319 { 0, 12, 2, "EtherStatsPkts64Octets" },
320 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
321 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
322 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
323 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
324 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
325 { 0, 24, 2, "EtherOversizeStats" },
326 { 0, 26, 2, "EtherStatsJabbers" },
327 { 0, 28, 2, "IfInUcastPkts" },
328 { 0, 30, 2, "EtherStatsMulticastPkts" },
329 { 0, 32, 2, "EtherStatsBroadcastPkts" },
330 { 0, 34, 2, "EtherStatsDropEvents" },
331 { 0, 36, 2, "Dot3StatsFCSErrors" },
332 { 0, 38, 2, "Dot3StatsSymbolErrors" },
333 { 0, 40, 2, "Dot3InPauseFrames" },
334 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
335 { 0, 44, 4, "IfOutOctets" },
336 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
337 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
338 { 0, 52, 2, "Dot3sDeferredTransmissions" },
339 { 0, 54, 2, "Dot3StatsLateCollisions" },
340 { 0, 56, 2, "EtherStatsCollisions" },
341 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
342 { 0, 60, 2, "Dot3OutPauseFrames" },
343 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
344 { 0, 64, 2, "Dot1dTpPortInDiscards" },
345 { 0, 66, 2, "IfOutUcastPkts" },
346 { 0, 68, 2, "IfOutMulticastPkts" },
347 { 0, 70, 2, "IfOutBroadcastPkts" },
348};
349
350static int rtl8366rb_get_mib_counter(struct realtek_smi *smi,
351 int port,
352 struct rtl8366_mib_counter *mib,
353 u64 *mibvalue)
354{
355 u32 addr, val;
356 int ret;
357 int i;
358
359 addr = RTL8366RB_MIB_COUNTER_BASE +
360 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
361 mib->offset;
362
363 /* Writing access counter address first
364 * then ASIC will prepare 64bits counter wait for being retrived
365 */
366 ret = regmap_write(smi->map, addr, 0); /* Write whatever */
367 if (ret)
368 return ret;
369
370 /* Read MIB control register */
371 ret = regmap_read(smi->map, RTL8366RB_MIB_CTRL_REG, &val);
372 if (ret)
373 return -EIO;
374
375 if (val & RTL8366RB_MIB_CTRL_BUSY_MASK)
376 return -EBUSY;
377
378 if (val & RTL8366RB_MIB_CTRL_RESET_MASK)
379 return -EIO;
380
381 /* Read each individual MIB 16 bits at the time */
382 *mibvalue = 0;
383 for (i = mib->length; i > 0; i--) {
384 ret = regmap_read(smi->map, addr + (i - 1), &val);
385 if (ret)
386 return ret;
387 *mibvalue = (*mibvalue << 16) | (val & 0xFFFF);
388 }
389 return 0;
390}
391
392static u32 rtl8366rb_get_irqmask(struct irq_data *d)
393{
394 int line = irqd_to_hwirq(d);
395 u32 val;
396
397 /* For line interrupts we combine link down in bits
398 * 6..11 with link up in bits 0..5 into one interrupt.
399 */
400 if (line < 12)
401 val = BIT(line) | BIT(line + 6);
402 else
403 val = BIT(line);
404 return val;
405}
406
407static void rtl8366rb_mask_irq(struct irq_data *d)
408{
409 struct realtek_smi *smi = irq_data_get_irq_chip_data(d);
410 int ret;
411
412 ret = regmap_update_bits(smi->map, RTL8366RB_INTERRUPT_MASK_REG,
413 rtl8366rb_get_irqmask(d), 0);
414 if (ret)
415 dev_err(smi->dev, "could not mask IRQ\n");
416}
417
418static void rtl8366rb_unmask_irq(struct irq_data *d)
419{
420 struct realtek_smi *smi = irq_data_get_irq_chip_data(d);
421 int ret;
422
423 ret = regmap_update_bits(smi->map, RTL8366RB_INTERRUPT_MASK_REG,
424 rtl8366rb_get_irqmask(d),
425 rtl8366rb_get_irqmask(d));
426 if (ret)
427 dev_err(smi->dev, "could not unmask IRQ\n");
428}
429
430static irqreturn_t rtl8366rb_irq(int irq, void *data)
431{
432 struct realtek_smi *smi = data;
433 u32 stat;
434 int ret;
435
436 /* This clears the IRQ status register */
437 ret = regmap_read(smi->map, RTL8366RB_INTERRUPT_STATUS_REG,
438 &stat);
439 if (ret) {
440 dev_err(smi->dev, "can't read interrupt status\n");
441 return IRQ_NONE;
442 }
443 stat &= RTL8366RB_INTERRUPT_VALID;
444 if (!stat)
445 return IRQ_NONE;
446 while (stat) {
447 int line = __ffs(stat);
448 int child_irq;
449
450 stat &= ~BIT(line);
451 /* For line interrupts we combine link down in bits
452 * 6..11 with link up in bits 0..5 into one interrupt.
453 */
454 if (line < 12 && line > 5)
455 line -= 5;
456 child_irq = irq_find_mapping(smi->irqdomain, line);
457 handle_nested_irq(child_irq);
458 }
459 return IRQ_HANDLED;
460}
461
462static struct irq_chip rtl8366rb_irq_chip = {
463 .name = "RTL8366RB",
464 .irq_mask = rtl8366rb_mask_irq,
465 .irq_unmask = rtl8366rb_unmask_irq,
466};
467
468static int rtl8366rb_irq_map(struct irq_domain *domain, unsigned int irq,
469 irq_hw_number_t hwirq)
470{
471 irq_set_chip_data(irq, domain->host_data);
472 irq_set_chip_and_handler(irq, &rtl8366rb_irq_chip, handle_simple_irq);
473 irq_set_nested_thread(irq, 1);
474 irq_set_noprobe(irq);
475
476 return 0;
477}
478
479static void rtl8366rb_irq_unmap(struct irq_domain *d, unsigned int irq)
480{
481 irq_set_nested_thread(irq, 0);
482 irq_set_chip_and_handler(irq, NULL, NULL);
483 irq_set_chip_data(irq, NULL);
484}
485
486static const struct irq_domain_ops rtl8366rb_irqdomain_ops = {
487 .map = rtl8366rb_irq_map,
488 .unmap = rtl8366rb_irq_unmap,
489 .xlate = irq_domain_xlate_onecell,
490};
491
492static int rtl8366rb_setup_cascaded_irq(struct realtek_smi *smi)
493{
494 struct device_node *intc;
495 unsigned long irq_trig;
496 int irq;
497 int ret;
498 u32 val;
499 int i;
500
501 intc = of_get_child_by_name(smi->dev->of_node, "interrupt-controller");
502 if (!intc) {
503 dev_err(smi->dev, "missing child interrupt-controller node\n");
504 return -EINVAL;
505 }
506 /* RB8366RB IRQs cascade off this one */
507 irq = of_irq_get(intc, 0);
508 if (irq <= 0) {
509 dev_err(smi->dev, "failed to get parent IRQ\n");
510 ret = irq ? irq : -EINVAL;
511 goto out_put_node;
512 }
513
514 /* This clears the IRQ status register */
515 ret = regmap_read(smi->map, RTL8366RB_INTERRUPT_STATUS_REG,
516 &val);
517 if (ret) {
518 dev_err(smi->dev, "can't read interrupt status\n");
519 goto out_put_node;
520 }
521
522 /* Fetch IRQ edge information from the descriptor */
523 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
524 switch (irq_trig) {
525 case IRQF_TRIGGER_RISING:
526 case IRQF_TRIGGER_HIGH:
527 dev_info(smi->dev, "active high/rising IRQ\n");
528 val = 0;
529 break;
530 case IRQF_TRIGGER_FALLING:
531 case IRQF_TRIGGER_LOW:
532 dev_info(smi->dev, "active low/falling IRQ\n");
533 val = RTL8366RB_INTERRUPT_POLARITY;
534 break;
535 }
536 ret = regmap_update_bits(smi->map, RTL8366RB_INTERRUPT_CONTROL_REG,
537 RTL8366RB_INTERRUPT_POLARITY,
538 val);
539 if (ret) {
540 dev_err(smi->dev, "could not configure IRQ polarity\n");
541 goto out_put_node;
542 }
543
544 ret = devm_request_threaded_irq(smi->dev, irq, NULL,
545 rtl8366rb_irq, IRQF_ONESHOT,
546 "RTL8366RB", smi);
547 if (ret) {
548 dev_err(smi->dev, "unable to request irq: %d\n", ret);
549 goto out_put_node;
550 }
551 smi->irqdomain = irq_domain_add_linear(intc,
552 RTL8366RB_NUM_INTERRUPT,
553 &rtl8366rb_irqdomain_ops,
554 smi);
555 if (!smi->irqdomain) {
556 dev_err(smi->dev, "failed to create IRQ domain\n");
557 ret = -EINVAL;
558 goto out_put_node;
559 }
560 for (i = 0; i < smi->num_ports; i++)
561 irq_set_parent(irq_create_mapping(smi->irqdomain, i), irq);
562
563out_put_node:
564 of_node_put(intc);
565 return ret;
566}
567
568static int rtl8366rb_set_addr(struct realtek_smi *smi)
569{
570 u8 addr[ETH_ALEN];
571 u16 val;
572 int ret;
573
574 eth_random_addr(addr);
575
576 dev_info(smi->dev, "set MAC: %02X:%02X:%02X:%02X:%02X:%02X\n",
577 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
578 val = addr[0] << 8 | addr[1];
579 ret = regmap_write(smi->map, RTL8366RB_SMAR0, val);
580 if (ret)
581 return ret;
582 val = addr[2] << 8 | addr[3];
583 ret = regmap_write(smi->map, RTL8366RB_SMAR1, val);
584 if (ret)
585 return ret;
586 val = addr[4] << 8 | addr[5];
587 ret = regmap_write(smi->map, RTL8366RB_SMAR2, val);
588 if (ret)
589 return ret;
590
591 return 0;
592}
593
594/* Found in a vendor driver */
595
596/* For the "version 0" early silicon, appear in most source releases */
597static const u16 rtl8366rb_init_jam_ver_0[] = {
598 0x000B, 0x0001, 0x03A6, 0x0100, 0x03A7, 0x0001, 0x02D1, 0x3FFF,
599 0x02D2, 0x3FFF, 0x02D3, 0x3FFF, 0x02D4, 0x3FFF, 0x02D5, 0x3FFF,
600 0x02D6, 0x3FFF, 0x02D7, 0x3FFF, 0x02D8, 0x3FFF, 0x022B, 0x0688,
601 0x022C, 0x0FAC, 0x03D0, 0x4688, 0x03D1, 0x01F5, 0x0000, 0x0830,
602 0x02F9, 0x0200, 0x02F7, 0x7FFF, 0x02F8, 0x03FF, 0x0080, 0x03E8,
603 0x0081, 0x00CE, 0x0082, 0x00DA, 0x0083, 0x0230, 0xBE0F, 0x2000,
604 0x0231, 0x422A, 0x0232, 0x422A, 0x0233, 0x422A, 0x0234, 0x422A,
605 0x0235, 0x422A, 0x0236, 0x422A, 0x0237, 0x422A, 0x0238, 0x422A,
606 0x0239, 0x422A, 0x023A, 0x422A, 0x023B, 0x422A, 0x023C, 0x422A,
607 0x023D, 0x422A, 0x023E, 0x422A, 0x023F, 0x422A, 0x0240, 0x422A,
608 0x0241, 0x422A, 0x0242, 0x422A, 0x0243, 0x422A, 0x0244, 0x422A,
609 0x0245, 0x422A, 0x0246, 0x422A, 0x0247, 0x422A, 0x0248, 0x422A,
610 0x0249, 0x0146, 0x024A, 0x0146, 0x024B, 0x0146, 0xBE03, 0xC961,
611 0x024D, 0x0146, 0x024E, 0x0146, 0x024F, 0x0146, 0x0250, 0x0146,
612 0xBE64, 0x0226, 0x0252, 0x0146, 0x0253, 0x0146, 0x024C, 0x0146,
613 0x0251, 0x0146, 0x0254, 0x0146, 0xBE62, 0x3FD0, 0x0084, 0x0320,
614 0x0255, 0x0146, 0x0256, 0x0146, 0x0257, 0x0146, 0x0258, 0x0146,
615 0x0259, 0x0146, 0x025A, 0x0146, 0x025B, 0x0146, 0x025C, 0x0146,
616 0x025D, 0x0146, 0x025E, 0x0146, 0x025F, 0x0146, 0x0260, 0x0146,
617 0x0261, 0xA23F, 0x0262, 0x0294, 0x0263, 0xA23F, 0x0264, 0x0294,
618 0x0265, 0xA23F, 0x0266, 0x0294, 0x0267, 0xA23F, 0x0268, 0x0294,
619 0x0269, 0xA23F, 0x026A, 0x0294, 0x026B, 0xA23F, 0x026C, 0x0294,
620 0x026D, 0xA23F, 0x026E, 0x0294, 0x026F, 0xA23F, 0x0270, 0x0294,
621 0x02F5, 0x0048, 0xBE09, 0x0E00, 0xBE1E, 0x0FA0, 0xBE14, 0x8448,
622 0xBE15, 0x1007, 0xBE4A, 0xA284, 0xC454, 0x3F0B, 0xC474, 0x3F0B,
623 0xBE48, 0x3672, 0xBE4B, 0x17A7, 0xBE4C, 0x0B15, 0xBE52, 0x0EDD,
624 0xBE49, 0x8C00, 0xBE5B, 0x785C, 0xBE5C, 0x785C, 0xBE5D, 0x785C,
625 0xBE61, 0x368A, 0xBE63, 0x9B84, 0xC456, 0xCC13, 0xC476, 0xCC13,
626 0xBE65, 0x307D, 0xBE6D, 0x0005, 0xBE6E, 0xE120, 0xBE2E, 0x7BAF,
627};
628
629/* This v1 init sequence is from Belkin F5D8235 U-Boot release */
630static const u16 rtl8366rb_init_jam_ver_1[] = {
631 0x0000, 0x0830, 0x0001, 0x8000, 0x0400, 0x8130, 0xBE78, 0x3C3C,
632 0x0431, 0x5432, 0xBE37, 0x0CE4, 0x02FA, 0xFFDF, 0x02FB, 0xFFE0,
633 0xC44C, 0x1585, 0xC44C, 0x1185, 0xC44C, 0x1585, 0xC46C, 0x1585,
634 0xC46C, 0x1185, 0xC46C, 0x1585, 0xC451, 0x2135, 0xC471, 0x2135,
635 0xBE10, 0x8140, 0xBE15, 0x0007, 0xBE6E, 0xE120, 0xBE69, 0xD20F,
636 0xBE6B, 0x0320, 0xBE24, 0xB000, 0xBE23, 0xFF51, 0xBE22, 0xDF20,
637 0xBE21, 0x0140, 0xBE20, 0x00BB, 0xBE24, 0xB800, 0xBE24, 0x0000,
638 0xBE24, 0x7000, 0xBE23, 0xFF51, 0xBE22, 0xDF60, 0xBE21, 0x0140,
639 0xBE20, 0x0077, 0xBE24, 0x7800, 0xBE24, 0x0000, 0xBE2E, 0x7B7A,
640 0xBE36, 0x0CE4, 0x02F5, 0x0048, 0xBE77, 0x2940, 0x000A, 0x83E0,
641 0xBE79, 0x3C3C, 0xBE00, 0x1340,
642};
643
644/* This v2 init sequence is from Belkin F5D8235 U-Boot release */
645static const u16 rtl8366rb_init_jam_ver_2[] = {
646 0x0450, 0x0000, 0x0400, 0x8130, 0x000A, 0x83ED, 0x0431, 0x5432,
647 0xC44F, 0x6250, 0xC46F, 0x6250, 0xC456, 0x0C14, 0xC476, 0x0C14,
648 0xC44C, 0x1C85, 0xC44C, 0x1885, 0xC44C, 0x1C85, 0xC46C, 0x1C85,
649 0xC46C, 0x1885, 0xC46C, 0x1C85, 0xC44C, 0x0885, 0xC44C, 0x0881,
650 0xC44C, 0x0885, 0xC46C, 0x0885, 0xC46C, 0x0881, 0xC46C, 0x0885,
651 0xBE2E, 0x7BA7, 0xBE36, 0x1000, 0xBE37, 0x1000, 0x8000, 0x0001,
652 0xBE69, 0xD50F, 0x8000, 0x0000, 0xBE69, 0xD50F, 0xBE6E, 0x0320,
653 0xBE77, 0x2940, 0xBE78, 0x3C3C, 0xBE79, 0x3C3C, 0xBE6E, 0xE120,
654 0x8000, 0x0001, 0xBE15, 0x1007, 0x8000, 0x0000, 0xBE15, 0x1007,
655 0xBE14, 0x0448, 0xBE1E, 0x00A0, 0xBE10, 0x8160, 0xBE10, 0x8140,
656 0xBE00, 0x1340, 0x0F51, 0x0010,
657};
658
659/* Appears in a DDWRT code dump */
660static const u16 rtl8366rb_init_jam_ver_3[] = {
661 0x0000, 0x0830, 0x0400, 0x8130, 0x000A, 0x83ED, 0x0431, 0x5432,
662 0x0F51, 0x0017, 0x02F5, 0x0048, 0x02FA, 0xFFDF, 0x02FB, 0xFFE0,
663 0xC456, 0x0C14, 0xC476, 0x0C14, 0xC454, 0x3F8B, 0xC474, 0x3F8B,
664 0xC450, 0x2071, 0xC470, 0x2071, 0xC451, 0x226B, 0xC471, 0x226B,
665 0xC452, 0xA293, 0xC472, 0xA293, 0xC44C, 0x1585, 0xC44C, 0x1185,
666 0xC44C, 0x1585, 0xC46C, 0x1585, 0xC46C, 0x1185, 0xC46C, 0x1585,
667 0xC44C, 0x0185, 0xC44C, 0x0181, 0xC44C, 0x0185, 0xC46C, 0x0185,
668 0xC46C, 0x0181, 0xC46C, 0x0185, 0xBE24, 0xB000, 0xBE23, 0xFF51,
669 0xBE22, 0xDF20, 0xBE21, 0x0140, 0xBE20, 0x00BB, 0xBE24, 0xB800,
670 0xBE24, 0x0000, 0xBE24, 0x7000, 0xBE23, 0xFF51, 0xBE22, 0xDF60,
671 0xBE21, 0x0140, 0xBE20, 0x0077, 0xBE24, 0x7800, 0xBE24, 0x0000,
672 0xBE2E, 0x7BA7, 0xBE36, 0x1000, 0xBE37, 0x1000, 0x8000, 0x0001,
673 0xBE69, 0xD50F, 0x8000, 0x0000, 0xBE69, 0xD50F, 0xBE6B, 0x0320,
674 0xBE77, 0x2800, 0xBE78, 0x3C3C, 0xBE79, 0x3C3C, 0xBE6E, 0xE120,
675 0x8000, 0x0001, 0xBE10, 0x8140, 0x8000, 0x0000, 0xBE10, 0x8140,
676 0xBE15, 0x1007, 0xBE14, 0x0448, 0xBE1E, 0x00A0, 0xBE10, 0x8160,
677 0xBE10, 0x8140, 0xBE00, 0x1340, 0x0450, 0x0000, 0x0401, 0x0000,
678};
679
680/* Belkin F5D8235 v1, "belkin,f5d8235-v1" */
681static const u16 rtl8366rb_init_jam_f5d8235[] = {
682 0x0242, 0x02BF, 0x0245, 0x02BF, 0x0248, 0x02BF, 0x024B, 0x02BF,
683 0x024E, 0x02BF, 0x0251, 0x02BF, 0x0254, 0x0A3F, 0x0256, 0x0A3F,
684 0x0258, 0x0A3F, 0x025A, 0x0A3F, 0x025C, 0x0A3F, 0x025E, 0x0A3F,
685 0x0263, 0x007C, 0x0100, 0x0004, 0xBE5B, 0x3500, 0x800E, 0x200F,
686 0xBE1D, 0x0F00, 0x8001, 0x5011, 0x800A, 0xA2F4, 0x800B, 0x17A3,
687 0xBE4B, 0x17A3, 0xBE41, 0x5011, 0xBE17, 0x2100, 0x8000, 0x8304,
688 0xBE40, 0x8304, 0xBE4A, 0xA2F4, 0x800C, 0xA8D5, 0x8014, 0x5500,
689 0x8015, 0x0004, 0xBE4C, 0xA8D5, 0xBE59, 0x0008, 0xBE09, 0x0E00,
690 0xBE36, 0x1036, 0xBE37, 0x1036, 0x800D, 0x00FF, 0xBE4D, 0x00FF,
691};
692
693/* DGN3500, "netgear,dgn3500", "netgear,dgn3500b" */
694static const u16 rtl8366rb_init_jam_dgn3500[] = {
695 0x0000, 0x0830, 0x0400, 0x8130, 0x000A, 0x83ED, 0x0F51, 0x0017,
696 0x02F5, 0x0048, 0x02FA, 0xFFDF, 0x02FB, 0xFFE0, 0x0450, 0x0000,
697 0x0401, 0x0000, 0x0431, 0x0960,
698};
699
700/* This jam table activates "green ethernet", which means low power mode
701 * and is claimed to detect the cable length and not use more power than
702 * necessary, and the ports should enter power saving mode 10 seconds after
703 * a cable is disconnected. Seems to always be the same.
704 */
705static const u16 rtl8366rb_green_jam[][2] = {
706 {0xBE78, 0x323C}, {0xBE77, 0x5000}, {0xBE2E, 0x7BA7},
707 {0xBE59, 0x3459}, {0xBE5A, 0x745A}, {0xBE5B, 0x785C},
708 {0xBE5C, 0x785C}, {0xBE6E, 0xE120}, {0xBE79, 0x323C},
709};
710
711static int rtl8366rb_setup(struct dsa_switch *ds)
712{
713 struct realtek_smi *smi = ds->priv;
714 const u16 *jam_table;
715 u32 chip_ver = 0;
716 u32 chip_id = 0;
717 int jam_size;
718 u32 val;
719 int ret;
720 int i;
721
722 ret = regmap_read(smi->map, RTL8366RB_CHIP_ID_REG, &chip_id);
723 if (ret) {
724 dev_err(smi->dev, "unable to read chip id\n");
725 return ret;
726 }
727
728 switch (chip_id) {
729 case RTL8366RB_CHIP_ID_8366:
730 break;
731 default:
732 dev_err(smi->dev, "unknown chip id (%04x)\n", chip_id);
733 return -ENODEV;
734 }
735
736 ret = regmap_read(smi->map, RTL8366RB_CHIP_VERSION_CTRL_REG,
737 &chip_ver);
738 if (ret) {
739 dev_err(smi->dev, "unable to read chip version\n");
740 return ret;
741 }
742
743 dev_info(smi->dev, "RTL%04x ver %u chip found\n",
744 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
745
746 /* Do the init dance using the right jam table */
747 switch (chip_ver) {
748 case 0:
749 jam_table = rtl8366rb_init_jam_ver_0;
750 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_0);
751 break;
752 case 1:
753 jam_table = rtl8366rb_init_jam_ver_1;
754 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_1);
755 break;
756 case 2:
757 jam_table = rtl8366rb_init_jam_ver_2;
758 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_2);
759 break;
760 default:
761 jam_table = rtl8366rb_init_jam_ver_3;
762 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_3);
763 break;
764 }
765
766 /* Special jam tables for special routers
767 * TODO: are these necessary? Maintainers, please test
768 * without them, using just the off-the-shelf tables.
769 */
770 if (of_machine_is_compatible("belkin,f5d8235-v1")) {
771 jam_table = rtl8366rb_init_jam_f5d8235;
772 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_f5d8235);
773 }
774 if (of_machine_is_compatible("netgear,dgn3500") ||
775 of_machine_is_compatible("netgear,dgn3500b")) {
776 jam_table = rtl8366rb_init_jam_dgn3500;
777 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_dgn3500);
778 }
779
780 i = 0;
781 while (i < jam_size) {
782 if ((jam_table[i] & 0xBE00) == 0xBE00) {
783 ret = regmap_read(smi->map,
784 RTL8366RB_PHY_ACCESS_BUSY_REG,
785 &val);
786 if (ret)
787 return ret;
788 if (!(val & RTL8366RB_PHY_INT_BUSY)) {
789 ret = regmap_write(smi->map,
790 RTL8366RB_PHY_ACCESS_CTRL_REG,
791 RTL8366RB_PHY_CTRL_WRITE);
792 if (ret)
793 return ret;
794 }
795 }
796 dev_dbg(smi->dev, "jam %04x into register %04x\n",
797 jam_table[i + 1],
798 jam_table[i]);
799 ret = regmap_write(smi->map,
800 jam_table[i],
801 jam_table[i + 1]);
802 if (ret)
803 return ret;
804 i += 2;
805 }
806
807 /* Set up the "green ethernet" feature */
808 i = 0;
809 while (i < ARRAY_SIZE(rtl8366rb_green_jam)) {
810 ret = regmap_read(smi->map, RTL8366RB_PHY_ACCESS_BUSY_REG,
811 &val);
812 if (ret)
813 return ret;
814 if (!(val & RTL8366RB_PHY_INT_BUSY)) {
815 ret = regmap_write(smi->map,
816 RTL8366RB_PHY_ACCESS_CTRL_REG,
817 RTL8366RB_PHY_CTRL_WRITE);
818 if (ret)
819 return ret;
820 ret = regmap_write(smi->map,
821 rtl8366rb_green_jam[i][0],
822 rtl8366rb_green_jam[i][1]);
823 if (ret)
824 return ret;
825 i++;
826 }
827 }
828 ret = regmap_write(smi->map,
829 RTL8366RB_GREEN_FEATURE_REG,
830 (chip_ver == 1) ? 0x0007 : 0x0003);
831 if (ret)
832 return ret;
833
834 /* Vendor driver sets 0x240 in registers 0xc and 0xd (undocumented) */
835 ret = regmap_write(smi->map, 0x0c, 0x240);
836 if (ret)
837 return ret;
838 ret = regmap_write(smi->map, 0x0d, 0x240);
839 if (ret)
840 return ret;
841
842 /* Set some random MAC address */
843 ret = rtl8366rb_set_addr(smi);
844 if (ret)
845 return ret;
846
847 /* Enable CPU port with custom DSA tag 8899.
848 *
849 * If you set RTL8368RB_CPU_NO_TAG (bit 15) in this registers
850 * the custom tag is turned off.
851 */
852 ret = regmap_update_bits(smi->map, RTL8368RB_CPU_CTRL_REG,
853 0xFFFF,
854 BIT(smi->cpu_port));
855 if (ret)
856 return ret;
857
858 /* Make sure we default-enable the fixed CPU port */
859 ret = regmap_update_bits(smi->map, RTL8366RB_PECR,
860 BIT(smi->cpu_port),
861 0);
862 if (ret)
863 return ret;
864
865 /* Set maximum packet length to 1536 bytes */
866 ret = regmap_update_bits(smi->map, RTL8366RB_SGCR,
867 RTL8366RB_SGCR_MAX_LENGTH_MASK,
868 RTL8366RB_SGCR_MAX_LENGTH_1536);
869 if (ret)
870 return ret;
871
872 /* Enable learning for all ports */
873 ret = regmap_write(smi->map, RTL8366RB_SSCR0, 0);
874 if (ret)
875 return ret;
876
877 /* Enable auto ageing for all ports */
878 ret = regmap_write(smi->map, RTL8366RB_SSCR1, 0);
879 if (ret)
880 return ret;
881
882 /* Port 4 setup: this enables Port 4, usually the WAN port,
883 * common PHY IO mode is apparently mode 0, and this is not what
884 * the port is initialized to. There is no explanation of the
885 * IO modes in the Realtek source code, if your WAN port is
886 * connected to something exotic such as fiber, then this might
887 * be worth experimenting with.
888 */
889 ret = regmap_update_bits(smi->map, RTL8366RB_PMC0,
890 RTL8366RB_PMC0_P4_IOMODE_MASK,
891 0 << RTL8366RB_PMC0_P4_IOMODE_SHIFT);
892 if (ret)
893 return ret;
894
895 /* Discard VLAN tagged packets if the port is not a member of
896 * the VLAN with which the packets is associated.
897 */
898 ret = regmap_write(smi->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
899 RTL8366RB_PORT_ALL);
900 if (ret)
901 return ret;
902
903 /* Don't drop packets whose DA has not been learned */
904 ret = regmap_update_bits(smi->map, RTL8366RB_SSCR2,
905 RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
906 if (ret)
907 return ret;
908
909 /* Set blinking, TODO: make this configurable */
910 ret = regmap_update_bits(smi->map, RTL8366RB_LED_BLINKRATE_REG,
911 RTL8366RB_LED_BLINKRATE_MASK,
912 RTL8366RB_LED_BLINKRATE_56MS);
913 if (ret)
914 return ret;
915
916 /* Set up LED activity:
917 * Each port has 4 LEDs, we configure all ports to the same
918 * behaviour (no individual config) but we can set up each
919 * LED separately.
920 */
921 if (smi->leds_disabled) {
922 /* Turn everything off */
923 regmap_update_bits(smi->map,
924 RTL8366RB_LED_0_1_CTRL_REG,
925 0x0FFF, 0);
926 regmap_update_bits(smi->map,
927 RTL8366RB_LED_2_3_CTRL_REG,
928 0x0FFF, 0);
929 regmap_update_bits(smi->map,
930 RTL8366RB_INTERRUPT_CONTROL_REG,
931 RTL8366RB_P4_RGMII_LED,
932 0);
933 val = RTL8366RB_LED_OFF;
934 } else {
935 /* TODO: make this configurable per LED */
936 val = RTL8366RB_LED_FORCE;
937 }
938 for (i = 0; i < 4; i++) {
939 ret = regmap_update_bits(smi->map,
940 RTL8366RB_LED_CTRL_REG,
941 0xf << (i * 4),
942 val << (i * 4));
943 if (ret)
944 return ret;
945 }
946
947 ret = rtl8366_init_vlan(smi);
948 if (ret)
949 return ret;
950
951 ret = rtl8366rb_setup_cascaded_irq(smi);
952 if (ret)
953 dev_info(smi->dev, "no interrupt support\n");
954
955 ret = realtek_smi_setup_mdio(smi);
956 if (ret) {
957 dev_info(smi->dev, "could not set up MDIO bus\n");
958 return -ENODEV;
959 }
960
961 return 0;
962}
963
964static enum dsa_tag_protocol rtl8366_get_tag_protocol(struct dsa_switch *ds,
965 int port,
966 enum dsa_tag_protocol mp)
967{
968 /* This switch uses the 4 byte protocol A Realtek DSA tag */
969 return DSA_TAG_PROTO_RTL4_A;
970}
971
972static void rtl8366rb_adjust_link(struct dsa_switch *ds, int port,
973 struct phy_device *phydev)
974{
975 struct realtek_smi *smi = ds->priv;
976 int ret;
977
978 if (port != smi->cpu_port)
979 return;
980
981 dev_info(smi->dev, "adjust link on CPU port (%d)\n", port);
982
983 /* Force the fixed CPU port into 1Gbit mode, no autonegotiation */
984 ret = regmap_update_bits(smi->map, RTL8366RB_MAC_FORCE_CTRL_REG,
985 BIT(port), BIT(port));
986 if (ret)
987 return;
988
989 ret = regmap_update_bits(smi->map, RTL8366RB_PAACR2,
990 0xFF00U,
991 RTL8366RB_PAACR_CPU_PORT << 8);
992 if (ret)
993 return;
994
995 /* Enable the CPU port */
996 ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port),
997 0);
998 if (ret)
999 return;
1000}
1001
1002static void rb8366rb_set_port_led(struct realtek_smi *smi,
1003 int port, bool enable)
1004{
1005 u16 val = enable ? 0x3f : 0;
1006 int ret;
1007
1008 if (smi->leds_disabled)
1009 return;
1010
1011 switch (port) {
1012 case 0:
1013 ret = regmap_update_bits(smi->map,
1014 RTL8366RB_LED_0_1_CTRL_REG,
1015 0x3F, val);
1016 break;
1017 case 1:
1018 ret = regmap_update_bits(smi->map,
1019 RTL8366RB_LED_0_1_CTRL_REG,
1020 0x3F << RTL8366RB_LED_1_OFFSET,
1021 val << RTL8366RB_LED_1_OFFSET);
1022 break;
1023 case 2:
1024 ret = regmap_update_bits(smi->map,
1025 RTL8366RB_LED_2_3_CTRL_REG,
1026 0x3F, val);
1027 break;
1028 case 3:
1029 ret = regmap_update_bits(smi->map,
1030 RTL8366RB_LED_2_3_CTRL_REG,
1031 0x3F << RTL8366RB_LED_3_OFFSET,
1032 val << RTL8366RB_LED_3_OFFSET);
1033 break;
1034 case 4:
1035 ret = regmap_update_bits(smi->map,
1036 RTL8366RB_INTERRUPT_CONTROL_REG,
1037 RTL8366RB_P4_RGMII_LED,
1038 enable ? RTL8366RB_P4_RGMII_LED : 0);
1039 break;
1040 default:
1041 dev_err(smi->dev, "no LED for port %d\n", port);
1042 return;
1043 }
1044 if (ret)
1045 dev_err(smi->dev, "error updating LED on port %d\n", port);
1046}
1047
1048static int
1049rtl8366rb_port_enable(struct dsa_switch *ds, int port,
1050 struct phy_device *phy)
1051{
1052 struct realtek_smi *smi = ds->priv;
1053 int ret;
1054
1055 dev_dbg(smi->dev, "enable port %d\n", port);
1056 ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port),
1057 0);
1058 if (ret)
1059 return ret;
1060
1061 rb8366rb_set_port_led(smi, port, true);
1062 return 0;
1063}
1064
1065static void
1066rtl8366rb_port_disable(struct dsa_switch *ds, int port)
1067{
1068 struct realtek_smi *smi = ds->priv;
1069 int ret;
1070
1071 dev_dbg(smi->dev, "disable port %d\n", port);
1072 ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port),
1073 BIT(port));
1074 if (ret)
1075 return;
1076
1077 rb8366rb_set_port_led(smi, port, false);
1078}
1079
1080static int rtl8366rb_get_vlan_4k(struct realtek_smi *smi, u32 vid,
1081 struct rtl8366_vlan_4k *vlan4k)
1082{
1083 u32 data[3];
1084 int ret;
1085 int i;
1086
1087 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1088
1089 if (vid >= RTL8366RB_NUM_VIDS)
1090 return -EINVAL;
1091
1092 /* write VID */
1093 ret = regmap_write(smi->map, RTL8366RB_VLAN_TABLE_WRITE_BASE,
1094 vid & RTL8366RB_VLAN_VID_MASK);
1095 if (ret)
1096 return ret;
1097
1098 /* write table access control word */
1099 ret = regmap_write(smi->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1100 RTL8366RB_TABLE_VLAN_READ_CTRL);
1101 if (ret)
1102 return ret;
1103
1104 for (i = 0; i < 3; i++) {
1105 ret = regmap_read(smi->map,
1106 RTL8366RB_VLAN_TABLE_READ_BASE + i,
1107 &data[i]);
1108 if (ret)
1109 return ret;
1110 }
1111
1112 vlan4k->vid = vid;
1113 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1114 RTL8366RB_VLAN_UNTAG_MASK;
1115 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1116 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1117
1118 return 0;
1119}
1120
1121static int rtl8366rb_set_vlan_4k(struct realtek_smi *smi,
1122 const struct rtl8366_vlan_4k *vlan4k)
1123{
1124 u32 data[3];
1125 int ret;
1126 int i;
1127
1128 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
1129 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
1130 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1131 vlan4k->fid > RTL8366RB_FIDMAX)
1132 return -EINVAL;
1133
1134 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
1135 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
1136 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1137 RTL8366RB_VLAN_UNTAG_SHIFT);
1138 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
1139
1140 for (i = 0; i < 3; i++) {
1141 ret = regmap_write(smi->map,
1142 RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
1143 data[i]);
1144 if (ret)
1145 return ret;
1146 }
1147
1148 /* write table access control word */
1149 ret = regmap_write(smi->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1150 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
1151
1152 return ret;
1153}
1154
1155static int rtl8366rb_get_vlan_mc(struct realtek_smi *smi, u32 index,
1156 struct rtl8366_vlan_mc *vlanmc)
1157{
1158 u32 data[3];
1159 int ret;
1160 int i;
1161
1162 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1163
1164 if (index >= RTL8366RB_NUM_VLANS)
1165 return -EINVAL;
1166
1167 for (i = 0; i < 3; i++) {
1168 ret = regmap_read(smi->map,
1169 RTL8366RB_VLAN_MC_BASE(index) + i,
1170 &data[i]);
1171 if (ret)
1172 return ret;
1173 }
1174
1175 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
1176 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
1177 RTL8366RB_VLAN_PRIORITY_MASK;
1178 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1179 RTL8366RB_VLAN_UNTAG_MASK;
1180 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1181 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1182
1183 return 0;
1184}
1185
1186static int rtl8366rb_set_vlan_mc(struct realtek_smi *smi, u32 index,
1187 const struct rtl8366_vlan_mc *vlanmc)
1188{
1189 u32 data[3];
1190 int ret;
1191 int i;
1192
1193 if (index >= RTL8366RB_NUM_VLANS ||
1194 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
1195 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
1196 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
1197 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1198 vlanmc->fid > RTL8366RB_FIDMAX)
1199 return -EINVAL;
1200
1201 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
1202 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
1203 RTL8366RB_VLAN_PRIORITY_SHIFT);
1204 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
1205 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1206 RTL8366RB_VLAN_UNTAG_SHIFT);
1207 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
1208
1209 for (i = 0; i < 3; i++) {
1210 ret = regmap_write(smi->map,
1211 RTL8366RB_VLAN_MC_BASE(index) + i,
1212 data[i]);
1213 if (ret)
1214 return ret;
1215 }
1216
1217 return 0;
1218}
1219
1220static int rtl8366rb_get_mc_index(struct realtek_smi *smi, int port, int *val)
1221{
1222 u32 data;
1223 int ret;
1224
1225 if (port >= smi->num_ports)
1226 return -EINVAL;
1227
1228 ret = regmap_read(smi->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1229 &data);
1230 if (ret)
1231 return ret;
1232
1233 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
1234 RTL8366RB_PORT_VLAN_CTRL_MASK;
1235
1236 return 0;
1237}
1238
1239static int rtl8366rb_set_mc_index(struct realtek_smi *smi, int port, int index)
1240{
1241 if (port >= smi->num_ports || index >= RTL8366RB_NUM_VLANS)
1242 return -EINVAL;
1243
1244 return regmap_update_bits(smi->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1245 RTL8366RB_PORT_VLAN_CTRL_MASK <<
1246 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
1247 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
1248 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
1249}
1250
1251static bool rtl8366rb_is_vlan_valid(struct realtek_smi *smi, unsigned int vlan)
1252{
1253 unsigned int max = RTL8366RB_NUM_VLANS;
1254
1255 if (smi->vlan4k_enabled)
1256 max = RTL8366RB_NUM_VIDS - 1;
1257
1258 if (vlan == 0 || vlan >= max)
1259 return false;
1260
1261 return true;
1262}
1263
1264static int rtl8366rb_enable_vlan(struct realtek_smi *smi, bool enable)
1265{
1266 dev_dbg(smi->dev, "%s VLAN\n", enable ? "enable" : "disable");
1267 return regmap_update_bits(smi->map,
1268 RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
1269 enable ? RTL8366RB_SGCR_EN_VLAN : 0);
1270}
1271
1272static int rtl8366rb_enable_vlan4k(struct realtek_smi *smi, bool enable)
1273{
1274 dev_dbg(smi->dev, "%s VLAN 4k\n", enable ? "enable" : "disable");
1275 return regmap_update_bits(smi->map, RTL8366RB_SGCR,
1276 RTL8366RB_SGCR_EN_VLAN_4KTB,
1277 enable ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
1278}
1279
1280static int rtl8366rb_phy_read(struct realtek_smi *smi, int phy, int regnum)
1281{
1282 u32 val;
1283 u32 reg;
1284 int ret;
1285
1286 if (phy > RTL8366RB_PHY_NO_MAX)
1287 return -EINVAL;
1288
1289 ret = regmap_write(smi->map, RTL8366RB_PHY_ACCESS_CTRL_REG,
1290 RTL8366RB_PHY_CTRL_READ);
1291 if (ret)
1292 return ret;
1293
1294 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1295
1296 ret = regmap_write(smi->map, reg, 0);
1297 if (ret) {
1298 dev_err(smi->dev,
1299 "failed to write PHY%d reg %04x @ %04x, ret %d\n",
1300 phy, regnum, reg, ret);
1301 return ret;
1302 }
1303
1304 ret = regmap_read(smi->map, RTL8366RB_PHY_ACCESS_DATA_REG, &val);
1305 if (ret)
1306 return ret;
1307
1308 dev_dbg(smi->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n",
1309 phy, regnum, reg, val);
1310
1311 return val;
1312}
1313
1314static int rtl8366rb_phy_write(struct realtek_smi *smi, int phy, int regnum,
1315 u16 val)
1316{
1317 u32 reg;
1318 int ret;
1319
1320 if (phy > RTL8366RB_PHY_NO_MAX)
1321 return -EINVAL;
1322
1323 ret = regmap_write(smi->map, RTL8366RB_PHY_ACCESS_CTRL_REG,
1324 RTL8366RB_PHY_CTRL_WRITE);
1325 if (ret)
1326 return ret;
1327
1328 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1329
1330 dev_dbg(smi->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n",
1331 phy, regnum, reg, val);
1332
1333 ret = regmap_write(smi->map, reg, val);
1334 if (ret)
1335 return ret;
1336
1337 return 0;
1338}
1339
1340static int rtl8366rb_reset_chip(struct realtek_smi *smi)
1341{
1342 int timeout = 10;
1343 u32 val;
1344 int ret;
1345
1346 realtek_smi_write_reg_noack(smi, RTL8366RB_RESET_CTRL_REG,
1347 RTL8366RB_CHIP_CTRL_RESET_HW);
1348 do {
1349 usleep_range(20000, 25000);
1350 ret = regmap_read(smi->map, RTL8366RB_RESET_CTRL_REG, &val);
1351 if (ret)
1352 return ret;
1353
1354 if (!(val & RTL8366RB_CHIP_CTRL_RESET_HW))
1355 break;
1356 } while (--timeout);
1357
1358 if (!timeout) {
1359 dev_err(smi->dev, "timeout waiting for the switch to reset\n");
1360 return -EIO;
1361 }
1362
1363 return 0;
1364}
1365
1366static int rtl8366rb_detect(struct realtek_smi *smi)
1367{
1368 struct device *dev = smi->dev;
1369 int ret;
1370 u32 val;
1371
1372 /* Detect device */
1373 ret = regmap_read(smi->map, 0x5c, &val);
1374 if (ret) {
1375 dev_err(dev, "can't get chip ID (%d)\n", ret);
1376 return ret;
1377 }
1378
1379 switch (val) {
1380 case 0x6027:
1381 dev_info(dev, "found an RTL8366S switch\n");
1382 dev_err(dev, "this switch is not yet supported, submit patches!\n");
1383 return -ENODEV;
1384 case 0x5937:
1385 dev_info(dev, "found an RTL8366RB switch\n");
1386 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1387 smi->num_ports = RTL8366RB_NUM_PORTS;
1388 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1389 smi->mib_counters = rtl8366rb_mib_counters;
1390 smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1391 break;
1392 default:
1393 dev_info(dev, "found an Unknown Realtek switch (id=0x%04x)\n",
1394 val);
1395 break;
1396 }
1397
1398 ret = rtl8366rb_reset_chip(smi);
1399 if (ret)
1400 return ret;
1401
1402 return 0;
1403}
1404
1405static const struct dsa_switch_ops rtl8366rb_switch_ops = {
1406 .get_tag_protocol = rtl8366_get_tag_protocol,
1407 .setup = rtl8366rb_setup,
1408 .adjust_link = rtl8366rb_adjust_link,
1409 .get_strings = rtl8366_get_strings,
1410 .get_ethtool_stats = rtl8366_get_ethtool_stats,
1411 .get_sset_count = rtl8366_get_sset_count,
1412 .port_vlan_filtering = rtl8366_vlan_filtering,
1413 .port_vlan_prepare = rtl8366_vlan_prepare,
1414 .port_vlan_add = rtl8366_vlan_add,
1415 .port_vlan_del = rtl8366_vlan_del,
1416 .port_enable = rtl8366rb_port_enable,
1417 .port_disable = rtl8366rb_port_disable,
1418};
1419
1420static const struct realtek_smi_ops rtl8366rb_smi_ops = {
1421 .detect = rtl8366rb_detect,
1422 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1423 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1424 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1425 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1426 .get_mc_index = rtl8366rb_get_mc_index,
1427 .set_mc_index = rtl8366rb_set_mc_index,
1428 .get_mib_counter = rtl8366rb_get_mib_counter,
1429 .is_vlan_valid = rtl8366rb_is_vlan_valid,
1430 .enable_vlan = rtl8366rb_enable_vlan,
1431 .enable_vlan4k = rtl8366rb_enable_vlan4k,
1432 .phy_read = rtl8366rb_phy_read,
1433 .phy_write = rtl8366rb_phy_write,
1434};
1435
1436const struct realtek_smi_variant rtl8366rb_variant = {
1437 .ds_ops = &rtl8366rb_switch_ops,
1438 .ops = &rtl8366rb_smi_ops,
1439 .clk_delay = 10,
1440 .cmd_read = 0xa9,
1441 .cmd_write = 0xa8,
1442};
1443EXPORT_SYMBOL_GPL(rtl8366rb_variant);