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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 */
11#ifndef _ASM_PROCESSOR_H
12#define _ASM_PROCESSOR_H
13
14#include <linux/cpumask.h>
15#include <linux/threads.h>
16
17#include <asm/cachectl.h>
18#include <asm/cpu.h>
19#include <asm/cpu-info.h>
20#include <asm/mipsregs.h>
21#include <asm/prefetch.h>
22
23/*
24 * Return current * instruction pointer ("program counter").
25 */
26#define current_text_addr() ({ __label__ _l; _l: &&_l;})
27
28/*
29 * System setup and hardware flags..
30 */
31
32extern unsigned int vced_count, vcei_count;
33
34/*
35 * MIPS does have an arch_pick_mmap_layout()
36 */
37#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
38
39/*
40 * A special page (the vdso) is mapped into all processes at the very
41 * top of the virtual memory space.
42 */
43#define SPECIAL_PAGES_SIZE PAGE_SIZE
44
45#ifdef CONFIG_32BIT
46#ifdef CONFIG_KVM_GUEST
47/* User space process size is limited to 1GB in KVM Guest Mode */
48#define TASK_SIZE 0x3fff8000UL
49#else
50/*
51 * User space process size: 2GB. This is hardcoded into a few places,
52 * so don't change it unless you know what you are doing.
53 */
54#define TASK_SIZE 0x7fff8000UL
55#endif
56
57#ifdef __KERNEL__
58#define STACK_TOP_MAX TASK_SIZE
59#endif
60
61#define TASK_IS_32BIT_ADDR 1
62
63#endif
64
65#ifdef CONFIG_64BIT
66/*
67 * User space process size: 1TB. This is hardcoded into a few places,
68 * so don't change it unless you know what you are doing. TASK_SIZE
69 * is limited to 1TB by the R4000 architecture; R10000 and better can
70 * support 16TB; the architectural reserve for future expansion is
71 * 8192EB ...
72 */
73#define TASK_SIZE32 0x7fff8000UL
74#define TASK_SIZE64 0x10000000000UL
75#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
76
77#ifdef __KERNEL__
78#define STACK_TOP_MAX TASK_SIZE64
79#endif
80
81
82#define TASK_SIZE_OF(tsk) \
83 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
84
85#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
86
87#endif
88
89#define STACK_TOP ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
90
91/*
92 * This decides where the kernel will search for a free chunk of vm
93 * space during mmap's.
94 */
95#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
96
97
98#define NUM_FPU_REGS 32
99
100#ifdef CONFIG_CPU_HAS_MSA
101# define FPU_REG_WIDTH 128
102#else
103# define FPU_REG_WIDTH 64
104#endif
105
106union fpureg {
107 __u32 val32[FPU_REG_WIDTH / 32];
108 __u64 val64[FPU_REG_WIDTH / 64];
109};
110
111#ifdef CONFIG_CPU_LITTLE_ENDIAN
112# define FPR_IDX(width, idx) (idx)
113#else
114# define FPR_IDX(width, idx) ((FPU_REG_WIDTH / (width)) - 1 - (idx))
115#endif
116
117#define BUILD_FPR_ACCESS(width) \
118static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx) \
119{ \
120 return fpr->val##width[FPR_IDX(width, idx)]; \
121} \
122 \
123static inline void set_fpr##width(union fpureg *fpr, unsigned idx, \
124 u##width val) \
125{ \
126 fpr->val##width[FPR_IDX(width, idx)] = val; \
127}
128
129BUILD_FPR_ACCESS(32)
130BUILD_FPR_ACCESS(64)
131
132/*
133 * It would be nice to add some more fields for emulator statistics,
134 * the additional information is private to the FPU emulator for now.
135 * See arch/mips/include/asm/fpu_emulator.h.
136 */
137
138struct mips_fpu_struct {
139 union fpureg fpr[NUM_FPU_REGS];
140 unsigned int fcr31;
141 unsigned int msacsr;
142};
143
144#define NUM_DSP_REGS 6
145
146typedef __u32 dspreg_t;
147
148struct mips_dsp_state {
149 dspreg_t dspr[NUM_DSP_REGS];
150 unsigned int dspcontrol;
151};
152
153#define INIT_CPUMASK { \
154 {0,} \
155}
156
157struct mips3264_watch_reg_state {
158 /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
159 64 bit kernel. We use unsigned long as it has the same
160 property. */
161 unsigned long watchlo[NUM_WATCH_REGS];
162 /* Only the mask and IRW bits from watchhi. */
163 u16 watchhi[NUM_WATCH_REGS];
164};
165
166union mips_watch_reg_state {
167 struct mips3264_watch_reg_state mips3264;
168};
169
170#if defined(CONFIG_CPU_CAVIUM_OCTEON)
171
172struct octeon_cop2_state {
173 /* DMFC2 rt, 0x0201 */
174 unsigned long cop2_crc_iv;
175 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
176 unsigned long cop2_crc_length;
177 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
178 unsigned long cop2_crc_poly;
179 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
180 unsigned long cop2_llm_dat[2];
181 /* DMFC2 rt, 0x0084 */
182 unsigned long cop2_3des_iv;
183 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
184 unsigned long cop2_3des_key[3];
185 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
186 unsigned long cop2_3des_result;
187 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
188 unsigned long cop2_aes_inp0;
189 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
190 unsigned long cop2_aes_iv[2];
191 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
192 * rt, 0x0107 */
193 unsigned long cop2_aes_key[4];
194 /* DMFC2 rt, 0x0110 */
195 unsigned long cop2_aes_keylen;
196 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
197 unsigned long cop2_aes_result[2];
198 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
199 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
200 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
201 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
202 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
203 unsigned long cop2_hsh_datw[15];
204 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
205 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
206 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
207 unsigned long cop2_hsh_ivw[8];
208 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
209 unsigned long cop2_gfm_mult[2];
210 /* DMFC2 rt, 0x025E - Pass2 */
211 unsigned long cop2_gfm_poly;
212 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
213 unsigned long cop2_gfm_result[2];
214};
215#define COP2_INIT \
216 .cp2 = {0,},
217
218struct octeon_cvmseg_state {
219 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
220 [cpu_dcache_line_size() / sizeof(unsigned long)];
221};
222
223#elif defined(CONFIG_CPU_XLP)
224struct nlm_cop2_state {
225 u64 rx[4];
226 u64 tx[4];
227 u32 tx_msg_status;
228 u32 rx_msg_status;
229};
230
231#define COP2_INIT \
232 .cp2 = {{0}, {0}, 0, 0},
233#else
234#define COP2_INIT
235#endif
236
237typedef struct {
238 unsigned long seg;
239} mm_segment_t;
240
241#define ARCH_MIN_TASKALIGN 8
242
243struct mips_abi;
244
245/*
246 * If you change thread_struct remember to change the #defines below too!
247 */
248struct thread_struct {
249 /* Saved main processor registers. */
250 unsigned long reg16;
251 unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
252 unsigned long reg29, reg30, reg31;
253
254 /* Saved cp0 stuff. */
255 unsigned long cp0_status;
256
257 /* Saved fpu/fpu emulator stuff. */
258 struct mips_fpu_struct fpu;
259#ifdef CONFIG_MIPS_MT_FPAFF
260 /* Emulated instruction count */
261 unsigned long emulated_fp;
262 /* Saved per-thread scheduler affinity mask */
263 cpumask_t user_cpus_allowed;
264#endif /* CONFIG_MIPS_MT_FPAFF */
265
266 /* Saved state of the DSP ASE, if available. */
267 struct mips_dsp_state dsp;
268
269 /* Saved watch register state, if available. */
270 union mips_watch_reg_state watch;
271
272 /* Other stuff associated with the thread. */
273 unsigned long cp0_badvaddr; /* Last user fault */
274 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
275 unsigned long error_code;
276#ifdef CONFIG_CPU_CAVIUM_OCTEON
277 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
278 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
279#endif
280#ifdef CONFIG_CPU_XLP
281 struct nlm_cop2_state cp2;
282#endif
283 struct mips_abi *abi;
284};
285
286#ifdef CONFIG_MIPS_MT_FPAFF
287#define FPAFF_INIT \
288 .emulated_fp = 0, \
289 .user_cpus_allowed = INIT_CPUMASK,
290#else
291#define FPAFF_INIT
292#endif /* CONFIG_MIPS_MT_FPAFF */
293
294#define INIT_THREAD { \
295 /* \
296 * Saved main processor registers \
297 */ \
298 .reg16 = 0, \
299 .reg17 = 0, \
300 .reg18 = 0, \
301 .reg19 = 0, \
302 .reg20 = 0, \
303 .reg21 = 0, \
304 .reg22 = 0, \
305 .reg23 = 0, \
306 .reg29 = 0, \
307 .reg30 = 0, \
308 .reg31 = 0, \
309 /* \
310 * Saved cp0 stuff \
311 */ \
312 .cp0_status = 0, \
313 /* \
314 * Saved FPU/FPU emulator stuff \
315 */ \
316 .fpu = { \
317 .fpr = {{{0,},},}, \
318 .fcr31 = 0, \
319 .msacsr = 0, \
320 }, \
321 /* \
322 * FPU affinity state (null if not FPAFF) \
323 */ \
324 FPAFF_INIT \
325 /* \
326 * Saved DSP stuff \
327 */ \
328 .dsp = { \
329 .dspr = {0, }, \
330 .dspcontrol = 0, \
331 }, \
332 /* \
333 * saved watch register stuff \
334 */ \
335 .watch = {{{0,},},}, \
336 /* \
337 * Other stuff associated with the process \
338 */ \
339 .cp0_badvaddr = 0, \
340 .cp0_baduaddr = 0, \
341 .error_code = 0, \
342 /* \
343 * Platform specific cop2 registers(null if no COP2) \
344 */ \
345 COP2_INIT \
346}
347
348struct task_struct;
349
350/* Free all resources held by a thread. */
351#define release_thread(thread) do { } while(0)
352
353extern unsigned long thread_saved_pc(struct task_struct *tsk);
354
355/*
356 * Do necessary setup to start up a newly executed thread.
357 */
358extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
359
360unsigned long get_wchan(struct task_struct *p);
361
362#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
363 THREAD_SIZE - 32 - sizeof(struct pt_regs))
364#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
365#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
366#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
367#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
368
369#define cpu_relax() barrier()
370
371/*
372 * Return_address is a replacement for __builtin_return_address(count)
373 * which on certain architectures cannot reasonably be implemented in GCC
374 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
375 * Note that __builtin_return_address(x>=1) is forbidden because GCC
376 * aborts compilation on some CPUs. It's simply not possible to unwind
377 * some CPU's stackframes.
378 *
379 * __builtin_return_address works only for non-leaf functions. We avoid the
380 * overhead of a function call by forcing the compiler to save the return
381 * address register on the stack.
382 */
383#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
384
385#ifdef CONFIG_CPU_HAS_PREFETCH
386
387#define ARCH_HAS_PREFETCH
388#define prefetch(x) __builtin_prefetch((x), 0, 1)
389
390#define ARCH_HAS_PREFETCHW
391#define prefetchw(x) __builtin_prefetch((x), 1, 1)
392
393/*
394 * See Documentation/scheduler/sched-arch.txt; prevents deadlock on SMP
395 * systems.
396 */
397#define __ARCH_WANT_UNLOCKED_CTXSW
398
399#endif
400
401#endif /* _ASM_PROCESSOR_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 */
11#ifndef _ASM_PROCESSOR_H
12#define _ASM_PROCESSOR_H
13
14#include <linux/atomic.h>
15#include <linux/cpumask.h>
16#include <linux/sizes.h>
17#include <linux/threads.h>
18
19#include <asm/cachectl.h>
20#include <asm/cpu.h>
21#include <asm/cpu-info.h>
22#include <asm/dsemul.h>
23#include <asm/mipsregs.h>
24#include <asm/prefetch.h>
25#include <asm/vdso/processor.h>
26
27/*
28 * System setup and hardware flags..
29 */
30
31extern unsigned int vced_count, vcei_count;
32
33#ifdef CONFIG_32BIT
34#ifdef CONFIG_KVM_GUEST
35/* User space process size is limited to 1GB in KVM Guest Mode */
36#define TASK_SIZE 0x3fff8000UL
37#else
38/*
39 * User space process size: 2GB. This is hardcoded into a few places,
40 * so don't change it unless you know what you are doing.
41 */
42#define TASK_SIZE 0x80000000UL
43#endif
44
45#define STACK_TOP_MAX TASK_SIZE
46
47#define TASK_IS_32BIT_ADDR 1
48
49#endif
50
51#ifdef CONFIG_64BIT
52/*
53 * User space process size: 1TB. This is hardcoded into a few places,
54 * so don't change it unless you know what you are doing. TASK_SIZE
55 * is limited to 1TB by the R4000 architecture; R10000 and better can
56 * support 16TB; the architectural reserve for future expansion is
57 * 8192EB ...
58 */
59#define TASK_SIZE32 0x7fff8000UL
60#ifdef CONFIG_MIPS_VA_BITS_48
61#define TASK_SIZE64 (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))
62#else
63#define TASK_SIZE64 0x10000000000UL
64#endif
65#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
66#define STACK_TOP_MAX TASK_SIZE64
67
68#define TASK_SIZE_OF(tsk) \
69 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
70
71#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
72
73#endif
74
75#define VDSO_RANDOMIZE_SIZE (TASK_IS_32BIT_ADDR ? SZ_1M : SZ_64M)
76
77extern unsigned long mips_stack_top(void);
78#define STACK_TOP mips_stack_top()
79
80/*
81 * This decides where the kernel will search for a free chunk of vm
82 * space during mmap's.
83 */
84#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
85
86
87#define NUM_FPU_REGS 32
88
89#ifdef CONFIG_CPU_HAS_MSA
90# define FPU_REG_WIDTH 128
91#else
92# define FPU_REG_WIDTH 64
93#endif
94
95union fpureg {
96 __u32 val32[FPU_REG_WIDTH / 32];
97 __u64 val64[FPU_REG_WIDTH / 64];
98};
99
100#ifdef CONFIG_CPU_LITTLE_ENDIAN
101# define FPR_IDX(width, idx) (idx)
102#else
103# define FPR_IDX(width, idx) ((idx) ^ ((64 / (width)) - 1))
104#endif
105
106#define BUILD_FPR_ACCESS(width) \
107static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx) \
108{ \
109 return fpr->val##width[FPR_IDX(width, idx)]; \
110} \
111 \
112static inline void set_fpr##width(union fpureg *fpr, unsigned idx, \
113 u##width val) \
114{ \
115 fpr->val##width[FPR_IDX(width, idx)] = val; \
116}
117
118BUILD_FPR_ACCESS(32)
119BUILD_FPR_ACCESS(64)
120
121/*
122 * It would be nice to add some more fields for emulator statistics,
123 * the additional information is private to the FPU emulator for now.
124 * See arch/mips/include/asm/fpu_emulator.h.
125 */
126
127struct mips_fpu_struct {
128 union fpureg fpr[NUM_FPU_REGS];
129 unsigned int fcr31;
130 unsigned int msacsr;
131};
132
133#define NUM_DSP_REGS 6
134
135typedef unsigned long dspreg_t;
136
137struct mips_dsp_state {
138 dspreg_t dspr[NUM_DSP_REGS];
139 unsigned int dspcontrol;
140};
141
142#define INIT_CPUMASK { \
143 {0,} \
144}
145
146struct mips3264_watch_reg_state {
147 /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
148 64 bit kernel. We use unsigned long as it has the same
149 property. */
150 unsigned long watchlo[NUM_WATCH_REGS];
151 /* Only the mask and IRW bits from watchhi. */
152 u16 watchhi[NUM_WATCH_REGS];
153};
154
155union mips_watch_reg_state {
156 struct mips3264_watch_reg_state mips3264;
157};
158
159#if defined(CONFIG_CPU_CAVIUM_OCTEON)
160
161struct octeon_cop2_state {
162 /* DMFC2 rt, 0x0201 */
163 unsigned long cop2_crc_iv;
164 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
165 unsigned long cop2_crc_length;
166 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
167 unsigned long cop2_crc_poly;
168 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
169 unsigned long cop2_llm_dat[2];
170 /* DMFC2 rt, 0x0084 */
171 unsigned long cop2_3des_iv;
172 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
173 unsigned long cop2_3des_key[3];
174 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
175 unsigned long cop2_3des_result;
176 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
177 unsigned long cop2_aes_inp0;
178 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
179 unsigned long cop2_aes_iv[2];
180 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
181 * rt, 0x0107 */
182 unsigned long cop2_aes_key[4];
183 /* DMFC2 rt, 0x0110 */
184 unsigned long cop2_aes_keylen;
185 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
186 unsigned long cop2_aes_result[2];
187 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
188 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
189 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
190 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
191 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
192 unsigned long cop2_hsh_datw[15];
193 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
194 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
195 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
196 unsigned long cop2_hsh_ivw[8];
197 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
198 unsigned long cop2_gfm_mult[2];
199 /* DMFC2 rt, 0x025E - Pass2 */
200 unsigned long cop2_gfm_poly;
201 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
202 unsigned long cop2_gfm_result[2];
203 /* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */
204 unsigned long cop2_sha3[2];
205};
206#define COP2_INIT \
207 .cp2 = {0,},
208
209struct octeon_cvmseg_state {
210 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
211 [cpu_dcache_line_size() / sizeof(unsigned long)];
212};
213
214#elif defined(CONFIG_CPU_XLP)
215struct nlm_cop2_state {
216 u64 rx[4];
217 u64 tx[4];
218 u32 tx_msg_status;
219 u32 rx_msg_status;
220};
221
222#define COP2_INIT \
223 .cp2 = {{0}, {0}, 0, 0},
224#else
225#define COP2_INIT
226#endif
227
228typedef struct {
229 unsigned long seg;
230} mm_segment_t;
231
232#ifdef CONFIG_CPU_HAS_MSA
233# define ARCH_MIN_TASKALIGN 16
234# define FPU_ALIGN __aligned(16)
235#else
236# define ARCH_MIN_TASKALIGN 8
237# define FPU_ALIGN
238#endif
239
240struct mips_abi;
241
242/*
243 * If you change thread_struct remember to change the #defines below too!
244 */
245struct thread_struct {
246 /* Saved main processor registers. */
247 unsigned long reg16;
248 unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
249 unsigned long reg29, reg30, reg31;
250
251 /* Saved cp0 stuff. */
252 unsigned long cp0_status;
253
254#ifdef CONFIG_MIPS_FP_SUPPORT
255 /* Saved fpu/fpu emulator stuff. */
256 struct mips_fpu_struct fpu FPU_ALIGN;
257 /* Assigned branch delay slot 'emulation' frame */
258 atomic_t bd_emu_frame;
259 /* PC of the branch from a branch delay slot 'emulation' */
260 unsigned long bd_emu_branch_pc;
261 /* PC to continue from following a branch delay slot 'emulation' */
262 unsigned long bd_emu_cont_pc;
263#endif
264#ifdef CONFIG_MIPS_MT_FPAFF
265 /* Emulated instruction count */
266 unsigned long emulated_fp;
267 /* Saved per-thread scheduler affinity mask */
268 cpumask_t user_cpus_allowed;
269#endif /* CONFIG_MIPS_MT_FPAFF */
270
271 /* Saved state of the DSP ASE, if available. */
272 struct mips_dsp_state dsp;
273
274 /* Saved watch register state, if available. */
275 union mips_watch_reg_state watch;
276
277 /* Other stuff associated with the thread. */
278 unsigned long cp0_badvaddr; /* Last user fault */
279 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
280 unsigned long error_code;
281 unsigned long trap_nr;
282#ifdef CONFIG_CPU_CAVIUM_OCTEON
283 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
284 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
285#endif
286#ifdef CONFIG_CPU_XLP
287 struct nlm_cop2_state cp2;
288#endif
289 struct mips_abi *abi;
290};
291
292#ifdef CONFIG_MIPS_MT_FPAFF
293#define FPAFF_INIT \
294 .emulated_fp = 0, \
295 .user_cpus_allowed = INIT_CPUMASK,
296#else
297#define FPAFF_INIT
298#endif /* CONFIG_MIPS_MT_FPAFF */
299
300#ifdef CONFIG_MIPS_FP_SUPPORT
301# define FPU_INIT \
302 .fpu = { \
303 .fpr = {{{0,},},}, \
304 .fcr31 = 0, \
305 .msacsr = 0, \
306 }, \
307 /* Delay slot emulation */ \
308 .bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE), \
309 .bd_emu_branch_pc = 0, \
310 .bd_emu_cont_pc = 0,
311#else
312# define FPU_INIT
313#endif
314
315#define INIT_THREAD { \
316 /* \
317 * Saved main processor registers \
318 */ \
319 .reg16 = 0, \
320 .reg17 = 0, \
321 .reg18 = 0, \
322 .reg19 = 0, \
323 .reg20 = 0, \
324 .reg21 = 0, \
325 .reg22 = 0, \
326 .reg23 = 0, \
327 .reg29 = 0, \
328 .reg30 = 0, \
329 .reg31 = 0, \
330 /* \
331 * Saved cp0 stuff \
332 */ \
333 .cp0_status = 0, \
334 /* \
335 * Saved FPU/FPU emulator stuff \
336 */ \
337 FPU_INIT \
338 /* \
339 * FPU affinity state (null if not FPAFF) \
340 */ \
341 FPAFF_INIT \
342 /* \
343 * Saved DSP stuff \
344 */ \
345 .dsp = { \
346 .dspr = {0, }, \
347 .dspcontrol = 0, \
348 }, \
349 /* \
350 * saved watch register stuff \
351 */ \
352 .watch = {{{0,},},}, \
353 /* \
354 * Other stuff associated with the process \
355 */ \
356 .cp0_badvaddr = 0, \
357 .cp0_baduaddr = 0, \
358 .error_code = 0, \
359 .trap_nr = 0, \
360 /* \
361 * Platform specific cop2 registers(null if no COP2) \
362 */ \
363 COP2_INIT \
364}
365
366struct task_struct;
367
368/* Free all resources held by a thread. */
369#define release_thread(thread) do { } while(0)
370
371/*
372 * Do necessary setup to start up a newly executed thread.
373 */
374extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
375
376static inline void flush_thread(void)
377{
378}
379
380unsigned long get_wchan(struct task_struct *p);
381
382#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
383 THREAD_SIZE - 32 - sizeof(struct pt_regs))
384#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
385#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
386#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
387#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
388
389/*
390 * Return_address is a replacement for __builtin_return_address(count)
391 * which on certain architectures cannot reasonably be implemented in GCC
392 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
393 * Note that __builtin_return_address(x>=1) is forbidden because GCC
394 * aborts compilation on some CPUs. It's simply not possible to unwind
395 * some CPU's stackframes.
396 *
397 * __builtin_return_address works only for non-leaf functions. We avoid the
398 * overhead of a function call by forcing the compiler to save the return
399 * address register on the stack.
400 */
401#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
402
403#ifdef CONFIG_CPU_HAS_PREFETCH
404
405#define ARCH_HAS_PREFETCH
406#define prefetch(x) __builtin_prefetch((x), 0, 1)
407
408#define ARCH_HAS_PREFETCHW
409#define prefetchw(x) __builtin_prefetch((x), 1, 1)
410
411#endif
412
413/*
414 * Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options
415 * to the prctl syscall.
416 */
417extern int mips_get_process_fp_mode(struct task_struct *task);
418extern int mips_set_process_fp_mode(struct task_struct *task,
419 unsigned int value);
420
421#define GET_FP_MODE(task) mips_get_process_fp_mode(task)
422#define SET_FP_MODE(task,value) mips_set_process_fp_mode(task, value)
423
424#endif /* _ASM_PROCESSOR_H */