1/*
 2 * Copyright 2012 Pavel Machek <pavel@denx.de>
 3 * Copyright (C) 2012 Altera Corporation
 4 *
 5 * This program is free software; you can redistribute it and/or modify
 6 * it under the terms of the GNU General Public License as published by
 7 * the Free Software Foundation; either version 2 of the License, or
 8 * (at your option) any later version.
 9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
18 */
19
20#ifndef __MACH_CORE_H
21#define __MACH_CORE_H
22
23#define SOCFPGA_RSTMGR_CTRL	0x04
 
24#define SOCFPGA_RSTMGR_MODPERRST	0x14
25#define SOCFPGA_RSTMGR_BRGMODRST	0x1c
26
 
 
 
27/* System Manager bits */
28#define RSTMGR_CTRL_SWCOLDRSTREQ	0x1	/* Cold Reset */
29#define RSTMGR_CTRL_SWWARMRSTREQ	0x2	/* Warm Reset */
30
31extern void socfpga_secondary_startup(void);
32extern void __iomem *socfpga_scu_base_addr;
33
34extern void socfpga_init_clocks(void);
35extern void socfpga_sysmgr_init(void);
 
 
36
37extern void __iomem *sys_manager_base_addr;
38extern void __iomem *rst_manager_base_addr;
 
 
 
 
39
40extern struct smp_operations socfpga_smp_ops;
41extern char secondary_trampoline, secondary_trampoline_end;
42
43extern unsigned long cpu1start_addr;
44
45#define SOCFPGA_SCU_VIRT_BASE   0xfffec000
46
47#endif

 1/* SPDX-License-Identifier: GPL-2.0-or-later */
 2/*
 3 * Copyright 2012 Pavel Machek <pavel@denx.de>
 4 * Copyright (C) 2012-2015 Altera Corporation
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 5 */
 6
 7#ifndef __MACH_CORE_H
 8#define __MACH_CORE_H
 9
10#define SOCFPGA_RSTMGR_CTRL	0x04
11#define SOCFPGA_RSTMGR_MODMPURST	0x10
12#define SOCFPGA_RSTMGR_MODPERRST	0x14
13#define SOCFPGA_RSTMGR_BRGMODRST	0x1c
14
15#define SOCFPGA_A10_RSTMGR_CTRL		0xC
16#define SOCFPGA_A10_RSTMGR_MODMPURST	0x20
17
18/* System Manager bits */
19#define RSTMGR_CTRL_SWCOLDRSTREQ	0x1	/* Cold Reset */
20#define RSTMGR_CTRL_SWWARMRSTREQ	0x2	/* Warm Reset */
21
22#define RSTMGR_MPUMODRST_CPU1		0x2     /* CPU1 Reset */
 
23
24void socfpga_init_l2_ecc(void);
25void socfpga_init_ocram_ecc(void);
26void socfpga_init_arria10_l2_ecc(void);
27void socfpga_init_arria10_ocram_ecc(void);
28
29extern void __iomem *sys_manager_base_addr;
30extern void __iomem *rst_manager_base_addr;
31extern void __iomem *sdr_ctl_base_addr;
32
33u32 socfpga_sdram_self_refresh(u32 sdr_base);
34extern unsigned int socfpga_sdram_self_refresh_sz;
35
 
36extern char secondary_trampoline, secondary_trampoline_end;
37
38extern unsigned long socfpga_cpu1start_addr;
39
40#define SOCFPGA_SCU_VIRT_BASE   0xfee00000
41
42#endif