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1/*
2 * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/rtc.h>
20
21/* These register offsets are relative to LP (Low Power) range */
22#define SNVS_LPCR 0x04
23#define SNVS_LPSR 0x18
24#define SNVS_LPSRTCMR 0x1c
25#define SNVS_LPSRTCLR 0x20
26#define SNVS_LPTAR 0x24
27#define SNVS_LPPGDR 0x30
28
29#define SNVS_LPCR_SRTC_ENV (1 << 0)
30#define SNVS_LPCR_LPTA_EN (1 << 1)
31#define SNVS_LPCR_LPWUI_EN (1 << 3)
32#define SNVS_LPSR_LPTA (1 << 0)
33
34#define SNVS_LPPGDR_INIT 0x41736166
35#define CNTR_TO_SECS_SH 15
36
37struct snvs_rtc_data {
38 struct rtc_device *rtc;
39 void __iomem *ioaddr;
40 int irq;
41 spinlock_t lock;
42};
43
44static u32 rtc_read_lp_counter(void __iomem *ioaddr)
45{
46 u64 read1, read2;
47
48 do {
49 read1 = readl(ioaddr + SNVS_LPSRTCMR);
50 read1 <<= 32;
51 read1 |= readl(ioaddr + SNVS_LPSRTCLR);
52
53 read2 = readl(ioaddr + SNVS_LPSRTCMR);
54 read2 <<= 32;
55 read2 |= readl(ioaddr + SNVS_LPSRTCLR);
56 } while (read1 != read2);
57
58 /* Convert 47-bit counter to 32-bit raw second count */
59 return (u32) (read1 >> CNTR_TO_SECS_SH);
60}
61
62static void rtc_write_sync_lp(void __iomem *ioaddr)
63{
64 u32 count1, count2, count3;
65 int i;
66
67 /* Wait for 3 CKIL cycles */
68 for (i = 0; i < 3; i++) {
69 do {
70 count1 = readl(ioaddr + SNVS_LPSRTCLR);
71 count2 = readl(ioaddr + SNVS_LPSRTCLR);
72 } while (count1 != count2);
73
74 /* Now wait until counter value changes */
75 do {
76 do {
77 count2 = readl(ioaddr + SNVS_LPSRTCLR);
78 count3 = readl(ioaddr + SNVS_LPSRTCLR);
79 } while (count2 != count3);
80 } while (count3 == count1);
81 }
82}
83
84static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
85{
86 unsigned long flags;
87 int timeout = 1000;
88 u32 lpcr;
89
90 spin_lock_irqsave(&data->lock, flags);
91
92 lpcr = readl(data->ioaddr + SNVS_LPCR);
93 if (enable)
94 lpcr |= SNVS_LPCR_SRTC_ENV;
95 else
96 lpcr &= ~SNVS_LPCR_SRTC_ENV;
97 writel(lpcr, data->ioaddr + SNVS_LPCR);
98
99 spin_unlock_irqrestore(&data->lock, flags);
100
101 while (--timeout) {
102 lpcr = readl(data->ioaddr + SNVS_LPCR);
103
104 if (enable) {
105 if (lpcr & SNVS_LPCR_SRTC_ENV)
106 break;
107 } else {
108 if (!(lpcr & SNVS_LPCR_SRTC_ENV))
109 break;
110 }
111 }
112
113 if (!timeout)
114 return -ETIMEDOUT;
115
116 return 0;
117}
118
119static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
120{
121 struct snvs_rtc_data *data = dev_get_drvdata(dev);
122 unsigned long time = rtc_read_lp_counter(data->ioaddr);
123
124 rtc_time_to_tm(time, tm);
125
126 return 0;
127}
128
129static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
130{
131 struct snvs_rtc_data *data = dev_get_drvdata(dev);
132 unsigned long time;
133
134 rtc_tm_to_time(tm, &time);
135
136 /* Disable RTC first */
137 snvs_rtc_enable(data, false);
138
139 /* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
140 writel(time << CNTR_TO_SECS_SH, data->ioaddr + SNVS_LPSRTCLR);
141 writel(time >> (32 - CNTR_TO_SECS_SH), data->ioaddr + SNVS_LPSRTCMR);
142
143 /* Enable RTC again */
144 snvs_rtc_enable(data, true);
145
146 return 0;
147}
148
149static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
150{
151 struct snvs_rtc_data *data = dev_get_drvdata(dev);
152 u32 lptar, lpsr;
153
154 lptar = readl(data->ioaddr + SNVS_LPTAR);
155 rtc_time_to_tm(lptar, &alrm->time);
156
157 lpsr = readl(data->ioaddr + SNVS_LPSR);
158 alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
159
160 return 0;
161}
162
163static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
164{
165 struct snvs_rtc_data *data = dev_get_drvdata(dev);
166 u32 lpcr;
167 unsigned long flags;
168
169 spin_lock_irqsave(&data->lock, flags);
170
171 lpcr = readl(data->ioaddr + SNVS_LPCR);
172 if (enable)
173 lpcr |= (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN);
174 else
175 lpcr &= ~(SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN);
176 writel(lpcr, data->ioaddr + SNVS_LPCR);
177
178 spin_unlock_irqrestore(&data->lock, flags);
179
180 rtc_write_sync_lp(data->ioaddr);
181
182 return 0;
183}
184
185static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
186{
187 struct snvs_rtc_data *data = dev_get_drvdata(dev);
188 struct rtc_time *alrm_tm = &alrm->time;
189 unsigned long time;
190 unsigned long flags;
191 u32 lpcr;
192
193 rtc_tm_to_time(alrm_tm, &time);
194
195 spin_lock_irqsave(&data->lock, flags);
196
197 /* Have to clear LPTA_EN before programming new alarm time in LPTAR */
198 lpcr = readl(data->ioaddr + SNVS_LPCR);
199 lpcr &= ~SNVS_LPCR_LPTA_EN;
200 writel(lpcr, data->ioaddr + SNVS_LPCR);
201
202 spin_unlock_irqrestore(&data->lock, flags);
203
204 writel(time, data->ioaddr + SNVS_LPTAR);
205
206 /* Clear alarm interrupt status bit */
207 writel(SNVS_LPSR_LPTA, data->ioaddr + SNVS_LPSR);
208
209 return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
210}
211
212static const struct rtc_class_ops snvs_rtc_ops = {
213 .read_time = snvs_rtc_read_time,
214 .set_time = snvs_rtc_set_time,
215 .read_alarm = snvs_rtc_read_alarm,
216 .set_alarm = snvs_rtc_set_alarm,
217 .alarm_irq_enable = snvs_rtc_alarm_irq_enable,
218};
219
220static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
221{
222 struct device *dev = dev_id;
223 struct snvs_rtc_data *data = dev_get_drvdata(dev);
224 u32 lpsr;
225 u32 events = 0;
226
227 lpsr = readl(data->ioaddr + SNVS_LPSR);
228
229 if (lpsr & SNVS_LPSR_LPTA) {
230 events |= (RTC_AF | RTC_IRQF);
231
232 /* RTC alarm should be one-shot */
233 snvs_rtc_alarm_irq_enable(dev, 0);
234
235 rtc_update_irq(data->rtc, 1, events);
236 }
237
238 /* clear interrupt status */
239 writel(lpsr, data->ioaddr + SNVS_LPSR);
240
241 return events ? IRQ_HANDLED : IRQ_NONE;
242}
243
244static int snvs_rtc_probe(struct platform_device *pdev)
245{
246 struct snvs_rtc_data *data;
247 struct resource *res;
248 int ret;
249
250 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
251 if (!data)
252 return -ENOMEM;
253
254 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
255 data->ioaddr = devm_ioremap_resource(&pdev->dev, res);
256 if (IS_ERR(data->ioaddr))
257 return PTR_ERR(data->ioaddr);
258
259 data->irq = platform_get_irq(pdev, 0);
260 if (data->irq < 0)
261 return data->irq;
262
263 platform_set_drvdata(pdev, data);
264
265 spin_lock_init(&data->lock);
266
267 /* Initialize glitch detect */
268 writel(SNVS_LPPGDR_INIT, data->ioaddr + SNVS_LPPGDR);
269
270 /* Clear interrupt status */
271 writel(0xffffffff, data->ioaddr + SNVS_LPSR);
272
273 /* Enable RTC */
274 snvs_rtc_enable(data, true);
275
276 device_init_wakeup(&pdev->dev, true);
277
278 ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
279 IRQF_SHARED, "rtc alarm", &pdev->dev);
280 if (ret) {
281 dev_err(&pdev->dev, "failed to request irq %d: %d\n",
282 data->irq, ret);
283 return ret;
284 }
285
286 data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
287 &snvs_rtc_ops, THIS_MODULE);
288 if (IS_ERR(data->rtc)) {
289 ret = PTR_ERR(data->rtc);
290 dev_err(&pdev->dev, "failed to register rtc: %d\n", ret);
291 return ret;
292 }
293
294 return 0;
295}
296
297#ifdef CONFIG_PM_SLEEP
298static int snvs_rtc_suspend(struct device *dev)
299{
300 struct snvs_rtc_data *data = dev_get_drvdata(dev);
301
302 if (device_may_wakeup(dev))
303 enable_irq_wake(data->irq);
304
305 return 0;
306}
307
308static int snvs_rtc_resume(struct device *dev)
309{
310 struct snvs_rtc_data *data = dev_get_drvdata(dev);
311
312 if (device_may_wakeup(dev))
313 disable_irq_wake(data->irq);
314
315 return 0;
316}
317#endif
318
319static SIMPLE_DEV_PM_OPS(snvs_rtc_pm_ops, snvs_rtc_suspend, snvs_rtc_resume);
320
321static const struct of_device_id snvs_dt_ids[] = {
322 { .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
323 { /* sentinel */ }
324};
325MODULE_DEVICE_TABLE(of, snvs_dt_ids);
326
327static struct platform_driver snvs_rtc_driver = {
328 .driver = {
329 .name = "snvs_rtc",
330 .owner = THIS_MODULE,
331 .pm = &snvs_rtc_pm_ops,
332 .of_match_table = snvs_dt_ids,
333 },
334 .probe = snvs_rtc_probe,
335};
336module_platform_driver(snvs_rtc_driver);
337
338MODULE_AUTHOR("Freescale Semiconductor, Inc.");
339MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
340MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
4
5#include <linux/init.h>
6#include <linux/io.h>
7#include <linux/kernel.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/of_device.h>
11#include <linux/platform_device.h>
12#include <linux/pm_wakeirq.h>
13#include <linux/rtc.h>
14#include <linux/clk.h>
15#include <linux/mfd/syscon.h>
16#include <linux/regmap.h>
17
18#define SNVS_LPREGISTER_OFFSET 0x34
19
20/* These register offsets are relative to LP (Low Power) range */
21#define SNVS_LPCR 0x04
22#define SNVS_LPSR 0x18
23#define SNVS_LPSRTCMR 0x1c
24#define SNVS_LPSRTCLR 0x20
25#define SNVS_LPTAR 0x24
26#define SNVS_LPPGDR 0x30
27
28#define SNVS_LPCR_SRTC_ENV (1 << 0)
29#define SNVS_LPCR_LPTA_EN (1 << 1)
30#define SNVS_LPCR_LPWUI_EN (1 << 3)
31#define SNVS_LPSR_LPTA (1 << 0)
32
33#define SNVS_LPPGDR_INIT 0x41736166
34#define CNTR_TO_SECS_SH 15
35
36struct snvs_rtc_data {
37 struct rtc_device *rtc;
38 struct regmap *regmap;
39 int offset;
40 int irq;
41 struct clk *clk;
42};
43
44/* Read 64 bit timer register, which could be in inconsistent state */
45static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)
46{
47 u32 msb, lsb;
48
49 regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);
50 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);
51 return (u64)msb << 32 | lsb;
52}
53
54/* Read the secure real time counter, taking care to deal with the cases of the
55 * counter updating while being read.
56 */
57static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
58{
59 u64 read1, read2;
60 unsigned int timeout = 100;
61
62 /* As expected, the registers might update between the read of the LSB
63 * reg and the MSB reg. It's also possible that one register might be
64 * in partially modified state as well.
65 */
66 read1 = rtc_read_lpsrt(data);
67 do {
68 read2 = read1;
69 read1 = rtc_read_lpsrt(data);
70 } while (read1 != read2 && --timeout);
71 if (!timeout)
72 dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
73
74 /* Convert 47-bit counter to 32-bit raw second count */
75 return (u32) (read1 >> CNTR_TO_SECS_SH);
76}
77
78/* Just read the lsb from the counter, dealing with inconsistent state */
79static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb)
80{
81 u32 count1, count2;
82 unsigned int timeout = 100;
83
84 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
85 do {
86 count2 = count1;
87 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
88 } while (count1 != count2 && --timeout);
89 if (!timeout) {
90 dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
91 return -ETIMEDOUT;
92 }
93
94 *lsb = count1;
95 return 0;
96}
97
98static int rtc_write_sync_lp(struct snvs_rtc_data *data)
99{
100 u32 count1, count2;
101 u32 elapsed;
102 unsigned int timeout = 1000;
103 int ret;
104
105 ret = rtc_read_lp_counter_lsb(data, &count1);
106 if (ret)
107 return ret;
108
109 /* Wait for 3 CKIL cycles, about 61.0-91.5 µs */
110 do {
111 ret = rtc_read_lp_counter_lsb(data, &count2);
112 if (ret)
113 return ret;
114 elapsed = count2 - count1; /* wrap around _is_ handled! */
115 } while (elapsed < 3 && --timeout);
116 if (!timeout) {
117 dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n");
118 return -ETIMEDOUT;
119 }
120 return 0;
121}
122
123static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
124{
125 int timeout = 1000;
126 u32 lpcr;
127
128 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
129 enable ? SNVS_LPCR_SRTC_ENV : 0);
130
131 while (--timeout) {
132 regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
133
134 if (enable) {
135 if (lpcr & SNVS_LPCR_SRTC_ENV)
136 break;
137 } else {
138 if (!(lpcr & SNVS_LPCR_SRTC_ENV))
139 break;
140 }
141 }
142
143 if (!timeout)
144 return -ETIMEDOUT;
145
146 return 0;
147}
148
149static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
150{
151 struct snvs_rtc_data *data = dev_get_drvdata(dev);
152 unsigned long time = rtc_read_lp_counter(data);
153
154 rtc_time64_to_tm(time, tm);
155
156 return 0;
157}
158
159static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
160{
161 struct snvs_rtc_data *data = dev_get_drvdata(dev);
162 unsigned long time = rtc_tm_to_time64(tm);
163 int ret;
164
165 /* Disable RTC first */
166 ret = snvs_rtc_enable(data, false);
167 if (ret)
168 return ret;
169
170 /* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
171 regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
172 regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
173
174 /* Enable RTC again */
175 ret = snvs_rtc_enable(data, true);
176
177 return ret;
178}
179
180static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
181{
182 struct snvs_rtc_data *data = dev_get_drvdata(dev);
183 u32 lptar, lpsr;
184
185 regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
186 rtc_time64_to_tm(lptar, &alrm->time);
187
188 regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
189 alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
190
191 return 0;
192}
193
194static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
195{
196 struct snvs_rtc_data *data = dev_get_drvdata(dev);
197
198 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
199 (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
200 enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);
201
202 return rtc_write_sync_lp(data);
203}
204
205static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
206{
207 struct snvs_rtc_data *data = dev_get_drvdata(dev);
208 unsigned long time = rtc_tm_to_time64(&alrm->time);
209 int ret;
210
211 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
212 ret = rtc_write_sync_lp(data);
213 if (ret)
214 return ret;
215 regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
216
217 /* Clear alarm interrupt status bit */
218 regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
219
220 return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
221}
222
223static const struct rtc_class_ops snvs_rtc_ops = {
224 .read_time = snvs_rtc_read_time,
225 .set_time = snvs_rtc_set_time,
226 .read_alarm = snvs_rtc_read_alarm,
227 .set_alarm = snvs_rtc_set_alarm,
228 .alarm_irq_enable = snvs_rtc_alarm_irq_enable,
229};
230
231static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
232{
233 struct device *dev = dev_id;
234 struct snvs_rtc_data *data = dev_get_drvdata(dev);
235 u32 lpsr;
236 u32 events = 0;
237
238 if (data->clk)
239 clk_enable(data->clk);
240
241 regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
242
243 if (lpsr & SNVS_LPSR_LPTA) {
244 events |= (RTC_AF | RTC_IRQF);
245
246 /* RTC alarm should be one-shot */
247 snvs_rtc_alarm_irq_enable(dev, 0);
248
249 rtc_update_irq(data->rtc, 1, events);
250 }
251
252 /* clear interrupt status */
253 regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
254
255 if (data->clk)
256 clk_disable(data->clk);
257
258 return events ? IRQ_HANDLED : IRQ_NONE;
259}
260
261static const struct regmap_config snvs_rtc_config = {
262 .reg_bits = 32,
263 .val_bits = 32,
264 .reg_stride = 4,
265};
266
267static int snvs_rtc_probe(struct platform_device *pdev)
268{
269 struct snvs_rtc_data *data;
270 int ret;
271 void __iomem *mmio;
272
273 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
274 if (!data)
275 return -ENOMEM;
276
277 data->rtc = devm_rtc_allocate_device(&pdev->dev);
278 if (IS_ERR(data->rtc))
279 return PTR_ERR(data->rtc);
280
281 data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
282
283 if (IS_ERR(data->regmap)) {
284 dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
285
286 mmio = devm_platform_ioremap_resource(pdev, 0);
287 if (IS_ERR(mmio))
288 return PTR_ERR(mmio);
289
290 data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
291 } else {
292 data->offset = SNVS_LPREGISTER_OFFSET;
293 of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
294 }
295
296 if (IS_ERR(data->regmap)) {
297 dev_err(&pdev->dev, "Can't find snvs syscon\n");
298 return -ENODEV;
299 }
300
301 data->irq = platform_get_irq(pdev, 0);
302 if (data->irq < 0)
303 return data->irq;
304
305 data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
306 if (IS_ERR(data->clk)) {
307 data->clk = NULL;
308 } else {
309 ret = clk_prepare_enable(data->clk);
310 if (ret) {
311 dev_err(&pdev->dev,
312 "Could not prepare or enable the snvs clock\n");
313 return ret;
314 }
315 }
316
317 platform_set_drvdata(pdev, data);
318
319 /* Initialize glitch detect */
320 regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
321
322 /* Clear interrupt status */
323 regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
324
325 /* Enable RTC */
326 ret = snvs_rtc_enable(data, true);
327 if (ret) {
328 dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
329 goto error_rtc_device_register;
330 }
331
332 device_init_wakeup(&pdev->dev, true);
333 ret = dev_pm_set_wake_irq(&pdev->dev, data->irq);
334 if (ret)
335 dev_err(&pdev->dev, "failed to enable irq wake\n");
336
337 ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
338 IRQF_SHARED, "rtc alarm", &pdev->dev);
339 if (ret) {
340 dev_err(&pdev->dev, "failed to request irq %d: %d\n",
341 data->irq, ret);
342 goto error_rtc_device_register;
343 }
344
345 data->rtc->ops = &snvs_rtc_ops;
346 data->rtc->range_max = U32_MAX;
347 ret = rtc_register_device(data->rtc);
348 if (ret) {
349 dev_err(&pdev->dev, "failed to register rtc: %d\n", ret);
350 goto error_rtc_device_register;
351 }
352
353 return 0;
354
355error_rtc_device_register:
356 if (data->clk)
357 clk_disable_unprepare(data->clk);
358
359 return ret;
360}
361
362static int __maybe_unused snvs_rtc_suspend_noirq(struct device *dev)
363{
364 struct snvs_rtc_data *data = dev_get_drvdata(dev);
365
366 if (data->clk)
367 clk_disable_unprepare(data->clk);
368
369 return 0;
370}
371
372static int __maybe_unused snvs_rtc_resume_noirq(struct device *dev)
373{
374 struct snvs_rtc_data *data = dev_get_drvdata(dev);
375
376 if (data->clk)
377 return clk_prepare_enable(data->clk);
378
379 return 0;
380}
381
382static const struct dev_pm_ops snvs_rtc_pm_ops = {
383 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(snvs_rtc_suspend_noirq, snvs_rtc_resume_noirq)
384};
385
386static const struct of_device_id snvs_dt_ids[] = {
387 { .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
388 { /* sentinel */ }
389};
390MODULE_DEVICE_TABLE(of, snvs_dt_ids);
391
392static struct platform_driver snvs_rtc_driver = {
393 .driver = {
394 .name = "snvs_rtc",
395 .pm = &snvs_rtc_pm_ops,
396 .of_match_table = snvs_dt_ids,
397 },
398 .probe = snvs_rtc_probe,
399};
400module_platform_driver(snvs_rtc_driver);
401
402MODULE_AUTHOR("Freescale Semiconductor, Inc.");
403MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
404MODULE_LICENSE("GPL");