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1/*
2 * FarSync WAN driver for Linux (2.6.x kernel version)
3 *
4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
5 *
6 * Copyright (C) 2001-2004 FarSite Communications Ltd.
7 * www.farsite.co.uk
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 *
14 * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk>
15 * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk>
16 */
17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/version.h>
23#include <linux/pci.h>
24#include <linux/sched.h>
25#include <linux/slab.h>
26#include <linux/ioport.h>
27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <linux/if.h>
30#include <linux/hdlc.h>
31#include <asm/io.h>
32#include <asm/uaccess.h>
33
34#include "farsync.h"
35
36/*
37 * Module info
38 */
39MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>");
40MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
41MODULE_LICENSE("GPL");
42
43/* Driver configuration and global parameters
44 * ==========================================
45 */
46
47/* Number of ports (per card) and cards supported
48 */
49#define FST_MAX_PORTS 4
50#define FST_MAX_CARDS 32
51
52/* Default parameters for the link
53 */
54#define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is
55 * useful */
56#define FST_TXQ_DEPTH 16 /* This one is for the buffering
57 * of frames on the way down to the card
58 * so that we can keep the card busy
59 * and maximise throughput
60 */
61#define FST_HIGH_WATER_MARK 12 /* Point at which we flow control
62 * network layer */
63#define FST_LOW_WATER_MARK 8 /* Point at which we remove flow
64 * control from network layer */
65#define FST_MAX_MTU 8000 /* Huge but possible */
66#define FST_DEF_MTU 1500 /* Common sane value */
67
68#define FST_TX_TIMEOUT (2*HZ)
69
70#ifdef ARPHRD_RAWHDLC
71#define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */
72#else
73#define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */
74#endif
75
76/*
77 * Modules parameters and associated variables
78 */
79static int fst_txq_low = FST_LOW_WATER_MARK;
80static int fst_txq_high = FST_HIGH_WATER_MARK;
81static int fst_max_reads = 7;
82static int fst_excluded_cards = 0;
83static int fst_excluded_list[FST_MAX_CARDS];
84
85module_param(fst_txq_low, int, 0);
86module_param(fst_txq_high, int, 0);
87module_param(fst_max_reads, int, 0);
88module_param(fst_excluded_cards, int, 0);
89module_param_array(fst_excluded_list, int, NULL, 0);
90
91/* Card shared memory layout
92 * =========================
93 */
94#pragma pack(1)
95
96/* This information is derived in part from the FarSite FarSync Smc.h
97 * file. Unfortunately various name clashes and the non-portability of the
98 * bit field declarations in that file have meant that I have chosen to
99 * recreate the information here.
100 *
101 * The SMC (Shared Memory Configuration) has a version number that is
102 * incremented every time there is a significant change. This number can
103 * be used to check that we have not got out of step with the firmware
104 * contained in the .CDE files.
105 */
106#define SMC_VERSION 24
107
108#define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */
109
110#define SMC_BASE 0x00002000L /* Base offset of the shared memory window main
111 * configuration structure */
112#define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA
113 * buffers */
114
115#define LEN_TX_BUFFER 8192 /* Size of packet buffers */
116#define LEN_RX_BUFFER 8192
117
118#define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */
119#define LEN_SMALL_RX_BUFFER 256
120
121#define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */
122#define NUM_RX_BUFFER 8
123
124/* Interrupt retry time in milliseconds */
125#define INT_RETRY_TIME 2
126
127/* The Am186CH/CC processors support a SmartDMA mode using circular pools
128 * of buffer descriptors. The structure is almost identical to that used
129 * in the LANCE Ethernet controllers. Details available as PDF from the
130 * AMD web site: http://www.amd.com/products/epd/processors/\
131 * 2.16bitcont/3.am186cxfa/a21914/21914.pdf
132 */
133struct txdesc { /* Transmit descriptor */
134 volatile u16 ladr; /* Low order address of packet. This is a
135 * linear address in the Am186 memory space
136 */
137 volatile u8 hadr; /* High order address. Low 4 bits only, high 4
138 * bits must be zero
139 */
140 volatile u8 bits; /* Status and config */
141 volatile u16 bcnt; /* 2s complement of packet size in low 15 bits.
142 * Transmit terminal count interrupt enable in
143 * top bit.
144 */
145 u16 unused; /* Not used in Tx */
146};
147
148struct rxdesc { /* Receive descriptor */
149 volatile u16 ladr; /* Low order address of packet */
150 volatile u8 hadr; /* High order address */
151 volatile u8 bits; /* Status and config */
152 volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits.
153 * Receive terminal count interrupt enable in
154 * top bit.
155 */
156 volatile u16 mcnt; /* Message byte count (15 bits) */
157};
158
159/* Convert a length into the 15 bit 2's complement */
160/* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */
161/* Since we need to set the high bit to enable the completion interrupt this
162 * can be made a lot simpler
163 */
164#define cnv_bcnt(len) (-(len))
165
166/* Status and config bits for the above */
167#define DMA_OWN 0x80 /* SmartDMA owns the descriptor */
168#define TX_STP 0x02 /* Tx: start of packet */
169#define TX_ENP 0x01 /* Tx: end of packet */
170#define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */
171#define RX_FRAM 0x20 /* Rx: framing error */
172#define RX_OFLO 0x10 /* Rx: overflow error */
173#define RX_CRC 0x08 /* Rx: CRC error */
174#define RX_HBUF 0x04 /* Rx: buffer error */
175#define RX_STP 0x02 /* Rx: start of packet */
176#define RX_ENP 0x01 /* Rx: end of packet */
177
178/* Interrupts from the card are caused by various events which are presented
179 * in a circular buffer as several events may be processed on one physical int
180 */
181#define MAX_CIRBUFF 32
182
183struct cirbuff {
184 u8 rdindex; /* read, then increment and wrap */
185 u8 wrindex; /* write, then increment and wrap */
186 u8 evntbuff[MAX_CIRBUFF];
187};
188
189/* Interrupt event codes.
190 * Where appropriate the two low order bits indicate the port number
191 */
192#define CTLA_CHG 0x18 /* Control signal changed */
193#define CTLB_CHG 0x19
194#define CTLC_CHG 0x1A
195#define CTLD_CHG 0x1B
196
197#define INIT_CPLT 0x20 /* Initialisation complete */
198#define INIT_FAIL 0x21 /* Initialisation failed */
199
200#define ABTA_SENT 0x24 /* Abort sent */
201#define ABTB_SENT 0x25
202#define ABTC_SENT 0x26
203#define ABTD_SENT 0x27
204
205#define TXA_UNDF 0x28 /* Transmission underflow */
206#define TXB_UNDF 0x29
207#define TXC_UNDF 0x2A
208#define TXD_UNDF 0x2B
209
210#define F56_INT 0x2C
211#define M32_INT 0x2D
212
213#define TE1_ALMA 0x30
214
215/* Port physical configuration. See farsync.h for field values */
216struct port_cfg {
217 u16 lineInterface; /* Physical interface type */
218 u8 x25op; /* Unused at present */
219 u8 internalClock; /* 1 => internal clock, 0 => external */
220 u8 transparentMode; /* 1 => on, 0 => off */
221 u8 invertClock; /* 0 => normal, 1 => inverted */
222 u8 padBytes[6]; /* Padding */
223 u32 lineSpeed; /* Speed in bps */
224};
225
226/* TE1 port physical configuration */
227struct su_config {
228 u32 dataRate;
229 u8 clocking;
230 u8 framing;
231 u8 structure;
232 u8 interface;
233 u8 coding;
234 u8 lineBuildOut;
235 u8 equalizer;
236 u8 transparentMode;
237 u8 loopMode;
238 u8 range;
239 u8 txBufferMode;
240 u8 rxBufferMode;
241 u8 startingSlot;
242 u8 losThreshold;
243 u8 enableIdleCode;
244 u8 idleCode;
245 u8 spare[44];
246};
247
248/* TE1 Status */
249struct su_status {
250 u32 receiveBufferDelay;
251 u32 framingErrorCount;
252 u32 codeViolationCount;
253 u32 crcErrorCount;
254 u32 lineAttenuation;
255 u8 portStarted;
256 u8 lossOfSignal;
257 u8 receiveRemoteAlarm;
258 u8 alarmIndicationSignal;
259 u8 spare[40];
260};
261
262/* Finally sling all the above together into the shared memory structure.
263 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been
264 * evolving under NT for some time so I guess we're stuck with it.
265 * The structure starts at offset SMC_BASE.
266 * See farsync.h for some field values.
267 */
268struct fst_shared {
269 /* DMA descriptor rings */
270 struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER];
271 struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER];
272
273 /* Obsolete small buffers */
274 u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER];
275 u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER];
276
277 u8 taskStatus; /* 0x00 => initialising, 0x01 => running,
278 * 0xFF => halted
279 */
280
281 u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt,
282 * set to 0xEE by host to acknowledge interrupt
283 */
284
285 u16 smcVersion; /* Must match SMC_VERSION */
286
287 u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major
288 * version, RR = revision and BB = build
289 */
290
291 u16 txa_done; /* Obsolete completion flags */
292 u16 rxa_done;
293 u16 txb_done;
294 u16 rxb_done;
295 u16 txc_done;
296 u16 rxc_done;
297 u16 txd_done;
298 u16 rxd_done;
299
300 u16 mailbox[4]; /* Diagnostics mailbox. Not used */
301
302 struct cirbuff interruptEvent; /* interrupt causes */
303
304 u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */
305 u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */
306
307 struct port_cfg portConfig[FST_MAX_PORTS];
308
309 u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */
310
311 u16 cableStatus; /* lsb: 0=> present, 1=> absent */
312
313 u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */
314 u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */
315
316 u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */
317 u16 cardMailbox[4]; /* Not used */
318
319 /* Number of times the card thinks the host has
320 * missed an interrupt by not acknowledging
321 * within 2mS (I guess NT has problems)
322 */
323 u32 interruptRetryCount;
324
325 /* Driver private data used as an ID. We'll not
326 * use this as I'd rather keep such things
327 * in main memory rather than on the PCI bus
328 */
329 u32 portHandle[FST_MAX_PORTS];
330
331 /* Count of Tx underflows for stats */
332 u32 transmitBufferUnderflow[FST_MAX_PORTS];
333
334 /* Debounced V.24 control input status */
335 u32 v24DebouncedSts[FST_MAX_PORTS];
336
337 /* Adapter debounce timers. Don't touch */
338 u32 ctsTimer[FST_MAX_PORTS];
339 u32 ctsTimerRun[FST_MAX_PORTS];
340 u32 dcdTimer[FST_MAX_PORTS];
341 u32 dcdTimerRun[FST_MAX_PORTS];
342
343 u32 numberOfPorts; /* Number of ports detected at startup */
344
345 u16 _reserved[64];
346
347 u16 cardMode; /* Bit-mask to enable features:
348 * Bit 0: 1 enables LED identify mode
349 */
350
351 u16 portScheduleOffset;
352
353 struct su_config suConfig; /* TE1 Bits */
354 struct su_status suStatus;
355
356 u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of
357 * the structure and marks the end of shared
358 * memory. Adapter code initializes it as
359 * END_SIG.
360 */
361};
362
363/* endOfSmcSignature value */
364#define END_SIG 0x12345678
365
366/* Mailbox values. (portMailbox) */
367#define NOP 0 /* No operation */
368#define ACK 1 /* Positive acknowledgement to PC driver */
369#define NAK 2 /* Negative acknowledgement to PC driver */
370#define STARTPORT 3 /* Start an HDLC port */
371#define STOPPORT 4 /* Stop an HDLC port */
372#define ABORTTX 5 /* Abort the transmitter for a port */
373#define SETV24O 6 /* Set V24 outputs */
374
375/* PLX Chip Register Offsets */
376#define CNTRL_9052 0x50 /* Control Register */
377#define CNTRL_9054 0x6c /* Control Register */
378
379#define INTCSR_9052 0x4c /* Interrupt control/status register */
380#define INTCSR_9054 0x68 /* Interrupt control/status register */
381
382/* 9054 DMA Registers */
383/*
384 * Note that we will be using DMA Channel 0 for copying rx data
385 * and Channel 1 for copying tx data
386 */
387#define DMAMODE0 0x80
388#define DMAPADR0 0x84
389#define DMALADR0 0x88
390#define DMASIZ0 0x8c
391#define DMADPR0 0x90
392#define DMAMODE1 0x94
393#define DMAPADR1 0x98
394#define DMALADR1 0x9c
395#define DMASIZ1 0xa0
396#define DMADPR1 0xa4
397#define DMACSR0 0xa8
398#define DMACSR1 0xa9
399#define DMAARB 0xac
400#define DMATHR 0xb0
401#define DMADAC0 0xb4
402#define DMADAC1 0xb8
403#define DMAMARBR 0xac
404
405#define FST_MIN_DMA_LEN 64
406#define FST_RX_DMA_INT 0x01
407#define FST_TX_DMA_INT 0x02
408#define FST_CARD_INT 0x04
409
410/* Larger buffers are positioned in memory at offset BFM_BASE */
411struct buf_window {
412 u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER];
413 u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER];
414};
415
416/* Calculate offset of a buffer object within the shared memory window */
417#define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X))
418
419#pragma pack()
420
421/* Device driver private information
422 * =================================
423 */
424/* Per port (line or channel) information
425 */
426struct fst_port_info {
427 struct net_device *dev; /* Device struct - must be first */
428 struct fst_card_info *card; /* Card we're associated with */
429 int index; /* Port index on the card */
430 int hwif; /* Line hardware (lineInterface copy) */
431 int run; /* Port is running */
432 int mode; /* Normal or FarSync raw */
433 int rxpos; /* Next Rx buffer to use */
434 int txpos; /* Next Tx buffer to use */
435 int txipos; /* Next Tx buffer to check for free */
436 int start; /* Indication of start/stop to network */
437 /*
438 * A sixteen entry transmit queue
439 */
440 int txqs; /* index to get next buffer to tx */
441 int txqe; /* index to queue next packet */
442 struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */
443 int rxqdepth;
444};
445
446/* Per card information
447 */
448struct fst_card_info {
449 char __iomem *mem; /* Card memory mapped to kernel space */
450 char __iomem *ctlmem; /* Control memory for PCI cards */
451 unsigned int phys_mem; /* Physical memory window address */
452 unsigned int phys_ctlmem; /* Physical control memory address */
453 unsigned int irq; /* Interrupt request line number */
454 unsigned int nports; /* Number of serial ports */
455 unsigned int type; /* Type index of card */
456 unsigned int state; /* State of card */
457 spinlock_t card_lock; /* Lock for SMP access */
458 unsigned short pci_conf; /* PCI card config in I/O space */
459 /* Per port info */
460 struct fst_port_info ports[FST_MAX_PORTS];
461 struct pci_dev *device; /* Information about the pci device */
462 int card_no; /* Inst of the card on the system */
463 int family; /* TxP or TxU */
464 int dmarx_in_progress;
465 int dmatx_in_progress;
466 unsigned long int_count;
467 unsigned long int_time_ave;
468 void *rx_dma_handle_host;
469 dma_addr_t rx_dma_handle_card;
470 void *tx_dma_handle_host;
471 dma_addr_t tx_dma_handle_card;
472 struct sk_buff *dma_skb_rx;
473 struct fst_port_info *dma_port_rx;
474 struct fst_port_info *dma_port_tx;
475 int dma_len_rx;
476 int dma_len_tx;
477 int dma_txpos;
478 int dma_rxpos;
479};
480
481/* Convert an HDLC device pointer into a port info pointer and similar */
482#define dev_to_port(D) (dev_to_hdlc(D)->priv)
483#define port_to_dev(P) ((P)->dev)
484
485
486/*
487 * Shared memory window access macros
488 *
489 * We have a nice memory based structure above, which could be directly
490 * mapped on i386 but might not work on other architectures unless we use
491 * the readb,w,l and writeb,w,l macros. Unfortunately these macros take
492 * physical offsets so we have to convert. The only saving grace is that
493 * this should all collapse back to a simple indirection eventually.
494 */
495#define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X))
496
497#define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E))
498#define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E))
499#define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E))
500
501#define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E))
502#define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E))
503#define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E))
504
505/*
506 * Debug support
507 */
508#if FST_DEBUG
509
510static int fst_debug_mask = { FST_DEBUG };
511
512/* Most common debug activity is to print something if the corresponding bit
513 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to
514 * support variable numbers of macro parameters. The inverted if prevents us
515 * eating someone else's else clause.
516 */
517#define dbg(F, fmt, args...) \
518do { \
519 if (fst_debug_mask & (F)) \
520 printk(KERN_DEBUG pr_fmt(fmt), ##args); \
521} while (0)
522#else
523#define dbg(F, fmt, args...) \
524do { \
525 if (0) \
526 printk(KERN_DEBUG pr_fmt(fmt), ##args); \
527} while (0)
528#endif
529
530/*
531 * PCI ID lookup table
532 */
533static DEFINE_PCI_DEVICE_TABLE(fst_pci_dev_id) = {
534 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID,
535 PCI_ANY_ID, 0, 0, FST_TYPE_T2P},
536
537 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID,
538 PCI_ANY_ID, 0, 0, FST_TYPE_T4P},
539
540 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID,
541 PCI_ANY_ID, 0, 0, FST_TYPE_T1U},
542
543 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID,
544 PCI_ANY_ID, 0, 0, FST_TYPE_T2U},
545
546 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID,
547 PCI_ANY_ID, 0, 0, FST_TYPE_T4U},
548
549 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID,
550 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
551
552 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID,
553 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
554 {0,} /* End */
555};
556
557MODULE_DEVICE_TABLE(pci, fst_pci_dev_id);
558
559/*
560 * Device Driver Work Queues
561 *
562 * So that we don't spend too much time processing events in the
563 * Interrupt Service routine, we will declare a work queue per Card
564 * and make the ISR schedule a task in the queue for later execution.
565 * In the 2.4 Kernel we used to use the immediate queue for BH's
566 * Now that they are gone, tasklets seem to be much better than work
567 * queues.
568 */
569
570static void do_bottom_half_tx(struct fst_card_info *card);
571static void do_bottom_half_rx(struct fst_card_info *card);
572static void fst_process_tx_work_q(unsigned long work_q);
573static void fst_process_int_work_q(unsigned long work_q);
574
575static DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q, 0);
576static DECLARE_TASKLET(fst_int_task, fst_process_int_work_q, 0);
577
578static struct fst_card_info *fst_card_array[FST_MAX_CARDS];
579static spinlock_t fst_work_q_lock;
580static u64 fst_work_txq;
581static u64 fst_work_intq;
582
583static void
584fst_q_work_item(u64 * queue, int card_index)
585{
586 unsigned long flags;
587 u64 mask;
588
589 /*
590 * Grab the queue exclusively
591 */
592 spin_lock_irqsave(&fst_work_q_lock, flags);
593
594 /*
595 * Making an entry in the queue is simply a matter of setting
596 * a bit for the card indicating that there is work to do in the
597 * bottom half for the card. Note the limitation of 64 cards.
598 * That ought to be enough
599 */
600 mask = (u64)1 << card_index;
601 *queue |= mask;
602 spin_unlock_irqrestore(&fst_work_q_lock, flags);
603}
604
605static void
606fst_process_tx_work_q(unsigned long /*void **/work_q)
607{
608 unsigned long flags;
609 u64 work_txq;
610 int i;
611
612 /*
613 * Grab the queue exclusively
614 */
615 dbg(DBG_TX, "fst_process_tx_work_q\n");
616 spin_lock_irqsave(&fst_work_q_lock, flags);
617 work_txq = fst_work_txq;
618 fst_work_txq = 0;
619 spin_unlock_irqrestore(&fst_work_q_lock, flags);
620
621 /*
622 * Call the bottom half for each card with work waiting
623 */
624 for (i = 0; i < FST_MAX_CARDS; i++) {
625 if (work_txq & 0x01) {
626 if (fst_card_array[i] != NULL) {
627 dbg(DBG_TX, "Calling tx bh for card %d\n", i);
628 do_bottom_half_tx(fst_card_array[i]);
629 }
630 }
631 work_txq = work_txq >> 1;
632 }
633}
634
635static void
636fst_process_int_work_q(unsigned long /*void **/work_q)
637{
638 unsigned long flags;
639 u64 work_intq;
640 int i;
641
642 /*
643 * Grab the queue exclusively
644 */
645 dbg(DBG_INTR, "fst_process_int_work_q\n");
646 spin_lock_irqsave(&fst_work_q_lock, flags);
647 work_intq = fst_work_intq;
648 fst_work_intq = 0;
649 spin_unlock_irqrestore(&fst_work_q_lock, flags);
650
651 /*
652 * Call the bottom half for each card with work waiting
653 */
654 for (i = 0; i < FST_MAX_CARDS; i++) {
655 if (work_intq & 0x01) {
656 if (fst_card_array[i] != NULL) {
657 dbg(DBG_INTR,
658 "Calling rx & tx bh for card %d\n", i);
659 do_bottom_half_rx(fst_card_array[i]);
660 do_bottom_half_tx(fst_card_array[i]);
661 }
662 }
663 work_intq = work_intq >> 1;
664 }
665}
666
667/* Card control functions
668 * ======================
669 */
670/* Place the processor in reset state
671 *
672 * Used to be a simple write to card control space but a glitch in the latest
673 * AMD Am186CH processor means that we now have to do it by asserting and de-
674 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register
675 * at offset 9052_CNTRL. Note the updates for the TXU.
676 */
677static inline void
678fst_cpureset(struct fst_card_info *card)
679{
680 unsigned char interrupt_line_register;
681 unsigned long j = jiffies + 1;
682 unsigned int regval;
683
684 if (card->family == FST_FAMILY_TXU) {
685 if (pci_read_config_byte
686 (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) {
687 dbg(DBG_ASS,
688 "Error in reading interrupt line register\n");
689 }
690 /*
691 * Assert PLX software reset and Am186 hardware reset
692 * and then deassert the PLX software reset but 186 still in reset
693 */
694 outw(0x440f, card->pci_conf + CNTRL_9054 + 2);
695 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
696 /*
697 * We are delaying here to allow the 9054 to reset itself
698 */
699 j = jiffies + 1;
700 while (jiffies < j)
701 /* Do nothing */ ;
702 outw(0x240f, card->pci_conf + CNTRL_9054 + 2);
703 /*
704 * We are delaying here to allow the 9054 to reload its eeprom
705 */
706 j = jiffies + 1;
707 while (jiffies < j)
708 /* Do nothing */ ;
709 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
710
711 if (pci_write_config_byte
712 (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) {
713 dbg(DBG_ASS,
714 "Error in writing interrupt line register\n");
715 }
716
717 } else {
718 regval = inl(card->pci_conf + CNTRL_9052);
719
720 outl(regval | 0x40000000, card->pci_conf + CNTRL_9052);
721 outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052);
722 }
723}
724
725/* Release the processor from reset
726 */
727static inline void
728fst_cpurelease(struct fst_card_info *card)
729{
730 if (card->family == FST_FAMILY_TXU) {
731 /*
732 * Force posted writes to complete
733 */
734 (void) readb(card->mem);
735
736 /*
737 * Release LRESET DO = 1
738 * Then release Local Hold, DO = 1
739 */
740 outw(0x040e, card->pci_conf + CNTRL_9054 + 2);
741 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
742 } else {
743 (void) readb(card->ctlmem);
744 }
745}
746
747/* Clear the cards interrupt flag
748 */
749static inline void
750fst_clear_intr(struct fst_card_info *card)
751{
752 if (card->family == FST_FAMILY_TXU) {
753 (void) readb(card->ctlmem);
754 } else {
755 /* Poke the appropriate PLX chip register (same as enabling interrupts)
756 */
757 outw(0x0543, card->pci_conf + INTCSR_9052);
758 }
759}
760
761/* Enable card interrupts
762 */
763static inline void
764fst_enable_intr(struct fst_card_info *card)
765{
766 if (card->family == FST_FAMILY_TXU) {
767 outl(0x0f0c0900, card->pci_conf + INTCSR_9054);
768 } else {
769 outw(0x0543, card->pci_conf + INTCSR_9052);
770 }
771}
772
773/* Disable card interrupts
774 */
775static inline void
776fst_disable_intr(struct fst_card_info *card)
777{
778 if (card->family == FST_FAMILY_TXU) {
779 outl(0x00000000, card->pci_conf + INTCSR_9054);
780 } else {
781 outw(0x0000, card->pci_conf + INTCSR_9052);
782 }
783}
784
785/* Process the result of trying to pass a received frame up the stack
786 */
787static void
788fst_process_rx_status(int rx_status, char *name)
789{
790 switch (rx_status) {
791 case NET_RX_SUCCESS:
792 {
793 /*
794 * Nothing to do here
795 */
796 break;
797 }
798 case NET_RX_DROP:
799 {
800 dbg(DBG_ASS, "%s: Received packet dropped\n", name);
801 break;
802 }
803 }
804}
805
806/* Initilaise DMA for PLX 9054
807 */
808static inline void
809fst_init_dma(struct fst_card_info *card)
810{
811 /*
812 * This is only required for the PLX 9054
813 */
814 if (card->family == FST_FAMILY_TXU) {
815 pci_set_master(card->device);
816 outl(0x00020441, card->pci_conf + DMAMODE0);
817 outl(0x00020441, card->pci_conf + DMAMODE1);
818 outl(0x0, card->pci_conf + DMATHR);
819 }
820}
821
822/* Tx dma complete interrupt
823 */
824static void
825fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
826 int len, int txpos)
827{
828 struct net_device *dev = port_to_dev(port);
829
830 /*
831 * Everything is now set, just tell the card to go
832 */
833 dbg(DBG_TX, "fst_tx_dma_complete\n");
834 FST_WRB(card, txDescrRing[port->index][txpos].bits,
835 DMA_OWN | TX_STP | TX_ENP);
836 dev->stats.tx_packets++;
837 dev->stats.tx_bytes += len;
838 dev->trans_start = jiffies;
839}
840
841/*
842 * Mark it for our own raw sockets interface
843 */
844static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev)
845{
846 skb->dev = dev;
847 skb_reset_mac_header(skb);
848 skb->pkt_type = PACKET_HOST;
849 return htons(ETH_P_CUST);
850}
851
852/* Rx dma complete interrupt
853 */
854static void
855fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
856 int len, struct sk_buff *skb, int rxp)
857{
858 struct net_device *dev = port_to_dev(port);
859 int pi;
860 int rx_status;
861
862 dbg(DBG_TX, "fst_rx_dma_complete\n");
863 pi = port->index;
864 memcpy(skb_put(skb, len), card->rx_dma_handle_host, len);
865
866 /* Reset buffer descriptor */
867 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
868
869 /* Update stats */
870 dev->stats.rx_packets++;
871 dev->stats.rx_bytes += len;
872
873 /* Push upstream */
874 dbg(DBG_RX, "Pushing the frame up the stack\n");
875 if (port->mode == FST_RAW)
876 skb->protocol = farsync_type_trans(skb, dev);
877 else
878 skb->protocol = hdlc_type_trans(skb, dev);
879 rx_status = netif_rx(skb);
880 fst_process_rx_status(rx_status, port_to_dev(port)->name);
881 if (rx_status == NET_RX_DROP)
882 dev->stats.rx_dropped++;
883}
884
885/*
886 * Receive a frame through the DMA
887 */
888static inline void
889fst_rx_dma(struct fst_card_info *card, dma_addr_t skb,
890 dma_addr_t mem, int len)
891{
892 /*
893 * This routine will setup the DMA and start it
894 */
895
896 dbg(DBG_RX, "In fst_rx_dma %lx %lx %d\n",
897 (unsigned long) skb, (unsigned long) mem, len);
898 if (card->dmarx_in_progress) {
899 dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n");
900 }
901
902 outl(skb, card->pci_conf + DMAPADR0); /* Copy to here */
903 outl(mem, card->pci_conf + DMALADR0); /* from here */
904 outl(len, card->pci_conf + DMASIZ0); /* for this length */
905 outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */
906
907 /*
908 * We use the dmarx_in_progress flag to flag the channel as busy
909 */
910 card->dmarx_in_progress = 1;
911 outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */
912}
913
914/*
915 * Send a frame through the DMA
916 */
917static inline void
918fst_tx_dma(struct fst_card_info *card, unsigned char *skb,
919 unsigned char *mem, int len)
920{
921 /*
922 * This routine will setup the DMA and start it.
923 */
924
925 dbg(DBG_TX, "In fst_tx_dma %p %p %d\n", skb, mem, len);
926 if (card->dmatx_in_progress) {
927 dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n");
928 }
929
930 outl((unsigned long) skb, card->pci_conf + DMAPADR1); /* Copy from here */
931 outl((unsigned long) mem, card->pci_conf + DMALADR1); /* to here */
932 outl(len, card->pci_conf + DMASIZ1); /* for this length */
933 outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */
934
935 /*
936 * We use the dmatx_in_progress to flag the channel as busy
937 */
938 card->dmatx_in_progress = 1;
939 outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */
940}
941
942/* Issue a Mailbox command for a port.
943 * Note we issue them on a fire and forget basis, not expecting to see an
944 * error and not waiting for completion.
945 */
946static void
947fst_issue_cmd(struct fst_port_info *port, unsigned short cmd)
948{
949 struct fst_card_info *card;
950 unsigned short mbval;
951 unsigned long flags;
952 int safety;
953
954 card = port->card;
955 spin_lock_irqsave(&card->card_lock, flags);
956 mbval = FST_RDW(card, portMailbox[port->index][0]);
957
958 safety = 0;
959 /* Wait for any previous command to complete */
960 while (mbval > NAK) {
961 spin_unlock_irqrestore(&card->card_lock, flags);
962 schedule_timeout_uninterruptible(1);
963 spin_lock_irqsave(&card->card_lock, flags);
964
965 if (++safety > 2000) {
966 pr_err("Mailbox safety timeout\n");
967 break;
968 }
969
970 mbval = FST_RDW(card, portMailbox[port->index][0]);
971 }
972 if (safety > 0) {
973 dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety);
974 }
975 if (mbval == NAK) {
976 dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n");
977 }
978
979 FST_WRW(card, portMailbox[port->index][0], cmd);
980
981 if (cmd == ABORTTX || cmd == STARTPORT) {
982 port->txpos = 0;
983 port->txipos = 0;
984 port->start = 0;
985 }
986
987 spin_unlock_irqrestore(&card->card_lock, flags);
988}
989
990/* Port output signals control
991 */
992static inline void
993fst_op_raise(struct fst_port_info *port, unsigned int outputs)
994{
995 outputs |= FST_RDL(port->card, v24OpSts[port->index]);
996 FST_WRL(port->card, v24OpSts[port->index], outputs);
997
998 if (port->run)
999 fst_issue_cmd(port, SETV24O);
1000}
1001
1002static inline void
1003fst_op_lower(struct fst_port_info *port, unsigned int outputs)
1004{
1005 outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]);
1006 FST_WRL(port->card, v24OpSts[port->index], outputs);
1007
1008 if (port->run)
1009 fst_issue_cmd(port, SETV24O);
1010}
1011
1012/*
1013 * Setup port Rx buffers
1014 */
1015static void
1016fst_rx_config(struct fst_port_info *port)
1017{
1018 int i;
1019 int pi;
1020 unsigned int offset;
1021 unsigned long flags;
1022 struct fst_card_info *card;
1023
1024 pi = port->index;
1025 card = port->card;
1026 spin_lock_irqsave(&card->card_lock, flags);
1027 for (i = 0; i < NUM_RX_BUFFER; i++) {
1028 offset = BUF_OFFSET(rxBuffer[pi][i][0]);
1029
1030 FST_WRW(card, rxDescrRing[pi][i].ladr, (u16) offset);
1031 FST_WRB(card, rxDescrRing[pi][i].hadr, (u8) (offset >> 16));
1032 FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER));
1033 FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER);
1034 FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN);
1035 }
1036 port->rxpos = 0;
1037 spin_unlock_irqrestore(&card->card_lock, flags);
1038}
1039
1040/*
1041 * Setup port Tx buffers
1042 */
1043static void
1044fst_tx_config(struct fst_port_info *port)
1045{
1046 int i;
1047 int pi;
1048 unsigned int offset;
1049 unsigned long flags;
1050 struct fst_card_info *card;
1051
1052 pi = port->index;
1053 card = port->card;
1054 spin_lock_irqsave(&card->card_lock, flags);
1055 for (i = 0; i < NUM_TX_BUFFER; i++) {
1056 offset = BUF_OFFSET(txBuffer[pi][i][0]);
1057
1058 FST_WRW(card, txDescrRing[pi][i].ladr, (u16) offset);
1059 FST_WRB(card, txDescrRing[pi][i].hadr, (u8) (offset >> 16));
1060 FST_WRW(card, txDescrRing[pi][i].bcnt, 0);
1061 FST_WRB(card, txDescrRing[pi][i].bits, 0);
1062 }
1063 port->txpos = 0;
1064 port->txipos = 0;
1065 port->start = 0;
1066 spin_unlock_irqrestore(&card->card_lock, flags);
1067}
1068
1069/* TE1 Alarm change interrupt event
1070 */
1071static void
1072fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port)
1073{
1074 u8 los;
1075 u8 rra;
1076 u8 ais;
1077
1078 los = FST_RDB(card, suStatus.lossOfSignal);
1079 rra = FST_RDB(card, suStatus.receiveRemoteAlarm);
1080 ais = FST_RDB(card, suStatus.alarmIndicationSignal);
1081
1082 if (los) {
1083 /*
1084 * Lost the link
1085 */
1086 if (netif_carrier_ok(port_to_dev(port))) {
1087 dbg(DBG_INTR, "Net carrier off\n");
1088 netif_carrier_off(port_to_dev(port));
1089 }
1090 } else {
1091 /*
1092 * Link available
1093 */
1094 if (!netif_carrier_ok(port_to_dev(port))) {
1095 dbg(DBG_INTR, "Net carrier on\n");
1096 netif_carrier_on(port_to_dev(port));
1097 }
1098 }
1099
1100 if (los)
1101 dbg(DBG_INTR, "Assert LOS Alarm\n");
1102 else
1103 dbg(DBG_INTR, "De-assert LOS Alarm\n");
1104 if (rra)
1105 dbg(DBG_INTR, "Assert RRA Alarm\n");
1106 else
1107 dbg(DBG_INTR, "De-assert RRA Alarm\n");
1108
1109 if (ais)
1110 dbg(DBG_INTR, "Assert AIS Alarm\n");
1111 else
1112 dbg(DBG_INTR, "De-assert AIS Alarm\n");
1113}
1114
1115/* Control signal change interrupt event
1116 */
1117static void
1118fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port)
1119{
1120 int signals;
1121
1122 signals = FST_RDL(card, v24DebouncedSts[port->index]);
1123
1124 if (signals & (((port->hwif == X21) || (port->hwif == X21D))
1125 ? IPSTS_INDICATE : IPSTS_DCD)) {
1126 if (!netif_carrier_ok(port_to_dev(port))) {
1127 dbg(DBG_INTR, "DCD active\n");
1128 netif_carrier_on(port_to_dev(port));
1129 }
1130 } else {
1131 if (netif_carrier_ok(port_to_dev(port))) {
1132 dbg(DBG_INTR, "DCD lost\n");
1133 netif_carrier_off(port_to_dev(port));
1134 }
1135 }
1136}
1137
1138/* Log Rx Errors
1139 */
1140static void
1141fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1142 unsigned char dmabits, int rxp, unsigned short len)
1143{
1144 struct net_device *dev = port_to_dev(port);
1145
1146 /*
1147 * Increment the appropriate error counter
1148 */
1149 dev->stats.rx_errors++;
1150 if (dmabits & RX_OFLO) {
1151 dev->stats.rx_fifo_errors++;
1152 dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n",
1153 card->card_no, port->index, rxp);
1154 }
1155 if (dmabits & RX_CRC) {
1156 dev->stats.rx_crc_errors++;
1157 dbg(DBG_ASS, "Rx crc error on card %d port %d\n",
1158 card->card_no, port->index);
1159 }
1160 if (dmabits & RX_FRAM) {
1161 dev->stats.rx_frame_errors++;
1162 dbg(DBG_ASS, "Rx frame error on card %d port %d\n",
1163 card->card_no, port->index);
1164 }
1165 if (dmabits == (RX_STP | RX_ENP)) {
1166 dev->stats.rx_length_errors++;
1167 dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n",
1168 len, card->card_no, port->index);
1169 }
1170}
1171
1172/* Rx Error Recovery
1173 */
1174static void
1175fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1176 unsigned char dmabits, int rxp, unsigned short len)
1177{
1178 int i;
1179 int pi;
1180
1181 pi = port->index;
1182 /*
1183 * Discard buffer descriptors until we see the start of the
1184 * next frame. Note that for long frames this could be in
1185 * a subsequent interrupt.
1186 */
1187 i = 0;
1188 while ((dmabits & (DMA_OWN | RX_STP)) == 0) {
1189 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1190 rxp = (rxp+1) % NUM_RX_BUFFER;
1191 if (++i > NUM_RX_BUFFER) {
1192 dbg(DBG_ASS, "intr_rx: Discarding more bufs"
1193 " than we have\n");
1194 break;
1195 }
1196 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1197 dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits);
1198 }
1199 dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i);
1200
1201 /* Discard the terminal buffer */
1202 if (!(dmabits & DMA_OWN)) {
1203 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1204 rxp = (rxp+1) % NUM_RX_BUFFER;
1205 }
1206 port->rxpos = rxp;
1207 return;
1208
1209}
1210
1211/* Rx complete interrupt
1212 */
1213static void
1214fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port)
1215{
1216 unsigned char dmabits;
1217 int pi;
1218 int rxp;
1219 int rx_status;
1220 unsigned short len;
1221 struct sk_buff *skb;
1222 struct net_device *dev = port_to_dev(port);
1223
1224 /* Check we have a buffer to process */
1225 pi = port->index;
1226 rxp = port->rxpos;
1227 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1228 if (dmabits & DMA_OWN) {
1229 dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n",
1230 pi, rxp);
1231 return;
1232 }
1233 if (card->dmarx_in_progress) {
1234 return;
1235 }
1236
1237 /* Get buffer length */
1238 len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt);
1239 /* Discard the CRC */
1240 len -= 2;
1241 if (len == 0) {
1242 /*
1243 * This seems to happen on the TE1 interface sometimes
1244 * so throw the frame away and log the event.
1245 */
1246 pr_err("Frame received with 0 length. Card %d Port %d\n",
1247 card->card_no, port->index);
1248 /* Return descriptor to card */
1249 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1250
1251 rxp = (rxp+1) % NUM_RX_BUFFER;
1252 port->rxpos = rxp;
1253 return;
1254 }
1255
1256 /* Check buffer length and for other errors. We insist on one packet
1257 * in one buffer. This simplifies things greatly and since we've
1258 * allocated 8K it shouldn't be a real world limitation
1259 */
1260 dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len);
1261 if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) {
1262 fst_log_rx_error(card, port, dmabits, rxp, len);
1263 fst_recover_rx_error(card, port, dmabits, rxp, len);
1264 return;
1265 }
1266
1267 /* Allocate SKB */
1268 if ((skb = dev_alloc_skb(len)) == NULL) {
1269 dbg(DBG_RX, "intr_rx: can't allocate buffer\n");
1270
1271 dev->stats.rx_dropped++;
1272
1273 /* Return descriptor to card */
1274 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1275
1276 rxp = (rxp+1) % NUM_RX_BUFFER;
1277 port->rxpos = rxp;
1278 return;
1279 }
1280
1281 /*
1282 * We know the length we need to receive, len.
1283 * It's not worth using the DMA for reads of less than
1284 * FST_MIN_DMA_LEN
1285 */
1286
1287 if ((len < FST_MIN_DMA_LEN) || (card->family == FST_FAMILY_TXP)) {
1288 memcpy_fromio(skb_put(skb, len),
1289 card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]),
1290 len);
1291
1292 /* Reset buffer descriptor */
1293 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1294
1295 /* Update stats */
1296 dev->stats.rx_packets++;
1297 dev->stats.rx_bytes += len;
1298
1299 /* Push upstream */
1300 dbg(DBG_RX, "Pushing frame up the stack\n");
1301 if (port->mode == FST_RAW)
1302 skb->protocol = farsync_type_trans(skb, dev);
1303 else
1304 skb->protocol = hdlc_type_trans(skb, dev);
1305 rx_status = netif_rx(skb);
1306 fst_process_rx_status(rx_status, port_to_dev(port)->name);
1307 if (rx_status == NET_RX_DROP)
1308 dev->stats.rx_dropped++;
1309 } else {
1310 card->dma_skb_rx = skb;
1311 card->dma_port_rx = port;
1312 card->dma_len_rx = len;
1313 card->dma_rxpos = rxp;
1314 fst_rx_dma(card, card->rx_dma_handle_card,
1315 BUF_OFFSET(rxBuffer[pi][rxp][0]), len);
1316 }
1317 if (rxp != port->rxpos) {
1318 dbg(DBG_ASS, "About to increment rxpos by more than 1\n");
1319 dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos);
1320 }
1321 rxp = (rxp+1) % NUM_RX_BUFFER;
1322 port->rxpos = rxp;
1323}
1324
1325/*
1326 * The bottom halfs to the ISR
1327 *
1328 */
1329
1330static void
1331do_bottom_half_tx(struct fst_card_info *card)
1332{
1333 struct fst_port_info *port;
1334 int pi;
1335 int txq_length;
1336 struct sk_buff *skb;
1337 unsigned long flags;
1338 struct net_device *dev;
1339
1340 /*
1341 * Find a free buffer for the transmit
1342 * Step through each port on this card
1343 */
1344
1345 dbg(DBG_TX, "do_bottom_half_tx\n");
1346 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1347 if (!port->run)
1348 continue;
1349
1350 dev = port_to_dev(port);
1351 while (!(FST_RDB(card, txDescrRing[pi][port->txpos].bits) &
1352 DMA_OWN) &&
1353 !(card->dmatx_in_progress)) {
1354 /*
1355 * There doesn't seem to be a txdone event per-se
1356 * We seem to have to deduce it, by checking the DMA_OWN
1357 * bit on the next buffer we think we can use
1358 */
1359 spin_lock_irqsave(&card->card_lock, flags);
1360 if ((txq_length = port->txqe - port->txqs) < 0) {
1361 /*
1362 * This is the case where one has wrapped and the
1363 * maths gives us a negative number
1364 */
1365 txq_length = txq_length + FST_TXQ_DEPTH;
1366 }
1367 spin_unlock_irqrestore(&card->card_lock, flags);
1368 if (txq_length > 0) {
1369 /*
1370 * There is something to send
1371 */
1372 spin_lock_irqsave(&card->card_lock, flags);
1373 skb = port->txq[port->txqs];
1374 port->txqs++;
1375 if (port->txqs == FST_TXQ_DEPTH) {
1376 port->txqs = 0;
1377 }
1378 spin_unlock_irqrestore(&card->card_lock, flags);
1379 /*
1380 * copy the data and set the required indicators on the
1381 * card.
1382 */
1383 FST_WRW(card, txDescrRing[pi][port->txpos].bcnt,
1384 cnv_bcnt(skb->len));
1385 if ((skb->len < FST_MIN_DMA_LEN) ||
1386 (card->family == FST_FAMILY_TXP)) {
1387 /* Enqueue the packet with normal io */
1388 memcpy_toio(card->mem +
1389 BUF_OFFSET(txBuffer[pi]
1390 [port->
1391 txpos][0]),
1392 skb->data, skb->len);
1393 FST_WRB(card,
1394 txDescrRing[pi][port->txpos].
1395 bits,
1396 DMA_OWN | TX_STP | TX_ENP);
1397 dev->stats.tx_packets++;
1398 dev->stats.tx_bytes += skb->len;
1399 dev->trans_start = jiffies;
1400 } else {
1401 /* Or do it through dma */
1402 memcpy(card->tx_dma_handle_host,
1403 skb->data, skb->len);
1404 card->dma_port_tx = port;
1405 card->dma_len_tx = skb->len;
1406 card->dma_txpos = port->txpos;
1407 fst_tx_dma(card,
1408 (char *) card->
1409 tx_dma_handle_card,
1410 (char *)
1411 BUF_OFFSET(txBuffer[pi]
1412 [port->txpos][0]),
1413 skb->len);
1414 }
1415 if (++port->txpos >= NUM_TX_BUFFER)
1416 port->txpos = 0;
1417 /*
1418 * If we have flow control on, can we now release it?
1419 */
1420 if (port->start) {
1421 if (txq_length < fst_txq_low) {
1422 netif_wake_queue(port_to_dev
1423 (port));
1424 port->start = 0;
1425 }
1426 }
1427 dev_kfree_skb(skb);
1428 } else {
1429 /*
1430 * Nothing to send so break out of the while loop
1431 */
1432 break;
1433 }
1434 }
1435 }
1436}
1437
1438static void
1439do_bottom_half_rx(struct fst_card_info *card)
1440{
1441 struct fst_port_info *port;
1442 int pi;
1443 int rx_count = 0;
1444
1445 /* Check for rx completions on all ports on this card */
1446 dbg(DBG_RX, "do_bottom_half_rx\n");
1447 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1448 if (!port->run)
1449 continue;
1450
1451 while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits)
1452 & DMA_OWN) && !(card->dmarx_in_progress)) {
1453 if (rx_count > fst_max_reads) {
1454 /*
1455 * Don't spend forever in receive processing
1456 * Schedule another event
1457 */
1458 fst_q_work_item(&fst_work_intq, card->card_no);
1459 tasklet_schedule(&fst_int_task);
1460 break; /* Leave the loop */
1461 }
1462 fst_intr_rx(card, port);
1463 rx_count++;
1464 }
1465 }
1466}
1467
1468/*
1469 * The interrupt service routine
1470 * Dev_id is our fst_card_info pointer
1471 */
1472static irqreturn_t
1473fst_intr(int dummy, void *dev_id)
1474{
1475 struct fst_card_info *card = dev_id;
1476 struct fst_port_info *port;
1477 int rdidx; /* Event buffer indices */
1478 int wridx;
1479 int event; /* Actual event for processing */
1480 unsigned int dma_intcsr = 0;
1481 unsigned int do_card_interrupt;
1482 unsigned int int_retry_count;
1483
1484 /*
1485 * Check to see if the interrupt was for this card
1486 * return if not
1487 * Note that the call to clear the interrupt is important
1488 */
1489 dbg(DBG_INTR, "intr: %d %p\n", card->irq, card);
1490 if (card->state != FST_RUNNING) {
1491 pr_err("Interrupt received for card %d in a non running state (%d)\n",
1492 card->card_no, card->state);
1493
1494 /*
1495 * It is possible to really be running, i.e. we have re-loaded
1496 * a running card
1497 * Clear and reprime the interrupt source
1498 */
1499 fst_clear_intr(card);
1500 return IRQ_HANDLED;
1501 }
1502
1503 /* Clear and reprime the interrupt source */
1504 fst_clear_intr(card);
1505
1506 /*
1507 * Is the interrupt for this card (handshake == 1)
1508 */
1509 do_card_interrupt = 0;
1510 if (FST_RDB(card, interruptHandshake) == 1) {
1511 do_card_interrupt += FST_CARD_INT;
1512 /* Set the software acknowledge */
1513 FST_WRB(card, interruptHandshake, 0xEE);
1514 }
1515 if (card->family == FST_FAMILY_TXU) {
1516 /*
1517 * Is it a DMA Interrupt
1518 */
1519 dma_intcsr = inl(card->pci_conf + INTCSR_9054);
1520 if (dma_intcsr & 0x00200000) {
1521 /*
1522 * DMA Channel 0 (Rx transfer complete)
1523 */
1524 dbg(DBG_RX, "DMA Rx xfer complete\n");
1525 outb(0x8, card->pci_conf + DMACSR0);
1526 fst_rx_dma_complete(card, card->dma_port_rx,
1527 card->dma_len_rx, card->dma_skb_rx,
1528 card->dma_rxpos);
1529 card->dmarx_in_progress = 0;
1530 do_card_interrupt += FST_RX_DMA_INT;
1531 }
1532 if (dma_intcsr & 0x00400000) {
1533 /*
1534 * DMA Channel 1 (Tx transfer complete)
1535 */
1536 dbg(DBG_TX, "DMA Tx xfer complete\n");
1537 outb(0x8, card->pci_conf + DMACSR1);
1538 fst_tx_dma_complete(card, card->dma_port_tx,
1539 card->dma_len_tx, card->dma_txpos);
1540 card->dmatx_in_progress = 0;
1541 do_card_interrupt += FST_TX_DMA_INT;
1542 }
1543 }
1544
1545 /*
1546 * Have we been missing Interrupts
1547 */
1548 int_retry_count = FST_RDL(card, interruptRetryCount);
1549 if (int_retry_count) {
1550 dbg(DBG_ASS, "Card %d int_retry_count is %d\n",
1551 card->card_no, int_retry_count);
1552 FST_WRL(card, interruptRetryCount, 0);
1553 }
1554
1555 if (!do_card_interrupt) {
1556 return IRQ_HANDLED;
1557 }
1558
1559 /* Scehdule the bottom half of the ISR */
1560 fst_q_work_item(&fst_work_intq, card->card_no);
1561 tasklet_schedule(&fst_int_task);
1562
1563 /* Drain the event queue */
1564 rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f;
1565 wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f;
1566 while (rdidx != wridx) {
1567 event = FST_RDB(card, interruptEvent.evntbuff[rdidx]);
1568 port = &card->ports[event & 0x03];
1569
1570 dbg(DBG_INTR, "Processing Interrupt event: %x\n", event);
1571
1572 switch (event) {
1573 case TE1_ALMA:
1574 dbg(DBG_INTR, "TE1 Alarm intr\n");
1575 if (port->run)
1576 fst_intr_te1_alarm(card, port);
1577 break;
1578
1579 case CTLA_CHG:
1580 case CTLB_CHG:
1581 case CTLC_CHG:
1582 case CTLD_CHG:
1583 if (port->run)
1584 fst_intr_ctlchg(card, port);
1585 break;
1586
1587 case ABTA_SENT:
1588 case ABTB_SENT:
1589 case ABTC_SENT:
1590 case ABTD_SENT:
1591 dbg(DBG_TX, "Abort complete port %d\n", port->index);
1592 break;
1593
1594 case TXA_UNDF:
1595 case TXB_UNDF:
1596 case TXC_UNDF:
1597 case TXD_UNDF:
1598 /* Difficult to see how we'd get this given that we
1599 * always load up the entire packet for DMA.
1600 */
1601 dbg(DBG_TX, "Tx underflow port %d\n", port->index);
1602 port_to_dev(port)->stats.tx_errors++;
1603 port_to_dev(port)->stats.tx_fifo_errors++;
1604 dbg(DBG_ASS, "Tx underflow on card %d port %d\n",
1605 card->card_no, port->index);
1606 break;
1607
1608 case INIT_CPLT:
1609 dbg(DBG_INIT, "Card init OK intr\n");
1610 break;
1611
1612 case INIT_FAIL:
1613 dbg(DBG_INIT, "Card init FAILED intr\n");
1614 card->state = FST_IFAILED;
1615 break;
1616
1617 default:
1618 pr_err("intr: unknown card event %d. ignored\n", event);
1619 break;
1620 }
1621
1622 /* Bump and wrap the index */
1623 if (++rdidx >= MAX_CIRBUFF)
1624 rdidx = 0;
1625 }
1626 FST_WRB(card, interruptEvent.rdindex, rdidx);
1627 return IRQ_HANDLED;
1628}
1629
1630/* Check that the shared memory configuration is one that we can handle
1631 * and that some basic parameters are correct
1632 */
1633static void
1634check_started_ok(struct fst_card_info *card)
1635{
1636 int i;
1637
1638 /* Check structure version and end marker */
1639 if (FST_RDW(card, smcVersion) != SMC_VERSION) {
1640 pr_err("Bad shared memory version %d expected %d\n",
1641 FST_RDW(card, smcVersion), SMC_VERSION);
1642 card->state = FST_BADVERSION;
1643 return;
1644 }
1645 if (FST_RDL(card, endOfSmcSignature) != END_SIG) {
1646 pr_err("Missing shared memory signature\n");
1647 card->state = FST_BADVERSION;
1648 return;
1649 }
1650 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */
1651 if ((i = FST_RDB(card, taskStatus)) == 0x01) {
1652 card->state = FST_RUNNING;
1653 } else if (i == 0xFF) {
1654 pr_err("Firmware initialisation failed. Card halted\n");
1655 card->state = FST_HALTED;
1656 return;
1657 } else if (i != 0x00) {
1658 pr_err("Unknown firmware status 0x%x\n", i);
1659 card->state = FST_HALTED;
1660 return;
1661 }
1662
1663 /* Finally check the number of ports reported by firmware against the
1664 * number we assumed at card detection. Should never happen with
1665 * existing firmware etc so we just report it for the moment.
1666 */
1667 if (FST_RDL(card, numberOfPorts) != card->nports) {
1668 pr_warn("Port count mismatch on card %d. Firmware thinks %d we say %d\n",
1669 card->card_no,
1670 FST_RDL(card, numberOfPorts), card->nports);
1671 }
1672}
1673
1674static int
1675set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port,
1676 struct fstioc_info *info)
1677{
1678 int err;
1679 unsigned char my_framing;
1680
1681 /* Set things according to the user set valid flags
1682 * Several of the old options have been invalidated/replaced by the
1683 * generic hdlc package.
1684 */
1685 err = 0;
1686 if (info->valid & FSTVAL_PROTO) {
1687 if (info->proto == FST_RAW)
1688 port->mode = FST_RAW;
1689 else
1690 port->mode = FST_GEN_HDLC;
1691 }
1692
1693 if (info->valid & FSTVAL_CABLE)
1694 err = -EINVAL;
1695
1696 if (info->valid & FSTVAL_SPEED)
1697 err = -EINVAL;
1698
1699 if (info->valid & FSTVAL_PHASE)
1700 FST_WRB(card, portConfig[port->index].invertClock,
1701 info->invertClock);
1702 if (info->valid & FSTVAL_MODE)
1703 FST_WRW(card, cardMode, info->cardMode);
1704 if (info->valid & FSTVAL_TE1) {
1705 FST_WRL(card, suConfig.dataRate, info->lineSpeed);
1706 FST_WRB(card, suConfig.clocking, info->clockSource);
1707 my_framing = FRAMING_E1;
1708 if (info->framing == E1)
1709 my_framing = FRAMING_E1;
1710 if (info->framing == T1)
1711 my_framing = FRAMING_T1;
1712 if (info->framing == J1)
1713 my_framing = FRAMING_J1;
1714 FST_WRB(card, suConfig.framing, my_framing);
1715 FST_WRB(card, suConfig.structure, info->structure);
1716 FST_WRB(card, suConfig.interface, info->interface);
1717 FST_WRB(card, suConfig.coding, info->coding);
1718 FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut);
1719 FST_WRB(card, suConfig.equalizer, info->equalizer);
1720 FST_WRB(card, suConfig.transparentMode, info->transparentMode);
1721 FST_WRB(card, suConfig.loopMode, info->loopMode);
1722 FST_WRB(card, suConfig.range, info->range);
1723 FST_WRB(card, suConfig.txBufferMode, info->txBufferMode);
1724 FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode);
1725 FST_WRB(card, suConfig.startingSlot, info->startingSlot);
1726 FST_WRB(card, suConfig.losThreshold, info->losThreshold);
1727 if (info->idleCode)
1728 FST_WRB(card, suConfig.enableIdleCode, 1);
1729 else
1730 FST_WRB(card, suConfig.enableIdleCode, 0);
1731 FST_WRB(card, suConfig.idleCode, info->idleCode);
1732#if FST_DEBUG
1733 if (info->valid & FSTVAL_TE1) {
1734 printk("Setting TE1 data\n");
1735 printk("Line Speed = %d\n", info->lineSpeed);
1736 printk("Start slot = %d\n", info->startingSlot);
1737 printk("Clock source = %d\n", info->clockSource);
1738 printk("Framing = %d\n", my_framing);
1739 printk("Structure = %d\n", info->structure);
1740 printk("interface = %d\n", info->interface);
1741 printk("Coding = %d\n", info->coding);
1742 printk("Line build out = %d\n", info->lineBuildOut);
1743 printk("Equaliser = %d\n", info->equalizer);
1744 printk("Transparent mode = %d\n",
1745 info->transparentMode);
1746 printk("Loop mode = %d\n", info->loopMode);
1747 printk("Range = %d\n", info->range);
1748 printk("Tx Buffer mode = %d\n", info->txBufferMode);
1749 printk("Rx Buffer mode = %d\n", info->rxBufferMode);
1750 printk("LOS Threshold = %d\n", info->losThreshold);
1751 printk("Idle Code = %d\n", info->idleCode);
1752 }
1753#endif
1754 }
1755#if FST_DEBUG
1756 if (info->valid & FSTVAL_DEBUG) {
1757 fst_debug_mask = info->debug;
1758 }
1759#endif
1760
1761 return err;
1762}
1763
1764static void
1765gather_conf_info(struct fst_card_info *card, struct fst_port_info *port,
1766 struct fstioc_info *info)
1767{
1768 int i;
1769
1770 memset(info, 0, sizeof (struct fstioc_info));
1771
1772 i = port->index;
1773 info->kernelVersion = LINUX_VERSION_CODE;
1774 info->nports = card->nports;
1775 info->type = card->type;
1776 info->state = card->state;
1777 info->proto = FST_GEN_HDLC;
1778 info->index = i;
1779#if FST_DEBUG
1780 info->debug = fst_debug_mask;
1781#endif
1782
1783 /* Only mark information as valid if card is running.
1784 * Copy the data anyway in case it is useful for diagnostics
1785 */
1786 info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD)
1787#if FST_DEBUG
1788 | FSTVAL_DEBUG
1789#endif
1790 ;
1791
1792 info->lineInterface = FST_RDW(card, portConfig[i].lineInterface);
1793 info->internalClock = FST_RDB(card, portConfig[i].internalClock);
1794 info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed);
1795 info->invertClock = FST_RDB(card, portConfig[i].invertClock);
1796 info->v24IpSts = FST_RDL(card, v24IpSts[i]);
1797 info->v24OpSts = FST_RDL(card, v24OpSts[i]);
1798 info->clockStatus = FST_RDW(card, clockStatus[i]);
1799 info->cableStatus = FST_RDW(card, cableStatus);
1800 info->cardMode = FST_RDW(card, cardMode);
1801 info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion);
1802
1803 /*
1804 * The T2U can report cable presence for both A or B
1805 * in bits 0 and 1 of cableStatus. See which port we are and
1806 * do the mapping.
1807 */
1808 if (card->family == FST_FAMILY_TXU) {
1809 if (port->index == 0) {
1810 /*
1811 * Port A
1812 */
1813 info->cableStatus = info->cableStatus & 1;
1814 } else {
1815 /*
1816 * Port B
1817 */
1818 info->cableStatus = info->cableStatus >> 1;
1819 info->cableStatus = info->cableStatus & 1;
1820 }
1821 }
1822 /*
1823 * Some additional bits if we are TE1
1824 */
1825 if (card->type == FST_TYPE_TE1) {
1826 info->lineSpeed = FST_RDL(card, suConfig.dataRate);
1827 info->clockSource = FST_RDB(card, suConfig.clocking);
1828 info->framing = FST_RDB(card, suConfig.framing);
1829 info->structure = FST_RDB(card, suConfig.structure);
1830 info->interface = FST_RDB(card, suConfig.interface);
1831 info->coding = FST_RDB(card, suConfig.coding);
1832 info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut);
1833 info->equalizer = FST_RDB(card, suConfig.equalizer);
1834 info->loopMode = FST_RDB(card, suConfig.loopMode);
1835 info->range = FST_RDB(card, suConfig.range);
1836 info->txBufferMode = FST_RDB(card, suConfig.txBufferMode);
1837 info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode);
1838 info->startingSlot = FST_RDB(card, suConfig.startingSlot);
1839 info->losThreshold = FST_RDB(card, suConfig.losThreshold);
1840 if (FST_RDB(card, suConfig.enableIdleCode))
1841 info->idleCode = FST_RDB(card, suConfig.idleCode);
1842 else
1843 info->idleCode = 0;
1844 info->receiveBufferDelay =
1845 FST_RDL(card, suStatus.receiveBufferDelay);
1846 info->framingErrorCount =
1847 FST_RDL(card, suStatus.framingErrorCount);
1848 info->codeViolationCount =
1849 FST_RDL(card, suStatus.codeViolationCount);
1850 info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount);
1851 info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation);
1852 info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal);
1853 info->receiveRemoteAlarm =
1854 FST_RDB(card, suStatus.receiveRemoteAlarm);
1855 info->alarmIndicationSignal =
1856 FST_RDB(card, suStatus.alarmIndicationSignal);
1857 }
1858}
1859
1860static int
1861fst_set_iface(struct fst_card_info *card, struct fst_port_info *port,
1862 struct ifreq *ifr)
1863{
1864 sync_serial_settings sync;
1865 int i;
1866
1867 if (ifr->ifr_settings.size != sizeof (sync)) {
1868 return -ENOMEM;
1869 }
1870
1871 if (copy_from_user
1872 (&sync, ifr->ifr_settings.ifs_ifsu.sync, sizeof (sync))) {
1873 return -EFAULT;
1874 }
1875
1876 if (sync.loopback)
1877 return -EINVAL;
1878
1879 i = port->index;
1880
1881 switch (ifr->ifr_settings.type) {
1882 case IF_IFACE_V35:
1883 FST_WRW(card, portConfig[i].lineInterface, V35);
1884 port->hwif = V35;
1885 break;
1886
1887 case IF_IFACE_V24:
1888 FST_WRW(card, portConfig[i].lineInterface, V24);
1889 port->hwif = V24;
1890 break;
1891
1892 case IF_IFACE_X21:
1893 FST_WRW(card, portConfig[i].lineInterface, X21);
1894 port->hwif = X21;
1895 break;
1896
1897 case IF_IFACE_X21D:
1898 FST_WRW(card, portConfig[i].lineInterface, X21D);
1899 port->hwif = X21D;
1900 break;
1901
1902 case IF_IFACE_T1:
1903 FST_WRW(card, portConfig[i].lineInterface, T1);
1904 port->hwif = T1;
1905 break;
1906
1907 case IF_IFACE_E1:
1908 FST_WRW(card, portConfig[i].lineInterface, E1);
1909 port->hwif = E1;
1910 break;
1911
1912 case IF_IFACE_SYNC_SERIAL:
1913 break;
1914
1915 default:
1916 return -EINVAL;
1917 }
1918
1919 switch (sync.clock_type) {
1920 case CLOCK_EXT:
1921 FST_WRB(card, portConfig[i].internalClock, EXTCLK);
1922 break;
1923
1924 case CLOCK_INT:
1925 FST_WRB(card, portConfig[i].internalClock, INTCLK);
1926 break;
1927
1928 default:
1929 return -EINVAL;
1930 }
1931 FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate);
1932 return 0;
1933}
1934
1935static int
1936fst_get_iface(struct fst_card_info *card, struct fst_port_info *port,
1937 struct ifreq *ifr)
1938{
1939 sync_serial_settings sync;
1940 int i;
1941
1942 /* First check what line type is set, we'll default to reporting X.21
1943 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be
1944 * changed
1945 */
1946 switch (port->hwif) {
1947 case E1:
1948 ifr->ifr_settings.type = IF_IFACE_E1;
1949 break;
1950 case T1:
1951 ifr->ifr_settings.type = IF_IFACE_T1;
1952 break;
1953 case V35:
1954 ifr->ifr_settings.type = IF_IFACE_V35;
1955 break;
1956 case V24:
1957 ifr->ifr_settings.type = IF_IFACE_V24;
1958 break;
1959 case X21D:
1960 ifr->ifr_settings.type = IF_IFACE_X21D;
1961 break;
1962 case X21:
1963 default:
1964 ifr->ifr_settings.type = IF_IFACE_X21;
1965 break;
1966 }
1967 if (ifr->ifr_settings.size == 0) {
1968 return 0; /* only type requested */
1969 }
1970 if (ifr->ifr_settings.size < sizeof (sync)) {
1971 return -ENOMEM;
1972 }
1973
1974 i = port->index;
1975 memset(&sync, 0, sizeof(sync));
1976 sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed);
1977 /* Lucky card and linux use same encoding here */
1978 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) ==
1979 INTCLK ? CLOCK_INT : CLOCK_EXT;
1980 sync.loopback = 0;
1981
1982 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &sync, sizeof (sync))) {
1983 return -EFAULT;
1984 }
1985
1986 ifr->ifr_settings.size = sizeof (sync);
1987 return 0;
1988}
1989
1990static int
1991fst_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1992{
1993 struct fst_card_info *card;
1994 struct fst_port_info *port;
1995 struct fstioc_write wrthdr;
1996 struct fstioc_info info;
1997 unsigned long flags;
1998 void *buf;
1999
2000 dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, ifr->ifr_data);
2001
2002 port = dev_to_port(dev);
2003 card = port->card;
2004
2005 if (!capable(CAP_NET_ADMIN))
2006 return -EPERM;
2007
2008 switch (cmd) {
2009 case FSTCPURESET:
2010 fst_cpureset(card);
2011 card->state = FST_RESET;
2012 return 0;
2013
2014 case FSTCPURELEASE:
2015 fst_cpurelease(card);
2016 card->state = FST_STARTING;
2017 return 0;
2018
2019 case FSTWRITE: /* Code write (download) */
2020
2021 /* First copy in the header with the length and offset of data
2022 * to write
2023 */
2024 if (ifr->ifr_data == NULL) {
2025 return -EINVAL;
2026 }
2027 if (copy_from_user(&wrthdr, ifr->ifr_data,
2028 sizeof (struct fstioc_write))) {
2029 return -EFAULT;
2030 }
2031
2032 /* Sanity check the parameters. We don't support partial writes
2033 * when going over the top
2034 */
2035 if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE ||
2036 wrthdr.size + wrthdr.offset > FST_MEMSIZE) {
2037 return -ENXIO;
2038 }
2039
2040 /* Now copy the data to the card. */
2041
2042 buf = memdup_user(ifr->ifr_data + sizeof(struct fstioc_write),
2043 wrthdr.size);
2044 if (IS_ERR(buf))
2045 return PTR_ERR(buf);
2046
2047 memcpy_toio(card->mem + wrthdr.offset, buf, wrthdr.size);
2048 kfree(buf);
2049
2050 /* Writes to the memory of a card in the reset state constitute
2051 * a download
2052 */
2053 if (card->state == FST_RESET) {
2054 card->state = FST_DOWNLOAD;
2055 }
2056 return 0;
2057
2058 case FSTGETCONF:
2059
2060 /* If card has just been started check the shared memory config
2061 * version and marker
2062 */
2063 if (card->state == FST_STARTING) {
2064 check_started_ok(card);
2065
2066 /* If everything checked out enable card interrupts */
2067 if (card->state == FST_RUNNING) {
2068 spin_lock_irqsave(&card->card_lock, flags);
2069 fst_enable_intr(card);
2070 FST_WRB(card, interruptHandshake, 0xEE);
2071 spin_unlock_irqrestore(&card->card_lock, flags);
2072 }
2073 }
2074
2075 if (ifr->ifr_data == NULL) {
2076 return -EINVAL;
2077 }
2078
2079 gather_conf_info(card, port, &info);
2080
2081 if (copy_to_user(ifr->ifr_data, &info, sizeof (info))) {
2082 return -EFAULT;
2083 }
2084 return 0;
2085
2086 case FSTSETCONF:
2087
2088 /*
2089 * Most of the settings have been moved to the generic ioctls
2090 * this just covers debug and board ident now
2091 */
2092
2093 if (card->state != FST_RUNNING) {
2094 pr_err("Attempt to configure card %d in non-running state (%d)\n",
2095 card->card_no, card->state);
2096 return -EIO;
2097 }
2098 if (copy_from_user(&info, ifr->ifr_data, sizeof (info))) {
2099 return -EFAULT;
2100 }
2101
2102 return set_conf_from_info(card, port, &info);
2103
2104 case SIOCWANDEV:
2105 switch (ifr->ifr_settings.type) {
2106 case IF_GET_IFACE:
2107 return fst_get_iface(card, port, ifr);
2108
2109 case IF_IFACE_SYNC_SERIAL:
2110 case IF_IFACE_V35:
2111 case IF_IFACE_V24:
2112 case IF_IFACE_X21:
2113 case IF_IFACE_X21D:
2114 case IF_IFACE_T1:
2115 case IF_IFACE_E1:
2116 return fst_set_iface(card, port, ifr);
2117
2118 case IF_PROTO_RAW:
2119 port->mode = FST_RAW;
2120 return 0;
2121
2122 case IF_GET_PROTO:
2123 if (port->mode == FST_RAW) {
2124 ifr->ifr_settings.type = IF_PROTO_RAW;
2125 return 0;
2126 }
2127 return hdlc_ioctl(dev, ifr, cmd);
2128
2129 default:
2130 port->mode = FST_GEN_HDLC;
2131 dbg(DBG_IOCTL, "Passing this type to hdlc %x\n",
2132 ifr->ifr_settings.type);
2133 return hdlc_ioctl(dev, ifr, cmd);
2134 }
2135
2136 default:
2137 /* Not one of ours. Pass through to HDLC package */
2138 return hdlc_ioctl(dev, ifr, cmd);
2139 }
2140}
2141
2142static void
2143fst_openport(struct fst_port_info *port)
2144{
2145 int signals;
2146 int txq_length;
2147
2148 /* Only init things if card is actually running. This allows open to
2149 * succeed for downloads etc.
2150 */
2151 if (port->card->state == FST_RUNNING) {
2152 if (port->run) {
2153 dbg(DBG_OPEN, "open: found port already running\n");
2154
2155 fst_issue_cmd(port, STOPPORT);
2156 port->run = 0;
2157 }
2158
2159 fst_rx_config(port);
2160 fst_tx_config(port);
2161 fst_op_raise(port, OPSTS_RTS | OPSTS_DTR);
2162
2163 fst_issue_cmd(port, STARTPORT);
2164 port->run = 1;
2165
2166 signals = FST_RDL(port->card, v24DebouncedSts[port->index]);
2167 if (signals & (((port->hwif == X21) || (port->hwif == X21D))
2168 ? IPSTS_INDICATE : IPSTS_DCD))
2169 netif_carrier_on(port_to_dev(port));
2170 else
2171 netif_carrier_off(port_to_dev(port));
2172
2173 txq_length = port->txqe - port->txqs;
2174 port->txqe = 0;
2175 port->txqs = 0;
2176 }
2177
2178}
2179
2180static void
2181fst_closeport(struct fst_port_info *port)
2182{
2183 if (port->card->state == FST_RUNNING) {
2184 if (port->run) {
2185 port->run = 0;
2186 fst_op_lower(port, OPSTS_RTS | OPSTS_DTR);
2187
2188 fst_issue_cmd(port, STOPPORT);
2189 } else {
2190 dbg(DBG_OPEN, "close: port not running\n");
2191 }
2192 }
2193}
2194
2195static int
2196fst_open(struct net_device *dev)
2197{
2198 int err;
2199 struct fst_port_info *port;
2200
2201 port = dev_to_port(dev);
2202 if (!try_module_get(THIS_MODULE))
2203 return -EBUSY;
2204
2205 if (port->mode != FST_RAW) {
2206 err = hdlc_open(dev);
2207 if (err) {
2208 module_put(THIS_MODULE);
2209 return err;
2210 }
2211 }
2212
2213 fst_openport(port);
2214 netif_wake_queue(dev);
2215 return 0;
2216}
2217
2218static int
2219fst_close(struct net_device *dev)
2220{
2221 struct fst_port_info *port;
2222 struct fst_card_info *card;
2223 unsigned char tx_dma_done;
2224 unsigned char rx_dma_done;
2225
2226 port = dev_to_port(dev);
2227 card = port->card;
2228
2229 tx_dma_done = inb(card->pci_conf + DMACSR1);
2230 rx_dma_done = inb(card->pci_conf + DMACSR0);
2231 dbg(DBG_OPEN,
2232 "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n",
2233 card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress,
2234 rx_dma_done);
2235
2236 netif_stop_queue(dev);
2237 fst_closeport(dev_to_port(dev));
2238 if (port->mode != FST_RAW) {
2239 hdlc_close(dev);
2240 }
2241 module_put(THIS_MODULE);
2242 return 0;
2243}
2244
2245static int
2246fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity)
2247{
2248 /*
2249 * Setting currently fixed in FarSync card so we check and forget
2250 */
2251 if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT)
2252 return -EINVAL;
2253 return 0;
2254}
2255
2256static void
2257fst_tx_timeout(struct net_device *dev)
2258{
2259 struct fst_port_info *port;
2260 struct fst_card_info *card;
2261
2262 port = dev_to_port(dev);
2263 card = port->card;
2264 dev->stats.tx_errors++;
2265 dev->stats.tx_aborted_errors++;
2266 dbg(DBG_ASS, "Tx timeout card %d port %d\n",
2267 card->card_no, port->index);
2268 fst_issue_cmd(port, ABORTTX);
2269
2270 dev->trans_start = jiffies;
2271 netif_wake_queue(dev);
2272 port->start = 0;
2273}
2274
2275static netdev_tx_t
2276fst_start_xmit(struct sk_buff *skb, struct net_device *dev)
2277{
2278 struct fst_card_info *card;
2279 struct fst_port_info *port;
2280 unsigned long flags;
2281 int txq_length;
2282
2283 port = dev_to_port(dev);
2284 card = port->card;
2285 dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len);
2286
2287 /* Drop packet with error if we don't have carrier */
2288 if (!netif_carrier_ok(dev)) {
2289 dev_kfree_skb(skb);
2290 dev->stats.tx_errors++;
2291 dev->stats.tx_carrier_errors++;
2292 dbg(DBG_ASS,
2293 "Tried to transmit but no carrier on card %d port %d\n",
2294 card->card_no, port->index);
2295 return NETDEV_TX_OK;
2296 }
2297
2298 /* Drop it if it's too big! MTU failure ? */
2299 if (skb->len > LEN_TX_BUFFER) {
2300 dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len,
2301 LEN_TX_BUFFER);
2302 dev_kfree_skb(skb);
2303 dev->stats.tx_errors++;
2304 return NETDEV_TX_OK;
2305 }
2306
2307 /*
2308 * We are always going to queue the packet
2309 * so that the bottom half is the only place we tx from
2310 * Check there is room in the port txq
2311 */
2312 spin_lock_irqsave(&card->card_lock, flags);
2313 if ((txq_length = port->txqe - port->txqs) < 0) {
2314 /*
2315 * This is the case where the next free has wrapped but the
2316 * last used hasn't
2317 */
2318 txq_length = txq_length + FST_TXQ_DEPTH;
2319 }
2320 spin_unlock_irqrestore(&card->card_lock, flags);
2321 if (txq_length > fst_txq_high) {
2322 /*
2323 * We have got enough buffers in the pipeline. Ask the network
2324 * layer to stop sending frames down
2325 */
2326 netif_stop_queue(dev);
2327 port->start = 1; /* I'm using this to signal stop sent up */
2328 }
2329
2330 if (txq_length == FST_TXQ_DEPTH - 1) {
2331 /*
2332 * This shouldn't have happened but such is life
2333 */
2334 dev_kfree_skb(skb);
2335 dev->stats.tx_errors++;
2336 dbg(DBG_ASS, "Tx queue overflow card %d port %d\n",
2337 card->card_no, port->index);
2338 return NETDEV_TX_OK;
2339 }
2340
2341 /*
2342 * queue the buffer
2343 */
2344 spin_lock_irqsave(&card->card_lock, flags);
2345 port->txq[port->txqe] = skb;
2346 port->txqe++;
2347 if (port->txqe == FST_TXQ_DEPTH)
2348 port->txqe = 0;
2349 spin_unlock_irqrestore(&card->card_lock, flags);
2350
2351 /* Scehdule the bottom half which now does transmit processing */
2352 fst_q_work_item(&fst_work_txq, card->card_no);
2353 tasklet_schedule(&fst_tx_task);
2354
2355 return NETDEV_TX_OK;
2356}
2357
2358/*
2359 * Card setup having checked hardware resources.
2360 * Should be pretty bizarre if we get an error here (kernel memory
2361 * exhaustion is one possibility). If we do see a problem we report it
2362 * via a printk and leave the corresponding interface and all that follow
2363 * disabled.
2364 */
2365static char *type_strings[] = {
2366 "no hardware", /* Should never be seen */
2367 "FarSync T2P",
2368 "FarSync T4P",
2369 "FarSync T1U",
2370 "FarSync T2U",
2371 "FarSync T4U",
2372 "FarSync TE1"
2373};
2374
2375static void
2376fst_init_card(struct fst_card_info *card)
2377{
2378 int i;
2379 int err;
2380
2381 /* We're working on a number of ports based on the card ID. If the
2382 * firmware detects something different later (should never happen)
2383 * we'll have to revise it in some way then.
2384 */
2385 for (i = 0; i < card->nports; i++) {
2386 err = register_hdlc_device(card->ports[i].dev);
2387 if (err < 0) {
2388 int j;
2389 pr_err("Cannot register HDLC device for port %d (errno %d)\n",
2390 i, -err);
2391 for (j = i; j < card->nports; j++) {
2392 free_netdev(card->ports[j].dev);
2393 card->ports[j].dev = NULL;
2394 }
2395 card->nports = i;
2396 break;
2397 }
2398 }
2399
2400 pr_info("%s-%s: %s IRQ%d, %d ports\n",
2401 port_to_dev(&card->ports[0])->name,
2402 port_to_dev(&card->ports[card->nports - 1])->name,
2403 type_strings[card->type], card->irq, card->nports);
2404}
2405
2406static const struct net_device_ops fst_ops = {
2407 .ndo_open = fst_open,
2408 .ndo_stop = fst_close,
2409 .ndo_change_mtu = hdlc_change_mtu,
2410 .ndo_start_xmit = hdlc_start_xmit,
2411 .ndo_do_ioctl = fst_ioctl,
2412 .ndo_tx_timeout = fst_tx_timeout,
2413};
2414
2415/*
2416 * Initialise card when detected.
2417 * Returns 0 to indicate success, or errno otherwise.
2418 */
2419static int
2420fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2421{
2422 static int no_of_cards_added = 0;
2423 struct fst_card_info *card;
2424 int err = 0;
2425 int i;
2426
2427 printk_once(KERN_INFO
2428 pr_fmt("FarSync WAN driver " FST_USER_VERSION
2429 " (c) 2001-2004 FarSite Communications Ltd.\n"));
2430#if FST_DEBUG
2431 dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask);
2432#endif
2433 /*
2434 * We are going to be clever and allow certain cards not to be
2435 * configured. An exclude list can be provided in /etc/modules.conf
2436 */
2437 if (fst_excluded_cards != 0) {
2438 /*
2439 * There are cards to exclude
2440 *
2441 */
2442 for (i = 0; i < fst_excluded_cards; i++) {
2443 if ((pdev->devfn) >> 3 == fst_excluded_list[i]) {
2444 pr_info("FarSync PCI device %d not assigned\n",
2445 (pdev->devfn) >> 3);
2446 return -EBUSY;
2447 }
2448 }
2449 }
2450
2451 /* Allocate driver private data */
2452 card = kzalloc(sizeof(struct fst_card_info), GFP_KERNEL);
2453 if (card == NULL)
2454 return -ENOMEM;
2455
2456 /* Try to enable the device */
2457 if ((err = pci_enable_device(pdev)) != 0) {
2458 pr_err("Failed to enable card. Err %d\n", -err);
2459 kfree(card);
2460 return err;
2461 }
2462
2463 if ((err = pci_request_regions(pdev, "FarSync")) !=0) {
2464 pr_err("Failed to allocate regions. Err %d\n", -err);
2465 pci_disable_device(pdev);
2466 kfree(card);
2467 return err;
2468 }
2469
2470 /* Get virtual addresses of memory regions */
2471 card->pci_conf = pci_resource_start(pdev, 1);
2472 card->phys_mem = pci_resource_start(pdev, 2);
2473 card->phys_ctlmem = pci_resource_start(pdev, 3);
2474 if ((card->mem = ioremap(card->phys_mem, FST_MEMSIZE)) == NULL) {
2475 pr_err("Physical memory remap failed\n");
2476 pci_release_regions(pdev);
2477 pci_disable_device(pdev);
2478 kfree(card);
2479 return -ENODEV;
2480 }
2481 if ((card->ctlmem = ioremap(card->phys_ctlmem, 0x10)) == NULL) {
2482 pr_err("Control memory remap failed\n");
2483 pci_release_regions(pdev);
2484 pci_disable_device(pdev);
2485 iounmap(card->mem);
2486 kfree(card);
2487 return -ENODEV;
2488 }
2489 dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem);
2490
2491 /* Register the interrupt handler */
2492 if (request_irq(pdev->irq, fst_intr, IRQF_SHARED, FST_DEV_NAME, card)) {
2493 pr_err("Unable to register interrupt %d\n", card->irq);
2494 pci_release_regions(pdev);
2495 pci_disable_device(pdev);
2496 iounmap(card->ctlmem);
2497 iounmap(card->mem);
2498 kfree(card);
2499 return -ENODEV;
2500 }
2501
2502 /* Record info we need */
2503 card->irq = pdev->irq;
2504 card->type = ent->driver_data;
2505 card->family = ((ent->driver_data == FST_TYPE_T2P) ||
2506 (ent->driver_data == FST_TYPE_T4P))
2507 ? FST_FAMILY_TXP : FST_FAMILY_TXU;
2508 if ((ent->driver_data == FST_TYPE_T1U) ||
2509 (ent->driver_data == FST_TYPE_TE1))
2510 card->nports = 1;
2511 else
2512 card->nports = ((ent->driver_data == FST_TYPE_T2P) ||
2513 (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4;
2514
2515 card->state = FST_UNINIT;
2516 spin_lock_init ( &card->card_lock );
2517
2518 for ( i = 0 ; i < card->nports ; i++ ) {
2519 struct net_device *dev = alloc_hdlcdev(&card->ports[i]);
2520 hdlc_device *hdlc;
2521 if (!dev) {
2522 while (i--)
2523 free_netdev(card->ports[i].dev);
2524 pr_err("FarSync: out of memory\n");
2525 free_irq(card->irq, card);
2526 pci_release_regions(pdev);
2527 pci_disable_device(pdev);
2528 iounmap(card->ctlmem);
2529 iounmap(card->mem);
2530 kfree(card);
2531 return -ENODEV;
2532 }
2533 card->ports[i].dev = dev;
2534 card->ports[i].card = card;
2535 card->ports[i].index = i;
2536 card->ports[i].run = 0;
2537
2538 hdlc = dev_to_hdlc(dev);
2539
2540 /* Fill in the net device info */
2541 /* Since this is a PCI setup this is purely
2542 * informational. Give them the buffer addresses
2543 * and basic card I/O.
2544 */
2545 dev->mem_start = card->phys_mem
2546 + BUF_OFFSET ( txBuffer[i][0][0]);
2547 dev->mem_end = card->phys_mem
2548 + BUF_OFFSET ( txBuffer[i][NUM_TX_BUFFER][0]);
2549 dev->base_addr = card->pci_conf;
2550 dev->irq = card->irq;
2551
2552 dev->netdev_ops = &fst_ops;
2553 dev->tx_queue_len = FST_TX_QUEUE_LEN;
2554 dev->watchdog_timeo = FST_TX_TIMEOUT;
2555 hdlc->attach = fst_attach;
2556 hdlc->xmit = fst_start_xmit;
2557 }
2558
2559 card->device = pdev;
2560
2561 dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type,
2562 card->nports, card->irq);
2563 dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n",
2564 card->pci_conf, card->phys_mem, card->phys_ctlmem);
2565
2566 /* Reset the card's processor */
2567 fst_cpureset(card);
2568 card->state = FST_RESET;
2569
2570 /* Initialise DMA (if required) */
2571 fst_init_dma(card);
2572
2573 /* Record driver data for later use */
2574 pci_set_drvdata(pdev, card);
2575
2576 /* Remainder of card setup */
2577 fst_card_array[no_of_cards_added] = card;
2578 card->card_no = no_of_cards_added++; /* Record instance and bump it */
2579 fst_init_card(card);
2580 if (card->family == FST_FAMILY_TXU) {
2581 /*
2582 * Allocate a dma buffer for transmit and receives
2583 */
2584 card->rx_dma_handle_host =
2585 pci_alloc_consistent(card->device, FST_MAX_MTU,
2586 &card->rx_dma_handle_card);
2587 if (card->rx_dma_handle_host == NULL) {
2588 pr_err("Could not allocate rx dma buffer\n");
2589 fst_disable_intr(card);
2590 pci_release_regions(pdev);
2591 pci_disable_device(pdev);
2592 iounmap(card->ctlmem);
2593 iounmap(card->mem);
2594 kfree(card);
2595 return -ENOMEM;
2596 }
2597 card->tx_dma_handle_host =
2598 pci_alloc_consistent(card->device, FST_MAX_MTU,
2599 &card->tx_dma_handle_card);
2600 if (card->tx_dma_handle_host == NULL) {
2601 pr_err("Could not allocate tx dma buffer\n");
2602 fst_disable_intr(card);
2603 pci_release_regions(pdev);
2604 pci_disable_device(pdev);
2605 iounmap(card->ctlmem);
2606 iounmap(card->mem);
2607 kfree(card);
2608 return -ENOMEM;
2609 }
2610 }
2611 return 0; /* Success */
2612}
2613
2614/*
2615 * Cleanup and close down a card
2616 */
2617static void
2618fst_remove_one(struct pci_dev *pdev)
2619{
2620 struct fst_card_info *card;
2621 int i;
2622
2623 card = pci_get_drvdata(pdev);
2624
2625 for (i = 0; i < card->nports; i++) {
2626 struct net_device *dev = port_to_dev(&card->ports[i]);
2627 unregister_hdlc_device(dev);
2628 }
2629
2630 fst_disable_intr(card);
2631 free_irq(card->irq, card);
2632
2633 iounmap(card->ctlmem);
2634 iounmap(card->mem);
2635 pci_release_regions(pdev);
2636 if (card->family == FST_FAMILY_TXU) {
2637 /*
2638 * Free dma buffers
2639 */
2640 pci_free_consistent(card->device, FST_MAX_MTU,
2641 card->rx_dma_handle_host,
2642 card->rx_dma_handle_card);
2643 pci_free_consistent(card->device, FST_MAX_MTU,
2644 card->tx_dma_handle_host,
2645 card->tx_dma_handle_card);
2646 }
2647 fst_card_array[card->card_no] = NULL;
2648}
2649
2650static struct pci_driver fst_driver = {
2651 .name = FST_NAME,
2652 .id_table = fst_pci_dev_id,
2653 .probe = fst_add_one,
2654 .remove = fst_remove_one,
2655 .suspend = NULL,
2656 .resume = NULL,
2657};
2658
2659static int __init
2660fst_init(void)
2661{
2662 int i;
2663
2664 for (i = 0; i < FST_MAX_CARDS; i++)
2665 fst_card_array[i] = NULL;
2666 spin_lock_init(&fst_work_q_lock);
2667 return pci_register_driver(&fst_driver);
2668}
2669
2670static void __exit
2671fst_cleanup_module(void)
2672{
2673 pr_info("FarSync WAN driver unloading\n");
2674 pci_unregister_driver(&fst_driver);
2675}
2676
2677module_init(fst_init);
2678module_exit(fst_cleanup_module);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * FarSync WAN driver for Linux (2.6.x kernel version)
4 *
5 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
6 *
7 * Copyright (C) 2001-2004 FarSite Communications Ltd.
8 * www.farsite.co.uk
9 *
10 * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk>
11 * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk>
12 */
13
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/version.h>
19#include <linux/pci.h>
20#include <linux/sched.h>
21#include <linux/slab.h>
22#include <linux/ioport.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/delay.h>
26#include <linux/if.h>
27#include <linux/hdlc.h>
28#include <asm/io.h>
29#include <linux/uaccess.h>
30
31#include "farsync.h"
32
33/*
34 * Module info
35 */
36MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>");
37MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
38MODULE_LICENSE("GPL");
39
40/* Driver configuration and global parameters
41 * ==========================================
42 */
43
44/* Number of ports (per card) and cards supported
45 */
46#define FST_MAX_PORTS 4
47#define FST_MAX_CARDS 32
48
49/* Default parameters for the link
50 */
51#define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is
52 * useful */
53#define FST_TXQ_DEPTH 16 /* This one is for the buffering
54 * of frames on the way down to the card
55 * so that we can keep the card busy
56 * and maximise throughput
57 */
58#define FST_HIGH_WATER_MARK 12 /* Point at which we flow control
59 * network layer */
60#define FST_LOW_WATER_MARK 8 /* Point at which we remove flow
61 * control from network layer */
62#define FST_MAX_MTU 8000 /* Huge but possible */
63#define FST_DEF_MTU 1500 /* Common sane value */
64
65#define FST_TX_TIMEOUT (2*HZ)
66
67#ifdef ARPHRD_RAWHDLC
68#define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */
69#else
70#define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */
71#endif
72
73/*
74 * Modules parameters and associated variables
75 */
76static int fst_txq_low = FST_LOW_WATER_MARK;
77static int fst_txq_high = FST_HIGH_WATER_MARK;
78static int fst_max_reads = 7;
79static int fst_excluded_cards = 0;
80static int fst_excluded_list[FST_MAX_CARDS];
81
82module_param(fst_txq_low, int, 0);
83module_param(fst_txq_high, int, 0);
84module_param(fst_max_reads, int, 0);
85module_param(fst_excluded_cards, int, 0);
86module_param_array(fst_excluded_list, int, NULL, 0);
87
88/* Card shared memory layout
89 * =========================
90 */
91#pragma pack(1)
92
93/* This information is derived in part from the FarSite FarSync Smc.h
94 * file. Unfortunately various name clashes and the non-portability of the
95 * bit field declarations in that file have meant that I have chosen to
96 * recreate the information here.
97 *
98 * The SMC (Shared Memory Configuration) has a version number that is
99 * incremented every time there is a significant change. This number can
100 * be used to check that we have not got out of step with the firmware
101 * contained in the .CDE files.
102 */
103#define SMC_VERSION 24
104
105#define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */
106
107#define SMC_BASE 0x00002000L /* Base offset of the shared memory window main
108 * configuration structure */
109#define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA
110 * buffers */
111
112#define LEN_TX_BUFFER 8192 /* Size of packet buffers */
113#define LEN_RX_BUFFER 8192
114
115#define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */
116#define LEN_SMALL_RX_BUFFER 256
117
118#define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */
119#define NUM_RX_BUFFER 8
120
121/* Interrupt retry time in milliseconds */
122#define INT_RETRY_TIME 2
123
124/* The Am186CH/CC processors support a SmartDMA mode using circular pools
125 * of buffer descriptors. The structure is almost identical to that used
126 * in the LANCE Ethernet controllers. Details available as PDF from the
127 * AMD web site: http://www.amd.com/products/epd/processors/\
128 * 2.16bitcont/3.am186cxfa/a21914/21914.pdf
129 */
130struct txdesc { /* Transmit descriptor */
131 volatile u16 ladr; /* Low order address of packet. This is a
132 * linear address in the Am186 memory space
133 */
134 volatile u8 hadr; /* High order address. Low 4 bits only, high 4
135 * bits must be zero
136 */
137 volatile u8 bits; /* Status and config */
138 volatile u16 bcnt; /* 2s complement of packet size in low 15 bits.
139 * Transmit terminal count interrupt enable in
140 * top bit.
141 */
142 u16 unused; /* Not used in Tx */
143};
144
145struct rxdesc { /* Receive descriptor */
146 volatile u16 ladr; /* Low order address of packet */
147 volatile u8 hadr; /* High order address */
148 volatile u8 bits; /* Status and config */
149 volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits.
150 * Receive terminal count interrupt enable in
151 * top bit.
152 */
153 volatile u16 mcnt; /* Message byte count (15 bits) */
154};
155
156/* Convert a length into the 15 bit 2's complement */
157/* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */
158/* Since we need to set the high bit to enable the completion interrupt this
159 * can be made a lot simpler
160 */
161#define cnv_bcnt(len) (-(len))
162
163/* Status and config bits for the above */
164#define DMA_OWN 0x80 /* SmartDMA owns the descriptor */
165#define TX_STP 0x02 /* Tx: start of packet */
166#define TX_ENP 0x01 /* Tx: end of packet */
167#define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */
168#define RX_FRAM 0x20 /* Rx: framing error */
169#define RX_OFLO 0x10 /* Rx: overflow error */
170#define RX_CRC 0x08 /* Rx: CRC error */
171#define RX_HBUF 0x04 /* Rx: buffer error */
172#define RX_STP 0x02 /* Rx: start of packet */
173#define RX_ENP 0x01 /* Rx: end of packet */
174
175/* Interrupts from the card are caused by various events which are presented
176 * in a circular buffer as several events may be processed on one physical int
177 */
178#define MAX_CIRBUFF 32
179
180struct cirbuff {
181 u8 rdindex; /* read, then increment and wrap */
182 u8 wrindex; /* write, then increment and wrap */
183 u8 evntbuff[MAX_CIRBUFF];
184};
185
186/* Interrupt event codes.
187 * Where appropriate the two low order bits indicate the port number
188 */
189#define CTLA_CHG 0x18 /* Control signal changed */
190#define CTLB_CHG 0x19
191#define CTLC_CHG 0x1A
192#define CTLD_CHG 0x1B
193
194#define INIT_CPLT 0x20 /* Initialisation complete */
195#define INIT_FAIL 0x21 /* Initialisation failed */
196
197#define ABTA_SENT 0x24 /* Abort sent */
198#define ABTB_SENT 0x25
199#define ABTC_SENT 0x26
200#define ABTD_SENT 0x27
201
202#define TXA_UNDF 0x28 /* Transmission underflow */
203#define TXB_UNDF 0x29
204#define TXC_UNDF 0x2A
205#define TXD_UNDF 0x2B
206
207#define F56_INT 0x2C
208#define M32_INT 0x2D
209
210#define TE1_ALMA 0x30
211
212/* Port physical configuration. See farsync.h for field values */
213struct port_cfg {
214 u16 lineInterface; /* Physical interface type */
215 u8 x25op; /* Unused at present */
216 u8 internalClock; /* 1 => internal clock, 0 => external */
217 u8 transparentMode; /* 1 => on, 0 => off */
218 u8 invertClock; /* 0 => normal, 1 => inverted */
219 u8 padBytes[6]; /* Padding */
220 u32 lineSpeed; /* Speed in bps */
221};
222
223/* TE1 port physical configuration */
224struct su_config {
225 u32 dataRate;
226 u8 clocking;
227 u8 framing;
228 u8 structure;
229 u8 interface;
230 u8 coding;
231 u8 lineBuildOut;
232 u8 equalizer;
233 u8 transparentMode;
234 u8 loopMode;
235 u8 range;
236 u8 txBufferMode;
237 u8 rxBufferMode;
238 u8 startingSlot;
239 u8 losThreshold;
240 u8 enableIdleCode;
241 u8 idleCode;
242 u8 spare[44];
243};
244
245/* TE1 Status */
246struct su_status {
247 u32 receiveBufferDelay;
248 u32 framingErrorCount;
249 u32 codeViolationCount;
250 u32 crcErrorCount;
251 u32 lineAttenuation;
252 u8 portStarted;
253 u8 lossOfSignal;
254 u8 receiveRemoteAlarm;
255 u8 alarmIndicationSignal;
256 u8 spare[40];
257};
258
259/* Finally sling all the above together into the shared memory structure.
260 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been
261 * evolving under NT for some time so I guess we're stuck with it.
262 * The structure starts at offset SMC_BASE.
263 * See farsync.h for some field values.
264 */
265struct fst_shared {
266 /* DMA descriptor rings */
267 struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER];
268 struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER];
269
270 /* Obsolete small buffers */
271 u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER];
272 u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER];
273
274 u8 taskStatus; /* 0x00 => initialising, 0x01 => running,
275 * 0xFF => halted
276 */
277
278 u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt,
279 * set to 0xEE by host to acknowledge interrupt
280 */
281
282 u16 smcVersion; /* Must match SMC_VERSION */
283
284 u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major
285 * version, RR = revision and BB = build
286 */
287
288 u16 txa_done; /* Obsolete completion flags */
289 u16 rxa_done;
290 u16 txb_done;
291 u16 rxb_done;
292 u16 txc_done;
293 u16 rxc_done;
294 u16 txd_done;
295 u16 rxd_done;
296
297 u16 mailbox[4]; /* Diagnostics mailbox. Not used */
298
299 struct cirbuff interruptEvent; /* interrupt causes */
300
301 u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */
302 u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */
303
304 struct port_cfg portConfig[FST_MAX_PORTS];
305
306 u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */
307
308 u16 cableStatus; /* lsb: 0=> present, 1=> absent */
309
310 u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */
311 u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */
312
313 u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */
314 u16 cardMailbox[4]; /* Not used */
315
316 /* Number of times the card thinks the host has
317 * missed an interrupt by not acknowledging
318 * within 2mS (I guess NT has problems)
319 */
320 u32 interruptRetryCount;
321
322 /* Driver private data used as an ID. We'll not
323 * use this as I'd rather keep such things
324 * in main memory rather than on the PCI bus
325 */
326 u32 portHandle[FST_MAX_PORTS];
327
328 /* Count of Tx underflows for stats */
329 u32 transmitBufferUnderflow[FST_MAX_PORTS];
330
331 /* Debounced V.24 control input status */
332 u32 v24DebouncedSts[FST_MAX_PORTS];
333
334 /* Adapter debounce timers. Don't touch */
335 u32 ctsTimer[FST_MAX_PORTS];
336 u32 ctsTimerRun[FST_MAX_PORTS];
337 u32 dcdTimer[FST_MAX_PORTS];
338 u32 dcdTimerRun[FST_MAX_PORTS];
339
340 u32 numberOfPorts; /* Number of ports detected at startup */
341
342 u16 _reserved[64];
343
344 u16 cardMode; /* Bit-mask to enable features:
345 * Bit 0: 1 enables LED identify mode
346 */
347
348 u16 portScheduleOffset;
349
350 struct su_config suConfig; /* TE1 Bits */
351 struct su_status suStatus;
352
353 u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of
354 * the structure and marks the end of shared
355 * memory. Adapter code initializes it as
356 * END_SIG.
357 */
358};
359
360/* endOfSmcSignature value */
361#define END_SIG 0x12345678
362
363/* Mailbox values. (portMailbox) */
364#define NOP 0 /* No operation */
365#define ACK 1 /* Positive acknowledgement to PC driver */
366#define NAK 2 /* Negative acknowledgement to PC driver */
367#define STARTPORT 3 /* Start an HDLC port */
368#define STOPPORT 4 /* Stop an HDLC port */
369#define ABORTTX 5 /* Abort the transmitter for a port */
370#define SETV24O 6 /* Set V24 outputs */
371
372/* PLX Chip Register Offsets */
373#define CNTRL_9052 0x50 /* Control Register */
374#define CNTRL_9054 0x6c /* Control Register */
375
376#define INTCSR_9052 0x4c /* Interrupt control/status register */
377#define INTCSR_9054 0x68 /* Interrupt control/status register */
378
379/* 9054 DMA Registers */
380/*
381 * Note that we will be using DMA Channel 0 for copying rx data
382 * and Channel 1 for copying tx data
383 */
384#define DMAMODE0 0x80
385#define DMAPADR0 0x84
386#define DMALADR0 0x88
387#define DMASIZ0 0x8c
388#define DMADPR0 0x90
389#define DMAMODE1 0x94
390#define DMAPADR1 0x98
391#define DMALADR1 0x9c
392#define DMASIZ1 0xa0
393#define DMADPR1 0xa4
394#define DMACSR0 0xa8
395#define DMACSR1 0xa9
396#define DMAARB 0xac
397#define DMATHR 0xb0
398#define DMADAC0 0xb4
399#define DMADAC1 0xb8
400#define DMAMARBR 0xac
401
402#define FST_MIN_DMA_LEN 64
403#define FST_RX_DMA_INT 0x01
404#define FST_TX_DMA_INT 0x02
405#define FST_CARD_INT 0x04
406
407/* Larger buffers are positioned in memory at offset BFM_BASE */
408struct buf_window {
409 u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER];
410 u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER];
411};
412
413/* Calculate offset of a buffer object within the shared memory window */
414#define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X))
415
416#pragma pack()
417
418/* Device driver private information
419 * =================================
420 */
421/* Per port (line or channel) information
422 */
423struct fst_port_info {
424 struct net_device *dev; /* Device struct - must be first */
425 struct fst_card_info *card; /* Card we're associated with */
426 int index; /* Port index on the card */
427 int hwif; /* Line hardware (lineInterface copy) */
428 int run; /* Port is running */
429 int mode; /* Normal or FarSync raw */
430 int rxpos; /* Next Rx buffer to use */
431 int txpos; /* Next Tx buffer to use */
432 int txipos; /* Next Tx buffer to check for free */
433 int start; /* Indication of start/stop to network */
434 /*
435 * A sixteen entry transmit queue
436 */
437 int txqs; /* index to get next buffer to tx */
438 int txqe; /* index to queue next packet */
439 struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */
440 int rxqdepth;
441};
442
443/* Per card information
444 */
445struct fst_card_info {
446 char __iomem *mem; /* Card memory mapped to kernel space */
447 char __iomem *ctlmem; /* Control memory for PCI cards */
448 unsigned int phys_mem; /* Physical memory window address */
449 unsigned int phys_ctlmem; /* Physical control memory address */
450 unsigned int irq; /* Interrupt request line number */
451 unsigned int nports; /* Number of serial ports */
452 unsigned int type; /* Type index of card */
453 unsigned int state; /* State of card */
454 spinlock_t card_lock; /* Lock for SMP access */
455 unsigned short pci_conf; /* PCI card config in I/O space */
456 /* Per port info */
457 struct fst_port_info ports[FST_MAX_PORTS];
458 struct pci_dev *device; /* Information about the pci device */
459 int card_no; /* Inst of the card on the system */
460 int family; /* TxP or TxU */
461 int dmarx_in_progress;
462 int dmatx_in_progress;
463 unsigned long int_count;
464 unsigned long int_time_ave;
465 void *rx_dma_handle_host;
466 dma_addr_t rx_dma_handle_card;
467 void *tx_dma_handle_host;
468 dma_addr_t tx_dma_handle_card;
469 struct sk_buff *dma_skb_rx;
470 struct fst_port_info *dma_port_rx;
471 struct fst_port_info *dma_port_tx;
472 int dma_len_rx;
473 int dma_len_tx;
474 int dma_txpos;
475 int dma_rxpos;
476};
477
478/* Convert an HDLC device pointer into a port info pointer and similar */
479#define dev_to_port(D) (dev_to_hdlc(D)->priv)
480#define port_to_dev(P) ((P)->dev)
481
482
483/*
484 * Shared memory window access macros
485 *
486 * We have a nice memory based structure above, which could be directly
487 * mapped on i386 but might not work on other architectures unless we use
488 * the readb,w,l and writeb,w,l macros. Unfortunately these macros take
489 * physical offsets so we have to convert. The only saving grace is that
490 * this should all collapse back to a simple indirection eventually.
491 */
492#define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X))
493
494#define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E))
495#define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E))
496#define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E))
497
498#define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E))
499#define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E))
500#define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E))
501
502/*
503 * Debug support
504 */
505#if FST_DEBUG
506
507static int fst_debug_mask = { FST_DEBUG };
508
509/* Most common debug activity is to print something if the corresponding bit
510 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to
511 * support variable numbers of macro parameters. The inverted if prevents us
512 * eating someone else's else clause.
513 */
514#define dbg(F, fmt, args...) \
515do { \
516 if (fst_debug_mask & (F)) \
517 printk(KERN_DEBUG pr_fmt(fmt), ##args); \
518} while (0)
519#else
520#define dbg(F, fmt, args...) \
521do { \
522 if (0) \
523 printk(KERN_DEBUG pr_fmt(fmt), ##args); \
524} while (0)
525#endif
526
527/*
528 * PCI ID lookup table
529 */
530static const struct pci_device_id fst_pci_dev_id[] = {
531 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID,
532 PCI_ANY_ID, 0, 0, FST_TYPE_T2P},
533
534 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID,
535 PCI_ANY_ID, 0, 0, FST_TYPE_T4P},
536
537 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID,
538 PCI_ANY_ID, 0, 0, FST_TYPE_T1U},
539
540 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID,
541 PCI_ANY_ID, 0, 0, FST_TYPE_T2U},
542
543 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID,
544 PCI_ANY_ID, 0, 0, FST_TYPE_T4U},
545
546 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID,
547 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
548
549 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID,
550 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
551 {0,} /* End */
552};
553
554MODULE_DEVICE_TABLE(pci, fst_pci_dev_id);
555
556/*
557 * Device Driver Work Queues
558 *
559 * So that we don't spend too much time processing events in the
560 * Interrupt Service routine, we will declare a work queue per Card
561 * and make the ISR schedule a task in the queue for later execution.
562 * In the 2.4 Kernel we used to use the immediate queue for BH's
563 * Now that they are gone, tasklets seem to be much better than work
564 * queues.
565 */
566
567static void do_bottom_half_tx(struct fst_card_info *card);
568static void do_bottom_half_rx(struct fst_card_info *card);
569static void fst_process_tx_work_q(unsigned long work_q);
570static void fst_process_int_work_q(unsigned long work_q);
571
572static DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q, 0);
573static DECLARE_TASKLET(fst_int_task, fst_process_int_work_q, 0);
574
575static struct fst_card_info *fst_card_array[FST_MAX_CARDS];
576static spinlock_t fst_work_q_lock;
577static u64 fst_work_txq;
578static u64 fst_work_intq;
579
580static void
581fst_q_work_item(u64 * queue, int card_index)
582{
583 unsigned long flags;
584 u64 mask;
585
586 /*
587 * Grab the queue exclusively
588 */
589 spin_lock_irqsave(&fst_work_q_lock, flags);
590
591 /*
592 * Making an entry in the queue is simply a matter of setting
593 * a bit for the card indicating that there is work to do in the
594 * bottom half for the card. Note the limitation of 64 cards.
595 * That ought to be enough
596 */
597 mask = (u64)1 << card_index;
598 *queue |= mask;
599 spin_unlock_irqrestore(&fst_work_q_lock, flags);
600}
601
602static void
603fst_process_tx_work_q(unsigned long /*void **/work_q)
604{
605 unsigned long flags;
606 u64 work_txq;
607 int i;
608
609 /*
610 * Grab the queue exclusively
611 */
612 dbg(DBG_TX, "fst_process_tx_work_q\n");
613 spin_lock_irqsave(&fst_work_q_lock, flags);
614 work_txq = fst_work_txq;
615 fst_work_txq = 0;
616 spin_unlock_irqrestore(&fst_work_q_lock, flags);
617
618 /*
619 * Call the bottom half for each card with work waiting
620 */
621 for (i = 0; i < FST_MAX_CARDS; i++) {
622 if (work_txq & 0x01) {
623 if (fst_card_array[i] != NULL) {
624 dbg(DBG_TX, "Calling tx bh for card %d\n", i);
625 do_bottom_half_tx(fst_card_array[i]);
626 }
627 }
628 work_txq = work_txq >> 1;
629 }
630}
631
632static void
633fst_process_int_work_q(unsigned long /*void **/work_q)
634{
635 unsigned long flags;
636 u64 work_intq;
637 int i;
638
639 /*
640 * Grab the queue exclusively
641 */
642 dbg(DBG_INTR, "fst_process_int_work_q\n");
643 spin_lock_irqsave(&fst_work_q_lock, flags);
644 work_intq = fst_work_intq;
645 fst_work_intq = 0;
646 spin_unlock_irqrestore(&fst_work_q_lock, flags);
647
648 /*
649 * Call the bottom half for each card with work waiting
650 */
651 for (i = 0; i < FST_MAX_CARDS; i++) {
652 if (work_intq & 0x01) {
653 if (fst_card_array[i] != NULL) {
654 dbg(DBG_INTR,
655 "Calling rx & tx bh for card %d\n", i);
656 do_bottom_half_rx(fst_card_array[i]);
657 do_bottom_half_tx(fst_card_array[i]);
658 }
659 }
660 work_intq = work_intq >> 1;
661 }
662}
663
664/* Card control functions
665 * ======================
666 */
667/* Place the processor in reset state
668 *
669 * Used to be a simple write to card control space but a glitch in the latest
670 * AMD Am186CH processor means that we now have to do it by asserting and de-
671 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register
672 * at offset 9052_CNTRL. Note the updates for the TXU.
673 */
674static inline void
675fst_cpureset(struct fst_card_info *card)
676{
677 unsigned char interrupt_line_register;
678 unsigned int regval;
679
680 if (card->family == FST_FAMILY_TXU) {
681 if (pci_read_config_byte
682 (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) {
683 dbg(DBG_ASS,
684 "Error in reading interrupt line register\n");
685 }
686 /*
687 * Assert PLX software reset and Am186 hardware reset
688 * and then deassert the PLX software reset but 186 still in reset
689 */
690 outw(0x440f, card->pci_conf + CNTRL_9054 + 2);
691 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
692 /*
693 * We are delaying here to allow the 9054 to reset itself
694 */
695 usleep_range(10, 20);
696 outw(0x240f, card->pci_conf + CNTRL_9054 + 2);
697 /*
698 * We are delaying here to allow the 9054 to reload its eeprom
699 */
700 usleep_range(10, 20);
701 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
702
703 if (pci_write_config_byte
704 (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) {
705 dbg(DBG_ASS,
706 "Error in writing interrupt line register\n");
707 }
708
709 } else {
710 regval = inl(card->pci_conf + CNTRL_9052);
711
712 outl(regval | 0x40000000, card->pci_conf + CNTRL_9052);
713 outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052);
714 }
715}
716
717/* Release the processor from reset
718 */
719static inline void
720fst_cpurelease(struct fst_card_info *card)
721{
722 if (card->family == FST_FAMILY_TXU) {
723 /*
724 * Force posted writes to complete
725 */
726 (void) readb(card->mem);
727
728 /*
729 * Release LRESET DO = 1
730 * Then release Local Hold, DO = 1
731 */
732 outw(0x040e, card->pci_conf + CNTRL_9054 + 2);
733 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
734 } else {
735 (void) readb(card->ctlmem);
736 }
737}
738
739/* Clear the cards interrupt flag
740 */
741static inline void
742fst_clear_intr(struct fst_card_info *card)
743{
744 if (card->family == FST_FAMILY_TXU) {
745 (void) readb(card->ctlmem);
746 } else {
747 /* Poke the appropriate PLX chip register (same as enabling interrupts)
748 */
749 outw(0x0543, card->pci_conf + INTCSR_9052);
750 }
751}
752
753/* Enable card interrupts
754 */
755static inline void
756fst_enable_intr(struct fst_card_info *card)
757{
758 if (card->family == FST_FAMILY_TXU) {
759 outl(0x0f0c0900, card->pci_conf + INTCSR_9054);
760 } else {
761 outw(0x0543, card->pci_conf + INTCSR_9052);
762 }
763}
764
765/* Disable card interrupts
766 */
767static inline void
768fst_disable_intr(struct fst_card_info *card)
769{
770 if (card->family == FST_FAMILY_TXU) {
771 outl(0x00000000, card->pci_conf + INTCSR_9054);
772 } else {
773 outw(0x0000, card->pci_conf + INTCSR_9052);
774 }
775}
776
777/* Process the result of trying to pass a received frame up the stack
778 */
779static void
780fst_process_rx_status(int rx_status, char *name)
781{
782 switch (rx_status) {
783 case NET_RX_SUCCESS:
784 {
785 /*
786 * Nothing to do here
787 */
788 break;
789 }
790 case NET_RX_DROP:
791 {
792 dbg(DBG_ASS, "%s: Received packet dropped\n", name);
793 break;
794 }
795 }
796}
797
798/* Initilaise DMA for PLX 9054
799 */
800static inline void
801fst_init_dma(struct fst_card_info *card)
802{
803 /*
804 * This is only required for the PLX 9054
805 */
806 if (card->family == FST_FAMILY_TXU) {
807 pci_set_master(card->device);
808 outl(0x00020441, card->pci_conf + DMAMODE0);
809 outl(0x00020441, card->pci_conf + DMAMODE1);
810 outl(0x0, card->pci_conf + DMATHR);
811 }
812}
813
814/* Tx dma complete interrupt
815 */
816static void
817fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
818 int len, int txpos)
819{
820 struct net_device *dev = port_to_dev(port);
821
822 /*
823 * Everything is now set, just tell the card to go
824 */
825 dbg(DBG_TX, "fst_tx_dma_complete\n");
826 FST_WRB(card, txDescrRing[port->index][txpos].bits,
827 DMA_OWN | TX_STP | TX_ENP);
828 dev->stats.tx_packets++;
829 dev->stats.tx_bytes += len;
830 netif_trans_update(dev);
831}
832
833/*
834 * Mark it for our own raw sockets interface
835 */
836static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev)
837{
838 skb->dev = dev;
839 skb_reset_mac_header(skb);
840 skb->pkt_type = PACKET_HOST;
841 return htons(ETH_P_CUST);
842}
843
844/* Rx dma complete interrupt
845 */
846static void
847fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
848 int len, struct sk_buff *skb, int rxp)
849{
850 struct net_device *dev = port_to_dev(port);
851 int pi;
852 int rx_status;
853
854 dbg(DBG_TX, "fst_rx_dma_complete\n");
855 pi = port->index;
856 skb_put_data(skb, card->rx_dma_handle_host, len);
857
858 /* Reset buffer descriptor */
859 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
860
861 /* Update stats */
862 dev->stats.rx_packets++;
863 dev->stats.rx_bytes += len;
864
865 /* Push upstream */
866 dbg(DBG_RX, "Pushing the frame up the stack\n");
867 if (port->mode == FST_RAW)
868 skb->protocol = farsync_type_trans(skb, dev);
869 else
870 skb->protocol = hdlc_type_trans(skb, dev);
871 rx_status = netif_rx(skb);
872 fst_process_rx_status(rx_status, port_to_dev(port)->name);
873 if (rx_status == NET_RX_DROP)
874 dev->stats.rx_dropped++;
875}
876
877/*
878 * Receive a frame through the DMA
879 */
880static inline void
881fst_rx_dma(struct fst_card_info *card, dma_addr_t dma, u32 mem, int len)
882{
883 /*
884 * This routine will setup the DMA and start it
885 */
886
887 dbg(DBG_RX, "In fst_rx_dma %x %x %d\n", (u32)dma, mem, len);
888 if (card->dmarx_in_progress) {
889 dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n");
890 }
891
892 outl(dma, card->pci_conf + DMAPADR0); /* Copy to here */
893 outl(mem, card->pci_conf + DMALADR0); /* from here */
894 outl(len, card->pci_conf + DMASIZ0); /* for this length */
895 outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */
896
897 /*
898 * We use the dmarx_in_progress flag to flag the channel as busy
899 */
900 card->dmarx_in_progress = 1;
901 outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */
902}
903
904/*
905 * Send a frame through the DMA
906 */
907static inline void
908fst_tx_dma(struct fst_card_info *card, dma_addr_t dma, u32 mem, int len)
909{
910 /*
911 * This routine will setup the DMA and start it.
912 */
913
914 dbg(DBG_TX, "In fst_tx_dma %x %x %d\n", (u32)dma, mem, len);
915 if (card->dmatx_in_progress) {
916 dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n");
917 }
918
919 outl(dma, card->pci_conf + DMAPADR1); /* Copy from here */
920 outl(mem, card->pci_conf + DMALADR1); /* to here */
921 outl(len, card->pci_conf + DMASIZ1); /* for this length */
922 outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */
923
924 /*
925 * We use the dmatx_in_progress to flag the channel as busy
926 */
927 card->dmatx_in_progress = 1;
928 outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */
929}
930
931/* Issue a Mailbox command for a port.
932 * Note we issue them on a fire and forget basis, not expecting to see an
933 * error and not waiting for completion.
934 */
935static void
936fst_issue_cmd(struct fst_port_info *port, unsigned short cmd)
937{
938 struct fst_card_info *card;
939 unsigned short mbval;
940 unsigned long flags;
941 int safety;
942
943 card = port->card;
944 spin_lock_irqsave(&card->card_lock, flags);
945 mbval = FST_RDW(card, portMailbox[port->index][0]);
946
947 safety = 0;
948 /* Wait for any previous command to complete */
949 while (mbval > NAK) {
950 spin_unlock_irqrestore(&card->card_lock, flags);
951 schedule_timeout_uninterruptible(1);
952 spin_lock_irqsave(&card->card_lock, flags);
953
954 if (++safety > 2000) {
955 pr_err("Mailbox safety timeout\n");
956 break;
957 }
958
959 mbval = FST_RDW(card, portMailbox[port->index][0]);
960 }
961 if (safety > 0) {
962 dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety);
963 }
964 if (mbval == NAK) {
965 dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n");
966 }
967
968 FST_WRW(card, portMailbox[port->index][0], cmd);
969
970 if (cmd == ABORTTX || cmd == STARTPORT) {
971 port->txpos = 0;
972 port->txipos = 0;
973 port->start = 0;
974 }
975
976 spin_unlock_irqrestore(&card->card_lock, flags);
977}
978
979/* Port output signals control
980 */
981static inline void
982fst_op_raise(struct fst_port_info *port, unsigned int outputs)
983{
984 outputs |= FST_RDL(port->card, v24OpSts[port->index]);
985 FST_WRL(port->card, v24OpSts[port->index], outputs);
986
987 if (port->run)
988 fst_issue_cmd(port, SETV24O);
989}
990
991static inline void
992fst_op_lower(struct fst_port_info *port, unsigned int outputs)
993{
994 outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]);
995 FST_WRL(port->card, v24OpSts[port->index], outputs);
996
997 if (port->run)
998 fst_issue_cmd(port, SETV24O);
999}
1000
1001/*
1002 * Setup port Rx buffers
1003 */
1004static void
1005fst_rx_config(struct fst_port_info *port)
1006{
1007 int i;
1008 int pi;
1009 unsigned int offset;
1010 unsigned long flags;
1011 struct fst_card_info *card;
1012
1013 pi = port->index;
1014 card = port->card;
1015 spin_lock_irqsave(&card->card_lock, flags);
1016 for (i = 0; i < NUM_RX_BUFFER; i++) {
1017 offset = BUF_OFFSET(rxBuffer[pi][i][0]);
1018
1019 FST_WRW(card, rxDescrRing[pi][i].ladr, (u16) offset);
1020 FST_WRB(card, rxDescrRing[pi][i].hadr, (u8) (offset >> 16));
1021 FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER));
1022 FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER);
1023 FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN);
1024 }
1025 port->rxpos = 0;
1026 spin_unlock_irqrestore(&card->card_lock, flags);
1027}
1028
1029/*
1030 * Setup port Tx buffers
1031 */
1032static void
1033fst_tx_config(struct fst_port_info *port)
1034{
1035 int i;
1036 int pi;
1037 unsigned int offset;
1038 unsigned long flags;
1039 struct fst_card_info *card;
1040
1041 pi = port->index;
1042 card = port->card;
1043 spin_lock_irqsave(&card->card_lock, flags);
1044 for (i = 0; i < NUM_TX_BUFFER; i++) {
1045 offset = BUF_OFFSET(txBuffer[pi][i][0]);
1046
1047 FST_WRW(card, txDescrRing[pi][i].ladr, (u16) offset);
1048 FST_WRB(card, txDescrRing[pi][i].hadr, (u8) (offset >> 16));
1049 FST_WRW(card, txDescrRing[pi][i].bcnt, 0);
1050 FST_WRB(card, txDescrRing[pi][i].bits, 0);
1051 }
1052 port->txpos = 0;
1053 port->txipos = 0;
1054 port->start = 0;
1055 spin_unlock_irqrestore(&card->card_lock, flags);
1056}
1057
1058/* TE1 Alarm change interrupt event
1059 */
1060static void
1061fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port)
1062{
1063 u8 los;
1064 u8 rra;
1065 u8 ais;
1066
1067 los = FST_RDB(card, suStatus.lossOfSignal);
1068 rra = FST_RDB(card, suStatus.receiveRemoteAlarm);
1069 ais = FST_RDB(card, suStatus.alarmIndicationSignal);
1070
1071 if (los) {
1072 /*
1073 * Lost the link
1074 */
1075 if (netif_carrier_ok(port_to_dev(port))) {
1076 dbg(DBG_INTR, "Net carrier off\n");
1077 netif_carrier_off(port_to_dev(port));
1078 }
1079 } else {
1080 /*
1081 * Link available
1082 */
1083 if (!netif_carrier_ok(port_to_dev(port))) {
1084 dbg(DBG_INTR, "Net carrier on\n");
1085 netif_carrier_on(port_to_dev(port));
1086 }
1087 }
1088
1089 if (los)
1090 dbg(DBG_INTR, "Assert LOS Alarm\n");
1091 else
1092 dbg(DBG_INTR, "De-assert LOS Alarm\n");
1093 if (rra)
1094 dbg(DBG_INTR, "Assert RRA Alarm\n");
1095 else
1096 dbg(DBG_INTR, "De-assert RRA Alarm\n");
1097
1098 if (ais)
1099 dbg(DBG_INTR, "Assert AIS Alarm\n");
1100 else
1101 dbg(DBG_INTR, "De-assert AIS Alarm\n");
1102}
1103
1104/* Control signal change interrupt event
1105 */
1106static void
1107fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port)
1108{
1109 int signals;
1110
1111 signals = FST_RDL(card, v24DebouncedSts[port->index]);
1112
1113 if (signals & (((port->hwif == X21) || (port->hwif == X21D))
1114 ? IPSTS_INDICATE : IPSTS_DCD)) {
1115 if (!netif_carrier_ok(port_to_dev(port))) {
1116 dbg(DBG_INTR, "DCD active\n");
1117 netif_carrier_on(port_to_dev(port));
1118 }
1119 } else {
1120 if (netif_carrier_ok(port_to_dev(port))) {
1121 dbg(DBG_INTR, "DCD lost\n");
1122 netif_carrier_off(port_to_dev(port));
1123 }
1124 }
1125}
1126
1127/* Log Rx Errors
1128 */
1129static void
1130fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1131 unsigned char dmabits, int rxp, unsigned short len)
1132{
1133 struct net_device *dev = port_to_dev(port);
1134
1135 /*
1136 * Increment the appropriate error counter
1137 */
1138 dev->stats.rx_errors++;
1139 if (dmabits & RX_OFLO) {
1140 dev->stats.rx_fifo_errors++;
1141 dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n",
1142 card->card_no, port->index, rxp);
1143 }
1144 if (dmabits & RX_CRC) {
1145 dev->stats.rx_crc_errors++;
1146 dbg(DBG_ASS, "Rx crc error on card %d port %d\n",
1147 card->card_no, port->index);
1148 }
1149 if (dmabits & RX_FRAM) {
1150 dev->stats.rx_frame_errors++;
1151 dbg(DBG_ASS, "Rx frame error on card %d port %d\n",
1152 card->card_no, port->index);
1153 }
1154 if (dmabits == (RX_STP | RX_ENP)) {
1155 dev->stats.rx_length_errors++;
1156 dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n",
1157 len, card->card_no, port->index);
1158 }
1159}
1160
1161/* Rx Error Recovery
1162 */
1163static void
1164fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1165 unsigned char dmabits, int rxp, unsigned short len)
1166{
1167 int i;
1168 int pi;
1169
1170 pi = port->index;
1171 /*
1172 * Discard buffer descriptors until we see the start of the
1173 * next frame. Note that for long frames this could be in
1174 * a subsequent interrupt.
1175 */
1176 i = 0;
1177 while ((dmabits & (DMA_OWN | RX_STP)) == 0) {
1178 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1179 rxp = (rxp+1) % NUM_RX_BUFFER;
1180 if (++i > NUM_RX_BUFFER) {
1181 dbg(DBG_ASS, "intr_rx: Discarding more bufs"
1182 " than we have\n");
1183 break;
1184 }
1185 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1186 dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits);
1187 }
1188 dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i);
1189
1190 /* Discard the terminal buffer */
1191 if (!(dmabits & DMA_OWN)) {
1192 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1193 rxp = (rxp+1) % NUM_RX_BUFFER;
1194 }
1195 port->rxpos = rxp;
1196 return;
1197
1198}
1199
1200/* Rx complete interrupt
1201 */
1202static void
1203fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port)
1204{
1205 unsigned char dmabits;
1206 int pi;
1207 int rxp;
1208 int rx_status;
1209 unsigned short len;
1210 struct sk_buff *skb;
1211 struct net_device *dev = port_to_dev(port);
1212
1213 /* Check we have a buffer to process */
1214 pi = port->index;
1215 rxp = port->rxpos;
1216 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1217 if (dmabits & DMA_OWN) {
1218 dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n",
1219 pi, rxp);
1220 return;
1221 }
1222 if (card->dmarx_in_progress) {
1223 return;
1224 }
1225
1226 /* Get buffer length */
1227 len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt);
1228 /* Discard the CRC */
1229 len -= 2;
1230 if (len == 0) {
1231 /*
1232 * This seems to happen on the TE1 interface sometimes
1233 * so throw the frame away and log the event.
1234 */
1235 pr_err("Frame received with 0 length. Card %d Port %d\n",
1236 card->card_no, port->index);
1237 /* Return descriptor to card */
1238 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1239
1240 rxp = (rxp+1) % NUM_RX_BUFFER;
1241 port->rxpos = rxp;
1242 return;
1243 }
1244
1245 /* Check buffer length and for other errors. We insist on one packet
1246 * in one buffer. This simplifies things greatly and since we've
1247 * allocated 8K it shouldn't be a real world limitation
1248 */
1249 dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len);
1250 if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) {
1251 fst_log_rx_error(card, port, dmabits, rxp, len);
1252 fst_recover_rx_error(card, port, dmabits, rxp, len);
1253 return;
1254 }
1255
1256 /* Allocate SKB */
1257 if ((skb = dev_alloc_skb(len)) == NULL) {
1258 dbg(DBG_RX, "intr_rx: can't allocate buffer\n");
1259
1260 dev->stats.rx_dropped++;
1261
1262 /* Return descriptor to card */
1263 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1264
1265 rxp = (rxp+1) % NUM_RX_BUFFER;
1266 port->rxpos = rxp;
1267 return;
1268 }
1269
1270 /*
1271 * We know the length we need to receive, len.
1272 * It's not worth using the DMA for reads of less than
1273 * FST_MIN_DMA_LEN
1274 */
1275
1276 if ((len < FST_MIN_DMA_LEN) || (card->family == FST_FAMILY_TXP)) {
1277 memcpy_fromio(skb_put(skb, len),
1278 card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]),
1279 len);
1280
1281 /* Reset buffer descriptor */
1282 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1283
1284 /* Update stats */
1285 dev->stats.rx_packets++;
1286 dev->stats.rx_bytes += len;
1287
1288 /* Push upstream */
1289 dbg(DBG_RX, "Pushing frame up the stack\n");
1290 if (port->mode == FST_RAW)
1291 skb->protocol = farsync_type_trans(skb, dev);
1292 else
1293 skb->protocol = hdlc_type_trans(skb, dev);
1294 rx_status = netif_rx(skb);
1295 fst_process_rx_status(rx_status, port_to_dev(port)->name);
1296 if (rx_status == NET_RX_DROP)
1297 dev->stats.rx_dropped++;
1298 } else {
1299 card->dma_skb_rx = skb;
1300 card->dma_port_rx = port;
1301 card->dma_len_rx = len;
1302 card->dma_rxpos = rxp;
1303 fst_rx_dma(card, card->rx_dma_handle_card,
1304 BUF_OFFSET(rxBuffer[pi][rxp][0]), len);
1305 }
1306 if (rxp != port->rxpos) {
1307 dbg(DBG_ASS, "About to increment rxpos by more than 1\n");
1308 dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos);
1309 }
1310 rxp = (rxp+1) % NUM_RX_BUFFER;
1311 port->rxpos = rxp;
1312}
1313
1314/*
1315 * The bottom halfs to the ISR
1316 *
1317 */
1318
1319static void
1320do_bottom_half_tx(struct fst_card_info *card)
1321{
1322 struct fst_port_info *port;
1323 int pi;
1324 int txq_length;
1325 struct sk_buff *skb;
1326 unsigned long flags;
1327 struct net_device *dev;
1328
1329 /*
1330 * Find a free buffer for the transmit
1331 * Step through each port on this card
1332 */
1333
1334 dbg(DBG_TX, "do_bottom_half_tx\n");
1335 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1336 if (!port->run)
1337 continue;
1338
1339 dev = port_to_dev(port);
1340 while (!(FST_RDB(card, txDescrRing[pi][port->txpos].bits) &
1341 DMA_OWN) &&
1342 !(card->dmatx_in_progress)) {
1343 /*
1344 * There doesn't seem to be a txdone event per-se
1345 * We seem to have to deduce it, by checking the DMA_OWN
1346 * bit on the next buffer we think we can use
1347 */
1348 spin_lock_irqsave(&card->card_lock, flags);
1349 if ((txq_length = port->txqe - port->txqs) < 0) {
1350 /*
1351 * This is the case where one has wrapped and the
1352 * maths gives us a negative number
1353 */
1354 txq_length = txq_length + FST_TXQ_DEPTH;
1355 }
1356 spin_unlock_irqrestore(&card->card_lock, flags);
1357 if (txq_length > 0) {
1358 /*
1359 * There is something to send
1360 */
1361 spin_lock_irqsave(&card->card_lock, flags);
1362 skb = port->txq[port->txqs];
1363 port->txqs++;
1364 if (port->txqs == FST_TXQ_DEPTH) {
1365 port->txqs = 0;
1366 }
1367 spin_unlock_irqrestore(&card->card_lock, flags);
1368 /*
1369 * copy the data and set the required indicators on the
1370 * card.
1371 */
1372 FST_WRW(card, txDescrRing[pi][port->txpos].bcnt,
1373 cnv_bcnt(skb->len));
1374 if ((skb->len < FST_MIN_DMA_LEN) ||
1375 (card->family == FST_FAMILY_TXP)) {
1376 /* Enqueue the packet with normal io */
1377 memcpy_toio(card->mem +
1378 BUF_OFFSET(txBuffer[pi]
1379 [port->
1380 txpos][0]),
1381 skb->data, skb->len);
1382 FST_WRB(card,
1383 txDescrRing[pi][port->txpos].
1384 bits,
1385 DMA_OWN | TX_STP | TX_ENP);
1386 dev->stats.tx_packets++;
1387 dev->stats.tx_bytes += skb->len;
1388 netif_trans_update(dev);
1389 } else {
1390 /* Or do it through dma */
1391 memcpy(card->tx_dma_handle_host,
1392 skb->data, skb->len);
1393 card->dma_port_tx = port;
1394 card->dma_len_tx = skb->len;
1395 card->dma_txpos = port->txpos;
1396 fst_tx_dma(card,
1397 card->tx_dma_handle_card,
1398 BUF_OFFSET(txBuffer[pi]
1399 [port->txpos][0]),
1400 skb->len);
1401 }
1402 if (++port->txpos >= NUM_TX_BUFFER)
1403 port->txpos = 0;
1404 /*
1405 * If we have flow control on, can we now release it?
1406 */
1407 if (port->start) {
1408 if (txq_length < fst_txq_low) {
1409 netif_wake_queue(port_to_dev
1410 (port));
1411 port->start = 0;
1412 }
1413 }
1414 dev_kfree_skb(skb);
1415 } else {
1416 /*
1417 * Nothing to send so break out of the while loop
1418 */
1419 break;
1420 }
1421 }
1422 }
1423}
1424
1425static void
1426do_bottom_half_rx(struct fst_card_info *card)
1427{
1428 struct fst_port_info *port;
1429 int pi;
1430 int rx_count = 0;
1431
1432 /* Check for rx completions on all ports on this card */
1433 dbg(DBG_RX, "do_bottom_half_rx\n");
1434 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1435 if (!port->run)
1436 continue;
1437
1438 while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits)
1439 & DMA_OWN) && !(card->dmarx_in_progress)) {
1440 if (rx_count > fst_max_reads) {
1441 /*
1442 * Don't spend forever in receive processing
1443 * Schedule another event
1444 */
1445 fst_q_work_item(&fst_work_intq, card->card_no);
1446 tasklet_schedule(&fst_int_task);
1447 break; /* Leave the loop */
1448 }
1449 fst_intr_rx(card, port);
1450 rx_count++;
1451 }
1452 }
1453}
1454
1455/*
1456 * The interrupt service routine
1457 * Dev_id is our fst_card_info pointer
1458 */
1459static irqreturn_t
1460fst_intr(int dummy, void *dev_id)
1461{
1462 struct fst_card_info *card = dev_id;
1463 struct fst_port_info *port;
1464 int rdidx; /* Event buffer indices */
1465 int wridx;
1466 int event; /* Actual event for processing */
1467 unsigned int dma_intcsr = 0;
1468 unsigned int do_card_interrupt;
1469 unsigned int int_retry_count;
1470
1471 /*
1472 * Check to see if the interrupt was for this card
1473 * return if not
1474 * Note that the call to clear the interrupt is important
1475 */
1476 dbg(DBG_INTR, "intr: %d %p\n", card->irq, card);
1477 if (card->state != FST_RUNNING) {
1478 pr_err("Interrupt received for card %d in a non running state (%d)\n",
1479 card->card_no, card->state);
1480
1481 /*
1482 * It is possible to really be running, i.e. we have re-loaded
1483 * a running card
1484 * Clear and reprime the interrupt source
1485 */
1486 fst_clear_intr(card);
1487 return IRQ_HANDLED;
1488 }
1489
1490 /* Clear and reprime the interrupt source */
1491 fst_clear_intr(card);
1492
1493 /*
1494 * Is the interrupt for this card (handshake == 1)
1495 */
1496 do_card_interrupt = 0;
1497 if (FST_RDB(card, interruptHandshake) == 1) {
1498 do_card_interrupt += FST_CARD_INT;
1499 /* Set the software acknowledge */
1500 FST_WRB(card, interruptHandshake, 0xEE);
1501 }
1502 if (card->family == FST_FAMILY_TXU) {
1503 /*
1504 * Is it a DMA Interrupt
1505 */
1506 dma_intcsr = inl(card->pci_conf + INTCSR_9054);
1507 if (dma_intcsr & 0x00200000) {
1508 /*
1509 * DMA Channel 0 (Rx transfer complete)
1510 */
1511 dbg(DBG_RX, "DMA Rx xfer complete\n");
1512 outb(0x8, card->pci_conf + DMACSR0);
1513 fst_rx_dma_complete(card, card->dma_port_rx,
1514 card->dma_len_rx, card->dma_skb_rx,
1515 card->dma_rxpos);
1516 card->dmarx_in_progress = 0;
1517 do_card_interrupt += FST_RX_DMA_INT;
1518 }
1519 if (dma_intcsr & 0x00400000) {
1520 /*
1521 * DMA Channel 1 (Tx transfer complete)
1522 */
1523 dbg(DBG_TX, "DMA Tx xfer complete\n");
1524 outb(0x8, card->pci_conf + DMACSR1);
1525 fst_tx_dma_complete(card, card->dma_port_tx,
1526 card->dma_len_tx, card->dma_txpos);
1527 card->dmatx_in_progress = 0;
1528 do_card_interrupt += FST_TX_DMA_INT;
1529 }
1530 }
1531
1532 /*
1533 * Have we been missing Interrupts
1534 */
1535 int_retry_count = FST_RDL(card, interruptRetryCount);
1536 if (int_retry_count) {
1537 dbg(DBG_ASS, "Card %d int_retry_count is %d\n",
1538 card->card_no, int_retry_count);
1539 FST_WRL(card, interruptRetryCount, 0);
1540 }
1541
1542 if (!do_card_interrupt) {
1543 return IRQ_HANDLED;
1544 }
1545
1546 /* Scehdule the bottom half of the ISR */
1547 fst_q_work_item(&fst_work_intq, card->card_no);
1548 tasklet_schedule(&fst_int_task);
1549
1550 /* Drain the event queue */
1551 rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f;
1552 wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f;
1553 while (rdidx != wridx) {
1554 event = FST_RDB(card, interruptEvent.evntbuff[rdidx]);
1555 port = &card->ports[event & 0x03];
1556
1557 dbg(DBG_INTR, "Processing Interrupt event: %x\n", event);
1558
1559 switch (event) {
1560 case TE1_ALMA:
1561 dbg(DBG_INTR, "TE1 Alarm intr\n");
1562 if (port->run)
1563 fst_intr_te1_alarm(card, port);
1564 break;
1565
1566 case CTLA_CHG:
1567 case CTLB_CHG:
1568 case CTLC_CHG:
1569 case CTLD_CHG:
1570 if (port->run)
1571 fst_intr_ctlchg(card, port);
1572 break;
1573
1574 case ABTA_SENT:
1575 case ABTB_SENT:
1576 case ABTC_SENT:
1577 case ABTD_SENT:
1578 dbg(DBG_TX, "Abort complete port %d\n", port->index);
1579 break;
1580
1581 case TXA_UNDF:
1582 case TXB_UNDF:
1583 case TXC_UNDF:
1584 case TXD_UNDF:
1585 /* Difficult to see how we'd get this given that we
1586 * always load up the entire packet for DMA.
1587 */
1588 dbg(DBG_TX, "Tx underflow port %d\n", port->index);
1589 port_to_dev(port)->stats.tx_errors++;
1590 port_to_dev(port)->stats.tx_fifo_errors++;
1591 dbg(DBG_ASS, "Tx underflow on card %d port %d\n",
1592 card->card_no, port->index);
1593 break;
1594
1595 case INIT_CPLT:
1596 dbg(DBG_INIT, "Card init OK intr\n");
1597 break;
1598
1599 case INIT_FAIL:
1600 dbg(DBG_INIT, "Card init FAILED intr\n");
1601 card->state = FST_IFAILED;
1602 break;
1603
1604 default:
1605 pr_err("intr: unknown card event %d. ignored\n", event);
1606 break;
1607 }
1608
1609 /* Bump and wrap the index */
1610 if (++rdidx >= MAX_CIRBUFF)
1611 rdidx = 0;
1612 }
1613 FST_WRB(card, interruptEvent.rdindex, rdidx);
1614 return IRQ_HANDLED;
1615}
1616
1617/* Check that the shared memory configuration is one that we can handle
1618 * and that some basic parameters are correct
1619 */
1620static void
1621check_started_ok(struct fst_card_info *card)
1622{
1623 int i;
1624
1625 /* Check structure version and end marker */
1626 if (FST_RDW(card, smcVersion) != SMC_VERSION) {
1627 pr_err("Bad shared memory version %d expected %d\n",
1628 FST_RDW(card, smcVersion), SMC_VERSION);
1629 card->state = FST_BADVERSION;
1630 return;
1631 }
1632 if (FST_RDL(card, endOfSmcSignature) != END_SIG) {
1633 pr_err("Missing shared memory signature\n");
1634 card->state = FST_BADVERSION;
1635 return;
1636 }
1637 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */
1638 if ((i = FST_RDB(card, taskStatus)) == 0x01) {
1639 card->state = FST_RUNNING;
1640 } else if (i == 0xFF) {
1641 pr_err("Firmware initialisation failed. Card halted\n");
1642 card->state = FST_HALTED;
1643 return;
1644 } else if (i != 0x00) {
1645 pr_err("Unknown firmware status 0x%x\n", i);
1646 card->state = FST_HALTED;
1647 return;
1648 }
1649
1650 /* Finally check the number of ports reported by firmware against the
1651 * number we assumed at card detection. Should never happen with
1652 * existing firmware etc so we just report it for the moment.
1653 */
1654 if (FST_RDL(card, numberOfPorts) != card->nports) {
1655 pr_warn("Port count mismatch on card %d. Firmware thinks %d we say %d\n",
1656 card->card_no,
1657 FST_RDL(card, numberOfPorts), card->nports);
1658 }
1659}
1660
1661static int
1662set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port,
1663 struct fstioc_info *info)
1664{
1665 int err;
1666 unsigned char my_framing;
1667
1668 /* Set things according to the user set valid flags
1669 * Several of the old options have been invalidated/replaced by the
1670 * generic hdlc package.
1671 */
1672 err = 0;
1673 if (info->valid & FSTVAL_PROTO) {
1674 if (info->proto == FST_RAW)
1675 port->mode = FST_RAW;
1676 else
1677 port->mode = FST_GEN_HDLC;
1678 }
1679
1680 if (info->valid & FSTVAL_CABLE)
1681 err = -EINVAL;
1682
1683 if (info->valid & FSTVAL_SPEED)
1684 err = -EINVAL;
1685
1686 if (info->valid & FSTVAL_PHASE)
1687 FST_WRB(card, portConfig[port->index].invertClock,
1688 info->invertClock);
1689 if (info->valid & FSTVAL_MODE)
1690 FST_WRW(card, cardMode, info->cardMode);
1691 if (info->valid & FSTVAL_TE1) {
1692 FST_WRL(card, suConfig.dataRate, info->lineSpeed);
1693 FST_WRB(card, suConfig.clocking, info->clockSource);
1694 my_framing = FRAMING_E1;
1695 if (info->framing == E1)
1696 my_framing = FRAMING_E1;
1697 if (info->framing == T1)
1698 my_framing = FRAMING_T1;
1699 if (info->framing == J1)
1700 my_framing = FRAMING_J1;
1701 FST_WRB(card, suConfig.framing, my_framing);
1702 FST_WRB(card, suConfig.structure, info->structure);
1703 FST_WRB(card, suConfig.interface, info->interface);
1704 FST_WRB(card, suConfig.coding, info->coding);
1705 FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut);
1706 FST_WRB(card, suConfig.equalizer, info->equalizer);
1707 FST_WRB(card, suConfig.transparentMode, info->transparentMode);
1708 FST_WRB(card, suConfig.loopMode, info->loopMode);
1709 FST_WRB(card, suConfig.range, info->range);
1710 FST_WRB(card, suConfig.txBufferMode, info->txBufferMode);
1711 FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode);
1712 FST_WRB(card, suConfig.startingSlot, info->startingSlot);
1713 FST_WRB(card, suConfig.losThreshold, info->losThreshold);
1714 if (info->idleCode)
1715 FST_WRB(card, suConfig.enableIdleCode, 1);
1716 else
1717 FST_WRB(card, suConfig.enableIdleCode, 0);
1718 FST_WRB(card, suConfig.idleCode, info->idleCode);
1719#if FST_DEBUG
1720 if (info->valid & FSTVAL_TE1) {
1721 printk("Setting TE1 data\n");
1722 printk("Line Speed = %d\n", info->lineSpeed);
1723 printk("Start slot = %d\n", info->startingSlot);
1724 printk("Clock source = %d\n", info->clockSource);
1725 printk("Framing = %d\n", my_framing);
1726 printk("Structure = %d\n", info->structure);
1727 printk("interface = %d\n", info->interface);
1728 printk("Coding = %d\n", info->coding);
1729 printk("Line build out = %d\n", info->lineBuildOut);
1730 printk("Equaliser = %d\n", info->equalizer);
1731 printk("Transparent mode = %d\n",
1732 info->transparentMode);
1733 printk("Loop mode = %d\n", info->loopMode);
1734 printk("Range = %d\n", info->range);
1735 printk("Tx Buffer mode = %d\n", info->txBufferMode);
1736 printk("Rx Buffer mode = %d\n", info->rxBufferMode);
1737 printk("LOS Threshold = %d\n", info->losThreshold);
1738 printk("Idle Code = %d\n", info->idleCode);
1739 }
1740#endif
1741 }
1742#if FST_DEBUG
1743 if (info->valid & FSTVAL_DEBUG) {
1744 fst_debug_mask = info->debug;
1745 }
1746#endif
1747
1748 return err;
1749}
1750
1751static void
1752gather_conf_info(struct fst_card_info *card, struct fst_port_info *port,
1753 struct fstioc_info *info)
1754{
1755 int i;
1756
1757 memset(info, 0, sizeof (struct fstioc_info));
1758
1759 i = port->index;
1760 info->kernelVersion = LINUX_VERSION_CODE;
1761 info->nports = card->nports;
1762 info->type = card->type;
1763 info->state = card->state;
1764 info->proto = FST_GEN_HDLC;
1765 info->index = i;
1766#if FST_DEBUG
1767 info->debug = fst_debug_mask;
1768#endif
1769
1770 /* Only mark information as valid if card is running.
1771 * Copy the data anyway in case it is useful for diagnostics
1772 */
1773 info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD)
1774#if FST_DEBUG
1775 | FSTVAL_DEBUG
1776#endif
1777 ;
1778
1779 info->lineInterface = FST_RDW(card, portConfig[i].lineInterface);
1780 info->internalClock = FST_RDB(card, portConfig[i].internalClock);
1781 info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed);
1782 info->invertClock = FST_RDB(card, portConfig[i].invertClock);
1783 info->v24IpSts = FST_RDL(card, v24IpSts[i]);
1784 info->v24OpSts = FST_RDL(card, v24OpSts[i]);
1785 info->clockStatus = FST_RDW(card, clockStatus[i]);
1786 info->cableStatus = FST_RDW(card, cableStatus);
1787 info->cardMode = FST_RDW(card, cardMode);
1788 info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion);
1789
1790 /*
1791 * The T2U can report cable presence for both A or B
1792 * in bits 0 and 1 of cableStatus. See which port we are and
1793 * do the mapping.
1794 */
1795 if (card->family == FST_FAMILY_TXU) {
1796 if (port->index == 0) {
1797 /*
1798 * Port A
1799 */
1800 info->cableStatus = info->cableStatus & 1;
1801 } else {
1802 /*
1803 * Port B
1804 */
1805 info->cableStatus = info->cableStatus >> 1;
1806 info->cableStatus = info->cableStatus & 1;
1807 }
1808 }
1809 /*
1810 * Some additional bits if we are TE1
1811 */
1812 if (card->type == FST_TYPE_TE1) {
1813 info->lineSpeed = FST_RDL(card, suConfig.dataRate);
1814 info->clockSource = FST_RDB(card, suConfig.clocking);
1815 info->framing = FST_RDB(card, suConfig.framing);
1816 info->structure = FST_RDB(card, suConfig.structure);
1817 info->interface = FST_RDB(card, suConfig.interface);
1818 info->coding = FST_RDB(card, suConfig.coding);
1819 info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut);
1820 info->equalizer = FST_RDB(card, suConfig.equalizer);
1821 info->loopMode = FST_RDB(card, suConfig.loopMode);
1822 info->range = FST_RDB(card, suConfig.range);
1823 info->txBufferMode = FST_RDB(card, suConfig.txBufferMode);
1824 info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode);
1825 info->startingSlot = FST_RDB(card, suConfig.startingSlot);
1826 info->losThreshold = FST_RDB(card, suConfig.losThreshold);
1827 if (FST_RDB(card, suConfig.enableIdleCode))
1828 info->idleCode = FST_RDB(card, suConfig.idleCode);
1829 else
1830 info->idleCode = 0;
1831 info->receiveBufferDelay =
1832 FST_RDL(card, suStatus.receiveBufferDelay);
1833 info->framingErrorCount =
1834 FST_RDL(card, suStatus.framingErrorCount);
1835 info->codeViolationCount =
1836 FST_RDL(card, suStatus.codeViolationCount);
1837 info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount);
1838 info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation);
1839 info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal);
1840 info->receiveRemoteAlarm =
1841 FST_RDB(card, suStatus.receiveRemoteAlarm);
1842 info->alarmIndicationSignal =
1843 FST_RDB(card, suStatus.alarmIndicationSignal);
1844 }
1845}
1846
1847static int
1848fst_set_iface(struct fst_card_info *card, struct fst_port_info *port,
1849 struct ifreq *ifr)
1850{
1851 sync_serial_settings sync;
1852 int i;
1853
1854 if (ifr->ifr_settings.size != sizeof (sync)) {
1855 return -ENOMEM;
1856 }
1857
1858 if (copy_from_user
1859 (&sync, ifr->ifr_settings.ifs_ifsu.sync, sizeof (sync))) {
1860 return -EFAULT;
1861 }
1862
1863 if (sync.loopback)
1864 return -EINVAL;
1865
1866 i = port->index;
1867
1868 switch (ifr->ifr_settings.type) {
1869 case IF_IFACE_V35:
1870 FST_WRW(card, portConfig[i].lineInterface, V35);
1871 port->hwif = V35;
1872 break;
1873
1874 case IF_IFACE_V24:
1875 FST_WRW(card, portConfig[i].lineInterface, V24);
1876 port->hwif = V24;
1877 break;
1878
1879 case IF_IFACE_X21:
1880 FST_WRW(card, portConfig[i].lineInterface, X21);
1881 port->hwif = X21;
1882 break;
1883
1884 case IF_IFACE_X21D:
1885 FST_WRW(card, portConfig[i].lineInterface, X21D);
1886 port->hwif = X21D;
1887 break;
1888
1889 case IF_IFACE_T1:
1890 FST_WRW(card, portConfig[i].lineInterface, T1);
1891 port->hwif = T1;
1892 break;
1893
1894 case IF_IFACE_E1:
1895 FST_WRW(card, portConfig[i].lineInterface, E1);
1896 port->hwif = E1;
1897 break;
1898
1899 case IF_IFACE_SYNC_SERIAL:
1900 break;
1901
1902 default:
1903 return -EINVAL;
1904 }
1905
1906 switch (sync.clock_type) {
1907 case CLOCK_EXT:
1908 FST_WRB(card, portConfig[i].internalClock, EXTCLK);
1909 break;
1910
1911 case CLOCK_INT:
1912 FST_WRB(card, portConfig[i].internalClock, INTCLK);
1913 break;
1914
1915 default:
1916 return -EINVAL;
1917 }
1918 FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate);
1919 return 0;
1920}
1921
1922static int
1923fst_get_iface(struct fst_card_info *card, struct fst_port_info *port,
1924 struct ifreq *ifr)
1925{
1926 sync_serial_settings sync;
1927 int i;
1928
1929 /* First check what line type is set, we'll default to reporting X.21
1930 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be
1931 * changed
1932 */
1933 switch (port->hwif) {
1934 case E1:
1935 ifr->ifr_settings.type = IF_IFACE_E1;
1936 break;
1937 case T1:
1938 ifr->ifr_settings.type = IF_IFACE_T1;
1939 break;
1940 case V35:
1941 ifr->ifr_settings.type = IF_IFACE_V35;
1942 break;
1943 case V24:
1944 ifr->ifr_settings.type = IF_IFACE_V24;
1945 break;
1946 case X21D:
1947 ifr->ifr_settings.type = IF_IFACE_X21D;
1948 break;
1949 case X21:
1950 default:
1951 ifr->ifr_settings.type = IF_IFACE_X21;
1952 break;
1953 }
1954 if (ifr->ifr_settings.size == 0) {
1955 return 0; /* only type requested */
1956 }
1957 if (ifr->ifr_settings.size < sizeof (sync)) {
1958 return -ENOMEM;
1959 }
1960
1961 i = port->index;
1962 memset(&sync, 0, sizeof(sync));
1963 sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed);
1964 /* Lucky card and linux use same encoding here */
1965 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) ==
1966 INTCLK ? CLOCK_INT : CLOCK_EXT;
1967 sync.loopback = 0;
1968
1969 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &sync, sizeof (sync))) {
1970 return -EFAULT;
1971 }
1972
1973 ifr->ifr_settings.size = sizeof (sync);
1974 return 0;
1975}
1976
1977static int
1978fst_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1979{
1980 struct fst_card_info *card;
1981 struct fst_port_info *port;
1982 struct fstioc_write wrthdr;
1983 struct fstioc_info info;
1984 unsigned long flags;
1985 void *buf;
1986
1987 dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, ifr->ifr_data);
1988
1989 port = dev_to_port(dev);
1990 card = port->card;
1991
1992 if (!capable(CAP_NET_ADMIN))
1993 return -EPERM;
1994
1995 switch (cmd) {
1996 case FSTCPURESET:
1997 fst_cpureset(card);
1998 card->state = FST_RESET;
1999 return 0;
2000
2001 case FSTCPURELEASE:
2002 fst_cpurelease(card);
2003 card->state = FST_STARTING;
2004 return 0;
2005
2006 case FSTWRITE: /* Code write (download) */
2007
2008 /* First copy in the header with the length and offset of data
2009 * to write
2010 */
2011 if (ifr->ifr_data == NULL) {
2012 return -EINVAL;
2013 }
2014 if (copy_from_user(&wrthdr, ifr->ifr_data,
2015 sizeof (struct fstioc_write))) {
2016 return -EFAULT;
2017 }
2018
2019 /* Sanity check the parameters. We don't support partial writes
2020 * when going over the top
2021 */
2022 if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE ||
2023 wrthdr.size + wrthdr.offset > FST_MEMSIZE) {
2024 return -ENXIO;
2025 }
2026
2027 /* Now copy the data to the card. */
2028
2029 buf = memdup_user(ifr->ifr_data + sizeof(struct fstioc_write),
2030 wrthdr.size);
2031 if (IS_ERR(buf))
2032 return PTR_ERR(buf);
2033
2034 memcpy_toio(card->mem + wrthdr.offset, buf, wrthdr.size);
2035 kfree(buf);
2036
2037 /* Writes to the memory of a card in the reset state constitute
2038 * a download
2039 */
2040 if (card->state == FST_RESET) {
2041 card->state = FST_DOWNLOAD;
2042 }
2043 return 0;
2044
2045 case FSTGETCONF:
2046
2047 /* If card has just been started check the shared memory config
2048 * version and marker
2049 */
2050 if (card->state == FST_STARTING) {
2051 check_started_ok(card);
2052
2053 /* If everything checked out enable card interrupts */
2054 if (card->state == FST_RUNNING) {
2055 spin_lock_irqsave(&card->card_lock, flags);
2056 fst_enable_intr(card);
2057 FST_WRB(card, interruptHandshake, 0xEE);
2058 spin_unlock_irqrestore(&card->card_lock, flags);
2059 }
2060 }
2061
2062 if (ifr->ifr_data == NULL) {
2063 return -EINVAL;
2064 }
2065
2066 gather_conf_info(card, port, &info);
2067
2068 if (copy_to_user(ifr->ifr_data, &info, sizeof (info))) {
2069 return -EFAULT;
2070 }
2071 return 0;
2072
2073 case FSTSETCONF:
2074
2075 /*
2076 * Most of the settings have been moved to the generic ioctls
2077 * this just covers debug and board ident now
2078 */
2079
2080 if (card->state != FST_RUNNING) {
2081 pr_err("Attempt to configure card %d in non-running state (%d)\n",
2082 card->card_no, card->state);
2083 return -EIO;
2084 }
2085 if (copy_from_user(&info, ifr->ifr_data, sizeof (info))) {
2086 return -EFAULT;
2087 }
2088
2089 return set_conf_from_info(card, port, &info);
2090
2091 case SIOCWANDEV:
2092 switch (ifr->ifr_settings.type) {
2093 case IF_GET_IFACE:
2094 return fst_get_iface(card, port, ifr);
2095
2096 case IF_IFACE_SYNC_SERIAL:
2097 case IF_IFACE_V35:
2098 case IF_IFACE_V24:
2099 case IF_IFACE_X21:
2100 case IF_IFACE_X21D:
2101 case IF_IFACE_T1:
2102 case IF_IFACE_E1:
2103 return fst_set_iface(card, port, ifr);
2104
2105 case IF_PROTO_RAW:
2106 port->mode = FST_RAW;
2107 return 0;
2108
2109 case IF_GET_PROTO:
2110 if (port->mode == FST_RAW) {
2111 ifr->ifr_settings.type = IF_PROTO_RAW;
2112 return 0;
2113 }
2114 return hdlc_ioctl(dev, ifr, cmd);
2115
2116 default:
2117 port->mode = FST_GEN_HDLC;
2118 dbg(DBG_IOCTL, "Passing this type to hdlc %x\n",
2119 ifr->ifr_settings.type);
2120 return hdlc_ioctl(dev, ifr, cmd);
2121 }
2122
2123 default:
2124 /* Not one of ours. Pass through to HDLC package */
2125 return hdlc_ioctl(dev, ifr, cmd);
2126 }
2127}
2128
2129static void
2130fst_openport(struct fst_port_info *port)
2131{
2132 int signals;
2133
2134 /* Only init things if card is actually running. This allows open to
2135 * succeed for downloads etc.
2136 */
2137 if (port->card->state == FST_RUNNING) {
2138 if (port->run) {
2139 dbg(DBG_OPEN, "open: found port already running\n");
2140
2141 fst_issue_cmd(port, STOPPORT);
2142 port->run = 0;
2143 }
2144
2145 fst_rx_config(port);
2146 fst_tx_config(port);
2147 fst_op_raise(port, OPSTS_RTS | OPSTS_DTR);
2148
2149 fst_issue_cmd(port, STARTPORT);
2150 port->run = 1;
2151
2152 signals = FST_RDL(port->card, v24DebouncedSts[port->index]);
2153 if (signals & (((port->hwif == X21) || (port->hwif == X21D))
2154 ? IPSTS_INDICATE : IPSTS_DCD))
2155 netif_carrier_on(port_to_dev(port));
2156 else
2157 netif_carrier_off(port_to_dev(port));
2158
2159 port->txqe = 0;
2160 port->txqs = 0;
2161 }
2162
2163}
2164
2165static void
2166fst_closeport(struct fst_port_info *port)
2167{
2168 if (port->card->state == FST_RUNNING) {
2169 if (port->run) {
2170 port->run = 0;
2171 fst_op_lower(port, OPSTS_RTS | OPSTS_DTR);
2172
2173 fst_issue_cmd(port, STOPPORT);
2174 } else {
2175 dbg(DBG_OPEN, "close: port not running\n");
2176 }
2177 }
2178}
2179
2180static int
2181fst_open(struct net_device *dev)
2182{
2183 int err;
2184 struct fst_port_info *port;
2185
2186 port = dev_to_port(dev);
2187 if (!try_module_get(THIS_MODULE))
2188 return -EBUSY;
2189
2190 if (port->mode != FST_RAW) {
2191 err = hdlc_open(dev);
2192 if (err) {
2193 module_put(THIS_MODULE);
2194 return err;
2195 }
2196 }
2197
2198 fst_openport(port);
2199 netif_wake_queue(dev);
2200 return 0;
2201}
2202
2203static int
2204fst_close(struct net_device *dev)
2205{
2206 struct fst_port_info *port;
2207 struct fst_card_info *card;
2208 unsigned char tx_dma_done;
2209 unsigned char rx_dma_done;
2210
2211 port = dev_to_port(dev);
2212 card = port->card;
2213
2214 tx_dma_done = inb(card->pci_conf + DMACSR1);
2215 rx_dma_done = inb(card->pci_conf + DMACSR0);
2216 dbg(DBG_OPEN,
2217 "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n",
2218 card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress,
2219 rx_dma_done);
2220
2221 netif_stop_queue(dev);
2222 fst_closeport(dev_to_port(dev));
2223 if (port->mode != FST_RAW) {
2224 hdlc_close(dev);
2225 }
2226 module_put(THIS_MODULE);
2227 return 0;
2228}
2229
2230static int
2231fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity)
2232{
2233 /*
2234 * Setting currently fixed in FarSync card so we check and forget
2235 */
2236 if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT)
2237 return -EINVAL;
2238 return 0;
2239}
2240
2241static void
2242fst_tx_timeout(struct net_device *dev)
2243{
2244 struct fst_port_info *port;
2245 struct fst_card_info *card;
2246
2247 port = dev_to_port(dev);
2248 card = port->card;
2249 dev->stats.tx_errors++;
2250 dev->stats.tx_aborted_errors++;
2251 dbg(DBG_ASS, "Tx timeout card %d port %d\n",
2252 card->card_no, port->index);
2253 fst_issue_cmd(port, ABORTTX);
2254
2255 netif_trans_update(dev);
2256 netif_wake_queue(dev);
2257 port->start = 0;
2258}
2259
2260static netdev_tx_t
2261fst_start_xmit(struct sk_buff *skb, struct net_device *dev)
2262{
2263 struct fst_card_info *card;
2264 struct fst_port_info *port;
2265 unsigned long flags;
2266 int txq_length;
2267
2268 port = dev_to_port(dev);
2269 card = port->card;
2270 dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len);
2271
2272 /* Drop packet with error if we don't have carrier */
2273 if (!netif_carrier_ok(dev)) {
2274 dev_kfree_skb(skb);
2275 dev->stats.tx_errors++;
2276 dev->stats.tx_carrier_errors++;
2277 dbg(DBG_ASS,
2278 "Tried to transmit but no carrier on card %d port %d\n",
2279 card->card_no, port->index);
2280 return NETDEV_TX_OK;
2281 }
2282
2283 /* Drop it if it's too big! MTU failure ? */
2284 if (skb->len > LEN_TX_BUFFER) {
2285 dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len,
2286 LEN_TX_BUFFER);
2287 dev_kfree_skb(skb);
2288 dev->stats.tx_errors++;
2289 return NETDEV_TX_OK;
2290 }
2291
2292 /*
2293 * We are always going to queue the packet
2294 * so that the bottom half is the only place we tx from
2295 * Check there is room in the port txq
2296 */
2297 spin_lock_irqsave(&card->card_lock, flags);
2298 if ((txq_length = port->txqe - port->txqs) < 0) {
2299 /*
2300 * This is the case where the next free has wrapped but the
2301 * last used hasn't
2302 */
2303 txq_length = txq_length + FST_TXQ_DEPTH;
2304 }
2305 spin_unlock_irqrestore(&card->card_lock, flags);
2306 if (txq_length > fst_txq_high) {
2307 /*
2308 * We have got enough buffers in the pipeline. Ask the network
2309 * layer to stop sending frames down
2310 */
2311 netif_stop_queue(dev);
2312 port->start = 1; /* I'm using this to signal stop sent up */
2313 }
2314
2315 if (txq_length == FST_TXQ_DEPTH - 1) {
2316 /*
2317 * This shouldn't have happened but such is life
2318 */
2319 dev_kfree_skb(skb);
2320 dev->stats.tx_errors++;
2321 dbg(DBG_ASS, "Tx queue overflow card %d port %d\n",
2322 card->card_no, port->index);
2323 return NETDEV_TX_OK;
2324 }
2325
2326 /*
2327 * queue the buffer
2328 */
2329 spin_lock_irqsave(&card->card_lock, flags);
2330 port->txq[port->txqe] = skb;
2331 port->txqe++;
2332 if (port->txqe == FST_TXQ_DEPTH)
2333 port->txqe = 0;
2334 spin_unlock_irqrestore(&card->card_lock, flags);
2335
2336 /* Scehdule the bottom half which now does transmit processing */
2337 fst_q_work_item(&fst_work_txq, card->card_no);
2338 tasklet_schedule(&fst_tx_task);
2339
2340 return NETDEV_TX_OK;
2341}
2342
2343/*
2344 * Card setup having checked hardware resources.
2345 * Should be pretty bizarre if we get an error here (kernel memory
2346 * exhaustion is one possibility). If we do see a problem we report it
2347 * via a printk and leave the corresponding interface and all that follow
2348 * disabled.
2349 */
2350static char *type_strings[] = {
2351 "no hardware", /* Should never be seen */
2352 "FarSync T2P",
2353 "FarSync T4P",
2354 "FarSync T1U",
2355 "FarSync T2U",
2356 "FarSync T4U",
2357 "FarSync TE1"
2358};
2359
2360static int
2361fst_init_card(struct fst_card_info *card)
2362{
2363 int i;
2364 int err;
2365
2366 /* We're working on a number of ports based on the card ID. If the
2367 * firmware detects something different later (should never happen)
2368 * we'll have to revise it in some way then.
2369 */
2370 for (i = 0; i < card->nports; i++) {
2371 err = register_hdlc_device(card->ports[i].dev);
2372 if (err < 0) {
2373 pr_err("Cannot register HDLC device for port %d (errno %d)\n",
2374 i, -err);
2375 while (i--)
2376 unregister_hdlc_device(card->ports[i].dev);
2377 return err;
2378 }
2379 }
2380
2381 pr_info("%s-%s: %s IRQ%d, %d ports\n",
2382 port_to_dev(&card->ports[0])->name,
2383 port_to_dev(&card->ports[card->nports - 1])->name,
2384 type_strings[card->type], card->irq, card->nports);
2385 return 0;
2386}
2387
2388static const struct net_device_ops fst_ops = {
2389 .ndo_open = fst_open,
2390 .ndo_stop = fst_close,
2391 .ndo_start_xmit = hdlc_start_xmit,
2392 .ndo_do_ioctl = fst_ioctl,
2393 .ndo_tx_timeout = fst_tx_timeout,
2394};
2395
2396/*
2397 * Initialise card when detected.
2398 * Returns 0 to indicate success, or errno otherwise.
2399 */
2400static int
2401fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2402{
2403 static int no_of_cards_added = 0;
2404 struct fst_card_info *card;
2405 int err = 0;
2406 int i;
2407
2408 printk_once(KERN_INFO
2409 pr_fmt("FarSync WAN driver " FST_USER_VERSION
2410 " (c) 2001-2004 FarSite Communications Ltd.\n"));
2411#if FST_DEBUG
2412 dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask);
2413#endif
2414 /*
2415 * We are going to be clever and allow certain cards not to be
2416 * configured. An exclude list can be provided in /etc/modules.conf
2417 */
2418 if (fst_excluded_cards != 0) {
2419 /*
2420 * There are cards to exclude
2421 *
2422 */
2423 for (i = 0; i < fst_excluded_cards; i++) {
2424 if ((pdev->devfn) >> 3 == fst_excluded_list[i]) {
2425 pr_info("FarSync PCI device %d not assigned\n",
2426 (pdev->devfn) >> 3);
2427 return -EBUSY;
2428 }
2429 }
2430 }
2431
2432 /* Allocate driver private data */
2433 card = kzalloc(sizeof(struct fst_card_info), GFP_KERNEL);
2434 if (card == NULL)
2435 return -ENOMEM;
2436
2437 /* Try to enable the device */
2438 if ((err = pci_enable_device(pdev)) != 0) {
2439 pr_err("Failed to enable card. Err %d\n", -err);
2440 goto enable_fail;
2441 }
2442
2443 if ((err = pci_request_regions(pdev, "FarSync")) !=0) {
2444 pr_err("Failed to allocate regions. Err %d\n", -err);
2445 goto regions_fail;
2446 }
2447
2448 /* Get virtual addresses of memory regions */
2449 card->pci_conf = pci_resource_start(pdev, 1);
2450 card->phys_mem = pci_resource_start(pdev, 2);
2451 card->phys_ctlmem = pci_resource_start(pdev, 3);
2452 if ((card->mem = ioremap(card->phys_mem, FST_MEMSIZE)) == NULL) {
2453 pr_err("Physical memory remap failed\n");
2454 err = -ENODEV;
2455 goto ioremap_physmem_fail;
2456 }
2457 if ((card->ctlmem = ioremap(card->phys_ctlmem, 0x10)) == NULL) {
2458 pr_err("Control memory remap failed\n");
2459 err = -ENODEV;
2460 goto ioremap_ctlmem_fail;
2461 }
2462 dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem);
2463
2464 /* Register the interrupt handler */
2465 if (request_irq(pdev->irq, fst_intr, IRQF_SHARED, FST_DEV_NAME, card)) {
2466 pr_err("Unable to register interrupt %d\n", card->irq);
2467 err = -ENODEV;
2468 goto irq_fail;
2469 }
2470
2471 /* Record info we need */
2472 card->irq = pdev->irq;
2473 card->type = ent->driver_data;
2474 card->family = ((ent->driver_data == FST_TYPE_T2P) ||
2475 (ent->driver_data == FST_TYPE_T4P))
2476 ? FST_FAMILY_TXP : FST_FAMILY_TXU;
2477 if ((ent->driver_data == FST_TYPE_T1U) ||
2478 (ent->driver_data == FST_TYPE_TE1))
2479 card->nports = 1;
2480 else
2481 card->nports = ((ent->driver_data == FST_TYPE_T2P) ||
2482 (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4;
2483
2484 card->state = FST_UNINIT;
2485 spin_lock_init ( &card->card_lock );
2486
2487 for ( i = 0 ; i < card->nports ; i++ ) {
2488 struct net_device *dev = alloc_hdlcdev(&card->ports[i]);
2489 hdlc_device *hdlc;
2490 if (!dev) {
2491 while (i--)
2492 free_netdev(card->ports[i].dev);
2493 pr_err("FarSync: out of memory\n");
2494 err = -ENOMEM;
2495 goto hdlcdev_fail;
2496 }
2497 card->ports[i].dev = dev;
2498 card->ports[i].card = card;
2499 card->ports[i].index = i;
2500 card->ports[i].run = 0;
2501
2502 hdlc = dev_to_hdlc(dev);
2503
2504 /* Fill in the net device info */
2505 /* Since this is a PCI setup this is purely
2506 * informational. Give them the buffer addresses
2507 * and basic card I/O.
2508 */
2509 dev->mem_start = card->phys_mem
2510 + BUF_OFFSET ( txBuffer[i][0][0]);
2511 dev->mem_end = card->phys_mem
2512 + BUF_OFFSET ( txBuffer[i][NUM_TX_BUFFER - 1][LEN_RX_BUFFER - 1]);
2513 dev->base_addr = card->pci_conf;
2514 dev->irq = card->irq;
2515
2516 dev->netdev_ops = &fst_ops;
2517 dev->tx_queue_len = FST_TX_QUEUE_LEN;
2518 dev->watchdog_timeo = FST_TX_TIMEOUT;
2519 hdlc->attach = fst_attach;
2520 hdlc->xmit = fst_start_xmit;
2521 }
2522
2523 card->device = pdev;
2524
2525 dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type,
2526 card->nports, card->irq);
2527 dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n",
2528 card->pci_conf, card->phys_mem, card->phys_ctlmem);
2529
2530 /* Reset the card's processor */
2531 fst_cpureset(card);
2532 card->state = FST_RESET;
2533
2534 /* Initialise DMA (if required) */
2535 fst_init_dma(card);
2536
2537 /* Record driver data for later use */
2538 pci_set_drvdata(pdev, card);
2539
2540 /* Remainder of card setup */
2541 if (no_of_cards_added >= FST_MAX_CARDS) {
2542 pr_err("FarSync: too many cards\n");
2543 err = -ENOMEM;
2544 goto card_array_fail;
2545 }
2546 fst_card_array[no_of_cards_added] = card;
2547 card->card_no = no_of_cards_added++; /* Record instance and bump it */
2548 err = fst_init_card(card);
2549 if (err)
2550 goto init_card_fail;
2551 if (card->family == FST_FAMILY_TXU) {
2552 /*
2553 * Allocate a dma buffer for transmit and receives
2554 */
2555 card->rx_dma_handle_host =
2556 pci_alloc_consistent(card->device, FST_MAX_MTU,
2557 &card->rx_dma_handle_card);
2558 if (card->rx_dma_handle_host == NULL) {
2559 pr_err("Could not allocate rx dma buffer\n");
2560 err = -ENOMEM;
2561 goto rx_dma_fail;
2562 }
2563 card->tx_dma_handle_host =
2564 pci_alloc_consistent(card->device, FST_MAX_MTU,
2565 &card->tx_dma_handle_card);
2566 if (card->tx_dma_handle_host == NULL) {
2567 pr_err("Could not allocate tx dma buffer\n");
2568 err = -ENOMEM;
2569 goto tx_dma_fail;
2570 }
2571 }
2572 return 0; /* Success */
2573
2574tx_dma_fail:
2575 pci_free_consistent(card->device, FST_MAX_MTU,
2576 card->rx_dma_handle_host,
2577 card->rx_dma_handle_card);
2578rx_dma_fail:
2579 fst_disable_intr(card);
2580 for (i = 0 ; i < card->nports ; i++)
2581 unregister_hdlc_device(card->ports[i].dev);
2582init_card_fail:
2583 fst_card_array[card->card_no] = NULL;
2584card_array_fail:
2585 for (i = 0 ; i < card->nports ; i++)
2586 free_netdev(card->ports[i].dev);
2587hdlcdev_fail:
2588 free_irq(card->irq, card);
2589irq_fail:
2590 iounmap(card->ctlmem);
2591ioremap_ctlmem_fail:
2592 iounmap(card->mem);
2593ioremap_physmem_fail:
2594 pci_release_regions(pdev);
2595regions_fail:
2596 pci_disable_device(pdev);
2597enable_fail:
2598 kfree(card);
2599 return err;
2600}
2601
2602/*
2603 * Cleanup and close down a card
2604 */
2605static void
2606fst_remove_one(struct pci_dev *pdev)
2607{
2608 struct fst_card_info *card;
2609 int i;
2610
2611 card = pci_get_drvdata(pdev);
2612
2613 for (i = 0; i < card->nports; i++) {
2614 struct net_device *dev = port_to_dev(&card->ports[i]);
2615 unregister_hdlc_device(dev);
2616 }
2617
2618 fst_disable_intr(card);
2619 free_irq(card->irq, card);
2620
2621 iounmap(card->ctlmem);
2622 iounmap(card->mem);
2623 pci_release_regions(pdev);
2624 if (card->family == FST_FAMILY_TXU) {
2625 /*
2626 * Free dma buffers
2627 */
2628 pci_free_consistent(card->device, FST_MAX_MTU,
2629 card->rx_dma_handle_host,
2630 card->rx_dma_handle_card);
2631 pci_free_consistent(card->device, FST_MAX_MTU,
2632 card->tx_dma_handle_host,
2633 card->tx_dma_handle_card);
2634 }
2635 fst_card_array[card->card_no] = NULL;
2636}
2637
2638static struct pci_driver fst_driver = {
2639 .name = FST_NAME,
2640 .id_table = fst_pci_dev_id,
2641 .probe = fst_add_one,
2642 .remove = fst_remove_one,
2643 .suspend = NULL,
2644 .resume = NULL,
2645};
2646
2647static int __init
2648fst_init(void)
2649{
2650 int i;
2651
2652 for (i = 0; i < FST_MAX_CARDS; i++)
2653 fst_card_array[i] = NULL;
2654 spin_lock_init(&fst_work_q_lock);
2655 return pci_register_driver(&fst_driver);
2656}
2657
2658static void __exit
2659fst_cleanup_module(void)
2660{
2661 pr_info("FarSync WAN driver unloading\n");
2662 pci_unregister_driver(&fst_driver);
2663}
2664
2665module_init(fst_init);
2666module_exit(fst_cleanup_module);