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1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2013 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#ifndef EFX_NIC_H
12#define EFX_NIC_H
13
14#include <linux/net_tstamp.h>
15#include <linux/i2c-algo-bit.h>
16#include "net_driver.h"
17#include "efx.h"
18#include "mcdi.h"
19
20enum {
21 EFX_REV_FALCON_A0 = 0,
22 EFX_REV_FALCON_A1 = 1,
23 EFX_REV_FALCON_B0 = 2,
24 EFX_REV_SIENA_A0 = 3,
25 EFX_REV_HUNT_A0 = 4,
26};
27
28static inline int efx_nic_rev(struct efx_nic *efx)
29{
30 return efx->type->revision;
31}
32
33u32 efx_farch_fpga_ver(struct efx_nic *efx);
34
35/* NIC has two interlinked PCI functions for the same port. */
36static inline bool efx_nic_is_dual_func(struct efx_nic *efx)
37{
38 return efx_nic_rev(efx) < EFX_REV_FALCON_B0;
39}
40
41/* Read the current event from the event queue */
42static inline efx_qword_t *efx_event(struct efx_channel *channel,
43 unsigned int index)
44{
45 return ((efx_qword_t *) (channel->eventq.buf.addr)) +
46 (index & channel->eventq_mask);
47}
48
49/* See if an event is present
50 *
51 * We check both the high and low dword of the event for all ones. We
52 * wrote all ones when we cleared the event, and no valid event can
53 * have all ones in either its high or low dwords. This approach is
54 * robust against reordering.
55 *
56 * Note that using a single 64-bit comparison is incorrect; even
57 * though the CPU read will be atomic, the DMA write may not be.
58 */
59static inline int efx_event_present(efx_qword_t *event)
60{
61 return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
62 EFX_DWORD_IS_ALL_ONES(event->dword[1]));
63}
64
65/* Returns a pointer to the specified transmit descriptor in the TX
66 * descriptor queue belonging to the specified channel.
67 */
68static inline efx_qword_t *
69efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
70{
71 return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index;
72}
73
74/* Report whether the NIC considers this TX queue empty, given the
75 * write_count used for the last doorbell push. May return false
76 * negative.
77 */
78static inline bool __efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue,
79 unsigned int write_count)
80{
81 unsigned int empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count);
82
83 if (empty_read_count == 0)
84 return false;
85
86 return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0;
87}
88
89static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue)
90{
91 return __efx_nic_tx_is_empty(tx_queue, tx_queue->write_count);
92}
93
94/* Decide whether to push a TX descriptor to the NIC vs merely writing
95 * the doorbell. This can reduce latency when we are adding a single
96 * descriptor to an empty queue, but is otherwise pointless. Further,
97 * Falcon and Siena have hardware bugs (SF bug 33851) that may be
98 * triggered if we don't check this.
99 */
100static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue,
101 unsigned int write_count)
102{
103 bool was_empty = __efx_nic_tx_is_empty(tx_queue, write_count);
104
105 tx_queue->empty_read_count = 0;
106 return was_empty && tx_queue->write_count - write_count == 1;
107}
108
109/* Returns a pointer to the specified descriptor in the RX descriptor queue */
110static inline efx_qword_t *
111efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
112{
113 return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index;
114}
115
116enum {
117 PHY_TYPE_NONE = 0,
118 PHY_TYPE_TXC43128 = 1,
119 PHY_TYPE_88E1111 = 2,
120 PHY_TYPE_SFX7101 = 3,
121 PHY_TYPE_QT2022C2 = 4,
122 PHY_TYPE_PM8358 = 6,
123 PHY_TYPE_SFT9001A = 8,
124 PHY_TYPE_QT2025C = 9,
125 PHY_TYPE_SFT9001B = 10,
126};
127
128#define FALCON_XMAC_LOOPBACKS \
129 ((1 << LOOPBACK_XGMII) | \
130 (1 << LOOPBACK_XGXS) | \
131 (1 << LOOPBACK_XAUI))
132
133/* Alignment of PCIe DMA boundaries (4KB) */
134#define EFX_PAGE_SIZE 4096
135/* Size and alignment of buffer table entries (same) */
136#define EFX_BUF_SIZE EFX_PAGE_SIZE
137
138/**
139 * struct falcon_board_type - board operations and type information
140 * @id: Board type id, as found in NVRAM
141 * @init: Allocate resources and initialise peripheral hardware
142 * @init_phy: Do board-specific PHY initialisation
143 * @fini: Shut down hardware and free resources
144 * @set_id_led: Set state of identifying LED or revert to automatic function
145 * @monitor: Board-specific health check function
146 */
147struct falcon_board_type {
148 u8 id;
149 int (*init) (struct efx_nic *nic);
150 void (*init_phy) (struct efx_nic *efx);
151 void (*fini) (struct efx_nic *nic);
152 void (*set_id_led) (struct efx_nic *efx, enum efx_led_mode mode);
153 int (*monitor) (struct efx_nic *nic);
154};
155
156/**
157 * struct falcon_board - board information
158 * @type: Type of board
159 * @major: Major rev. ('A', 'B' ...)
160 * @minor: Minor rev. (0, 1, ...)
161 * @i2c_adap: I2C adapter for on-board peripherals
162 * @i2c_data: Data for bit-banging algorithm
163 * @hwmon_client: I2C client for hardware monitor
164 * @ioexp_client: I2C client for power/port control
165 */
166struct falcon_board {
167 const struct falcon_board_type *type;
168 int major;
169 int minor;
170 struct i2c_adapter i2c_adap;
171 struct i2c_algo_bit_data i2c_data;
172 struct i2c_client *hwmon_client, *ioexp_client;
173};
174
175/**
176 * struct falcon_spi_device - a Falcon SPI (Serial Peripheral Interface) device
177 * @device_id: Controller's id for the device
178 * @size: Size (in bytes)
179 * @addr_len: Number of address bytes in read/write commands
180 * @munge_address: Flag whether addresses should be munged.
181 * Some devices with 9-bit addresses (e.g. AT25040A EEPROM)
182 * use bit 3 of the command byte as address bit A8, rather
183 * than having a two-byte address. If this flag is set, then
184 * commands should be munged in this way.
185 * @erase_command: Erase command (or 0 if sector erase not needed).
186 * @erase_size: Erase sector size (in bytes)
187 * Erase commands affect sectors with this size and alignment.
188 * This must be a power of two.
189 * @block_size: Write block size (in bytes).
190 * Write commands are limited to blocks with this size and alignment.
191 */
192struct falcon_spi_device {
193 int device_id;
194 unsigned int size;
195 unsigned int addr_len;
196 unsigned int munge_address:1;
197 u8 erase_command;
198 unsigned int erase_size;
199 unsigned int block_size;
200};
201
202static inline bool falcon_spi_present(const struct falcon_spi_device *spi)
203{
204 return spi->size != 0;
205}
206
207enum {
208 FALCON_STAT_tx_bytes,
209 FALCON_STAT_tx_packets,
210 FALCON_STAT_tx_pause,
211 FALCON_STAT_tx_control,
212 FALCON_STAT_tx_unicast,
213 FALCON_STAT_tx_multicast,
214 FALCON_STAT_tx_broadcast,
215 FALCON_STAT_tx_lt64,
216 FALCON_STAT_tx_64,
217 FALCON_STAT_tx_65_to_127,
218 FALCON_STAT_tx_128_to_255,
219 FALCON_STAT_tx_256_to_511,
220 FALCON_STAT_tx_512_to_1023,
221 FALCON_STAT_tx_1024_to_15xx,
222 FALCON_STAT_tx_15xx_to_jumbo,
223 FALCON_STAT_tx_gtjumbo,
224 FALCON_STAT_tx_non_tcpudp,
225 FALCON_STAT_tx_mac_src_error,
226 FALCON_STAT_tx_ip_src_error,
227 FALCON_STAT_rx_bytes,
228 FALCON_STAT_rx_good_bytes,
229 FALCON_STAT_rx_bad_bytes,
230 FALCON_STAT_rx_packets,
231 FALCON_STAT_rx_good,
232 FALCON_STAT_rx_bad,
233 FALCON_STAT_rx_pause,
234 FALCON_STAT_rx_control,
235 FALCON_STAT_rx_unicast,
236 FALCON_STAT_rx_multicast,
237 FALCON_STAT_rx_broadcast,
238 FALCON_STAT_rx_lt64,
239 FALCON_STAT_rx_64,
240 FALCON_STAT_rx_65_to_127,
241 FALCON_STAT_rx_128_to_255,
242 FALCON_STAT_rx_256_to_511,
243 FALCON_STAT_rx_512_to_1023,
244 FALCON_STAT_rx_1024_to_15xx,
245 FALCON_STAT_rx_15xx_to_jumbo,
246 FALCON_STAT_rx_gtjumbo,
247 FALCON_STAT_rx_bad_lt64,
248 FALCON_STAT_rx_bad_gtjumbo,
249 FALCON_STAT_rx_overflow,
250 FALCON_STAT_rx_symbol_error,
251 FALCON_STAT_rx_align_error,
252 FALCON_STAT_rx_length_error,
253 FALCON_STAT_rx_internal_error,
254 FALCON_STAT_rx_nodesc_drop_cnt,
255 FALCON_STAT_COUNT
256};
257
258/**
259 * struct falcon_nic_data - Falcon NIC state
260 * @pci_dev2: Secondary function of Falcon A
261 * @board: Board state and functions
262 * @stats: Hardware statistics
263 * @stats_disable_count: Nest count for disabling statistics fetches
264 * @stats_pending: Is there a pending DMA of MAC statistics.
265 * @stats_timer: A timer for regularly fetching MAC statistics.
266 * @spi_flash: SPI flash device
267 * @spi_eeprom: SPI EEPROM device
268 * @spi_lock: SPI bus lock
269 * @mdio_lock: MDIO bus lock
270 * @xmac_poll_required: XMAC link state needs polling
271 */
272struct falcon_nic_data {
273 struct pci_dev *pci_dev2;
274 struct falcon_board board;
275 u64 stats[FALCON_STAT_COUNT];
276 unsigned int stats_disable_count;
277 bool stats_pending;
278 struct timer_list stats_timer;
279 struct falcon_spi_device spi_flash;
280 struct falcon_spi_device spi_eeprom;
281 struct mutex spi_lock;
282 struct mutex mdio_lock;
283 bool xmac_poll_required;
284};
285
286static inline struct falcon_board *falcon_board(struct efx_nic *efx)
287{
288 struct falcon_nic_data *data = efx->nic_data;
289 return &data->board;
290}
291
292enum {
293 SIENA_STAT_tx_bytes,
294 SIENA_STAT_tx_good_bytes,
295 SIENA_STAT_tx_bad_bytes,
296 SIENA_STAT_tx_packets,
297 SIENA_STAT_tx_bad,
298 SIENA_STAT_tx_pause,
299 SIENA_STAT_tx_control,
300 SIENA_STAT_tx_unicast,
301 SIENA_STAT_tx_multicast,
302 SIENA_STAT_tx_broadcast,
303 SIENA_STAT_tx_lt64,
304 SIENA_STAT_tx_64,
305 SIENA_STAT_tx_65_to_127,
306 SIENA_STAT_tx_128_to_255,
307 SIENA_STAT_tx_256_to_511,
308 SIENA_STAT_tx_512_to_1023,
309 SIENA_STAT_tx_1024_to_15xx,
310 SIENA_STAT_tx_15xx_to_jumbo,
311 SIENA_STAT_tx_gtjumbo,
312 SIENA_STAT_tx_collision,
313 SIENA_STAT_tx_single_collision,
314 SIENA_STAT_tx_multiple_collision,
315 SIENA_STAT_tx_excessive_collision,
316 SIENA_STAT_tx_deferred,
317 SIENA_STAT_tx_late_collision,
318 SIENA_STAT_tx_excessive_deferred,
319 SIENA_STAT_tx_non_tcpudp,
320 SIENA_STAT_tx_mac_src_error,
321 SIENA_STAT_tx_ip_src_error,
322 SIENA_STAT_rx_bytes,
323 SIENA_STAT_rx_good_bytes,
324 SIENA_STAT_rx_bad_bytes,
325 SIENA_STAT_rx_packets,
326 SIENA_STAT_rx_good,
327 SIENA_STAT_rx_bad,
328 SIENA_STAT_rx_pause,
329 SIENA_STAT_rx_control,
330 SIENA_STAT_rx_unicast,
331 SIENA_STAT_rx_multicast,
332 SIENA_STAT_rx_broadcast,
333 SIENA_STAT_rx_lt64,
334 SIENA_STAT_rx_64,
335 SIENA_STAT_rx_65_to_127,
336 SIENA_STAT_rx_128_to_255,
337 SIENA_STAT_rx_256_to_511,
338 SIENA_STAT_rx_512_to_1023,
339 SIENA_STAT_rx_1024_to_15xx,
340 SIENA_STAT_rx_15xx_to_jumbo,
341 SIENA_STAT_rx_gtjumbo,
342 SIENA_STAT_rx_bad_gtjumbo,
343 SIENA_STAT_rx_overflow,
344 SIENA_STAT_rx_false_carrier,
345 SIENA_STAT_rx_symbol_error,
346 SIENA_STAT_rx_align_error,
347 SIENA_STAT_rx_length_error,
348 SIENA_STAT_rx_internal_error,
349 SIENA_STAT_rx_nodesc_drop_cnt,
350 SIENA_STAT_COUNT
351};
352
353/**
354 * struct siena_nic_data - Siena NIC state
355 * @wol_filter_id: Wake-on-LAN packet filter id
356 * @stats: Hardware statistics
357 */
358struct siena_nic_data {
359 int wol_filter_id;
360 u64 stats[SIENA_STAT_COUNT];
361};
362
363enum {
364 EF10_STAT_tx_bytes,
365 EF10_STAT_tx_packets,
366 EF10_STAT_tx_pause,
367 EF10_STAT_tx_control,
368 EF10_STAT_tx_unicast,
369 EF10_STAT_tx_multicast,
370 EF10_STAT_tx_broadcast,
371 EF10_STAT_tx_lt64,
372 EF10_STAT_tx_64,
373 EF10_STAT_tx_65_to_127,
374 EF10_STAT_tx_128_to_255,
375 EF10_STAT_tx_256_to_511,
376 EF10_STAT_tx_512_to_1023,
377 EF10_STAT_tx_1024_to_15xx,
378 EF10_STAT_tx_15xx_to_jumbo,
379 EF10_STAT_rx_bytes,
380 EF10_STAT_rx_bytes_minus_good_bytes,
381 EF10_STAT_rx_good_bytes,
382 EF10_STAT_rx_bad_bytes,
383 EF10_STAT_rx_packets,
384 EF10_STAT_rx_good,
385 EF10_STAT_rx_bad,
386 EF10_STAT_rx_pause,
387 EF10_STAT_rx_control,
388 EF10_STAT_rx_unicast,
389 EF10_STAT_rx_multicast,
390 EF10_STAT_rx_broadcast,
391 EF10_STAT_rx_lt64,
392 EF10_STAT_rx_64,
393 EF10_STAT_rx_65_to_127,
394 EF10_STAT_rx_128_to_255,
395 EF10_STAT_rx_256_to_511,
396 EF10_STAT_rx_512_to_1023,
397 EF10_STAT_rx_1024_to_15xx,
398 EF10_STAT_rx_15xx_to_jumbo,
399 EF10_STAT_rx_gtjumbo,
400 EF10_STAT_rx_bad_gtjumbo,
401 EF10_STAT_rx_overflow,
402 EF10_STAT_rx_align_error,
403 EF10_STAT_rx_length_error,
404 EF10_STAT_rx_nodesc_drops,
405 EF10_STAT_rx_pm_trunc_bb_overflow,
406 EF10_STAT_rx_pm_discard_bb_overflow,
407 EF10_STAT_rx_pm_trunc_vfifo_full,
408 EF10_STAT_rx_pm_discard_vfifo_full,
409 EF10_STAT_rx_pm_trunc_qbb,
410 EF10_STAT_rx_pm_discard_qbb,
411 EF10_STAT_rx_pm_discard_mapping,
412 EF10_STAT_rx_dp_q_disabled_packets,
413 EF10_STAT_rx_dp_di_dropped_packets,
414 EF10_STAT_rx_dp_streaming_packets,
415 EF10_STAT_rx_dp_hlb_fetch,
416 EF10_STAT_rx_dp_hlb_wait,
417 EF10_STAT_COUNT
418};
419
420/* Maximum number of TX PIO buffers we may allocate to a function.
421 * This matches the total number of buffers on each SFC9100-family
422 * controller.
423 */
424#define EF10_TX_PIOBUF_COUNT 16
425
426/**
427 * struct efx_ef10_nic_data - EF10 architecture NIC state
428 * @mcdi_buf: DMA buffer for MCDI
429 * @warm_boot_count: Last seen MC warm boot count
430 * @vi_base: Absolute index of first VI in this function
431 * @n_allocated_vis: Number of VIs allocated to this function
432 * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot
433 * @must_restore_filters: Flag: filters have yet to be restored after MC reboot
434 * @n_piobufs: Number of PIO buffers allocated to this function
435 * @wc_membase: Base address of write-combining mapping of the memory BAR
436 * @pio_write_base: Base address for writing PIO buffers
437 * @pio_write_vi_base: Relative VI number for @pio_write_base
438 * @piobuf_handle: Handle of each PIO buffer allocated
439 * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC
440 * reboot
441 * @rx_rss_context: Firmware handle for our RSS context
442 * @stats: Hardware statistics
443 * @workaround_35388: Flag: firmware supports workaround for bug 35388
444 * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated
445 * after MC reboot
446 * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of
447 * %MC_CMD_GET_CAPABILITIES response)
448 */
449struct efx_ef10_nic_data {
450 struct efx_buffer mcdi_buf;
451 u16 warm_boot_count;
452 unsigned int vi_base;
453 unsigned int n_allocated_vis;
454 bool must_realloc_vis;
455 bool must_restore_filters;
456 unsigned int n_piobufs;
457 void __iomem *wc_membase, *pio_write_base;
458 unsigned int pio_write_vi_base;
459 unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT];
460 bool must_restore_piobufs;
461 u32 rx_rss_context;
462 u64 stats[EF10_STAT_COUNT];
463 bool workaround_35388;
464 bool must_check_datapath_caps;
465 u32 datapath_caps;
466};
467
468/*
469 * On the SFC9000 family each port is associated with 1 PCI physical
470 * function (PF) handled by sfc and a configurable number of virtual
471 * functions (VFs) that may be handled by some other driver, often in
472 * a VM guest. The queue pointer registers are mapped in both PF and
473 * VF BARs such that an 8K region provides access to a single RX, TX
474 * and event queue (collectively a Virtual Interface, VI or VNIC).
475 *
476 * The PF has access to all 1024 VIs while VFs are mapped to VIs
477 * according to VI_BASE and VI_SCALE: VF i has access to VIs numbered
478 * in range [VI_BASE + i << VI_SCALE, VI_BASE + i + 1 << VI_SCALE).
479 * The number of VIs and the VI_SCALE value are configurable but must
480 * be established at boot time by firmware.
481 */
482
483/* Maximum VI_SCALE parameter supported by Siena */
484#define EFX_VI_SCALE_MAX 6
485/* Base VI to use for SR-IOV. Must be aligned to (1 << EFX_VI_SCALE_MAX),
486 * so this is the smallest allowed value. */
487#define EFX_VI_BASE 128U
488/* Maximum number of VFs allowed */
489#define EFX_VF_COUNT_MAX 127
490/* Limit EVQs on VFs to be only 8k to reduce buffer table reservation */
491#define EFX_MAX_VF_EVQ_SIZE 8192UL
492/* The number of buffer table entries reserved for each VI on a VF */
493#define EFX_VF_BUFTBL_PER_VI \
494 ((EFX_MAX_VF_EVQ_SIZE + 2 * EFX_MAX_DMAQ_SIZE) * \
495 sizeof(efx_qword_t) / EFX_BUF_SIZE)
496
497#ifdef CONFIG_SFC_SRIOV
498
499static inline bool efx_sriov_wanted(struct efx_nic *efx)
500{
501 return efx->vf_count != 0;
502}
503static inline bool efx_sriov_enabled(struct efx_nic *efx)
504{
505 return efx->vf_init_count != 0;
506}
507static inline unsigned int efx_vf_size(struct efx_nic *efx)
508{
509 return 1 << efx->vi_scale;
510}
511
512int efx_init_sriov(void);
513void efx_sriov_probe(struct efx_nic *efx);
514int efx_sriov_init(struct efx_nic *efx);
515void efx_sriov_mac_address_changed(struct efx_nic *efx);
516void efx_sriov_tx_flush_done(struct efx_nic *efx, efx_qword_t *event);
517void efx_sriov_rx_flush_done(struct efx_nic *efx, efx_qword_t *event);
518void efx_sriov_event(struct efx_channel *channel, efx_qword_t *event);
519void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq);
520void efx_sriov_flr(struct efx_nic *efx, unsigned flr);
521void efx_sriov_reset(struct efx_nic *efx);
522void efx_sriov_fini(struct efx_nic *efx);
523void efx_fini_sriov(void);
524
525#else
526
527static inline bool efx_sriov_wanted(struct efx_nic *efx) { return false; }
528static inline bool efx_sriov_enabled(struct efx_nic *efx) { return false; }
529static inline unsigned int efx_vf_size(struct efx_nic *efx) { return 0; }
530
531static inline int efx_init_sriov(void) { return 0; }
532static inline void efx_sriov_probe(struct efx_nic *efx) {}
533static inline int efx_sriov_init(struct efx_nic *efx) { return -EOPNOTSUPP; }
534static inline void efx_sriov_mac_address_changed(struct efx_nic *efx) {}
535static inline void efx_sriov_tx_flush_done(struct efx_nic *efx,
536 efx_qword_t *event) {}
537static inline void efx_sriov_rx_flush_done(struct efx_nic *efx,
538 efx_qword_t *event) {}
539static inline void efx_sriov_event(struct efx_channel *channel,
540 efx_qword_t *event) {}
541static inline void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq) {}
542static inline void efx_sriov_flr(struct efx_nic *efx, unsigned flr) {}
543static inline void efx_sriov_reset(struct efx_nic *efx) {}
544static inline void efx_sriov_fini(struct efx_nic *efx) {}
545static inline void efx_fini_sriov(void) {}
546
547#endif
548
549int efx_sriov_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
550int efx_sriov_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos);
551int efx_sriov_get_vf_config(struct net_device *dev, int vf,
552 struct ifla_vf_info *ivf);
553int efx_sriov_set_vf_spoofchk(struct net_device *net_dev, int vf,
554 bool spoofchk);
555
556struct ethtool_ts_info;
557int efx_ptp_probe(struct efx_nic *efx, struct efx_channel *channel);
558void efx_ptp_defer_probe_with_channel(struct efx_nic *efx);
559void efx_ptp_remove(struct efx_nic *efx);
560int efx_ptp_set_ts_config(struct efx_nic *efx, struct ifreq *ifr);
561int efx_ptp_get_ts_config(struct efx_nic *efx, struct ifreq *ifr);
562void efx_ptp_get_ts_info(struct efx_nic *efx, struct ethtool_ts_info *ts_info);
563bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
564int efx_ptp_get_mode(struct efx_nic *efx);
565int efx_ptp_change_mode(struct efx_nic *efx, bool enable_wanted,
566 unsigned int new_mode);
567int efx_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
568void efx_ptp_event(struct efx_nic *efx, efx_qword_t *ev);
569size_t efx_ptp_describe_stats(struct efx_nic *efx, u8 *strings);
570size_t efx_ptp_update_stats(struct efx_nic *efx, u64 *stats);
571void efx_time_sync_event(struct efx_channel *channel, efx_qword_t *ev);
572void __efx_rx_skb_attach_timestamp(struct efx_channel *channel,
573 struct sk_buff *skb);
574static inline void efx_rx_skb_attach_timestamp(struct efx_channel *channel,
575 struct sk_buff *skb)
576{
577 if (channel->sync_events_state == SYNC_EVENTS_VALID)
578 __efx_rx_skb_attach_timestamp(channel, skb);
579}
580void efx_ptp_start_datapath(struct efx_nic *efx);
581void efx_ptp_stop_datapath(struct efx_nic *efx);
582
583extern const struct efx_nic_type falcon_a1_nic_type;
584extern const struct efx_nic_type falcon_b0_nic_type;
585extern const struct efx_nic_type siena_a0_nic_type;
586extern const struct efx_nic_type efx_hunt_a0_nic_type;
587
588/**************************************************************************
589 *
590 * Externs
591 *
592 **************************************************************************
593 */
594
595int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
596
597/* TX data path */
598static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
599{
600 return tx_queue->efx->type->tx_probe(tx_queue);
601}
602static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
603{
604 tx_queue->efx->type->tx_init(tx_queue);
605}
606static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
607{
608 tx_queue->efx->type->tx_remove(tx_queue);
609}
610static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
611{
612 tx_queue->efx->type->tx_write(tx_queue);
613}
614
615/* RX data path */
616static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
617{
618 return rx_queue->efx->type->rx_probe(rx_queue);
619}
620static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
621{
622 rx_queue->efx->type->rx_init(rx_queue);
623}
624static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
625{
626 rx_queue->efx->type->rx_remove(rx_queue);
627}
628static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
629{
630 rx_queue->efx->type->rx_write(rx_queue);
631}
632static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue)
633{
634 rx_queue->efx->type->rx_defer_refill(rx_queue);
635}
636
637/* Event data path */
638static inline int efx_nic_probe_eventq(struct efx_channel *channel)
639{
640 return channel->efx->type->ev_probe(channel);
641}
642static inline int efx_nic_init_eventq(struct efx_channel *channel)
643{
644 return channel->efx->type->ev_init(channel);
645}
646static inline void efx_nic_fini_eventq(struct efx_channel *channel)
647{
648 channel->efx->type->ev_fini(channel);
649}
650static inline void efx_nic_remove_eventq(struct efx_channel *channel)
651{
652 channel->efx->type->ev_remove(channel);
653}
654static inline int
655efx_nic_process_eventq(struct efx_channel *channel, int quota)
656{
657 return channel->efx->type->ev_process(channel, quota);
658}
659static inline void efx_nic_eventq_read_ack(struct efx_channel *channel)
660{
661 channel->efx->type->ev_read_ack(channel);
662}
663void efx_nic_event_test_start(struct efx_channel *channel);
664
665/* Falcon/Siena queue operations */
666int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);
667void efx_farch_tx_init(struct efx_tx_queue *tx_queue);
668void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);
669void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);
670void efx_farch_tx_write(struct efx_tx_queue *tx_queue);
671int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);
672void efx_farch_rx_init(struct efx_rx_queue *rx_queue);
673void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);
674void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);
675void efx_farch_rx_write(struct efx_rx_queue *rx_queue);
676void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);
677int efx_farch_ev_probe(struct efx_channel *channel);
678int efx_farch_ev_init(struct efx_channel *channel);
679void efx_farch_ev_fini(struct efx_channel *channel);
680void efx_farch_ev_remove(struct efx_channel *channel);
681int efx_farch_ev_process(struct efx_channel *channel, int quota);
682void efx_farch_ev_read_ack(struct efx_channel *channel);
683void efx_farch_ev_test_generate(struct efx_channel *channel);
684
685/* Falcon/Siena filter operations */
686int efx_farch_filter_table_probe(struct efx_nic *efx);
687void efx_farch_filter_table_restore(struct efx_nic *efx);
688void efx_farch_filter_table_remove(struct efx_nic *efx);
689void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);
690s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec,
691 bool replace);
692int efx_farch_filter_remove_safe(struct efx_nic *efx,
693 enum efx_filter_priority priority,
694 u32 filter_id);
695int efx_farch_filter_get_safe(struct efx_nic *efx,
696 enum efx_filter_priority priority, u32 filter_id,
697 struct efx_filter_spec *);
698int efx_farch_filter_clear_rx(struct efx_nic *efx,
699 enum efx_filter_priority priority);
700u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
701 enum efx_filter_priority priority);
702u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);
703s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
704 enum efx_filter_priority priority, u32 *buf,
705 u32 size);
706#ifdef CONFIG_RFS_ACCEL
707s32 efx_farch_filter_rfs_insert(struct efx_nic *efx,
708 struct efx_filter_spec *spec);
709bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
710 unsigned int index);
711#endif
712void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);
713
714bool efx_nic_event_present(struct efx_channel *channel);
715
716/* Some statistics are computed as A - B where A and B each increase
717 * linearly with some hardware counter(s) and the counters are read
718 * asynchronously. If the counters contributing to B are always read
719 * after those contributing to A, the computed value may be lower than
720 * the true value by some variable amount, and may decrease between
721 * subsequent computations.
722 *
723 * We should never allow statistics to decrease or to exceed the true
724 * value. Since the computed value will never be greater than the
725 * true value, we can achieve this by only storing the computed value
726 * when it increases.
727 */
728static inline void efx_update_diff_stat(u64 *stat, u64 diff)
729{
730 if ((s64)(diff - *stat) > 0)
731 *stat = diff;
732}
733
734/* Interrupts */
735int efx_nic_init_interrupt(struct efx_nic *efx);
736void efx_nic_irq_test_start(struct efx_nic *efx);
737void efx_nic_fini_interrupt(struct efx_nic *efx);
738
739/* Falcon/Siena interrupts */
740void efx_farch_irq_enable_master(struct efx_nic *efx);
741void efx_farch_irq_test_generate(struct efx_nic *efx);
742void efx_farch_irq_disable_master(struct efx_nic *efx);
743irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);
744irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);
745irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);
746
747static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel)
748{
749 return ACCESS_ONCE(channel->event_test_cpu);
750}
751static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx)
752{
753 return ACCESS_ONCE(efx->last_irq_cpu);
754}
755
756/* Global Resources */
757int efx_nic_flush_queues(struct efx_nic *efx);
758void siena_prepare_flush(struct efx_nic *efx);
759int efx_farch_fini_dmaq(struct efx_nic *efx);
760void efx_farch_finish_flr(struct efx_nic *efx);
761void siena_finish_flush(struct efx_nic *efx);
762void falcon_start_nic_stats(struct efx_nic *efx);
763void falcon_stop_nic_stats(struct efx_nic *efx);
764int falcon_reset_xaui(struct efx_nic *efx);
765void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
766void efx_farch_init_common(struct efx_nic *efx);
767void efx_ef10_handle_drain_event(struct efx_nic *efx);
768void efx_farch_rx_push_indir_table(struct efx_nic *efx);
769
770int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
771 unsigned int len, gfp_t gfp_flags);
772void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer);
773
774/* Tests */
775struct efx_farch_register_test {
776 unsigned address;
777 efx_oword_t mask;
778};
779int efx_farch_test_registers(struct efx_nic *efx,
780 const struct efx_farch_register_test *regs,
781 size_t n_regs);
782
783size_t efx_nic_get_regs_len(struct efx_nic *efx);
784void efx_nic_get_regs(struct efx_nic *efx, void *buf);
785
786size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
787 const unsigned long *mask, u8 *names);
788void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
789 const unsigned long *mask, u64 *stats,
790 const void *dma_buf, bool accumulate);
791void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat);
792
793#define EFX_MAX_FLUSH_TIME 5000
794
795void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
796 efx_qword_t *event);
797
798#endif /* EFX_NIC_H */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
6 */
7
8#ifndef EFX_NIC_H
9#define EFX_NIC_H
10
11#include <linux/net_tstamp.h>
12#include <linux/i2c-algo-bit.h>
13#include "net_driver.h"
14#include "efx.h"
15#include "mcdi.h"
16
17enum {
18 /* Revisions 0-2 were Falcon A0, A1 and B0 respectively.
19 * They are not supported by this driver but these revision numbers
20 * form part of the ethtool API for register dumping.
21 */
22 EFX_REV_SIENA_A0 = 3,
23 EFX_REV_HUNT_A0 = 4,
24};
25
26static inline int efx_nic_rev(struct efx_nic *efx)
27{
28 return efx->type->revision;
29}
30
31u32 efx_farch_fpga_ver(struct efx_nic *efx);
32
33/* Read the current event from the event queue */
34static inline efx_qword_t *efx_event(struct efx_channel *channel,
35 unsigned int index)
36{
37 return ((efx_qword_t *) (channel->eventq.buf.addr)) +
38 (index & channel->eventq_mask);
39}
40
41/* See if an event is present
42 *
43 * We check both the high and low dword of the event for all ones. We
44 * wrote all ones when we cleared the event, and no valid event can
45 * have all ones in either its high or low dwords. This approach is
46 * robust against reordering.
47 *
48 * Note that using a single 64-bit comparison is incorrect; even
49 * though the CPU read will be atomic, the DMA write may not be.
50 */
51static inline int efx_event_present(efx_qword_t *event)
52{
53 return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
54 EFX_DWORD_IS_ALL_ONES(event->dword[1]));
55}
56
57/* Returns a pointer to the specified transmit descriptor in the TX
58 * descriptor queue belonging to the specified channel.
59 */
60static inline efx_qword_t *
61efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
62{
63 return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index;
64}
65
66/* Get partner of a TX queue, seen as part of the same net core queue */
67static struct efx_tx_queue *efx_tx_queue_partner(struct efx_tx_queue *tx_queue)
68{
69 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
70 return tx_queue - EFX_TXQ_TYPE_OFFLOAD;
71 else
72 return tx_queue + EFX_TXQ_TYPE_OFFLOAD;
73}
74
75/* Report whether this TX queue would be empty for the given write_count.
76 * May return false negative.
77 */
78static inline bool __efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue,
79 unsigned int write_count)
80{
81 unsigned int empty_read_count = READ_ONCE(tx_queue->empty_read_count);
82
83 if (empty_read_count == 0)
84 return false;
85
86 return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0;
87}
88
89/* Report whether the NIC considers this TX queue empty, using
90 * packet_write_count (the write count recorded for the last completable
91 * doorbell push). May return false negative. EF10 only, which is OK
92 * because only EF10 supports PIO.
93 */
94static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue)
95{
96 EFX_WARN_ON_ONCE_PARANOID(!tx_queue->efx->type->option_descriptors);
97 return __efx_nic_tx_is_empty(tx_queue, tx_queue->packet_write_count);
98}
99
100/* Decide whether we can use TX PIO, ie. write packet data directly into
101 * a buffer on the device. This can reduce latency at the expense of
102 * throughput, so we only do this if both hardware and software TX rings
103 * are empty. This also ensures that only one packet at a time can be
104 * using the PIO buffer.
105 */
106static inline bool efx_nic_may_tx_pio(struct efx_tx_queue *tx_queue)
107{
108 struct efx_tx_queue *partner = efx_tx_queue_partner(tx_queue);
109
110 return tx_queue->piobuf && efx_nic_tx_is_empty(tx_queue) &&
111 efx_nic_tx_is_empty(partner);
112}
113
114/* Decide whether to push a TX descriptor to the NIC vs merely writing
115 * the doorbell. This can reduce latency when we are adding a single
116 * descriptor to an empty queue, but is otherwise pointless. Further,
117 * Falcon and Siena have hardware bugs (SF bug 33851) that may be
118 * triggered if we don't check this.
119 * We use the write_count used for the last doorbell push, to get the
120 * NIC's view of the tx queue.
121 */
122static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue,
123 unsigned int write_count)
124{
125 bool was_empty = __efx_nic_tx_is_empty(tx_queue, write_count);
126
127 tx_queue->empty_read_count = 0;
128 return was_empty && tx_queue->write_count - write_count == 1;
129}
130
131/* Returns a pointer to the specified descriptor in the RX descriptor queue */
132static inline efx_qword_t *
133efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
134{
135 return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index;
136}
137
138enum {
139 PHY_TYPE_NONE = 0,
140 PHY_TYPE_TXC43128 = 1,
141 PHY_TYPE_88E1111 = 2,
142 PHY_TYPE_SFX7101 = 3,
143 PHY_TYPE_QT2022C2 = 4,
144 PHY_TYPE_PM8358 = 6,
145 PHY_TYPE_SFT9001A = 8,
146 PHY_TYPE_QT2025C = 9,
147 PHY_TYPE_SFT9001B = 10,
148};
149
150/* Alignment of PCIe DMA boundaries (4KB) */
151#define EFX_PAGE_SIZE 4096
152/* Size and alignment of buffer table entries (same) */
153#define EFX_BUF_SIZE EFX_PAGE_SIZE
154
155/* NIC-generic software stats */
156enum {
157 GENERIC_STAT_rx_noskb_drops,
158 GENERIC_STAT_rx_nodesc_trunc,
159 GENERIC_STAT_COUNT
160};
161
162enum {
163 SIENA_STAT_tx_bytes = GENERIC_STAT_COUNT,
164 SIENA_STAT_tx_good_bytes,
165 SIENA_STAT_tx_bad_bytes,
166 SIENA_STAT_tx_packets,
167 SIENA_STAT_tx_bad,
168 SIENA_STAT_tx_pause,
169 SIENA_STAT_tx_control,
170 SIENA_STAT_tx_unicast,
171 SIENA_STAT_tx_multicast,
172 SIENA_STAT_tx_broadcast,
173 SIENA_STAT_tx_lt64,
174 SIENA_STAT_tx_64,
175 SIENA_STAT_tx_65_to_127,
176 SIENA_STAT_tx_128_to_255,
177 SIENA_STAT_tx_256_to_511,
178 SIENA_STAT_tx_512_to_1023,
179 SIENA_STAT_tx_1024_to_15xx,
180 SIENA_STAT_tx_15xx_to_jumbo,
181 SIENA_STAT_tx_gtjumbo,
182 SIENA_STAT_tx_collision,
183 SIENA_STAT_tx_single_collision,
184 SIENA_STAT_tx_multiple_collision,
185 SIENA_STAT_tx_excessive_collision,
186 SIENA_STAT_tx_deferred,
187 SIENA_STAT_tx_late_collision,
188 SIENA_STAT_tx_excessive_deferred,
189 SIENA_STAT_tx_non_tcpudp,
190 SIENA_STAT_tx_mac_src_error,
191 SIENA_STAT_tx_ip_src_error,
192 SIENA_STAT_rx_bytes,
193 SIENA_STAT_rx_good_bytes,
194 SIENA_STAT_rx_bad_bytes,
195 SIENA_STAT_rx_packets,
196 SIENA_STAT_rx_good,
197 SIENA_STAT_rx_bad,
198 SIENA_STAT_rx_pause,
199 SIENA_STAT_rx_control,
200 SIENA_STAT_rx_unicast,
201 SIENA_STAT_rx_multicast,
202 SIENA_STAT_rx_broadcast,
203 SIENA_STAT_rx_lt64,
204 SIENA_STAT_rx_64,
205 SIENA_STAT_rx_65_to_127,
206 SIENA_STAT_rx_128_to_255,
207 SIENA_STAT_rx_256_to_511,
208 SIENA_STAT_rx_512_to_1023,
209 SIENA_STAT_rx_1024_to_15xx,
210 SIENA_STAT_rx_15xx_to_jumbo,
211 SIENA_STAT_rx_gtjumbo,
212 SIENA_STAT_rx_bad_gtjumbo,
213 SIENA_STAT_rx_overflow,
214 SIENA_STAT_rx_false_carrier,
215 SIENA_STAT_rx_symbol_error,
216 SIENA_STAT_rx_align_error,
217 SIENA_STAT_rx_length_error,
218 SIENA_STAT_rx_internal_error,
219 SIENA_STAT_rx_nodesc_drop_cnt,
220 SIENA_STAT_COUNT
221};
222
223/**
224 * struct siena_nic_data - Siena NIC state
225 * @efx: Pointer back to main interface structure
226 * @wol_filter_id: Wake-on-LAN packet filter id
227 * @stats: Hardware statistics
228 * @vf: Array of &struct siena_vf objects
229 * @vf_buftbl_base: The zeroth buffer table index used to back VF queues.
230 * @vfdi_status: Common VFDI status page to be dmad to VF address space.
231 * @local_addr_list: List of local addresses. Protected by %local_lock.
232 * @local_page_list: List of DMA addressable pages used to broadcast
233 * %local_addr_list. Protected by %local_lock.
234 * @local_lock: Mutex protecting %local_addr_list and %local_page_list.
235 * @peer_work: Work item to broadcast peer addresses to VMs.
236 */
237struct siena_nic_data {
238 struct efx_nic *efx;
239 int wol_filter_id;
240 u64 stats[SIENA_STAT_COUNT];
241#ifdef CONFIG_SFC_SRIOV
242 struct siena_vf *vf;
243 struct efx_channel *vfdi_channel;
244 unsigned vf_buftbl_base;
245 struct efx_buffer vfdi_status;
246 struct list_head local_addr_list;
247 struct list_head local_page_list;
248 struct mutex local_lock;
249 struct work_struct peer_work;
250#endif
251};
252
253enum {
254 EF10_STAT_port_tx_bytes = GENERIC_STAT_COUNT,
255 EF10_STAT_port_tx_packets,
256 EF10_STAT_port_tx_pause,
257 EF10_STAT_port_tx_control,
258 EF10_STAT_port_tx_unicast,
259 EF10_STAT_port_tx_multicast,
260 EF10_STAT_port_tx_broadcast,
261 EF10_STAT_port_tx_lt64,
262 EF10_STAT_port_tx_64,
263 EF10_STAT_port_tx_65_to_127,
264 EF10_STAT_port_tx_128_to_255,
265 EF10_STAT_port_tx_256_to_511,
266 EF10_STAT_port_tx_512_to_1023,
267 EF10_STAT_port_tx_1024_to_15xx,
268 EF10_STAT_port_tx_15xx_to_jumbo,
269 EF10_STAT_port_rx_bytes,
270 EF10_STAT_port_rx_bytes_minus_good_bytes,
271 EF10_STAT_port_rx_good_bytes,
272 EF10_STAT_port_rx_bad_bytes,
273 EF10_STAT_port_rx_packets,
274 EF10_STAT_port_rx_good,
275 EF10_STAT_port_rx_bad,
276 EF10_STAT_port_rx_pause,
277 EF10_STAT_port_rx_control,
278 EF10_STAT_port_rx_unicast,
279 EF10_STAT_port_rx_multicast,
280 EF10_STAT_port_rx_broadcast,
281 EF10_STAT_port_rx_lt64,
282 EF10_STAT_port_rx_64,
283 EF10_STAT_port_rx_65_to_127,
284 EF10_STAT_port_rx_128_to_255,
285 EF10_STAT_port_rx_256_to_511,
286 EF10_STAT_port_rx_512_to_1023,
287 EF10_STAT_port_rx_1024_to_15xx,
288 EF10_STAT_port_rx_15xx_to_jumbo,
289 EF10_STAT_port_rx_gtjumbo,
290 EF10_STAT_port_rx_bad_gtjumbo,
291 EF10_STAT_port_rx_overflow,
292 EF10_STAT_port_rx_align_error,
293 EF10_STAT_port_rx_length_error,
294 EF10_STAT_port_rx_nodesc_drops,
295 EF10_STAT_port_rx_pm_trunc_bb_overflow,
296 EF10_STAT_port_rx_pm_discard_bb_overflow,
297 EF10_STAT_port_rx_pm_trunc_vfifo_full,
298 EF10_STAT_port_rx_pm_discard_vfifo_full,
299 EF10_STAT_port_rx_pm_trunc_qbb,
300 EF10_STAT_port_rx_pm_discard_qbb,
301 EF10_STAT_port_rx_pm_discard_mapping,
302 EF10_STAT_port_rx_dp_q_disabled_packets,
303 EF10_STAT_port_rx_dp_di_dropped_packets,
304 EF10_STAT_port_rx_dp_streaming_packets,
305 EF10_STAT_port_rx_dp_hlb_fetch,
306 EF10_STAT_port_rx_dp_hlb_wait,
307 EF10_STAT_rx_unicast,
308 EF10_STAT_rx_unicast_bytes,
309 EF10_STAT_rx_multicast,
310 EF10_STAT_rx_multicast_bytes,
311 EF10_STAT_rx_broadcast,
312 EF10_STAT_rx_broadcast_bytes,
313 EF10_STAT_rx_bad,
314 EF10_STAT_rx_bad_bytes,
315 EF10_STAT_rx_overflow,
316 EF10_STAT_tx_unicast,
317 EF10_STAT_tx_unicast_bytes,
318 EF10_STAT_tx_multicast,
319 EF10_STAT_tx_multicast_bytes,
320 EF10_STAT_tx_broadcast,
321 EF10_STAT_tx_broadcast_bytes,
322 EF10_STAT_tx_bad,
323 EF10_STAT_tx_bad_bytes,
324 EF10_STAT_tx_overflow,
325 EF10_STAT_V1_COUNT,
326 EF10_STAT_fec_uncorrected_errors = EF10_STAT_V1_COUNT,
327 EF10_STAT_fec_corrected_errors,
328 EF10_STAT_fec_corrected_symbols_lane0,
329 EF10_STAT_fec_corrected_symbols_lane1,
330 EF10_STAT_fec_corrected_symbols_lane2,
331 EF10_STAT_fec_corrected_symbols_lane3,
332 EF10_STAT_ctpio_vi_busy_fallback,
333 EF10_STAT_ctpio_long_write_success,
334 EF10_STAT_ctpio_missing_dbell_fail,
335 EF10_STAT_ctpio_overflow_fail,
336 EF10_STAT_ctpio_underflow_fail,
337 EF10_STAT_ctpio_timeout_fail,
338 EF10_STAT_ctpio_noncontig_wr_fail,
339 EF10_STAT_ctpio_frm_clobber_fail,
340 EF10_STAT_ctpio_invalid_wr_fail,
341 EF10_STAT_ctpio_vi_clobber_fallback,
342 EF10_STAT_ctpio_unqualified_fallback,
343 EF10_STAT_ctpio_runt_fallback,
344 EF10_STAT_ctpio_success,
345 EF10_STAT_ctpio_fallback,
346 EF10_STAT_ctpio_poison,
347 EF10_STAT_ctpio_erase,
348 EF10_STAT_COUNT
349};
350
351/* Maximum number of TX PIO buffers we may allocate to a function.
352 * This matches the total number of buffers on each SFC9100-family
353 * controller.
354 */
355#define EF10_TX_PIOBUF_COUNT 16
356
357/**
358 * struct efx_ef10_nic_data - EF10 architecture NIC state
359 * @mcdi_buf: DMA buffer for MCDI
360 * @warm_boot_count: Last seen MC warm boot count
361 * @vi_base: Absolute index of first VI in this function
362 * @n_allocated_vis: Number of VIs allocated to this function
363 * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot
364 * @must_restore_rss_contexts: Flag: RSS contexts have yet to be restored after
365 * MC reboot
366 * @must_restore_filters: Flag: filters have yet to be restored after MC reboot
367 * @n_piobufs: Number of PIO buffers allocated to this function
368 * @wc_membase: Base address of write-combining mapping of the memory BAR
369 * @pio_write_base: Base address for writing PIO buffers
370 * @pio_write_vi_base: Relative VI number for @pio_write_base
371 * @piobuf_handle: Handle of each PIO buffer allocated
372 * @piobuf_size: size of a single PIO buffer
373 * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC
374 * reboot
375 * @rx_rss_context_exclusive: Whether our RSS context is exclusive or shared
376 * @stats: Hardware statistics
377 * @workaround_35388: Flag: firmware supports workaround for bug 35388
378 * @workaround_26807: Flag: firmware supports workaround for bug 26807
379 * @workaround_61265: Flag: firmware supports workaround for bug 61265
380 * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated
381 * after MC reboot
382 * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of
383 * %MC_CMD_GET_CAPABILITIES response)
384 * @datapath_caps2: Further Capabilities of datapath firmware (FLAGS2 field of
385 * %MC_CMD_GET_CAPABILITIES response)
386 * @rx_dpcpu_fw_id: Firmware ID of the RxDPCPU
387 * @tx_dpcpu_fw_id: Firmware ID of the TxDPCPU
388 * @vport_id: The function's vport ID, only relevant for PFs
389 * @must_probe_vswitching: Flag: vswitching has yet to be setup after MC reboot
390 * @pf_index: The number for this PF, or the parent PF if this is a VF
391#ifdef CONFIG_SFC_SRIOV
392 * @vf: Pointer to VF data structure
393#endif
394 * @vport_mac: The MAC address on the vport, only for PFs; VFs will be zero
395 * @vlan_list: List of VLANs added over the interface. Serialised by vlan_lock.
396 * @vlan_lock: Lock to serialize access to vlan_list.
397 * @udp_tunnels: UDP tunnel port numbers and types.
398 * @udp_tunnels_dirty: flag indicating a reboot occurred while pushing
399 * @udp_tunnels to hardware and thus the push must be re-done.
400 * @udp_tunnels_lock: Serialises writes to @udp_tunnels and @udp_tunnels_dirty.
401 */
402struct efx_ef10_nic_data {
403 struct efx_buffer mcdi_buf;
404 u16 warm_boot_count;
405 unsigned int vi_base;
406 unsigned int n_allocated_vis;
407 bool must_realloc_vis;
408 bool must_restore_rss_contexts;
409 bool must_restore_filters;
410 unsigned int n_piobufs;
411 void __iomem *wc_membase, *pio_write_base;
412 unsigned int pio_write_vi_base;
413 unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT];
414 u16 piobuf_size;
415 bool must_restore_piobufs;
416 bool rx_rss_context_exclusive;
417 u64 stats[EF10_STAT_COUNT];
418 bool workaround_35388;
419 bool workaround_26807;
420 bool workaround_61265;
421 bool must_check_datapath_caps;
422 u32 datapath_caps;
423 u32 datapath_caps2;
424 unsigned int rx_dpcpu_fw_id;
425 unsigned int tx_dpcpu_fw_id;
426 unsigned int vport_id;
427 bool must_probe_vswitching;
428 unsigned int pf_index;
429 u8 port_id[ETH_ALEN];
430#ifdef CONFIG_SFC_SRIOV
431 unsigned int vf_index;
432 struct ef10_vf *vf;
433#endif
434 u8 vport_mac[ETH_ALEN];
435 struct list_head vlan_list;
436 struct mutex vlan_lock;
437 struct efx_udp_tunnel udp_tunnels[16];
438 bool udp_tunnels_dirty;
439 struct mutex udp_tunnels_lock;
440 u64 licensed_features;
441};
442
443int efx_init_sriov(void);
444void efx_fini_sriov(void);
445
446struct ethtool_ts_info;
447int efx_ptp_probe(struct efx_nic *efx, struct efx_channel *channel);
448void efx_ptp_defer_probe_with_channel(struct efx_nic *efx);
449struct efx_channel *efx_ptp_channel(struct efx_nic *efx);
450void efx_ptp_remove(struct efx_nic *efx);
451int efx_ptp_set_ts_config(struct efx_nic *efx, struct ifreq *ifr);
452int efx_ptp_get_ts_config(struct efx_nic *efx, struct ifreq *ifr);
453void efx_ptp_get_ts_info(struct efx_nic *efx, struct ethtool_ts_info *ts_info);
454bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
455int efx_ptp_get_mode(struct efx_nic *efx);
456int efx_ptp_change_mode(struct efx_nic *efx, bool enable_wanted,
457 unsigned int new_mode);
458int efx_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
459void efx_ptp_event(struct efx_nic *efx, efx_qword_t *ev);
460size_t efx_ptp_describe_stats(struct efx_nic *efx, u8 *strings);
461size_t efx_ptp_update_stats(struct efx_nic *efx, u64 *stats);
462void efx_time_sync_event(struct efx_channel *channel, efx_qword_t *ev);
463void __efx_rx_skb_attach_timestamp(struct efx_channel *channel,
464 struct sk_buff *skb);
465static inline void efx_rx_skb_attach_timestamp(struct efx_channel *channel,
466 struct sk_buff *skb)
467{
468 if (channel->sync_events_state == SYNC_EVENTS_VALID)
469 __efx_rx_skb_attach_timestamp(channel, skb);
470}
471void efx_ptp_start_datapath(struct efx_nic *efx);
472void efx_ptp_stop_datapath(struct efx_nic *efx);
473bool efx_ptp_use_mac_tx_timestamps(struct efx_nic *efx);
474ktime_t efx_ptp_nic_to_kernel_time(struct efx_tx_queue *tx_queue);
475
476extern const struct efx_nic_type falcon_a1_nic_type;
477extern const struct efx_nic_type falcon_b0_nic_type;
478extern const struct efx_nic_type siena_a0_nic_type;
479extern const struct efx_nic_type efx_hunt_a0_nic_type;
480extern const struct efx_nic_type efx_hunt_a0_vf_nic_type;
481
482/**************************************************************************
483 *
484 * Externs
485 *
486 **************************************************************************
487 */
488
489int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
490
491/* TX data path */
492static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
493{
494 return tx_queue->efx->type->tx_probe(tx_queue);
495}
496static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
497{
498 tx_queue->efx->type->tx_init(tx_queue);
499}
500static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
501{
502 tx_queue->efx->type->tx_remove(tx_queue);
503}
504static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
505{
506 tx_queue->efx->type->tx_write(tx_queue);
507}
508
509/* RX data path */
510static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
511{
512 return rx_queue->efx->type->rx_probe(rx_queue);
513}
514static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
515{
516 rx_queue->efx->type->rx_init(rx_queue);
517}
518static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
519{
520 rx_queue->efx->type->rx_remove(rx_queue);
521}
522static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
523{
524 rx_queue->efx->type->rx_write(rx_queue);
525}
526static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue)
527{
528 rx_queue->efx->type->rx_defer_refill(rx_queue);
529}
530
531/* Event data path */
532static inline int efx_nic_probe_eventq(struct efx_channel *channel)
533{
534 return channel->efx->type->ev_probe(channel);
535}
536static inline int efx_nic_init_eventq(struct efx_channel *channel)
537{
538 return channel->efx->type->ev_init(channel);
539}
540static inline void efx_nic_fini_eventq(struct efx_channel *channel)
541{
542 channel->efx->type->ev_fini(channel);
543}
544static inline void efx_nic_remove_eventq(struct efx_channel *channel)
545{
546 channel->efx->type->ev_remove(channel);
547}
548static inline int
549efx_nic_process_eventq(struct efx_channel *channel, int quota)
550{
551 return channel->efx->type->ev_process(channel, quota);
552}
553static inline void efx_nic_eventq_read_ack(struct efx_channel *channel)
554{
555 channel->efx->type->ev_read_ack(channel);
556}
557void efx_nic_event_test_start(struct efx_channel *channel);
558
559/* Falcon/Siena queue operations */
560int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);
561void efx_farch_tx_init(struct efx_tx_queue *tx_queue);
562void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);
563void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);
564void efx_farch_tx_write(struct efx_tx_queue *tx_queue);
565unsigned int efx_farch_tx_limit_len(struct efx_tx_queue *tx_queue,
566 dma_addr_t dma_addr, unsigned int len);
567int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);
568void efx_farch_rx_init(struct efx_rx_queue *rx_queue);
569void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);
570void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);
571void efx_farch_rx_write(struct efx_rx_queue *rx_queue);
572void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);
573int efx_farch_ev_probe(struct efx_channel *channel);
574int efx_farch_ev_init(struct efx_channel *channel);
575void efx_farch_ev_fini(struct efx_channel *channel);
576void efx_farch_ev_remove(struct efx_channel *channel);
577int efx_farch_ev_process(struct efx_channel *channel, int quota);
578void efx_farch_ev_read_ack(struct efx_channel *channel);
579void efx_farch_ev_test_generate(struct efx_channel *channel);
580
581/* Falcon/Siena filter operations */
582int efx_farch_filter_table_probe(struct efx_nic *efx);
583void efx_farch_filter_table_restore(struct efx_nic *efx);
584void efx_farch_filter_table_remove(struct efx_nic *efx);
585void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);
586s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec,
587 bool replace);
588int efx_farch_filter_remove_safe(struct efx_nic *efx,
589 enum efx_filter_priority priority,
590 u32 filter_id);
591int efx_farch_filter_get_safe(struct efx_nic *efx,
592 enum efx_filter_priority priority, u32 filter_id,
593 struct efx_filter_spec *);
594int efx_farch_filter_clear_rx(struct efx_nic *efx,
595 enum efx_filter_priority priority);
596u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
597 enum efx_filter_priority priority);
598u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);
599s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
600 enum efx_filter_priority priority, u32 *buf,
601 u32 size);
602#ifdef CONFIG_RFS_ACCEL
603bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
604 unsigned int index);
605#endif
606void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);
607
608bool efx_nic_event_present(struct efx_channel *channel);
609
610/* Some statistics are computed as A - B where A and B each increase
611 * linearly with some hardware counter(s) and the counters are read
612 * asynchronously. If the counters contributing to B are always read
613 * after those contributing to A, the computed value may be lower than
614 * the true value by some variable amount, and may decrease between
615 * subsequent computations.
616 *
617 * We should never allow statistics to decrease or to exceed the true
618 * value. Since the computed value will never be greater than the
619 * true value, we can achieve this by only storing the computed value
620 * when it increases.
621 */
622static inline void efx_update_diff_stat(u64 *stat, u64 diff)
623{
624 if ((s64)(diff - *stat) > 0)
625 *stat = diff;
626}
627
628/* Interrupts */
629int efx_nic_init_interrupt(struct efx_nic *efx);
630int efx_nic_irq_test_start(struct efx_nic *efx);
631void efx_nic_fini_interrupt(struct efx_nic *efx);
632
633/* Falcon/Siena interrupts */
634void efx_farch_irq_enable_master(struct efx_nic *efx);
635int efx_farch_irq_test_generate(struct efx_nic *efx);
636void efx_farch_irq_disable_master(struct efx_nic *efx);
637irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);
638irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);
639irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);
640
641static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel)
642{
643 return READ_ONCE(channel->event_test_cpu);
644}
645static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx)
646{
647 return READ_ONCE(efx->last_irq_cpu);
648}
649
650/* Global Resources */
651int efx_nic_flush_queues(struct efx_nic *efx);
652void siena_prepare_flush(struct efx_nic *efx);
653int efx_farch_fini_dmaq(struct efx_nic *efx);
654void efx_farch_finish_flr(struct efx_nic *efx);
655void siena_finish_flush(struct efx_nic *efx);
656void falcon_start_nic_stats(struct efx_nic *efx);
657void falcon_stop_nic_stats(struct efx_nic *efx);
658int falcon_reset_xaui(struct efx_nic *efx);
659void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
660void efx_farch_init_common(struct efx_nic *efx);
661void efx_ef10_handle_drain_event(struct efx_nic *efx);
662void efx_farch_rx_push_indir_table(struct efx_nic *efx);
663void efx_farch_rx_pull_indir_table(struct efx_nic *efx);
664
665int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
666 unsigned int len, gfp_t gfp_flags);
667void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer);
668
669/* Tests */
670struct efx_farch_register_test {
671 unsigned address;
672 efx_oword_t mask;
673};
674int efx_farch_test_registers(struct efx_nic *efx,
675 const struct efx_farch_register_test *regs,
676 size_t n_regs);
677
678size_t efx_nic_get_regs_len(struct efx_nic *efx);
679void efx_nic_get_regs(struct efx_nic *efx, void *buf);
680
681size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
682 const unsigned long *mask, u8 *names);
683void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
684 const unsigned long *mask, u64 *stats,
685 const void *dma_buf, bool accumulate);
686void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat);
687
688#define EFX_MAX_FLUSH_TIME 5000
689
690void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
691 efx_qword_t *event);
692
693#endif /* EFX_NIC_H */