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1// SPDX-License-Identifier: GPL-2.0
2/* Renesas Ethernet AVB device driver
3 *
4 * Copyright (C) 2014-2019 Renesas Electronics Corporation
5 * Copyright (C) 2015 Renesas Solutions Corp.
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7 *
8 * Based on the SuperH Ethernet driver
9 */
10
11#include <linux/cache.h>
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/dma-mapping.h>
15#include <linux/err.h>
16#include <linux/etherdevice.h>
17#include <linux/ethtool.h>
18#include <linux/if_vlan.h>
19#include <linux/kernel.h>
20#include <linux/list.h>
21#include <linux/module.h>
22#include <linux/net_tstamp.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/of_irq.h>
26#include <linux/of_mdio.h>
27#include <linux/of_net.h>
28#include <linux/pm_runtime.h>
29#include <linux/slab.h>
30#include <linux/spinlock.h>
31#include <linux/sys_soc.h>
32
33#include <asm/div64.h>
34
35#include "ravb.h"
36
37#define RAVB_DEF_MSG_ENABLE \
38 (NETIF_MSG_LINK | \
39 NETIF_MSG_TIMER | \
40 NETIF_MSG_RX_ERR | \
41 NETIF_MSG_TX_ERR)
42
43static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
44 "ch0", /* RAVB_BE */
45 "ch1", /* RAVB_NC */
46};
47
48static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
49 "ch18", /* RAVB_BE */
50 "ch19", /* RAVB_NC */
51};
52
53void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
54 u32 set)
55{
56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
57}
58
59int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
60{
61 int i;
62
63 for (i = 0; i < 10000; i++) {
64 if ((ravb_read(ndev, reg) & mask) == value)
65 return 0;
66 udelay(10);
67 }
68 return -ETIMEDOUT;
69}
70
71static int ravb_config(struct net_device *ndev)
72{
73 int error;
74
75 /* Set config mode */
76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
77 /* Check if the operating mode is changed to the config mode */
78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
79 if (error)
80 netdev_err(ndev, "failed to switch device to config mode\n");
81
82 return error;
83}
84
85static void ravb_set_rate(struct net_device *ndev)
86{
87 struct ravb_private *priv = netdev_priv(ndev);
88
89 switch (priv->speed) {
90 case 100: /* 100BASE */
91 ravb_write(ndev, GECMR_SPEED_100, GECMR);
92 break;
93 case 1000: /* 1000BASE */
94 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
95 break;
96 }
97}
98
99static void ravb_set_buffer_align(struct sk_buff *skb)
100{
101 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
102
103 if (reserve)
104 skb_reserve(skb, RAVB_ALIGN - reserve);
105}
106
107/* Get MAC address from the MAC address registers
108 *
109 * Ethernet AVB device doesn't have ROM for MAC address.
110 * This function gets the MAC address that was used by a bootloader.
111 */
112static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
113{
114 if (!IS_ERR(mac)) {
115 ether_addr_copy(ndev->dev_addr, mac);
116 } else {
117 u32 mahr = ravb_read(ndev, MAHR);
118 u32 malr = ravb_read(ndev, MALR);
119
120 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
121 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
122 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
123 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
124 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
125 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
126 }
127}
128
129static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
130{
131 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
132 mdiobb);
133
134 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
135}
136
137/* MDC pin control */
138static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
139{
140 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
141}
142
143/* Data I/O pin control */
144static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
145{
146 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
147}
148
149/* Set data bit */
150static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
151{
152 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
153}
154
155/* Get data bit */
156static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
157{
158 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
159 mdiobb);
160
161 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
162}
163
164/* MDIO bus control struct */
165static struct mdiobb_ops bb_ops = {
166 .owner = THIS_MODULE,
167 .set_mdc = ravb_set_mdc,
168 .set_mdio_dir = ravb_set_mdio_dir,
169 .set_mdio_data = ravb_set_mdio_data,
170 .get_mdio_data = ravb_get_mdio_data,
171};
172
173/* Free TX skb function for AVB-IP */
174static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
175{
176 struct ravb_private *priv = netdev_priv(ndev);
177 struct net_device_stats *stats = &priv->stats[q];
178 int num_tx_desc = priv->num_tx_desc;
179 struct ravb_tx_desc *desc;
180 int free_num = 0;
181 int entry;
182 u32 size;
183
184 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
185 bool txed;
186
187 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
188 num_tx_desc);
189 desc = &priv->tx_ring[q][entry];
190 txed = desc->die_dt == DT_FEMPTY;
191 if (free_txed_only && !txed)
192 break;
193 /* Descriptor type must be checked before all other reads */
194 dma_rmb();
195 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
196 /* Free the original skb. */
197 if (priv->tx_skb[q][entry / num_tx_desc]) {
198 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
199 size, DMA_TO_DEVICE);
200 /* Last packet descriptor? */
201 if (entry % num_tx_desc == num_tx_desc - 1) {
202 entry /= num_tx_desc;
203 dev_kfree_skb_any(priv->tx_skb[q][entry]);
204 priv->tx_skb[q][entry] = NULL;
205 if (txed)
206 stats->tx_packets++;
207 }
208 free_num++;
209 }
210 if (txed)
211 stats->tx_bytes += size;
212 desc->die_dt = DT_EEMPTY;
213 }
214 return free_num;
215}
216
217/* Free skb's and DMA buffers for Ethernet AVB */
218static void ravb_ring_free(struct net_device *ndev, int q)
219{
220 struct ravb_private *priv = netdev_priv(ndev);
221 int num_tx_desc = priv->num_tx_desc;
222 int ring_size;
223 int i;
224
225 if (priv->rx_ring[q]) {
226 for (i = 0; i < priv->num_rx_ring[q]; i++) {
227 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
228
229 if (!dma_mapping_error(ndev->dev.parent,
230 le32_to_cpu(desc->dptr)))
231 dma_unmap_single(ndev->dev.parent,
232 le32_to_cpu(desc->dptr),
233 RX_BUF_SZ,
234 DMA_FROM_DEVICE);
235 }
236 ring_size = sizeof(struct ravb_ex_rx_desc) *
237 (priv->num_rx_ring[q] + 1);
238 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
239 priv->rx_desc_dma[q]);
240 priv->rx_ring[q] = NULL;
241 }
242
243 if (priv->tx_ring[q]) {
244 ravb_tx_free(ndev, q, false);
245
246 ring_size = sizeof(struct ravb_tx_desc) *
247 (priv->num_tx_ring[q] * num_tx_desc + 1);
248 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
249 priv->tx_desc_dma[q]);
250 priv->tx_ring[q] = NULL;
251 }
252
253 /* Free RX skb ringbuffer */
254 if (priv->rx_skb[q]) {
255 for (i = 0; i < priv->num_rx_ring[q]; i++)
256 dev_kfree_skb(priv->rx_skb[q][i]);
257 }
258 kfree(priv->rx_skb[q]);
259 priv->rx_skb[q] = NULL;
260
261 /* Free aligned TX buffers */
262 kfree(priv->tx_align[q]);
263 priv->tx_align[q] = NULL;
264
265 /* Free TX skb ringbuffer.
266 * SKBs are freed by ravb_tx_free() call above.
267 */
268 kfree(priv->tx_skb[q]);
269 priv->tx_skb[q] = NULL;
270}
271
272/* Format skb and descriptor buffer for Ethernet AVB */
273static void ravb_ring_format(struct net_device *ndev, int q)
274{
275 struct ravb_private *priv = netdev_priv(ndev);
276 int num_tx_desc = priv->num_tx_desc;
277 struct ravb_ex_rx_desc *rx_desc;
278 struct ravb_tx_desc *tx_desc;
279 struct ravb_desc *desc;
280 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
281 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
282 num_tx_desc;
283 dma_addr_t dma_addr;
284 int i;
285
286 priv->cur_rx[q] = 0;
287 priv->cur_tx[q] = 0;
288 priv->dirty_rx[q] = 0;
289 priv->dirty_tx[q] = 0;
290
291 memset(priv->rx_ring[q], 0, rx_ring_size);
292 /* Build RX ring buffer */
293 for (i = 0; i < priv->num_rx_ring[q]; i++) {
294 /* RX descriptor */
295 rx_desc = &priv->rx_ring[q][i];
296 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
297 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
298 RX_BUF_SZ,
299 DMA_FROM_DEVICE);
300 /* We just set the data size to 0 for a failed mapping which
301 * should prevent DMA from happening...
302 */
303 if (dma_mapping_error(ndev->dev.parent, dma_addr))
304 rx_desc->ds_cc = cpu_to_le16(0);
305 rx_desc->dptr = cpu_to_le32(dma_addr);
306 rx_desc->die_dt = DT_FEMPTY;
307 }
308 rx_desc = &priv->rx_ring[q][i];
309 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
310 rx_desc->die_dt = DT_LINKFIX; /* type */
311
312 memset(priv->tx_ring[q], 0, tx_ring_size);
313 /* Build TX ring buffer */
314 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
315 i++, tx_desc++) {
316 tx_desc->die_dt = DT_EEMPTY;
317 if (num_tx_desc > 1) {
318 tx_desc++;
319 tx_desc->die_dt = DT_EEMPTY;
320 }
321 }
322 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
323 tx_desc->die_dt = DT_LINKFIX; /* type */
324
325 /* RX descriptor base address for best effort */
326 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
327 desc->die_dt = DT_LINKFIX; /* type */
328 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
329
330 /* TX descriptor base address for best effort */
331 desc = &priv->desc_bat[q];
332 desc->die_dt = DT_LINKFIX; /* type */
333 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
334}
335
336/* Init skb and descriptor buffer for Ethernet AVB */
337static int ravb_ring_init(struct net_device *ndev, int q)
338{
339 struct ravb_private *priv = netdev_priv(ndev);
340 int num_tx_desc = priv->num_tx_desc;
341 struct sk_buff *skb;
342 int ring_size;
343 int i;
344
345 /* Allocate RX and TX skb rings */
346 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
347 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
348 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
349 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
350 if (!priv->rx_skb[q] || !priv->tx_skb[q])
351 goto error;
352
353 for (i = 0; i < priv->num_rx_ring[q]; i++) {
354 skb = netdev_alloc_skb(ndev, RX_BUF_SZ + RAVB_ALIGN - 1);
355 if (!skb)
356 goto error;
357 ravb_set_buffer_align(skb);
358 priv->rx_skb[q][i] = skb;
359 }
360
361 if (num_tx_desc > 1) {
362 /* Allocate rings for the aligned buffers */
363 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
364 DPTR_ALIGN - 1, GFP_KERNEL);
365 if (!priv->tx_align[q])
366 goto error;
367 }
368
369 /* Allocate all RX descriptors. */
370 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
371 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
372 &priv->rx_desc_dma[q],
373 GFP_KERNEL);
374 if (!priv->rx_ring[q])
375 goto error;
376
377 priv->dirty_rx[q] = 0;
378
379 /* Allocate all TX descriptors. */
380 ring_size = sizeof(struct ravb_tx_desc) *
381 (priv->num_tx_ring[q] * num_tx_desc + 1);
382 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
383 &priv->tx_desc_dma[q],
384 GFP_KERNEL);
385 if (!priv->tx_ring[q])
386 goto error;
387
388 return 0;
389
390error:
391 ravb_ring_free(ndev, q);
392
393 return -ENOMEM;
394}
395
396/* E-MAC init function */
397static void ravb_emac_init(struct net_device *ndev)
398{
399 /* Receive frame limit set register */
400 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
401
402 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
403 ravb_write(ndev, ECMR_ZPF | ECMR_DM |
404 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
405 ECMR_TE | ECMR_RE, ECMR);
406
407 ravb_set_rate(ndev);
408
409 /* Set MAC address */
410 ravb_write(ndev,
411 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
412 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
413 ravb_write(ndev,
414 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
415
416 /* E-MAC status register clear */
417 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
418
419 /* E-MAC interrupt enable register */
420 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
421}
422
423/* Device init function for Ethernet AVB */
424static int ravb_dmac_init(struct net_device *ndev)
425{
426 struct ravb_private *priv = netdev_priv(ndev);
427 int error;
428
429 /* Set CONFIG mode */
430 error = ravb_config(ndev);
431 if (error)
432 return error;
433
434 error = ravb_ring_init(ndev, RAVB_BE);
435 if (error)
436 return error;
437 error = ravb_ring_init(ndev, RAVB_NC);
438 if (error) {
439 ravb_ring_free(ndev, RAVB_BE);
440 return error;
441 }
442
443 /* Descriptor format */
444 ravb_ring_format(ndev, RAVB_BE);
445 ravb_ring_format(ndev, RAVB_NC);
446
447 /* Set AVB RX */
448 ravb_write(ndev,
449 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
450
451 /* Set FIFO size */
452 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
453
454 /* Timestamp enable */
455 ravb_write(ndev, TCCR_TFEN, TCCR);
456
457 /* Interrupt init: */
458 if (priv->chip_id == RCAR_GEN3) {
459 /* Clear DIL.DPLx */
460 ravb_write(ndev, 0, DIL);
461 /* Set queue specific interrupt */
462 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
463 }
464 /* Frame receive */
465 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
466 /* Disable FIFO full warning */
467 ravb_write(ndev, 0, RIC1);
468 /* Receive FIFO full error, descriptor empty */
469 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
470 /* Frame transmitted, timestamp FIFO updated */
471 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
472
473 /* Setting the control will start the AVB-DMAC process. */
474 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
475
476 return 0;
477}
478
479static void ravb_get_tx_tstamp(struct net_device *ndev)
480{
481 struct ravb_private *priv = netdev_priv(ndev);
482 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
483 struct skb_shared_hwtstamps shhwtstamps;
484 struct sk_buff *skb;
485 struct timespec64 ts;
486 u16 tag, tfa_tag;
487 int count;
488 u32 tfa2;
489
490 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
491 while (count--) {
492 tfa2 = ravb_read(ndev, TFA2);
493 tfa_tag = (tfa2 & TFA2_TST) >> 16;
494 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
495 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
496 ravb_read(ndev, TFA1);
497 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
498 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
499 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
500 list) {
501 skb = ts_skb->skb;
502 tag = ts_skb->tag;
503 list_del(&ts_skb->list);
504 kfree(ts_skb);
505 if (tag == tfa_tag) {
506 skb_tstamp_tx(skb, &shhwtstamps);
507 dev_consume_skb_any(skb);
508 break;
509 } else {
510 dev_kfree_skb_any(skb);
511 }
512 }
513 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
514 }
515}
516
517static void ravb_rx_csum(struct sk_buff *skb)
518{
519 u8 *hw_csum;
520
521 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes
522 * appended to packet data
523 */
524 if (unlikely(skb->len < sizeof(__sum16)))
525 return;
526 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
527 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
528 skb->ip_summed = CHECKSUM_COMPLETE;
529 skb_trim(skb, skb->len - sizeof(__sum16));
530}
531
532/* Packet receive function for Ethernet AVB */
533static bool ravb_rx(struct net_device *ndev, int *quota, int q)
534{
535 struct ravb_private *priv = netdev_priv(ndev);
536 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
537 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
538 priv->cur_rx[q];
539 struct net_device_stats *stats = &priv->stats[q];
540 struct ravb_ex_rx_desc *desc;
541 struct sk_buff *skb;
542 dma_addr_t dma_addr;
543 struct timespec64 ts;
544 u8 desc_status;
545 u16 pkt_len;
546 int limit;
547
548 boguscnt = min(boguscnt, *quota);
549 limit = boguscnt;
550 desc = &priv->rx_ring[q][entry];
551 while (desc->die_dt != DT_FEMPTY) {
552 /* Descriptor type must be checked before all other reads */
553 dma_rmb();
554 desc_status = desc->msc;
555 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
556
557 if (--boguscnt < 0)
558 break;
559
560 /* We use 0-byte descriptors to mark the DMA mapping errors */
561 if (!pkt_len)
562 continue;
563
564 if (desc_status & MSC_MC)
565 stats->multicast++;
566
567 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
568 MSC_CEEF)) {
569 stats->rx_errors++;
570 if (desc_status & MSC_CRC)
571 stats->rx_crc_errors++;
572 if (desc_status & MSC_RFE)
573 stats->rx_frame_errors++;
574 if (desc_status & (MSC_RTLF | MSC_RTSF))
575 stats->rx_length_errors++;
576 if (desc_status & MSC_CEEF)
577 stats->rx_missed_errors++;
578 } else {
579 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
580
581 skb = priv->rx_skb[q][entry];
582 priv->rx_skb[q][entry] = NULL;
583 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
584 RX_BUF_SZ,
585 DMA_FROM_DEVICE);
586 get_ts &= (q == RAVB_NC) ?
587 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
588 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
589 if (get_ts) {
590 struct skb_shared_hwtstamps *shhwtstamps;
591
592 shhwtstamps = skb_hwtstamps(skb);
593 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
594 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
595 32) | le32_to_cpu(desc->ts_sl);
596 ts.tv_nsec = le32_to_cpu(desc->ts_n);
597 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
598 }
599
600 skb_put(skb, pkt_len);
601 skb->protocol = eth_type_trans(skb, ndev);
602 if (ndev->features & NETIF_F_RXCSUM)
603 ravb_rx_csum(skb);
604 napi_gro_receive(&priv->napi[q], skb);
605 stats->rx_packets++;
606 stats->rx_bytes += pkt_len;
607 }
608
609 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
610 desc = &priv->rx_ring[q][entry];
611 }
612
613 /* Refill the RX ring buffers. */
614 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
615 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
616 desc = &priv->rx_ring[q][entry];
617 desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
618
619 if (!priv->rx_skb[q][entry]) {
620 skb = netdev_alloc_skb(ndev,
621 RX_BUF_SZ +
622 RAVB_ALIGN - 1);
623 if (!skb)
624 break; /* Better luck next round. */
625 ravb_set_buffer_align(skb);
626 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
627 le16_to_cpu(desc->ds_cc),
628 DMA_FROM_DEVICE);
629 skb_checksum_none_assert(skb);
630 /* We just set the data size to 0 for a failed mapping
631 * which should prevent DMA from happening...
632 */
633 if (dma_mapping_error(ndev->dev.parent, dma_addr))
634 desc->ds_cc = cpu_to_le16(0);
635 desc->dptr = cpu_to_le32(dma_addr);
636 priv->rx_skb[q][entry] = skb;
637 }
638 /* Descriptor type must be set after all the above writes */
639 dma_wmb();
640 desc->die_dt = DT_FEMPTY;
641 }
642
643 *quota -= limit - (++boguscnt);
644
645 return boguscnt <= 0;
646}
647
648static void ravb_rcv_snd_disable(struct net_device *ndev)
649{
650 /* Disable TX and RX */
651 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
652}
653
654static void ravb_rcv_snd_enable(struct net_device *ndev)
655{
656 /* Enable TX and RX */
657 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
658}
659
660/* function for waiting dma process finished */
661static int ravb_stop_dma(struct net_device *ndev)
662{
663 int error;
664
665 /* Wait for stopping the hardware TX process */
666 error = ravb_wait(ndev, TCCR,
667 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
668 if (error)
669 return error;
670
671 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
672 0);
673 if (error)
674 return error;
675
676 /* Stop the E-MAC's RX/TX processes. */
677 ravb_rcv_snd_disable(ndev);
678
679 /* Wait for stopping the RX DMA process */
680 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
681 if (error)
682 return error;
683
684 /* Stop AVB-DMAC process */
685 return ravb_config(ndev);
686}
687
688/* E-MAC interrupt handler */
689static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
690{
691 struct ravb_private *priv = netdev_priv(ndev);
692 u32 ecsr, psr;
693
694 ecsr = ravb_read(ndev, ECSR);
695 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
696
697 if (ecsr & ECSR_MPD)
698 pm_wakeup_event(&priv->pdev->dev, 0);
699 if (ecsr & ECSR_ICD)
700 ndev->stats.tx_carrier_errors++;
701 if (ecsr & ECSR_LCHNG) {
702 /* Link changed */
703 if (priv->no_avb_link)
704 return;
705 psr = ravb_read(ndev, PSR);
706 if (priv->avb_link_active_low)
707 psr ^= PSR_LMON;
708 if (!(psr & PSR_LMON)) {
709 /* DIsable RX and TX */
710 ravb_rcv_snd_disable(ndev);
711 } else {
712 /* Enable RX and TX */
713 ravb_rcv_snd_enable(ndev);
714 }
715 }
716}
717
718static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
719{
720 struct net_device *ndev = dev_id;
721 struct ravb_private *priv = netdev_priv(ndev);
722
723 spin_lock(&priv->lock);
724 ravb_emac_interrupt_unlocked(ndev);
725 spin_unlock(&priv->lock);
726 return IRQ_HANDLED;
727}
728
729/* Error interrupt handler */
730static void ravb_error_interrupt(struct net_device *ndev)
731{
732 struct ravb_private *priv = netdev_priv(ndev);
733 u32 eis, ris2;
734
735 eis = ravb_read(ndev, EIS);
736 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);
737 if (eis & EIS_QFS) {
738 ris2 = ravb_read(ndev, RIS2);
739 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED),
740 RIS2);
741
742 /* Receive Descriptor Empty int */
743 if (ris2 & RIS2_QFF0)
744 priv->stats[RAVB_BE].rx_over_errors++;
745
746 /* Receive Descriptor Empty int */
747 if (ris2 & RIS2_QFF1)
748 priv->stats[RAVB_NC].rx_over_errors++;
749
750 /* Receive FIFO Overflow int */
751 if (ris2 & RIS2_RFFF)
752 priv->rx_fifo_errors++;
753 }
754}
755
756static bool ravb_queue_interrupt(struct net_device *ndev, int q)
757{
758 struct ravb_private *priv = netdev_priv(ndev);
759 u32 ris0 = ravb_read(ndev, RIS0);
760 u32 ric0 = ravb_read(ndev, RIC0);
761 u32 tis = ravb_read(ndev, TIS);
762 u32 tic = ravb_read(ndev, TIC);
763
764 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
765 if (napi_schedule_prep(&priv->napi[q])) {
766 /* Mask RX and TX interrupts */
767 if (priv->chip_id == RCAR_GEN2) {
768 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
769 ravb_write(ndev, tic & ~BIT(q), TIC);
770 } else {
771 ravb_write(ndev, BIT(q), RID0);
772 ravb_write(ndev, BIT(q), TID);
773 }
774 __napi_schedule(&priv->napi[q]);
775 } else {
776 netdev_warn(ndev,
777 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
778 ris0, ric0);
779 netdev_warn(ndev,
780 " tx status 0x%08x, tx mask 0x%08x.\n",
781 tis, tic);
782 }
783 return true;
784 }
785 return false;
786}
787
788static bool ravb_timestamp_interrupt(struct net_device *ndev)
789{
790 u32 tis = ravb_read(ndev, TIS);
791
792 if (tis & TIS_TFUF) {
793 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);
794 ravb_get_tx_tstamp(ndev);
795 return true;
796 }
797 return false;
798}
799
800static irqreturn_t ravb_interrupt(int irq, void *dev_id)
801{
802 struct net_device *ndev = dev_id;
803 struct ravb_private *priv = netdev_priv(ndev);
804 irqreturn_t result = IRQ_NONE;
805 u32 iss;
806
807 spin_lock(&priv->lock);
808 /* Get interrupt status */
809 iss = ravb_read(ndev, ISS);
810
811 /* Received and transmitted interrupts */
812 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
813 int q;
814
815 /* Timestamp updated */
816 if (ravb_timestamp_interrupt(ndev))
817 result = IRQ_HANDLED;
818
819 /* Network control and best effort queue RX/TX */
820 for (q = RAVB_NC; q >= RAVB_BE; q--) {
821 if (ravb_queue_interrupt(ndev, q))
822 result = IRQ_HANDLED;
823 }
824 }
825
826 /* E-MAC status summary */
827 if (iss & ISS_MS) {
828 ravb_emac_interrupt_unlocked(ndev);
829 result = IRQ_HANDLED;
830 }
831
832 /* Error status summary */
833 if (iss & ISS_ES) {
834 ravb_error_interrupt(ndev);
835 result = IRQ_HANDLED;
836 }
837
838 /* gPTP interrupt status summary */
839 if (iss & ISS_CGIS) {
840 ravb_ptp_interrupt(ndev);
841 result = IRQ_HANDLED;
842 }
843
844 spin_unlock(&priv->lock);
845 return result;
846}
847
848/* Timestamp/Error/gPTP interrupt handler */
849static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
850{
851 struct net_device *ndev = dev_id;
852 struct ravb_private *priv = netdev_priv(ndev);
853 irqreturn_t result = IRQ_NONE;
854 u32 iss;
855
856 spin_lock(&priv->lock);
857 /* Get interrupt status */
858 iss = ravb_read(ndev, ISS);
859
860 /* Timestamp updated */
861 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
862 result = IRQ_HANDLED;
863
864 /* Error status summary */
865 if (iss & ISS_ES) {
866 ravb_error_interrupt(ndev);
867 result = IRQ_HANDLED;
868 }
869
870 /* gPTP interrupt status summary */
871 if (iss & ISS_CGIS) {
872 ravb_ptp_interrupt(ndev);
873 result = IRQ_HANDLED;
874 }
875
876 spin_unlock(&priv->lock);
877 return result;
878}
879
880static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
881{
882 struct net_device *ndev = dev_id;
883 struct ravb_private *priv = netdev_priv(ndev);
884 irqreturn_t result = IRQ_NONE;
885
886 spin_lock(&priv->lock);
887
888 /* Network control/Best effort queue RX/TX */
889 if (ravb_queue_interrupt(ndev, q))
890 result = IRQ_HANDLED;
891
892 spin_unlock(&priv->lock);
893 return result;
894}
895
896static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
897{
898 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
899}
900
901static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
902{
903 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
904}
905
906static int ravb_poll(struct napi_struct *napi, int budget)
907{
908 struct net_device *ndev = napi->dev;
909 struct ravb_private *priv = netdev_priv(ndev);
910 unsigned long flags;
911 int q = napi - priv->napi;
912 int mask = BIT(q);
913 int quota = budget;
914 u32 ris0, tis;
915
916 for (;;) {
917 tis = ravb_read(ndev, TIS);
918 ris0 = ravb_read(ndev, RIS0);
919 if (!((ris0 & mask) || (tis & mask)))
920 break;
921
922 /* Processing RX Descriptor Ring */
923 if (ris0 & mask) {
924 /* Clear RX interrupt */
925 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);
926 if (ravb_rx(ndev, "a, q))
927 goto out;
928 }
929 /* Processing TX Descriptor Ring */
930 if (tis & mask) {
931 spin_lock_irqsave(&priv->lock, flags);
932 /* Clear TX interrupt */
933 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);
934 ravb_tx_free(ndev, q, true);
935 netif_wake_subqueue(ndev, q);
936 spin_unlock_irqrestore(&priv->lock, flags);
937 }
938 }
939
940 napi_complete(napi);
941
942 /* Re-enable RX/TX interrupts */
943 spin_lock_irqsave(&priv->lock, flags);
944 if (priv->chip_id == RCAR_GEN2) {
945 ravb_modify(ndev, RIC0, mask, mask);
946 ravb_modify(ndev, TIC, mask, mask);
947 } else {
948 ravb_write(ndev, mask, RIE0);
949 ravb_write(ndev, mask, TIE);
950 }
951 spin_unlock_irqrestore(&priv->lock, flags);
952
953 /* Receive error message handling */
954 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
955 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
956 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
957 ndev->stats.rx_over_errors = priv->rx_over_errors;
958 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
959 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
960out:
961 return budget - quota;
962}
963
964/* PHY state control function */
965static void ravb_adjust_link(struct net_device *ndev)
966{
967 struct ravb_private *priv = netdev_priv(ndev);
968 struct phy_device *phydev = ndev->phydev;
969 bool new_state = false;
970 unsigned long flags;
971
972 spin_lock_irqsave(&priv->lock, flags);
973
974 /* Disable TX and RX right over here, if E-MAC change is ignored */
975 if (priv->no_avb_link)
976 ravb_rcv_snd_disable(ndev);
977
978 if (phydev->link) {
979 if (phydev->speed != priv->speed) {
980 new_state = true;
981 priv->speed = phydev->speed;
982 ravb_set_rate(ndev);
983 }
984 if (!priv->link) {
985 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
986 new_state = true;
987 priv->link = phydev->link;
988 }
989 } else if (priv->link) {
990 new_state = true;
991 priv->link = 0;
992 priv->speed = 0;
993 }
994
995 /* Enable TX and RX right over here, if E-MAC change is ignored */
996 if (priv->no_avb_link && phydev->link)
997 ravb_rcv_snd_enable(ndev);
998
999 spin_unlock_irqrestore(&priv->lock, flags);
1000
1001 if (new_state && netif_msg_link(priv))
1002 phy_print_status(phydev);
1003}
1004
1005static const struct soc_device_attribute r8a7795es10[] = {
1006 { .soc_id = "r8a7795", .revision = "ES1.0", },
1007 { /* sentinel */ }
1008};
1009
1010/* PHY init function */
1011static int ravb_phy_init(struct net_device *ndev)
1012{
1013 struct device_node *np = ndev->dev.parent->of_node;
1014 struct ravb_private *priv = netdev_priv(ndev);
1015 struct phy_device *phydev;
1016 struct device_node *pn;
1017 int err;
1018
1019 priv->link = 0;
1020 priv->speed = 0;
1021
1022 /* Try connecting to PHY */
1023 pn = of_parse_phandle(np, "phy-handle", 0);
1024 if (!pn) {
1025 /* In the case of a fixed PHY, the DT node associated
1026 * to the PHY is the Ethernet MAC DT node.
1027 */
1028 if (of_phy_is_fixed_link(np)) {
1029 err = of_phy_register_fixed_link(np);
1030 if (err)
1031 return err;
1032 }
1033 pn = of_node_get(np);
1034 }
1035 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
1036 priv->phy_interface);
1037 of_node_put(pn);
1038 if (!phydev) {
1039 netdev_err(ndev, "failed to connect PHY\n");
1040 err = -ENOENT;
1041 goto err_deregister_fixed_link;
1042 }
1043
1044 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0
1045 * at this time.
1046 */
1047 if (soc_device_match(r8a7795es10)) {
1048 err = phy_set_max_speed(phydev, SPEED_100);
1049 if (err) {
1050 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
1051 goto err_phy_disconnect;
1052 }
1053
1054 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1055 }
1056
1057 /* 10BASE, Pause and Asym Pause is not supported */
1058 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1059 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
1060 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT);
1061 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT);
1062
1063 /* Half Duplex is not supported */
1064 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1065 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1066
1067 phy_attached_info(phydev);
1068
1069 return 0;
1070
1071err_phy_disconnect:
1072 phy_disconnect(phydev);
1073err_deregister_fixed_link:
1074 if (of_phy_is_fixed_link(np))
1075 of_phy_deregister_fixed_link(np);
1076
1077 return err;
1078}
1079
1080/* PHY control start function */
1081static int ravb_phy_start(struct net_device *ndev)
1082{
1083 int error;
1084
1085 error = ravb_phy_init(ndev);
1086 if (error)
1087 return error;
1088
1089 phy_start(ndev->phydev);
1090
1091 return 0;
1092}
1093
1094static u32 ravb_get_msglevel(struct net_device *ndev)
1095{
1096 struct ravb_private *priv = netdev_priv(ndev);
1097
1098 return priv->msg_enable;
1099}
1100
1101static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1102{
1103 struct ravb_private *priv = netdev_priv(ndev);
1104
1105 priv->msg_enable = value;
1106}
1107
1108static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1109 "rx_queue_0_current",
1110 "tx_queue_0_current",
1111 "rx_queue_0_dirty",
1112 "tx_queue_0_dirty",
1113 "rx_queue_0_packets",
1114 "tx_queue_0_packets",
1115 "rx_queue_0_bytes",
1116 "tx_queue_0_bytes",
1117 "rx_queue_0_mcast_packets",
1118 "rx_queue_0_errors",
1119 "rx_queue_0_crc_errors",
1120 "rx_queue_0_frame_errors",
1121 "rx_queue_0_length_errors",
1122 "rx_queue_0_missed_errors",
1123 "rx_queue_0_over_errors",
1124
1125 "rx_queue_1_current",
1126 "tx_queue_1_current",
1127 "rx_queue_1_dirty",
1128 "tx_queue_1_dirty",
1129 "rx_queue_1_packets",
1130 "tx_queue_1_packets",
1131 "rx_queue_1_bytes",
1132 "tx_queue_1_bytes",
1133 "rx_queue_1_mcast_packets",
1134 "rx_queue_1_errors",
1135 "rx_queue_1_crc_errors",
1136 "rx_queue_1_frame_errors",
1137 "rx_queue_1_length_errors",
1138 "rx_queue_1_missed_errors",
1139 "rx_queue_1_over_errors",
1140};
1141
1142#define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1143
1144static int ravb_get_sset_count(struct net_device *netdev, int sset)
1145{
1146 switch (sset) {
1147 case ETH_SS_STATS:
1148 return RAVB_STATS_LEN;
1149 default:
1150 return -EOPNOTSUPP;
1151 }
1152}
1153
1154static void ravb_get_ethtool_stats(struct net_device *ndev,
1155 struct ethtool_stats *estats, u64 *data)
1156{
1157 struct ravb_private *priv = netdev_priv(ndev);
1158 int i = 0;
1159 int q;
1160
1161 /* Device-specific stats */
1162 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1163 struct net_device_stats *stats = &priv->stats[q];
1164
1165 data[i++] = priv->cur_rx[q];
1166 data[i++] = priv->cur_tx[q];
1167 data[i++] = priv->dirty_rx[q];
1168 data[i++] = priv->dirty_tx[q];
1169 data[i++] = stats->rx_packets;
1170 data[i++] = stats->tx_packets;
1171 data[i++] = stats->rx_bytes;
1172 data[i++] = stats->tx_bytes;
1173 data[i++] = stats->multicast;
1174 data[i++] = stats->rx_errors;
1175 data[i++] = stats->rx_crc_errors;
1176 data[i++] = stats->rx_frame_errors;
1177 data[i++] = stats->rx_length_errors;
1178 data[i++] = stats->rx_missed_errors;
1179 data[i++] = stats->rx_over_errors;
1180 }
1181}
1182
1183static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1184{
1185 switch (stringset) {
1186 case ETH_SS_STATS:
1187 memcpy(data, ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1188 break;
1189 }
1190}
1191
1192static void ravb_get_ringparam(struct net_device *ndev,
1193 struct ethtool_ringparam *ring)
1194{
1195 struct ravb_private *priv = netdev_priv(ndev);
1196
1197 ring->rx_max_pending = BE_RX_RING_MAX;
1198 ring->tx_max_pending = BE_TX_RING_MAX;
1199 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1200 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1201}
1202
1203static int ravb_set_ringparam(struct net_device *ndev,
1204 struct ethtool_ringparam *ring)
1205{
1206 struct ravb_private *priv = netdev_priv(ndev);
1207 int error;
1208
1209 if (ring->tx_pending > BE_TX_RING_MAX ||
1210 ring->rx_pending > BE_RX_RING_MAX ||
1211 ring->tx_pending < BE_TX_RING_MIN ||
1212 ring->rx_pending < BE_RX_RING_MIN)
1213 return -EINVAL;
1214 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1215 return -EINVAL;
1216
1217 if (netif_running(ndev)) {
1218 netif_device_detach(ndev);
1219 /* Stop PTP Clock driver */
1220 if (priv->chip_id == RCAR_GEN2)
1221 ravb_ptp_stop(ndev);
1222 /* Wait for DMA stopping */
1223 error = ravb_stop_dma(ndev);
1224 if (error) {
1225 netdev_err(ndev,
1226 "cannot set ringparam! Any AVB processes are still running?\n");
1227 return error;
1228 }
1229 synchronize_irq(ndev->irq);
1230
1231 /* Free all the skb's in the RX queue and the DMA buffers. */
1232 ravb_ring_free(ndev, RAVB_BE);
1233 ravb_ring_free(ndev, RAVB_NC);
1234 }
1235
1236 /* Set new parameters */
1237 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1238 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1239
1240 if (netif_running(ndev)) {
1241 error = ravb_dmac_init(ndev);
1242 if (error) {
1243 netdev_err(ndev,
1244 "%s: ravb_dmac_init() failed, error %d\n",
1245 __func__, error);
1246 return error;
1247 }
1248
1249 ravb_emac_init(ndev);
1250
1251 /* Initialise PTP Clock driver */
1252 if (priv->chip_id == RCAR_GEN2)
1253 ravb_ptp_init(ndev, priv->pdev);
1254
1255 netif_device_attach(ndev);
1256 }
1257
1258 return 0;
1259}
1260
1261static int ravb_get_ts_info(struct net_device *ndev,
1262 struct ethtool_ts_info *info)
1263{
1264 struct ravb_private *priv = netdev_priv(ndev);
1265
1266 info->so_timestamping =
1267 SOF_TIMESTAMPING_TX_SOFTWARE |
1268 SOF_TIMESTAMPING_RX_SOFTWARE |
1269 SOF_TIMESTAMPING_SOFTWARE |
1270 SOF_TIMESTAMPING_TX_HARDWARE |
1271 SOF_TIMESTAMPING_RX_HARDWARE |
1272 SOF_TIMESTAMPING_RAW_HARDWARE;
1273 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1274 info->rx_filters =
1275 (1 << HWTSTAMP_FILTER_NONE) |
1276 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1277 (1 << HWTSTAMP_FILTER_ALL);
1278 info->phc_index = ptp_clock_index(priv->ptp.clock);
1279
1280 return 0;
1281}
1282
1283static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1284{
1285 struct ravb_private *priv = netdev_priv(ndev);
1286
1287 wol->supported = WAKE_MAGIC;
1288 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
1289}
1290
1291static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1292{
1293 struct ravb_private *priv = netdev_priv(ndev);
1294
1295 if (wol->wolopts & ~WAKE_MAGIC)
1296 return -EOPNOTSUPP;
1297
1298 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
1299
1300 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled);
1301
1302 return 0;
1303}
1304
1305static const struct ethtool_ops ravb_ethtool_ops = {
1306 .nway_reset = phy_ethtool_nway_reset,
1307 .get_msglevel = ravb_get_msglevel,
1308 .set_msglevel = ravb_set_msglevel,
1309 .get_link = ethtool_op_get_link,
1310 .get_strings = ravb_get_strings,
1311 .get_ethtool_stats = ravb_get_ethtool_stats,
1312 .get_sset_count = ravb_get_sset_count,
1313 .get_ringparam = ravb_get_ringparam,
1314 .set_ringparam = ravb_set_ringparam,
1315 .get_ts_info = ravb_get_ts_info,
1316 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1317 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1318 .get_wol = ravb_get_wol,
1319 .set_wol = ravb_set_wol,
1320};
1321
1322static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1323 struct net_device *ndev, struct device *dev,
1324 const char *ch)
1325{
1326 char *name;
1327 int error;
1328
1329 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1330 if (!name)
1331 return -ENOMEM;
1332 error = request_irq(irq, handler, 0, name, ndev);
1333 if (error)
1334 netdev_err(ndev, "cannot request IRQ %s\n", name);
1335
1336 return error;
1337}
1338
1339/* Network device open function for Ethernet AVB */
1340static int ravb_open(struct net_device *ndev)
1341{
1342 struct ravb_private *priv = netdev_priv(ndev);
1343 struct platform_device *pdev = priv->pdev;
1344 struct device *dev = &pdev->dev;
1345 int error;
1346
1347 napi_enable(&priv->napi[RAVB_BE]);
1348 napi_enable(&priv->napi[RAVB_NC]);
1349
1350 if (priv->chip_id == RCAR_GEN2) {
1351 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1352 ndev->name, ndev);
1353 if (error) {
1354 netdev_err(ndev, "cannot request IRQ\n");
1355 goto out_napi_off;
1356 }
1357 } else {
1358 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1359 dev, "ch22:multi");
1360 if (error)
1361 goto out_napi_off;
1362 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1363 dev, "ch24:emac");
1364 if (error)
1365 goto out_free_irq;
1366 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1367 ndev, dev, "ch0:rx_be");
1368 if (error)
1369 goto out_free_irq_emac;
1370 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1371 ndev, dev, "ch18:tx_be");
1372 if (error)
1373 goto out_free_irq_be_rx;
1374 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1375 ndev, dev, "ch1:rx_nc");
1376 if (error)
1377 goto out_free_irq_be_tx;
1378 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1379 ndev, dev, "ch19:tx_nc");
1380 if (error)
1381 goto out_free_irq_nc_rx;
1382 }
1383
1384 /* Device init */
1385 error = ravb_dmac_init(ndev);
1386 if (error)
1387 goto out_free_irq_nc_tx;
1388 ravb_emac_init(ndev);
1389
1390 /* Initialise PTP Clock driver */
1391 if (priv->chip_id == RCAR_GEN2)
1392 ravb_ptp_init(ndev, priv->pdev);
1393
1394 netif_tx_start_all_queues(ndev);
1395
1396 /* PHY control start */
1397 error = ravb_phy_start(ndev);
1398 if (error)
1399 goto out_ptp_stop;
1400
1401 return 0;
1402
1403out_ptp_stop:
1404 /* Stop PTP Clock driver */
1405 if (priv->chip_id == RCAR_GEN2)
1406 ravb_ptp_stop(ndev);
1407out_free_irq_nc_tx:
1408 if (priv->chip_id == RCAR_GEN2)
1409 goto out_free_irq;
1410 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1411out_free_irq_nc_rx:
1412 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1413out_free_irq_be_tx:
1414 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1415out_free_irq_be_rx:
1416 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1417out_free_irq_emac:
1418 free_irq(priv->emac_irq, ndev);
1419out_free_irq:
1420 free_irq(ndev->irq, ndev);
1421out_napi_off:
1422 napi_disable(&priv->napi[RAVB_NC]);
1423 napi_disable(&priv->napi[RAVB_BE]);
1424 return error;
1425}
1426
1427/* Timeout function for Ethernet AVB */
1428static void ravb_tx_timeout(struct net_device *ndev)
1429{
1430 struct ravb_private *priv = netdev_priv(ndev);
1431
1432 netif_err(priv, tx_err, ndev,
1433 "transmit timed out, status %08x, resetting...\n",
1434 ravb_read(ndev, ISS));
1435
1436 /* tx_errors count up */
1437 ndev->stats.tx_errors++;
1438
1439 schedule_work(&priv->work);
1440}
1441
1442static void ravb_tx_timeout_work(struct work_struct *work)
1443{
1444 struct ravb_private *priv = container_of(work, struct ravb_private,
1445 work);
1446 struct net_device *ndev = priv->ndev;
1447
1448 netif_tx_stop_all_queues(ndev);
1449
1450 /* Stop PTP Clock driver */
1451 if (priv->chip_id == RCAR_GEN2)
1452 ravb_ptp_stop(ndev);
1453
1454 /* Wait for DMA stopping */
1455 ravb_stop_dma(ndev);
1456
1457 ravb_ring_free(ndev, RAVB_BE);
1458 ravb_ring_free(ndev, RAVB_NC);
1459
1460 /* Device init */
1461 ravb_dmac_init(ndev);
1462 ravb_emac_init(ndev);
1463
1464 /* Initialise PTP Clock driver */
1465 if (priv->chip_id == RCAR_GEN2)
1466 ravb_ptp_init(ndev, priv->pdev);
1467
1468 netif_tx_start_all_queues(ndev);
1469}
1470
1471/* Packet transmit function for Ethernet AVB */
1472static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1473{
1474 struct ravb_private *priv = netdev_priv(ndev);
1475 int num_tx_desc = priv->num_tx_desc;
1476 u16 q = skb_get_queue_mapping(skb);
1477 struct ravb_tstamp_skb *ts_skb;
1478 struct ravb_tx_desc *desc;
1479 unsigned long flags;
1480 u32 dma_addr;
1481 void *buffer;
1482 u32 entry;
1483 u32 len;
1484
1485 spin_lock_irqsave(&priv->lock, flags);
1486 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1487 num_tx_desc) {
1488 netif_err(priv, tx_queued, ndev,
1489 "still transmitting with the full ring!\n");
1490 netif_stop_subqueue(ndev, q);
1491 spin_unlock_irqrestore(&priv->lock, flags);
1492 return NETDEV_TX_BUSY;
1493 }
1494
1495 if (skb_put_padto(skb, ETH_ZLEN))
1496 goto exit;
1497
1498 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc);
1499 priv->tx_skb[q][entry / num_tx_desc] = skb;
1500
1501 if (num_tx_desc > 1) {
1502 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1503 entry / num_tx_desc * DPTR_ALIGN;
1504 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1505
1506 /* Zero length DMA descriptors are problematic as they seem
1507 * to terminate DMA transfers. Avoid them by simply using a
1508 * length of DPTR_ALIGN (4) when skb data is aligned to
1509 * DPTR_ALIGN.
1510 *
1511 * As skb is guaranteed to have at least ETH_ZLEN (60)
1512 * bytes of data by the call to skb_put_padto() above this
1513 * is safe with respect to both the length of the first DMA
1514 * descriptor (len) overflowing the available data and the
1515 * length of the second DMA descriptor (skb->len - len)
1516 * being negative.
1517 */
1518 if (len == 0)
1519 len = DPTR_ALIGN;
1520
1521 memcpy(buffer, skb->data, len);
1522 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1523 DMA_TO_DEVICE);
1524 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1525 goto drop;
1526
1527 desc = &priv->tx_ring[q][entry];
1528 desc->ds_tagl = cpu_to_le16(len);
1529 desc->dptr = cpu_to_le32(dma_addr);
1530
1531 buffer = skb->data + len;
1532 len = skb->len - len;
1533 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1534 DMA_TO_DEVICE);
1535 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1536 goto unmap;
1537
1538 desc++;
1539 } else {
1540 desc = &priv->tx_ring[q][entry];
1541 len = skb->len;
1542 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len,
1543 DMA_TO_DEVICE);
1544 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1545 goto drop;
1546 }
1547 desc->ds_tagl = cpu_to_le16(len);
1548 desc->dptr = cpu_to_le32(dma_addr);
1549
1550 /* TX timestamp required */
1551 if (q == RAVB_NC) {
1552 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1553 if (!ts_skb) {
1554 if (num_tx_desc > 1) {
1555 desc--;
1556 dma_unmap_single(ndev->dev.parent, dma_addr,
1557 len, DMA_TO_DEVICE);
1558 }
1559 goto unmap;
1560 }
1561 ts_skb->skb = skb_get(skb);
1562 ts_skb->tag = priv->ts_skb_tag++;
1563 priv->ts_skb_tag &= 0x3ff;
1564 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1565
1566 /* TAG and timestamp required flag */
1567 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1568 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1569 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12);
1570 }
1571
1572 skb_tx_timestamp(skb);
1573 /* Descriptor type must be set after all the above writes */
1574 dma_wmb();
1575 if (num_tx_desc > 1) {
1576 desc->die_dt = DT_FEND;
1577 desc--;
1578 desc->die_dt = DT_FSTART;
1579 } else {
1580 desc->die_dt = DT_FSINGLE;
1581 }
1582 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
1583
1584 priv->cur_tx[q] += num_tx_desc;
1585 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1586 (priv->num_tx_ring[q] - 1) * num_tx_desc &&
1587 !ravb_tx_free(ndev, q, true))
1588 netif_stop_subqueue(ndev, q);
1589
1590exit:
1591 spin_unlock_irqrestore(&priv->lock, flags);
1592 return NETDEV_TX_OK;
1593
1594unmap:
1595 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1596 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1597drop:
1598 dev_kfree_skb_any(skb);
1599 priv->tx_skb[q][entry / num_tx_desc] = NULL;
1600 goto exit;
1601}
1602
1603static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1604 struct net_device *sb_dev)
1605{
1606 /* If skb needs TX timestamp, it is handled in network control queue */
1607 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1608 RAVB_BE;
1609
1610}
1611
1612static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1613{
1614 struct ravb_private *priv = netdev_priv(ndev);
1615 struct net_device_stats *nstats, *stats0, *stats1;
1616
1617 nstats = &ndev->stats;
1618 stats0 = &priv->stats[RAVB_BE];
1619 stats1 = &priv->stats[RAVB_NC];
1620
1621 if (priv->chip_id == RCAR_GEN3) {
1622 nstats->tx_dropped += ravb_read(ndev, TROCR);
1623 ravb_write(ndev, 0, TROCR); /* (write clear) */
1624 }
1625
1626 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1627 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1628 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1629 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1630 nstats->multicast = stats0->multicast + stats1->multicast;
1631 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1632 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1633 nstats->rx_frame_errors =
1634 stats0->rx_frame_errors + stats1->rx_frame_errors;
1635 nstats->rx_length_errors =
1636 stats0->rx_length_errors + stats1->rx_length_errors;
1637 nstats->rx_missed_errors =
1638 stats0->rx_missed_errors + stats1->rx_missed_errors;
1639 nstats->rx_over_errors =
1640 stats0->rx_over_errors + stats1->rx_over_errors;
1641
1642 return nstats;
1643}
1644
1645/* Update promiscuous bit */
1646static void ravb_set_rx_mode(struct net_device *ndev)
1647{
1648 struct ravb_private *priv = netdev_priv(ndev);
1649 unsigned long flags;
1650
1651 spin_lock_irqsave(&priv->lock, flags);
1652 ravb_modify(ndev, ECMR, ECMR_PRM,
1653 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
1654 spin_unlock_irqrestore(&priv->lock, flags);
1655}
1656
1657/* Device close function for Ethernet AVB */
1658static int ravb_close(struct net_device *ndev)
1659{
1660 struct device_node *np = ndev->dev.parent->of_node;
1661 struct ravb_private *priv = netdev_priv(ndev);
1662 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1663
1664 netif_tx_stop_all_queues(ndev);
1665
1666 /* Disable interrupts by clearing the interrupt masks. */
1667 ravb_write(ndev, 0, RIC0);
1668 ravb_write(ndev, 0, RIC2);
1669 ravb_write(ndev, 0, TIC);
1670
1671 /* Stop PTP Clock driver */
1672 if (priv->chip_id == RCAR_GEN2)
1673 ravb_ptp_stop(ndev);
1674
1675 /* Set the config mode to stop the AVB-DMAC's processes */
1676 if (ravb_stop_dma(ndev) < 0)
1677 netdev_err(ndev,
1678 "device will be stopped after h/w processes are done.\n");
1679
1680 /* Clear the timestamp list */
1681 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1682 list_del(&ts_skb->list);
1683 kfree_skb(ts_skb->skb);
1684 kfree(ts_skb);
1685 }
1686
1687 /* PHY disconnect */
1688 if (ndev->phydev) {
1689 phy_stop(ndev->phydev);
1690 phy_disconnect(ndev->phydev);
1691 if (of_phy_is_fixed_link(np))
1692 of_phy_deregister_fixed_link(np);
1693 }
1694
1695 if (priv->chip_id != RCAR_GEN2) {
1696 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1697 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1698 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1699 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1700 free_irq(priv->emac_irq, ndev);
1701 }
1702 free_irq(ndev->irq, ndev);
1703
1704 napi_disable(&priv->napi[RAVB_NC]);
1705 napi_disable(&priv->napi[RAVB_BE]);
1706
1707 /* Free all the skb's in the RX queue and the DMA buffers. */
1708 ravb_ring_free(ndev, RAVB_BE);
1709 ravb_ring_free(ndev, RAVB_NC);
1710
1711 return 0;
1712}
1713
1714static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1715{
1716 struct ravb_private *priv = netdev_priv(ndev);
1717 struct hwtstamp_config config;
1718
1719 config.flags = 0;
1720 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1721 HWTSTAMP_TX_OFF;
1722 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1723 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1724 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1725 config.rx_filter = HWTSTAMP_FILTER_ALL;
1726 else
1727 config.rx_filter = HWTSTAMP_FILTER_NONE;
1728
1729 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1730 -EFAULT : 0;
1731}
1732
1733/* Control hardware time stamping */
1734static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1735{
1736 struct ravb_private *priv = netdev_priv(ndev);
1737 struct hwtstamp_config config;
1738 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1739 u32 tstamp_tx_ctrl;
1740
1741 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1742 return -EFAULT;
1743
1744 /* Reserved for future extensions */
1745 if (config.flags)
1746 return -EINVAL;
1747
1748 switch (config.tx_type) {
1749 case HWTSTAMP_TX_OFF:
1750 tstamp_tx_ctrl = 0;
1751 break;
1752 case HWTSTAMP_TX_ON:
1753 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1754 break;
1755 default:
1756 return -ERANGE;
1757 }
1758
1759 switch (config.rx_filter) {
1760 case HWTSTAMP_FILTER_NONE:
1761 tstamp_rx_ctrl = 0;
1762 break;
1763 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1764 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1765 break;
1766 default:
1767 config.rx_filter = HWTSTAMP_FILTER_ALL;
1768 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1769 }
1770
1771 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1772 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1773
1774 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1775 -EFAULT : 0;
1776}
1777
1778/* ioctl to device function */
1779static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1780{
1781 struct phy_device *phydev = ndev->phydev;
1782
1783 if (!netif_running(ndev))
1784 return -EINVAL;
1785
1786 if (!phydev)
1787 return -ENODEV;
1788
1789 switch (cmd) {
1790 case SIOCGHWTSTAMP:
1791 return ravb_hwtstamp_get(ndev, req);
1792 case SIOCSHWTSTAMP:
1793 return ravb_hwtstamp_set(ndev, req);
1794 }
1795
1796 return phy_mii_ioctl(phydev, req, cmd);
1797}
1798
1799static int ravb_change_mtu(struct net_device *ndev, int new_mtu)
1800{
1801 struct ravb_private *priv = netdev_priv(ndev);
1802
1803 ndev->mtu = new_mtu;
1804
1805 if (netif_running(ndev)) {
1806 synchronize_irq(priv->emac_irq);
1807 ravb_emac_init(ndev);
1808 }
1809
1810 netdev_update_features(ndev);
1811
1812 return 0;
1813}
1814
1815static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
1816{
1817 struct ravb_private *priv = netdev_priv(ndev);
1818 unsigned long flags;
1819
1820 spin_lock_irqsave(&priv->lock, flags);
1821
1822 /* Disable TX and RX */
1823 ravb_rcv_snd_disable(ndev);
1824
1825 /* Modify RX Checksum setting */
1826 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
1827
1828 /* Enable TX and RX */
1829 ravb_rcv_snd_enable(ndev);
1830
1831 spin_unlock_irqrestore(&priv->lock, flags);
1832}
1833
1834static int ravb_set_features(struct net_device *ndev,
1835 netdev_features_t features)
1836{
1837 netdev_features_t changed = ndev->features ^ features;
1838
1839 if (changed & NETIF_F_RXCSUM)
1840 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
1841
1842 ndev->features = features;
1843
1844 return 0;
1845}
1846
1847static const struct net_device_ops ravb_netdev_ops = {
1848 .ndo_open = ravb_open,
1849 .ndo_stop = ravb_close,
1850 .ndo_start_xmit = ravb_start_xmit,
1851 .ndo_select_queue = ravb_select_queue,
1852 .ndo_get_stats = ravb_get_stats,
1853 .ndo_set_rx_mode = ravb_set_rx_mode,
1854 .ndo_tx_timeout = ravb_tx_timeout,
1855 .ndo_do_ioctl = ravb_do_ioctl,
1856 .ndo_change_mtu = ravb_change_mtu,
1857 .ndo_validate_addr = eth_validate_addr,
1858 .ndo_set_mac_address = eth_mac_addr,
1859 .ndo_set_features = ravb_set_features,
1860};
1861
1862/* MDIO bus init function */
1863static int ravb_mdio_init(struct ravb_private *priv)
1864{
1865 struct platform_device *pdev = priv->pdev;
1866 struct device *dev = &pdev->dev;
1867 int error;
1868
1869 /* Bitbang init */
1870 priv->mdiobb.ops = &bb_ops;
1871
1872 /* MII controller setting */
1873 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1874 if (!priv->mii_bus)
1875 return -ENOMEM;
1876
1877 /* Hook up MII support for ethtool */
1878 priv->mii_bus->name = "ravb_mii";
1879 priv->mii_bus->parent = dev;
1880 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1881 pdev->name, pdev->id);
1882
1883 /* Register MDIO bus */
1884 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1885 if (error)
1886 goto out_free_bus;
1887
1888 return 0;
1889
1890out_free_bus:
1891 free_mdio_bitbang(priv->mii_bus);
1892 return error;
1893}
1894
1895/* MDIO bus release function */
1896static int ravb_mdio_release(struct ravb_private *priv)
1897{
1898 /* Unregister mdio bus */
1899 mdiobus_unregister(priv->mii_bus);
1900
1901 /* Free bitbang info */
1902 free_mdio_bitbang(priv->mii_bus);
1903
1904 return 0;
1905}
1906
1907static const struct of_device_id ravb_match_table[] = {
1908 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1909 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1910 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
1911 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1912 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
1913 { }
1914};
1915MODULE_DEVICE_TABLE(of, ravb_match_table);
1916
1917static int ravb_set_gti(struct net_device *ndev)
1918{
1919 struct ravb_private *priv = netdev_priv(ndev);
1920 struct device *dev = ndev->dev.parent;
1921 unsigned long rate;
1922 uint64_t inc;
1923
1924 rate = clk_get_rate(priv->clk);
1925 if (!rate)
1926 return -EINVAL;
1927
1928 inc = 1000000000ULL << 20;
1929 do_div(inc, rate);
1930
1931 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1932 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1933 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1934 return -EINVAL;
1935 }
1936
1937 ravb_write(ndev, inc, GTI);
1938
1939 return 0;
1940}
1941
1942static void ravb_set_config_mode(struct net_device *ndev)
1943{
1944 struct ravb_private *priv = netdev_priv(ndev);
1945
1946 if (priv->chip_id == RCAR_GEN2) {
1947 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
1948 /* Set CSEL value */
1949 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
1950 } else {
1951 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
1952 CCC_GAC | CCC_CSEL_HPB);
1953 }
1954}
1955
1956static const struct soc_device_attribute ravb_delay_mode_quirk_match[] = {
1957 { .soc_id = "r8a774c0" },
1958 { .soc_id = "r8a77990" },
1959 { .soc_id = "r8a77995" },
1960 { /* sentinel */ }
1961};
1962
1963/* Set tx and rx clock internal delay modes */
1964static void ravb_set_delay_mode(struct net_device *ndev)
1965{
1966 struct ravb_private *priv = netdev_priv(ndev);
1967 int set = 0;
1968
1969 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1970 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
1971 set |= APSR_DM_RDM;
1972
1973 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1974 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
1975 if (!WARN(soc_device_match(ravb_delay_mode_quirk_match),
1976 "phy-mode %s requires TX clock internal delay mode which is not supported by this hardware revision. Please update device tree",
1977 phy_modes(priv->phy_interface)))
1978 set |= APSR_DM_TDM;
1979 }
1980
1981 ravb_modify(ndev, APSR, APSR_DM, set);
1982}
1983
1984static int ravb_probe(struct platform_device *pdev)
1985{
1986 struct device_node *np = pdev->dev.of_node;
1987 struct ravb_private *priv;
1988 enum ravb_chip_id chip_id;
1989 struct net_device *ndev;
1990 int error, irq, q;
1991 struct resource *res;
1992 int i;
1993
1994 if (!np) {
1995 dev_err(&pdev->dev,
1996 "this driver is required to be instantiated from device tree\n");
1997 return -EINVAL;
1998 }
1999
2000 /* Get base address */
2001 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2002 if (!res) {
2003 dev_err(&pdev->dev, "invalid resource\n");
2004 return -EINVAL;
2005 }
2006
2007 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
2008 NUM_TX_QUEUE, NUM_RX_QUEUE);
2009 if (!ndev)
2010 return -ENOMEM;
2011
2012 ndev->features = NETIF_F_RXCSUM;
2013 ndev->hw_features = NETIF_F_RXCSUM;
2014
2015 pm_runtime_enable(&pdev->dev);
2016 pm_runtime_get_sync(&pdev->dev);
2017
2018 /* The Ether-specific entries in the device structure. */
2019 ndev->base_addr = res->start;
2020
2021 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev);
2022
2023 if (chip_id == RCAR_GEN3)
2024 irq = platform_get_irq_byname(pdev, "ch22");
2025 else
2026 irq = platform_get_irq(pdev, 0);
2027 if (irq < 0) {
2028 error = irq;
2029 goto out_release;
2030 }
2031 ndev->irq = irq;
2032
2033 SET_NETDEV_DEV(ndev, &pdev->dev);
2034
2035 priv = netdev_priv(ndev);
2036 priv->ndev = ndev;
2037 priv->pdev = pdev;
2038 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
2039 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
2040 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2041 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2042 priv->addr = devm_ioremap_resource(&pdev->dev, res);
2043 if (IS_ERR(priv->addr)) {
2044 error = PTR_ERR(priv->addr);
2045 goto out_release;
2046 }
2047
2048 spin_lock_init(&priv->lock);
2049 INIT_WORK(&priv->work, ravb_tx_timeout_work);
2050
2051 priv->phy_interface = of_get_phy_mode(np);
2052
2053 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2054 priv->avb_link_active_low =
2055 of_property_read_bool(np, "renesas,ether-link-active-low");
2056
2057 if (chip_id == RCAR_GEN3) {
2058 irq = platform_get_irq_byname(pdev, "ch24");
2059 if (irq < 0) {
2060 error = irq;
2061 goto out_release;
2062 }
2063 priv->emac_irq = irq;
2064 for (i = 0; i < NUM_RX_QUEUE; i++) {
2065 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2066 if (irq < 0) {
2067 error = irq;
2068 goto out_release;
2069 }
2070 priv->rx_irqs[i] = irq;
2071 }
2072 for (i = 0; i < NUM_TX_QUEUE; i++) {
2073 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2074 if (irq < 0) {
2075 error = irq;
2076 goto out_release;
2077 }
2078 priv->tx_irqs[i] = irq;
2079 }
2080 }
2081
2082 priv->chip_id = chip_id;
2083
2084 priv->clk = devm_clk_get(&pdev->dev, NULL);
2085 if (IS_ERR(priv->clk)) {
2086 error = PTR_ERR(priv->clk);
2087 goto out_release;
2088 }
2089
2090 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
2091 ndev->min_mtu = ETH_MIN_MTU;
2092
2093 priv->num_tx_desc = chip_id == RCAR_GEN2 ?
2094 NUM_TX_DESC_GEN2 : NUM_TX_DESC_GEN3;
2095
2096 /* Set function */
2097 ndev->netdev_ops = &ravb_netdev_ops;
2098 ndev->ethtool_ops = &ravb_ethtool_ops;
2099
2100 /* Set AVB config mode */
2101 ravb_set_config_mode(ndev);
2102
2103 /* Set GTI value */
2104 error = ravb_set_gti(ndev);
2105 if (error)
2106 goto out_release;
2107
2108 /* Request GTI loading */
2109 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2110
2111 if (priv->chip_id != RCAR_GEN2)
2112 ravb_set_delay_mode(ndev);
2113
2114 /* Allocate descriptor base address table */
2115 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2116 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2117 &priv->desc_bat_dma, GFP_KERNEL);
2118 if (!priv->desc_bat) {
2119 dev_err(&pdev->dev,
2120 "Cannot allocate desc base address table (size %d bytes)\n",
2121 priv->desc_bat_size);
2122 error = -ENOMEM;
2123 goto out_release;
2124 }
2125 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2126 priv->desc_bat[q].die_dt = DT_EOS;
2127 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2128
2129 /* Initialise HW timestamp list */
2130 INIT_LIST_HEAD(&priv->ts_skb_list);
2131
2132 /* Initialise PTP Clock driver */
2133 if (chip_id != RCAR_GEN2)
2134 ravb_ptp_init(ndev, pdev);
2135
2136 /* Debug message level */
2137 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2138
2139 /* Read and set MAC address */
2140 ravb_read_mac_address(ndev, of_get_mac_address(np));
2141 if (!is_valid_ether_addr(ndev->dev_addr)) {
2142 dev_warn(&pdev->dev,
2143 "no valid MAC address supplied, using a random one\n");
2144 eth_hw_addr_random(ndev);
2145 }
2146
2147 /* MDIO bus init */
2148 error = ravb_mdio_init(priv);
2149 if (error) {
2150 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2151 goto out_dma_free;
2152 }
2153
2154 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2155 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2156
2157 /* Network device register */
2158 error = register_netdev(ndev);
2159 if (error)
2160 goto out_napi_del;
2161
2162 device_set_wakeup_capable(&pdev->dev, 1);
2163
2164 /* Print device information */
2165 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2166 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2167
2168 platform_set_drvdata(pdev, ndev);
2169
2170 return 0;
2171
2172out_napi_del:
2173 netif_napi_del(&priv->napi[RAVB_NC]);
2174 netif_napi_del(&priv->napi[RAVB_BE]);
2175 ravb_mdio_release(priv);
2176out_dma_free:
2177 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2178 priv->desc_bat_dma);
2179
2180 /* Stop PTP Clock driver */
2181 if (chip_id != RCAR_GEN2)
2182 ravb_ptp_stop(ndev);
2183out_release:
2184 free_netdev(ndev);
2185
2186 pm_runtime_put(&pdev->dev);
2187 pm_runtime_disable(&pdev->dev);
2188 return error;
2189}
2190
2191static int ravb_remove(struct platform_device *pdev)
2192{
2193 struct net_device *ndev = platform_get_drvdata(pdev);
2194 struct ravb_private *priv = netdev_priv(ndev);
2195
2196 /* Stop PTP Clock driver */
2197 if (priv->chip_id != RCAR_GEN2)
2198 ravb_ptp_stop(ndev);
2199
2200 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2201 priv->desc_bat_dma);
2202 /* Set reset mode */
2203 ravb_write(ndev, CCC_OPC_RESET, CCC);
2204 pm_runtime_put_sync(&pdev->dev);
2205 unregister_netdev(ndev);
2206 netif_napi_del(&priv->napi[RAVB_NC]);
2207 netif_napi_del(&priv->napi[RAVB_BE]);
2208 ravb_mdio_release(priv);
2209 pm_runtime_disable(&pdev->dev);
2210 free_netdev(ndev);
2211 platform_set_drvdata(pdev, NULL);
2212
2213 return 0;
2214}
2215
2216static int ravb_wol_setup(struct net_device *ndev)
2217{
2218 struct ravb_private *priv = netdev_priv(ndev);
2219
2220 /* Disable interrupts by clearing the interrupt masks. */
2221 ravb_write(ndev, 0, RIC0);
2222 ravb_write(ndev, 0, RIC2);
2223 ravb_write(ndev, 0, TIC);
2224
2225 /* Only allow ECI interrupts */
2226 synchronize_irq(priv->emac_irq);
2227 napi_disable(&priv->napi[RAVB_NC]);
2228 napi_disable(&priv->napi[RAVB_BE]);
2229 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);
2230
2231 /* Enable MagicPacket */
2232 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
2233
2234 return enable_irq_wake(priv->emac_irq);
2235}
2236
2237static int ravb_wol_restore(struct net_device *ndev)
2238{
2239 struct ravb_private *priv = netdev_priv(ndev);
2240 int ret;
2241
2242 napi_enable(&priv->napi[RAVB_NC]);
2243 napi_enable(&priv->napi[RAVB_BE]);
2244
2245 /* Disable MagicPacket */
2246 ravb_modify(ndev, ECMR, ECMR_MPDE, 0);
2247
2248 ret = ravb_close(ndev);
2249 if (ret < 0)
2250 return ret;
2251
2252 return disable_irq_wake(priv->emac_irq);
2253}
2254
2255static int __maybe_unused ravb_suspend(struct device *dev)
2256{
2257 struct net_device *ndev = dev_get_drvdata(dev);
2258 struct ravb_private *priv = netdev_priv(ndev);
2259 int ret;
2260
2261 if (!netif_running(ndev))
2262 return 0;
2263
2264 netif_device_detach(ndev);
2265
2266 if (priv->wol_enabled)
2267 ret = ravb_wol_setup(ndev);
2268 else
2269 ret = ravb_close(ndev);
2270
2271 return ret;
2272}
2273
2274static int __maybe_unused ravb_resume(struct device *dev)
2275{
2276 struct net_device *ndev = dev_get_drvdata(dev);
2277 struct ravb_private *priv = netdev_priv(ndev);
2278 int ret = 0;
2279
2280 /* If WoL is enabled set reset mode to rearm the WoL logic */
2281 if (priv->wol_enabled)
2282 ravb_write(ndev, CCC_OPC_RESET, CCC);
2283
2284 /* All register have been reset to default values.
2285 * Restore all registers which where setup at probe time and
2286 * reopen device if it was running before system suspended.
2287 */
2288
2289 /* Set AVB config mode */
2290 ravb_set_config_mode(ndev);
2291
2292 /* Set GTI value */
2293 ret = ravb_set_gti(ndev);
2294 if (ret)
2295 return ret;
2296
2297 /* Request GTI loading */
2298 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2299
2300 if (priv->chip_id != RCAR_GEN2)
2301 ravb_set_delay_mode(ndev);
2302
2303 /* Restore descriptor base address table */
2304 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2305
2306 if (netif_running(ndev)) {
2307 if (priv->wol_enabled) {
2308 ret = ravb_wol_restore(ndev);
2309 if (ret)
2310 return ret;
2311 }
2312 ret = ravb_open(ndev);
2313 if (ret < 0)
2314 return ret;
2315 netif_device_attach(ndev);
2316 }
2317
2318 return ret;
2319}
2320
2321static int __maybe_unused ravb_runtime_nop(struct device *dev)
2322{
2323 /* Runtime PM callback shared between ->runtime_suspend()
2324 * and ->runtime_resume(). Simply returns success.
2325 *
2326 * This driver re-initializes all registers after
2327 * pm_runtime_get_sync() anyway so there is no need
2328 * to save and restore registers here.
2329 */
2330 return 0;
2331}
2332
2333static const struct dev_pm_ops ravb_dev_pm_ops = {
2334 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
2335 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
2336};
2337
2338static struct platform_driver ravb_driver = {
2339 .probe = ravb_probe,
2340 .remove = ravb_remove,
2341 .driver = {
2342 .name = "ravb",
2343 .pm = &ravb_dev_pm_ops,
2344 .of_match_table = ravb_match_table,
2345 },
2346};
2347
2348module_platform_driver(ravb_driver);
2349
2350MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
2351MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
2352MODULE_LICENSE("GPL v2");