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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7#include <linux/etherdevice.h>
8#include <linux/ethtool.h>
9#include <linux/if_bridge.h>
10#include <linux/if_ether.h>
11#include <linux/if_vlan.h>
12#include <linux/interrupt.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/netdevice.h>
16#include <linux/phy.h>
17#include <linux/ptp_clock_kernel.h>
18#include <linux/skbuff.h>
19#include <linux/iopoll.h>
20#include <net/arp.h>
21#include <net/netevent.h>
22#include <net/rtnetlink.h>
23#include <net/switchdev.h>
24
25#include "ocelot.h"
26#include "ocelot_ace.h"
27
28#define TABLE_UPDATE_SLEEP_US 10
29#define TABLE_UPDATE_TIMEOUT_US 100000
30
31/* MAC table entry types.
32 * ENTRYTYPE_NORMAL is subject to aging.
33 * ENTRYTYPE_LOCKED is not subject to aging.
34 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
35 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
36 */
37enum macaccess_entry_type {
38 ENTRYTYPE_NORMAL = 0,
39 ENTRYTYPE_LOCKED,
40 ENTRYTYPE_MACv4,
41 ENTRYTYPE_MACv6,
42};
43
44struct ocelot_mact_entry {
45 u8 mac[ETH_ALEN];
46 u16 vid;
47 enum macaccess_entry_type type;
48};
49
50static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
51{
52 return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
53}
54
55static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
56{
57 u32 val;
58
59 return readx_poll_timeout(ocelot_mact_read_macaccess,
60 ocelot, val,
61 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
62 MACACCESS_CMD_IDLE,
63 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
64}
65
66static void ocelot_mact_select(struct ocelot *ocelot,
67 const unsigned char mac[ETH_ALEN],
68 unsigned int vid)
69{
70 u32 macl = 0, mach = 0;
71
72 /* Set the MAC address to handle and the vlan associated in a format
73 * understood by the hardware.
74 */
75 mach |= vid << 16;
76 mach |= mac[0] << 8;
77 mach |= mac[1] << 0;
78 macl |= mac[2] << 24;
79 macl |= mac[3] << 16;
80 macl |= mac[4] << 8;
81 macl |= mac[5] << 0;
82
83 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
84 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
85
86}
87
88static int ocelot_mact_learn(struct ocelot *ocelot, int port,
89 const unsigned char mac[ETH_ALEN],
90 unsigned int vid,
91 enum macaccess_entry_type type)
92{
93 ocelot_mact_select(ocelot, mac, vid);
94
95 /* Issue a write command */
96 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID |
97 ANA_TABLES_MACACCESS_DEST_IDX(port) |
98 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
99 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
100 ANA_TABLES_MACACCESS);
101
102 return ocelot_mact_wait_for_completion(ocelot);
103}
104
105static int ocelot_mact_forget(struct ocelot *ocelot,
106 const unsigned char mac[ETH_ALEN],
107 unsigned int vid)
108{
109 ocelot_mact_select(ocelot, mac, vid);
110
111 /* Issue a forget command */
112 ocelot_write(ocelot,
113 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
114 ANA_TABLES_MACACCESS);
115
116 return ocelot_mact_wait_for_completion(ocelot);
117}
118
119static void ocelot_mact_init(struct ocelot *ocelot)
120{
121 /* Configure the learning mode entries attributes:
122 * - Do not copy the frame to the CPU extraction queues.
123 * - Use the vlan and mac_cpoy for dmac lookup.
124 */
125 ocelot_rmw(ocelot, 0,
126 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
127 | ANA_AGENCTRL_LEARN_FWD_KILL
128 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
129 ANA_AGENCTRL);
130
131 /* Clear the MAC table */
132 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
133}
134
135static void ocelot_vcap_enable(struct ocelot *ocelot, struct ocelot_port *port)
136{
137 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
138 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
139 ANA_PORT_VCAP_S2_CFG, port->chip_port);
140}
141
142static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
143{
144 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
145}
146
147static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
148{
149 u32 val;
150
151 return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
152 ocelot,
153 val,
154 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
155 ANA_TABLES_VLANACCESS_CMD_IDLE,
156 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
157}
158
159static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
160{
161 /* Select the VID to configure */
162 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
163 ANA_TABLES_VLANTIDX);
164 /* Set the vlan port members mask and issue a write command */
165 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
166 ANA_TABLES_VLANACCESS_CMD_WRITE,
167 ANA_TABLES_VLANACCESS);
168
169 return ocelot_vlant_wait_for_completion(ocelot);
170}
171
172static void ocelot_vlan_mode(struct ocelot_port *port,
173 netdev_features_t features)
174{
175 struct ocelot *ocelot = port->ocelot;
176 u8 p = port->chip_port;
177 u32 val;
178
179 /* Filtering */
180 val = ocelot_read(ocelot, ANA_VLANMASK);
181 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
182 val |= BIT(p);
183 else
184 val &= ~BIT(p);
185 ocelot_write(ocelot, val, ANA_VLANMASK);
186}
187
188static void ocelot_vlan_port_apply(struct ocelot *ocelot,
189 struct ocelot_port *port)
190{
191 u32 val;
192
193 /* Ingress clasification (ANA_PORT_VLAN_CFG) */
194 /* Default vlan to clasify for untagged frames (may be zero) */
195 val = ANA_PORT_VLAN_CFG_VLAN_VID(port->pvid);
196 if (port->vlan_aware)
197 val |= ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
198 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
199
200 ocelot_rmw_gix(ocelot, val,
201 ANA_PORT_VLAN_CFG_VLAN_VID_M |
202 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
203 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
204 ANA_PORT_VLAN_CFG, port->chip_port);
205
206 /* Drop frames with multicast source address */
207 val = ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA;
208 if (port->vlan_aware && !port->vid)
209 /* If port is vlan-aware and tagged, drop untagged and priority
210 * tagged frames.
211 */
212 val |= ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA |
213 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
214 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
215 ocelot_write_gix(ocelot, val, ANA_PORT_DROP_CFG, port->chip_port);
216
217 /* Egress configuration (REW_TAG_CFG): VLAN tag type to 8021Q. */
218 val = REW_TAG_CFG_TAG_TPID_CFG(0);
219
220 if (port->vlan_aware) {
221 if (port->vid)
222 /* Tag all frames except when VID == DEFAULT_VLAN */
223 val |= REW_TAG_CFG_TAG_CFG(1);
224 else
225 /* Tag all frames */
226 val |= REW_TAG_CFG_TAG_CFG(3);
227 }
228 ocelot_rmw_gix(ocelot, val,
229 REW_TAG_CFG_TAG_TPID_CFG_M |
230 REW_TAG_CFG_TAG_CFG_M,
231 REW_TAG_CFG, port->chip_port);
232
233 /* Set default VLAN and tag type to 8021Q. */
234 val = REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q) |
235 REW_PORT_VLAN_CFG_PORT_VID(port->vid);
236 ocelot_rmw_gix(ocelot, val,
237 REW_PORT_VLAN_CFG_PORT_TPID_M |
238 REW_PORT_VLAN_CFG_PORT_VID_M,
239 REW_PORT_VLAN_CFG, port->chip_port);
240}
241
242static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid,
243 bool untagged)
244{
245 struct ocelot_port *port = netdev_priv(dev);
246 struct ocelot *ocelot = port->ocelot;
247 int ret;
248
249 /* Add the port MAC address to with the right VLAN information */
250 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid,
251 ENTRYTYPE_LOCKED);
252
253 /* Make the port a member of the VLAN */
254 ocelot->vlan_mask[vid] |= BIT(port->chip_port);
255 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
256 if (ret)
257 return ret;
258
259 /* Default ingress vlan classification */
260 if (pvid)
261 port->pvid = vid;
262
263 /* Untagged egress vlan clasification */
264 if (untagged && port->vid != vid) {
265 if (port->vid) {
266 dev_err(ocelot->dev,
267 "Port already has a native VLAN: %d\n",
268 port->vid);
269 return -EBUSY;
270 }
271 port->vid = vid;
272 }
273
274 ocelot_vlan_port_apply(ocelot, port);
275
276 return 0;
277}
278
279static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid)
280{
281 struct ocelot_port *port = netdev_priv(dev);
282 struct ocelot *ocelot = port->ocelot;
283 int ret;
284
285 /* 8021q removes VID 0 on module unload for all interfaces
286 * with VLAN filtering feature. We need to keep it to receive
287 * untagged traffic.
288 */
289 if (vid == 0)
290 return 0;
291
292 /* Del the port MAC address to with the right VLAN information */
293 ocelot_mact_forget(ocelot, dev->dev_addr, vid);
294
295 /* Stop the port from being a member of the vlan */
296 ocelot->vlan_mask[vid] &= ~BIT(port->chip_port);
297 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
298 if (ret)
299 return ret;
300
301 /* Ingress */
302 if (port->pvid == vid)
303 port->pvid = 0;
304
305 /* Egress */
306 if (port->vid == vid)
307 port->vid = 0;
308
309 ocelot_vlan_port_apply(ocelot, port);
310
311 return 0;
312}
313
314static void ocelot_vlan_init(struct ocelot *ocelot)
315{
316 u16 port, vid;
317
318 /* Clear VLAN table, by default all ports are members of all VLANs */
319 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
320 ANA_TABLES_VLANACCESS);
321 ocelot_vlant_wait_for_completion(ocelot);
322
323 /* Configure the port VLAN memberships */
324 for (vid = 1; vid < VLAN_N_VID; vid++) {
325 ocelot->vlan_mask[vid] = 0;
326 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
327 }
328
329 /* Because VLAN filtering is enabled, we need VID 0 to get untagged
330 * traffic. It is added automatically if 8021q module is loaded, but
331 * we can't rely on it since module may be not loaded.
332 */
333 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0);
334 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]);
335
336 /* Configure the CPU port to be VLAN aware */
337 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
338 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
339 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
340 ANA_PORT_VLAN_CFG, ocelot->num_phys_ports);
341
342 /* Set vlan ingress filter mask to all ports but the CPU port by
343 * default.
344 */
345 ocelot_write(ocelot, GENMASK(9, 0), ANA_VLANMASK);
346
347 for (port = 0; port < ocelot->num_phys_ports; port++) {
348 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
349 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
350 }
351}
352
353/* Watermark encode
354 * Bit 8: Unit; 0:1, 1:16
355 * Bit 7-0: Value to be multiplied with unit
356 */
357static u16 ocelot_wm_enc(u16 value)
358{
359 if (value >= BIT(8))
360 return BIT(8) | (value / 16);
361
362 return value;
363}
364
365static void ocelot_port_adjust_link(struct net_device *dev)
366{
367 struct ocelot_port *port = netdev_priv(dev);
368 struct ocelot *ocelot = port->ocelot;
369 u8 p = port->chip_port;
370 int speed, atop_wm, mode = 0;
371
372 switch (dev->phydev->speed) {
373 case SPEED_10:
374 speed = OCELOT_SPEED_10;
375 break;
376 case SPEED_100:
377 speed = OCELOT_SPEED_100;
378 break;
379 case SPEED_1000:
380 speed = OCELOT_SPEED_1000;
381 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
382 break;
383 case SPEED_2500:
384 speed = OCELOT_SPEED_2500;
385 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
386 break;
387 default:
388 netdev_err(dev, "Unsupported PHY speed: %d\n",
389 dev->phydev->speed);
390 return;
391 }
392
393 phy_print_status(dev->phydev);
394
395 if (!dev->phydev->link)
396 return;
397
398 /* Only full duplex supported for now */
399 ocelot_port_writel(port, DEV_MAC_MODE_CFG_FDX_ENA |
400 mode, DEV_MAC_MODE_CFG);
401
402 /* Set MAC IFG Gaps
403 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
404 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
405 */
406 ocelot_port_writel(port, DEV_MAC_IFG_CFG_TX_IFG(5), DEV_MAC_IFG_CFG);
407
408 /* Load seed (0) and set MAC HDX late collision */
409 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
410 DEV_MAC_HDX_CFG_SEED_LOAD,
411 DEV_MAC_HDX_CFG);
412 mdelay(1);
413 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
414 DEV_MAC_HDX_CFG);
415
416 /* Disable HDX fast control */
417 ocelot_port_writel(port, DEV_PORT_MISC_HDX_FAST_DIS, DEV_PORT_MISC);
418
419 /* SGMII only for now */
420 ocelot_port_writel(port, PCS1G_MODE_CFG_SGMII_MODE_ENA, PCS1G_MODE_CFG);
421 ocelot_port_writel(port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
422
423 /* Enable PCS */
424 ocelot_port_writel(port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
425
426 /* No aneg on SGMII */
427 ocelot_port_writel(port, 0, PCS1G_ANEG_CFG);
428
429 /* No loopback */
430 ocelot_port_writel(port, 0, PCS1G_LB_CFG);
431
432 /* Set Max Length and maximum tags allowed */
433 ocelot_port_writel(port, VLAN_ETH_FRAME_LEN, DEV_MAC_MAXLEN_CFG);
434 ocelot_port_writel(port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
435 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
436 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
437 DEV_MAC_TAGS_CFG);
438
439 /* Enable MAC module */
440 ocelot_port_writel(port, DEV_MAC_ENA_CFG_RX_ENA |
441 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
442
443 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
444 * reset */
445 ocelot_port_writel(port, DEV_CLOCK_CFG_LINK_SPEED(speed),
446 DEV_CLOCK_CFG);
447
448 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
449 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
450 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_LOW_CFG);
451
452 /* No PFC */
453 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
454 ANA_PFC_PFC_CFG, p);
455
456 /* Set Pause WM hysteresis
457 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
458 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
459 */
460 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
461 SYS_PAUSE_CFG_PAUSE_STOP(101) |
462 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, p);
463
464 /* Core: Enable port for frame transfer */
465 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
466 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
467 QSYS_SWITCH_PORT_MODE_PORT_ENA,
468 QSYS_SWITCH_PORT_MODE, p);
469
470 /* Flow control */
471 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
472 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA |
473 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |
474 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
475 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
476 SYS_MAC_FC_CFG, p);
477 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, p);
478
479 /* Tail dropping watermark */
480 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
481 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
482 SYS_ATOP, p);
483 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
484}
485
486static int ocelot_port_open(struct net_device *dev)
487{
488 struct ocelot_port *port = netdev_priv(dev);
489 struct ocelot *ocelot = port->ocelot;
490 int err;
491
492 /* Enable receiving frames on the port, and activate auto-learning of
493 * MAC addresses.
494 */
495 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
496 ANA_PORT_PORT_CFG_RECV_ENA |
497 ANA_PORT_PORT_CFG_PORTID_VAL(port->chip_port),
498 ANA_PORT_PORT_CFG, port->chip_port);
499
500 if (port->serdes) {
501 err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET,
502 port->phy_mode);
503 if (err) {
504 netdev_err(dev, "Could not set mode of SerDes\n");
505 return err;
506 }
507 }
508
509 err = phy_connect_direct(dev, port->phy, &ocelot_port_adjust_link,
510 port->phy_mode);
511 if (err) {
512 netdev_err(dev, "Could not attach to PHY\n");
513 return err;
514 }
515
516 dev->phydev = port->phy;
517
518 phy_attached_info(port->phy);
519 phy_start(port->phy);
520 return 0;
521}
522
523static int ocelot_port_stop(struct net_device *dev)
524{
525 struct ocelot_port *port = netdev_priv(dev);
526
527 phy_disconnect(port->phy);
528
529 dev->phydev = NULL;
530
531 ocelot_port_writel(port, 0, DEV_MAC_ENA_CFG);
532 ocelot_rmw_rix(port->ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA,
533 QSYS_SWITCH_PORT_MODE, port->chip_port);
534 return 0;
535}
536
537/* Generate the IFH for frame injection
538 *
539 * The IFH is a 128bit-value
540 * bit 127: bypass the analyzer processing
541 * bit 56-67: destination mask
542 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
543 * bit 20-27: cpu extraction queue mask
544 * bit 16: tag type 0: C-tag, 1: S-tag
545 * bit 0-11: VID
546 */
547static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info)
548{
549 ifh[0] = IFH_INJ_BYPASS | ((0x1ff & info->rew_op) << 21);
550 ifh[1] = (0xf00 & info->port) >> 8;
551 ifh[2] = (0xff & info->port) << 24;
552 ifh[3] = (info->tag_type << 16) | info->vid;
553
554 return 0;
555}
556
557static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev)
558{
559 struct skb_shared_info *shinfo = skb_shinfo(skb);
560 struct ocelot_port *port = netdev_priv(dev);
561 struct ocelot *ocelot = port->ocelot;
562 u32 val, ifh[IFH_LEN];
563 struct frame_info info = {};
564 u8 grp = 0; /* Send everything on CPU group 0 */
565 unsigned int i, count, last;
566
567 val = ocelot_read(ocelot, QS_INJ_STATUS);
568 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) ||
569 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))))
570 return NETDEV_TX_BUSY;
571
572 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
573 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
574
575 info.port = BIT(port->chip_port);
576 info.tag_type = IFH_TAG_TYPE_C;
577 info.vid = skb_vlan_tag_get(skb);
578
579 /* Check if timestamping is needed */
580 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP) {
581 info.rew_op = port->ptp_cmd;
582 if (port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP)
583 info.rew_op |= (port->ts_id % 4) << 3;
584 }
585
586 ocelot_gen_ifh(ifh, &info);
587
588 for (i = 0; i < IFH_LEN; i++)
589 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]),
590 QS_INJ_WR, grp);
591
592 count = (skb->len + 3) / 4;
593 last = skb->len % 4;
594 for (i = 0; i < count; i++) {
595 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
596 }
597
598 /* Add padding */
599 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
600 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
601 i++;
602 }
603
604 /* Indicate EOF and valid bytes in last word */
605 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
606 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
607 QS_INJ_CTRL_EOF,
608 QS_INJ_CTRL, grp);
609
610 /* Add dummy CRC */
611 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
612 skb_tx_timestamp(skb);
613
614 dev->stats.tx_packets++;
615 dev->stats.tx_bytes += skb->len;
616
617 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP &&
618 port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) {
619 struct ocelot_skb *oskb =
620 kzalloc(sizeof(struct ocelot_skb), GFP_ATOMIC);
621
622 if (unlikely(!oskb))
623 goto out;
624
625 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
626
627 oskb->skb = skb;
628 oskb->id = port->ts_id % 4;
629 port->ts_id++;
630
631 list_add_tail(&oskb->head, &port->skbs);
632
633 return NETDEV_TX_OK;
634 }
635
636out:
637 dev_kfree_skb_any(skb);
638 return NETDEV_TX_OK;
639}
640
641void ocelot_get_hwtimestamp(struct ocelot *ocelot, struct timespec64 *ts)
642{
643 unsigned long flags;
644 u32 val;
645
646 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
647
648 /* Read current PTP time to get seconds */
649 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
650
651 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
652 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE);
653 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
654 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
655
656 /* Read packet HW timestamp from FIFO */
657 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP);
658 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val);
659
660 /* Sec has incremented since the ts was registered */
661 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC))
662 ts->tv_sec--;
663
664 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
665}
666EXPORT_SYMBOL(ocelot_get_hwtimestamp);
667
668static int ocelot_mc_unsync(struct net_device *dev, const unsigned char *addr)
669{
670 struct ocelot_port *port = netdev_priv(dev);
671
672 return ocelot_mact_forget(port->ocelot, addr, port->pvid);
673}
674
675static int ocelot_mc_sync(struct net_device *dev, const unsigned char *addr)
676{
677 struct ocelot_port *port = netdev_priv(dev);
678
679 return ocelot_mact_learn(port->ocelot, PGID_CPU, addr, port->pvid,
680 ENTRYTYPE_LOCKED);
681}
682
683static void ocelot_set_rx_mode(struct net_device *dev)
684{
685 struct ocelot_port *port = netdev_priv(dev);
686 struct ocelot *ocelot = port->ocelot;
687 int i;
688 u32 val;
689
690 /* This doesn't handle promiscuous mode because the bridge core is
691 * setting IFF_PROMISC on all slave interfaces and all frames would be
692 * forwarded to the CPU port.
693 */
694 val = GENMASK(ocelot->num_phys_ports - 1, 0);
695 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++)
696 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
697
698 __dev_mc_sync(dev, ocelot_mc_sync, ocelot_mc_unsync);
699}
700
701static int ocelot_port_get_phys_port_name(struct net_device *dev,
702 char *buf, size_t len)
703{
704 struct ocelot_port *port = netdev_priv(dev);
705 int ret;
706
707 ret = snprintf(buf, len, "p%d", port->chip_port);
708 if (ret >= len)
709 return -EINVAL;
710
711 return 0;
712}
713
714static int ocelot_port_set_mac_address(struct net_device *dev, void *p)
715{
716 struct ocelot_port *port = netdev_priv(dev);
717 struct ocelot *ocelot = port->ocelot;
718 const struct sockaddr *addr = p;
719
720 /* Learn the new net device MAC address in the mac table. */
721 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, port->pvid,
722 ENTRYTYPE_LOCKED);
723 /* Then forget the previous one. */
724 ocelot_mact_forget(ocelot, dev->dev_addr, port->pvid);
725
726 ether_addr_copy(dev->dev_addr, addr->sa_data);
727 return 0;
728}
729
730static void ocelot_get_stats64(struct net_device *dev,
731 struct rtnl_link_stats64 *stats)
732{
733 struct ocelot_port *port = netdev_priv(dev);
734 struct ocelot *ocelot = port->ocelot;
735
736 /* Configure the port to read the stats from */
737 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port->chip_port),
738 SYS_STAT_CFG);
739
740 /* Get Rx stats */
741 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS);
742 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) +
743 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) +
744 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) +
745 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) +
746 ocelot_read(ocelot, SYS_COUNT_RX_64) +
747 ocelot_read(ocelot, SYS_COUNT_RX_65_127) +
748 ocelot_read(ocelot, SYS_COUNT_RX_128_255) +
749 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) +
750 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) +
751 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX);
752 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST);
753 stats->rx_dropped = dev->stats.rx_dropped;
754
755 /* Get Tx stats */
756 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS);
757 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) +
758 ocelot_read(ocelot, SYS_COUNT_TX_65_127) +
759 ocelot_read(ocelot, SYS_COUNT_TX_128_511) +
760 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) +
761 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) +
762 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX);
763 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) +
764 ocelot_read(ocelot, SYS_COUNT_TX_AGING);
765 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION);
766}
767
768static int ocelot_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
769 struct net_device *dev, const unsigned char *addr,
770 u16 vid, u16 flags,
771 struct netlink_ext_ack *extack)
772{
773 struct ocelot_port *port = netdev_priv(dev);
774 struct ocelot *ocelot = port->ocelot;
775
776 if (!vid) {
777 if (!port->vlan_aware)
778 /* If the bridge is not VLAN aware and no VID was
779 * provided, set it to pvid to ensure the MAC entry
780 * matches incoming untagged packets
781 */
782 vid = port->pvid;
783 else
784 /* If the bridge is VLAN aware a VID must be provided as
785 * otherwise the learnt entry wouldn't match any frame.
786 */
787 return -EINVAL;
788 }
789
790 return ocelot_mact_learn(ocelot, port->chip_port, addr, vid,
791 ENTRYTYPE_LOCKED);
792}
793
794static int ocelot_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
795 struct net_device *dev,
796 const unsigned char *addr, u16 vid)
797{
798 struct ocelot_port *port = netdev_priv(dev);
799 struct ocelot *ocelot = port->ocelot;
800
801 return ocelot_mact_forget(ocelot, addr, vid);
802}
803
804struct ocelot_dump_ctx {
805 struct net_device *dev;
806 struct sk_buff *skb;
807 struct netlink_callback *cb;
808 int idx;
809};
810
811static int ocelot_fdb_do_dump(struct ocelot_mact_entry *entry,
812 struct ocelot_dump_ctx *dump)
813{
814 u32 portid = NETLINK_CB(dump->cb->skb).portid;
815 u32 seq = dump->cb->nlh->nlmsg_seq;
816 struct nlmsghdr *nlh;
817 struct ndmsg *ndm;
818
819 if (dump->idx < dump->cb->args[2])
820 goto skip;
821
822 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH,
823 sizeof(*ndm), NLM_F_MULTI);
824 if (!nlh)
825 return -EMSGSIZE;
826
827 ndm = nlmsg_data(nlh);
828 ndm->ndm_family = AF_BRIDGE;
829 ndm->ndm_pad1 = 0;
830 ndm->ndm_pad2 = 0;
831 ndm->ndm_flags = NTF_SELF;
832 ndm->ndm_type = 0;
833 ndm->ndm_ifindex = dump->dev->ifindex;
834 ndm->ndm_state = NUD_REACHABLE;
835
836 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, entry->mac))
837 goto nla_put_failure;
838
839 if (entry->vid && nla_put_u16(dump->skb, NDA_VLAN, entry->vid))
840 goto nla_put_failure;
841
842 nlmsg_end(dump->skb, nlh);
843
844skip:
845 dump->idx++;
846 return 0;
847
848nla_put_failure:
849 nlmsg_cancel(dump->skb, nlh);
850 return -EMSGSIZE;
851}
852
853static inline int ocelot_mact_read(struct ocelot_port *port, int row, int col,
854 struct ocelot_mact_entry *entry)
855{
856 struct ocelot *ocelot = port->ocelot;
857 char mac[ETH_ALEN];
858 u32 val, dst, macl, mach;
859
860 /* Set row and column to read from */
861 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
862 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
863
864 /* Issue a read command */
865 ocelot_write(ocelot,
866 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
867 ANA_TABLES_MACACCESS);
868
869 if (ocelot_mact_wait_for_completion(ocelot))
870 return -ETIMEDOUT;
871
872 /* Read the entry flags */
873 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
874 if (!(val & ANA_TABLES_MACACCESS_VALID))
875 return -EINVAL;
876
877 /* If the entry read has another port configured as its destination,
878 * do not report it.
879 */
880 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
881 if (dst != port->chip_port)
882 return -EINVAL;
883
884 /* Get the entry's MAC address and VLAN id */
885 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
886 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
887
888 mac[0] = (mach >> 8) & 0xff;
889 mac[1] = (mach >> 0) & 0xff;
890 mac[2] = (macl >> 24) & 0xff;
891 mac[3] = (macl >> 16) & 0xff;
892 mac[4] = (macl >> 8) & 0xff;
893 mac[5] = (macl >> 0) & 0xff;
894
895 entry->vid = (mach >> 16) & 0xfff;
896 ether_addr_copy(entry->mac, mac);
897
898 return 0;
899}
900
901static int ocelot_fdb_dump(struct sk_buff *skb, struct netlink_callback *cb,
902 struct net_device *dev,
903 struct net_device *filter_dev, int *idx)
904{
905 struct ocelot_port *port = netdev_priv(dev);
906 int i, j, ret = 0;
907 struct ocelot_dump_ctx dump = {
908 .dev = dev,
909 .skb = skb,
910 .cb = cb,
911 .idx = *idx,
912 };
913
914 struct ocelot_mact_entry entry;
915
916 /* Loop through all the mac tables entries. There are 1024 rows of 4
917 * entries.
918 */
919 for (i = 0; i < 1024; i++) {
920 for (j = 0; j < 4; j++) {
921 ret = ocelot_mact_read(port, i, j, &entry);
922 /* If the entry is invalid (wrong port, invalid...),
923 * skip it.
924 */
925 if (ret == -EINVAL)
926 continue;
927 else if (ret)
928 goto end;
929
930 ret = ocelot_fdb_do_dump(&entry, &dump);
931 if (ret)
932 goto end;
933 }
934 }
935
936end:
937 *idx = dump.idx;
938 return ret;
939}
940
941static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto,
942 u16 vid)
943{
944 return ocelot_vlan_vid_add(dev, vid, false, false);
945}
946
947static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto,
948 u16 vid)
949{
950 return ocelot_vlan_vid_del(dev, vid);
951}
952
953static int ocelot_set_features(struct net_device *dev,
954 netdev_features_t features)
955{
956 struct ocelot_port *port = netdev_priv(dev);
957 netdev_features_t changed = dev->features ^ features;
958
959 if ((dev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
960 port->tc.offload_cnt) {
961 netdev_err(dev,
962 "Cannot disable HW TC offload while offloads active\n");
963 return -EBUSY;
964 }
965
966 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER)
967 ocelot_vlan_mode(port, features);
968
969 return 0;
970}
971
972static int ocelot_get_port_parent_id(struct net_device *dev,
973 struct netdev_phys_item_id *ppid)
974{
975 struct ocelot_port *ocelot_port = netdev_priv(dev);
976 struct ocelot *ocelot = ocelot_port->ocelot;
977
978 ppid->id_len = sizeof(ocelot->base_mac);
979 memcpy(&ppid->id, &ocelot->base_mac, ppid->id_len);
980
981 return 0;
982}
983
984static int ocelot_hwstamp_get(struct ocelot_port *port, struct ifreq *ifr)
985{
986 struct ocelot *ocelot = port->ocelot;
987
988 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config,
989 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0;
990}
991
992static int ocelot_hwstamp_set(struct ocelot_port *port, struct ifreq *ifr)
993{
994 struct ocelot *ocelot = port->ocelot;
995 struct hwtstamp_config cfg;
996
997 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
998 return -EFAULT;
999
1000 /* reserved for future extensions */
1001 if (cfg.flags)
1002 return -EINVAL;
1003
1004 /* Tx type sanity check */
1005 switch (cfg.tx_type) {
1006 case HWTSTAMP_TX_ON:
1007 port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
1008 break;
1009 case HWTSTAMP_TX_ONESTEP_SYNC:
1010 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we
1011 * need to update the origin time.
1012 */
1013 port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP;
1014 break;
1015 case HWTSTAMP_TX_OFF:
1016 port->ptp_cmd = 0;
1017 break;
1018 default:
1019 return -ERANGE;
1020 }
1021
1022 mutex_lock(&ocelot->ptp_lock);
1023
1024 switch (cfg.rx_filter) {
1025 case HWTSTAMP_FILTER_NONE:
1026 break;
1027 case HWTSTAMP_FILTER_ALL:
1028 case HWTSTAMP_FILTER_SOME:
1029 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1030 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1031 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1032 case HWTSTAMP_FILTER_NTP_ALL:
1033 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1034 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1035 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1036 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1037 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1038 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1039 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1040 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1041 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1042 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1043 break;
1044 default:
1045 mutex_unlock(&ocelot->ptp_lock);
1046 return -ERANGE;
1047 }
1048
1049 /* Commit back the result & save it */
1050 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg));
1051 mutex_unlock(&ocelot->ptp_lock);
1052
1053 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1054}
1055
1056static int ocelot_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1057{
1058 struct ocelot_port *port = netdev_priv(dev);
1059 struct ocelot *ocelot = port->ocelot;
1060
1061 /* The function is only used for PTP operations for now */
1062 if (!ocelot->ptp)
1063 return -EOPNOTSUPP;
1064
1065 switch (cmd) {
1066 case SIOCSHWTSTAMP:
1067 return ocelot_hwstamp_set(port, ifr);
1068 case SIOCGHWTSTAMP:
1069 return ocelot_hwstamp_get(port, ifr);
1070 default:
1071 return -EOPNOTSUPP;
1072 }
1073}
1074
1075static const struct net_device_ops ocelot_port_netdev_ops = {
1076 .ndo_open = ocelot_port_open,
1077 .ndo_stop = ocelot_port_stop,
1078 .ndo_start_xmit = ocelot_port_xmit,
1079 .ndo_set_rx_mode = ocelot_set_rx_mode,
1080 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name,
1081 .ndo_set_mac_address = ocelot_port_set_mac_address,
1082 .ndo_get_stats64 = ocelot_get_stats64,
1083 .ndo_fdb_add = ocelot_fdb_add,
1084 .ndo_fdb_del = ocelot_fdb_del,
1085 .ndo_fdb_dump = ocelot_fdb_dump,
1086 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid,
1087 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid,
1088 .ndo_set_features = ocelot_set_features,
1089 .ndo_get_port_parent_id = ocelot_get_port_parent_id,
1090 .ndo_setup_tc = ocelot_setup_tc,
1091 .ndo_do_ioctl = ocelot_ioctl,
1092};
1093
1094static void ocelot_get_strings(struct net_device *netdev, u32 sset, u8 *data)
1095{
1096 struct ocelot_port *port = netdev_priv(netdev);
1097 struct ocelot *ocelot = port->ocelot;
1098 int i;
1099
1100 if (sset != ETH_SS_STATS)
1101 return;
1102
1103 for (i = 0; i < ocelot->num_stats; i++)
1104 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
1105 ETH_GSTRING_LEN);
1106}
1107
1108static void ocelot_update_stats(struct ocelot *ocelot)
1109{
1110 int i, j;
1111
1112 mutex_lock(&ocelot->stats_lock);
1113
1114 for (i = 0; i < ocelot->num_phys_ports; i++) {
1115 /* Configure the port to read the stats from */
1116 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG);
1117
1118 for (j = 0; j < ocelot->num_stats; j++) {
1119 u32 val;
1120 unsigned int idx = i * ocelot->num_stats + j;
1121
1122 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS,
1123 ocelot->stats_layout[j].offset);
1124
1125 if (val < (ocelot->stats[idx] & U32_MAX))
1126 ocelot->stats[idx] += (u64)1 << 32;
1127
1128 ocelot->stats[idx] = (ocelot->stats[idx] &
1129 ~(u64)U32_MAX) + val;
1130 }
1131 }
1132
1133 mutex_unlock(&ocelot->stats_lock);
1134}
1135
1136static void ocelot_check_stats_work(struct work_struct *work)
1137{
1138 struct delayed_work *del_work = to_delayed_work(work);
1139 struct ocelot *ocelot = container_of(del_work, struct ocelot,
1140 stats_work);
1141
1142 ocelot_update_stats(ocelot);
1143
1144 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
1145 OCELOT_STATS_CHECK_DELAY);
1146}
1147
1148static void ocelot_get_ethtool_stats(struct net_device *dev,
1149 struct ethtool_stats *stats, u64 *data)
1150{
1151 struct ocelot_port *port = netdev_priv(dev);
1152 struct ocelot *ocelot = port->ocelot;
1153 int i;
1154
1155 /* check and update now */
1156 ocelot_update_stats(ocelot);
1157
1158 /* Copy all counters */
1159 for (i = 0; i < ocelot->num_stats; i++)
1160 *data++ = ocelot->stats[port->chip_port * ocelot->num_stats + i];
1161}
1162
1163static int ocelot_get_sset_count(struct net_device *dev, int sset)
1164{
1165 struct ocelot_port *port = netdev_priv(dev);
1166 struct ocelot *ocelot = port->ocelot;
1167
1168 if (sset != ETH_SS_STATS)
1169 return -EOPNOTSUPP;
1170 return ocelot->num_stats;
1171}
1172
1173static int ocelot_get_ts_info(struct net_device *dev,
1174 struct ethtool_ts_info *info)
1175{
1176 struct ocelot_port *ocelot_port = netdev_priv(dev);
1177 struct ocelot *ocelot = ocelot_port->ocelot;
1178
1179 if (!ocelot->ptp)
1180 return ethtool_op_get_ts_info(dev, info);
1181
1182 info->phc_index = ocelot->ptp_clock ?
1183 ptp_clock_index(ocelot->ptp_clock) : -1;
1184 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
1185 SOF_TIMESTAMPING_RX_SOFTWARE |
1186 SOF_TIMESTAMPING_SOFTWARE |
1187 SOF_TIMESTAMPING_TX_HARDWARE |
1188 SOF_TIMESTAMPING_RX_HARDWARE |
1189 SOF_TIMESTAMPING_RAW_HARDWARE;
1190 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) |
1191 BIT(HWTSTAMP_TX_ONESTEP_SYNC);
1192 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL);
1193
1194 return 0;
1195}
1196
1197static const struct ethtool_ops ocelot_ethtool_ops = {
1198 .get_strings = ocelot_get_strings,
1199 .get_ethtool_stats = ocelot_get_ethtool_stats,
1200 .get_sset_count = ocelot_get_sset_count,
1201 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1202 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1203 .get_ts_info = ocelot_get_ts_info,
1204};
1205
1206static int ocelot_port_attr_stp_state_set(struct ocelot_port *ocelot_port,
1207 struct switchdev_trans *trans,
1208 u8 state)
1209{
1210 struct ocelot *ocelot = ocelot_port->ocelot;
1211 u32 port_cfg;
1212 int port, i;
1213
1214 if (switchdev_trans_ph_prepare(trans))
1215 return 0;
1216
1217 if (!(BIT(ocelot_port->chip_port) & ocelot->bridge_mask))
1218 return 0;
1219
1220 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG,
1221 ocelot_port->chip_port);
1222
1223 switch (state) {
1224 case BR_STATE_FORWARDING:
1225 ocelot->bridge_fwd_mask |= BIT(ocelot_port->chip_port);
1226 /* Fallthrough */
1227 case BR_STATE_LEARNING:
1228 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
1229 break;
1230
1231 default:
1232 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
1233 ocelot->bridge_fwd_mask &= ~BIT(ocelot_port->chip_port);
1234 break;
1235 }
1236
1237 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG,
1238 ocelot_port->chip_port);
1239
1240 /* Apply FWD mask. The loop is needed to add/remove the current port as
1241 * a source for the other ports.
1242 */
1243 for (port = 0; port < ocelot->num_phys_ports; port++) {
1244 if (ocelot->bridge_fwd_mask & BIT(port)) {
1245 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port);
1246
1247 for (i = 0; i < ocelot->num_phys_ports; i++) {
1248 unsigned long bond_mask = ocelot->lags[i];
1249
1250 if (!bond_mask)
1251 continue;
1252
1253 if (bond_mask & BIT(port)) {
1254 mask &= ~bond_mask;
1255 break;
1256 }
1257 }
1258
1259 ocelot_write_rix(ocelot,
1260 BIT(ocelot->num_phys_ports) | mask,
1261 ANA_PGID_PGID, PGID_SRC + port);
1262 } else {
1263 /* Only the CPU port, this is compatible with link
1264 * aggregation.
1265 */
1266 ocelot_write_rix(ocelot,
1267 BIT(ocelot->num_phys_ports),
1268 ANA_PGID_PGID, PGID_SRC + port);
1269 }
1270 }
1271
1272 return 0;
1273}
1274
1275static void ocelot_port_attr_ageing_set(struct ocelot_port *ocelot_port,
1276 unsigned long ageing_clock_t)
1277{
1278 struct ocelot *ocelot = ocelot_port->ocelot;
1279 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t);
1280 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000;
1281
1282 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(ageing_time / 2),
1283 ANA_AUTOAGE);
1284}
1285
1286static void ocelot_port_attr_mc_set(struct ocelot_port *port, bool mc)
1287{
1288 struct ocelot *ocelot = port->ocelot;
1289 u32 val = ocelot_read_gix(ocelot, ANA_PORT_CPU_FWD_CFG,
1290 port->chip_port);
1291
1292 if (mc)
1293 val |= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
1294 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
1295 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA;
1296 else
1297 val &= ~(ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
1298 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
1299 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA);
1300
1301 ocelot_write_gix(ocelot, val, ANA_PORT_CPU_FWD_CFG, port->chip_port);
1302}
1303
1304static int ocelot_port_attr_set(struct net_device *dev,
1305 const struct switchdev_attr *attr,
1306 struct switchdev_trans *trans)
1307{
1308 struct ocelot_port *ocelot_port = netdev_priv(dev);
1309 int err = 0;
1310
1311 switch (attr->id) {
1312 case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
1313 ocelot_port_attr_stp_state_set(ocelot_port, trans,
1314 attr->u.stp_state);
1315 break;
1316 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME:
1317 ocelot_port_attr_ageing_set(ocelot_port, attr->u.ageing_time);
1318 break;
1319 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING:
1320 ocelot_port->vlan_aware = attr->u.vlan_filtering;
1321 ocelot_vlan_port_apply(ocelot_port->ocelot, ocelot_port);
1322 break;
1323 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED:
1324 ocelot_port_attr_mc_set(ocelot_port, !attr->u.mc_disabled);
1325 break;
1326 default:
1327 err = -EOPNOTSUPP;
1328 break;
1329 }
1330
1331 return err;
1332}
1333
1334static int ocelot_port_obj_add_vlan(struct net_device *dev,
1335 const struct switchdev_obj_port_vlan *vlan,
1336 struct switchdev_trans *trans)
1337{
1338 int ret;
1339 u16 vid;
1340
1341 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
1342 ret = ocelot_vlan_vid_add(dev, vid,
1343 vlan->flags & BRIDGE_VLAN_INFO_PVID,
1344 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED);
1345 if (ret)
1346 return ret;
1347 }
1348
1349 return 0;
1350}
1351
1352static int ocelot_port_vlan_del_vlan(struct net_device *dev,
1353 const struct switchdev_obj_port_vlan *vlan)
1354{
1355 int ret;
1356 u16 vid;
1357
1358 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
1359 ret = ocelot_vlan_vid_del(dev, vid);
1360
1361 if (ret)
1362 return ret;
1363 }
1364
1365 return 0;
1366}
1367
1368static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
1369 const unsigned char *addr,
1370 u16 vid)
1371{
1372 struct ocelot_multicast *mc;
1373
1374 list_for_each_entry(mc, &ocelot->multicast, list) {
1375 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
1376 return mc;
1377 }
1378
1379 return NULL;
1380}
1381
1382static int ocelot_port_obj_add_mdb(struct net_device *dev,
1383 const struct switchdev_obj_port_mdb *mdb,
1384 struct switchdev_trans *trans)
1385{
1386 struct ocelot_port *port = netdev_priv(dev);
1387 struct ocelot *ocelot = port->ocelot;
1388 struct ocelot_multicast *mc;
1389 unsigned char addr[ETH_ALEN];
1390 u16 vid = mdb->vid;
1391 bool new = false;
1392
1393 if (!vid)
1394 vid = port->pvid;
1395
1396 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1397 if (!mc) {
1398 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
1399 if (!mc)
1400 return -ENOMEM;
1401
1402 memcpy(mc->addr, mdb->addr, ETH_ALEN);
1403 mc->vid = vid;
1404
1405 list_add_tail(&mc->list, &ocelot->multicast);
1406 new = true;
1407 }
1408
1409 memcpy(addr, mc->addr, ETH_ALEN);
1410 addr[0] = 0;
1411
1412 if (!new) {
1413 addr[2] = mc->ports << 0;
1414 addr[1] = mc->ports << 8;
1415 ocelot_mact_forget(ocelot, addr, vid);
1416 }
1417
1418 mc->ports |= BIT(port->chip_port);
1419 addr[2] = mc->ports << 0;
1420 addr[1] = mc->ports << 8;
1421
1422 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4);
1423}
1424
1425static int ocelot_port_obj_del_mdb(struct net_device *dev,
1426 const struct switchdev_obj_port_mdb *mdb)
1427{
1428 struct ocelot_port *port = netdev_priv(dev);
1429 struct ocelot *ocelot = port->ocelot;
1430 struct ocelot_multicast *mc;
1431 unsigned char addr[ETH_ALEN];
1432 u16 vid = mdb->vid;
1433
1434 if (!vid)
1435 vid = port->pvid;
1436
1437 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1438 if (!mc)
1439 return -ENOENT;
1440
1441 memcpy(addr, mc->addr, ETH_ALEN);
1442 addr[2] = mc->ports << 0;
1443 addr[1] = mc->ports << 8;
1444 addr[0] = 0;
1445 ocelot_mact_forget(ocelot, addr, vid);
1446
1447 mc->ports &= ~BIT(port->chip_port);
1448 if (!mc->ports) {
1449 list_del(&mc->list);
1450 devm_kfree(ocelot->dev, mc);
1451 return 0;
1452 }
1453
1454 addr[2] = mc->ports << 0;
1455 addr[1] = mc->ports << 8;
1456
1457 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4);
1458}
1459
1460static int ocelot_port_obj_add(struct net_device *dev,
1461 const struct switchdev_obj *obj,
1462 struct switchdev_trans *trans,
1463 struct netlink_ext_ack *extack)
1464{
1465 int ret = 0;
1466
1467 switch (obj->id) {
1468 case SWITCHDEV_OBJ_ID_PORT_VLAN:
1469 ret = ocelot_port_obj_add_vlan(dev,
1470 SWITCHDEV_OBJ_PORT_VLAN(obj),
1471 trans);
1472 break;
1473 case SWITCHDEV_OBJ_ID_PORT_MDB:
1474 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj),
1475 trans);
1476 break;
1477 default:
1478 return -EOPNOTSUPP;
1479 }
1480
1481 return ret;
1482}
1483
1484static int ocelot_port_obj_del(struct net_device *dev,
1485 const struct switchdev_obj *obj)
1486{
1487 int ret = 0;
1488
1489 switch (obj->id) {
1490 case SWITCHDEV_OBJ_ID_PORT_VLAN:
1491 ret = ocelot_port_vlan_del_vlan(dev,
1492 SWITCHDEV_OBJ_PORT_VLAN(obj));
1493 break;
1494 case SWITCHDEV_OBJ_ID_PORT_MDB:
1495 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj));
1496 break;
1497 default:
1498 return -EOPNOTSUPP;
1499 }
1500
1501 return ret;
1502}
1503
1504static int ocelot_port_bridge_join(struct ocelot_port *ocelot_port,
1505 struct net_device *bridge)
1506{
1507 struct ocelot *ocelot = ocelot_port->ocelot;
1508
1509 if (!ocelot->bridge_mask) {
1510 ocelot->hw_bridge_dev = bridge;
1511 } else {
1512 if (ocelot->hw_bridge_dev != bridge)
1513 /* This is adding the port to a second bridge, this is
1514 * unsupported */
1515 return -ENODEV;
1516 }
1517
1518 ocelot->bridge_mask |= BIT(ocelot_port->chip_port);
1519
1520 return 0;
1521}
1522
1523static void ocelot_port_bridge_leave(struct ocelot_port *ocelot_port,
1524 struct net_device *bridge)
1525{
1526 struct ocelot *ocelot = ocelot_port->ocelot;
1527
1528 ocelot->bridge_mask &= ~BIT(ocelot_port->chip_port);
1529
1530 if (!ocelot->bridge_mask)
1531 ocelot->hw_bridge_dev = NULL;
1532
1533 /* Clear bridge vlan settings before calling ocelot_vlan_port_apply */
1534 ocelot_port->vlan_aware = 0;
1535 ocelot_port->pvid = 0;
1536 ocelot_port->vid = 0;
1537}
1538
1539static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
1540{
1541 int i, port, lag;
1542
1543 /* Reset destination and aggregation PGIDS */
1544 for (port = 0; port < ocelot->num_phys_ports; port++)
1545 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1546
1547 for (i = PGID_AGGR; i < PGID_SRC; i++)
1548 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
1549 ANA_PGID_PGID, i);
1550
1551 /* Now, set PGIDs for each LAG */
1552 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
1553 unsigned long bond_mask;
1554 int aggr_count = 0;
1555 u8 aggr_idx[16];
1556
1557 bond_mask = ocelot->lags[lag];
1558 if (!bond_mask)
1559 continue;
1560
1561 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
1562 // Destination mask
1563 ocelot_write_rix(ocelot, bond_mask,
1564 ANA_PGID_PGID, port);
1565 aggr_idx[aggr_count] = port;
1566 aggr_count++;
1567 }
1568
1569 for (i = PGID_AGGR; i < PGID_SRC; i++) {
1570 u32 ac;
1571
1572 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
1573 ac &= ~bond_mask;
1574 ac |= BIT(aggr_idx[i % aggr_count]);
1575 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
1576 }
1577 }
1578}
1579
1580static void ocelot_setup_lag(struct ocelot *ocelot, int lag)
1581{
1582 unsigned long bond_mask = ocelot->lags[lag];
1583 unsigned int p;
1584
1585 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) {
1586 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p);
1587
1588 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1589
1590 /* Use lag port as logical port for port i */
1591 ocelot_write_gix(ocelot, port_cfg |
1592 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
1593 ANA_PORT_PORT_CFG, p);
1594 }
1595}
1596
1597static int ocelot_port_lag_join(struct ocelot_port *ocelot_port,
1598 struct net_device *bond)
1599{
1600 struct ocelot *ocelot = ocelot_port->ocelot;
1601 int p = ocelot_port->chip_port;
1602 int lag, lp;
1603 struct net_device *ndev;
1604 u32 bond_mask = 0;
1605
1606 rcu_read_lock();
1607 for_each_netdev_in_bond_rcu(bond, ndev) {
1608 struct ocelot_port *port = netdev_priv(ndev);
1609
1610 bond_mask |= BIT(port->chip_port);
1611 }
1612 rcu_read_unlock();
1613
1614 lp = __ffs(bond_mask);
1615
1616 /* If the new port is the lowest one, use it as the logical port from
1617 * now on
1618 */
1619 if (p == lp) {
1620 lag = p;
1621 ocelot->lags[p] = bond_mask;
1622 bond_mask &= ~BIT(p);
1623 if (bond_mask) {
1624 lp = __ffs(bond_mask);
1625 ocelot->lags[lp] = 0;
1626 }
1627 } else {
1628 lag = lp;
1629 ocelot->lags[lp] |= BIT(p);
1630 }
1631
1632 ocelot_setup_lag(ocelot, lag);
1633 ocelot_set_aggr_pgids(ocelot);
1634
1635 return 0;
1636}
1637
1638static void ocelot_port_lag_leave(struct ocelot_port *ocelot_port,
1639 struct net_device *bond)
1640{
1641 struct ocelot *ocelot = ocelot_port->ocelot;
1642 int p = ocelot_port->chip_port;
1643 u32 port_cfg;
1644 int i;
1645
1646 /* Remove port from any lag */
1647 for (i = 0; i < ocelot->num_phys_ports; i++)
1648 ocelot->lags[i] &= ~BIT(ocelot_port->chip_port);
1649
1650 /* if it was the logical port of the lag, move the lag config to the
1651 * next port
1652 */
1653 if (ocelot->lags[p]) {
1654 int n = __ffs(ocelot->lags[p]);
1655
1656 ocelot->lags[n] = ocelot->lags[p];
1657 ocelot->lags[p] = 0;
1658
1659 ocelot_setup_lag(ocelot, n);
1660 }
1661
1662 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p);
1663 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1664 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(p),
1665 ANA_PORT_PORT_CFG, p);
1666
1667 ocelot_set_aggr_pgids(ocelot);
1668}
1669
1670/* Checks if the net_device instance given to us originate from our driver. */
1671static bool ocelot_netdevice_dev_check(const struct net_device *dev)
1672{
1673 return dev->netdev_ops == &ocelot_port_netdev_ops;
1674}
1675
1676static int ocelot_netdevice_port_event(struct net_device *dev,
1677 unsigned long event,
1678 struct netdev_notifier_changeupper_info *info)
1679{
1680 struct ocelot_port *ocelot_port = netdev_priv(dev);
1681 int err = 0;
1682
1683 switch (event) {
1684 case NETDEV_CHANGEUPPER:
1685 if (netif_is_bridge_master(info->upper_dev)) {
1686 if (info->linking)
1687 err = ocelot_port_bridge_join(ocelot_port,
1688 info->upper_dev);
1689 else
1690 ocelot_port_bridge_leave(ocelot_port,
1691 info->upper_dev);
1692
1693 ocelot_vlan_port_apply(ocelot_port->ocelot,
1694 ocelot_port);
1695 }
1696 if (netif_is_lag_master(info->upper_dev)) {
1697 if (info->linking)
1698 err = ocelot_port_lag_join(ocelot_port,
1699 info->upper_dev);
1700 else
1701 ocelot_port_lag_leave(ocelot_port,
1702 info->upper_dev);
1703 }
1704 break;
1705 default:
1706 break;
1707 }
1708
1709 return err;
1710}
1711
1712static int ocelot_netdevice_event(struct notifier_block *unused,
1713 unsigned long event, void *ptr)
1714{
1715 struct netdev_notifier_changeupper_info *info = ptr;
1716 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
1717 int ret = 0;
1718
1719 if (!ocelot_netdevice_dev_check(dev))
1720 return 0;
1721
1722 if (event == NETDEV_PRECHANGEUPPER &&
1723 netif_is_lag_master(info->upper_dev)) {
1724 struct netdev_lag_upper_info *lag_upper_info = info->upper_info;
1725 struct netlink_ext_ack *extack;
1726
1727 if (lag_upper_info &&
1728 lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
1729 extack = netdev_notifier_info_to_extack(&info->info);
1730 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
1731
1732 ret = -EINVAL;
1733 goto notify;
1734 }
1735 }
1736
1737 if (netif_is_lag_master(dev)) {
1738 struct net_device *slave;
1739 struct list_head *iter;
1740
1741 netdev_for_each_lower_dev(dev, slave, iter) {
1742 ret = ocelot_netdevice_port_event(slave, event, info);
1743 if (ret)
1744 goto notify;
1745 }
1746 } else {
1747 ret = ocelot_netdevice_port_event(dev, event, info);
1748 }
1749
1750notify:
1751 return notifier_from_errno(ret);
1752}
1753
1754struct notifier_block ocelot_netdevice_nb __read_mostly = {
1755 .notifier_call = ocelot_netdevice_event,
1756};
1757EXPORT_SYMBOL(ocelot_netdevice_nb);
1758
1759static int ocelot_switchdev_event(struct notifier_block *unused,
1760 unsigned long event, void *ptr)
1761{
1762 struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
1763 int err;
1764
1765 switch (event) {
1766 case SWITCHDEV_PORT_ATTR_SET:
1767 err = switchdev_handle_port_attr_set(dev, ptr,
1768 ocelot_netdevice_dev_check,
1769 ocelot_port_attr_set);
1770 return notifier_from_errno(err);
1771 }
1772
1773 return NOTIFY_DONE;
1774}
1775
1776struct notifier_block ocelot_switchdev_nb __read_mostly = {
1777 .notifier_call = ocelot_switchdev_event,
1778};
1779EXPORT_SYMBOL(ocelot_switchdev_nb);
1780
1781static int ocelot_switchdev_blocking_event(struct notifier_block *unused,
1782 unsigned long event, void *ptr)
1783{
1784 struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
1785 int err;
1786
1787 switch (event) {
1788 /* Blocking events. */
1789 case SWITCHDEV_PORT_OBJ_ADD:
1790 err = switchdev_handle_port_obj_add(dev, ptr,
1791 ocelot_netdevice_dev_check,
1792 ocelot_port_obj_add);
1793 return notifier_from_errno(err);
1794 case SWITCHDEV_PORT_OBJ_DEL:
1795 err = switchdev_handle_port_obj_del(dev, ptr,
1796 ocelot_netdevice_dev_check,
1797 ocelot_port_obj_del);
1798 return notifier_from_errno(err);
1799 case SWITCHDEV_PORT_ATTR_SET:
1800 err = switchdev_handle_port_attr_set(dev, ptr,
1801 ocelot_netdevice_dev_check,
1802 ocelot_port_attr_set);
1803 return notifier_from_errno(err);
1804 }
1805
1806 return NOTIFY_DONE;
1807}
1808
1809struct notifier_block ocelot_switchdev_blocking_nb __read_mostly = {
1810 .notifier_call = ocelot_switchdev_blocking_event,
1811};
1812EXPORT_SYMBOL(ocelot_switchdev_blocking_nb);
1813
1814int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts)
1815{
1816 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info);
1817 unsigned long flags;
1818 time64_t s;
1819 u32 val;
1820 s64 ns;
1821
1822 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
1823
1824 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
1825 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
1826 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE);
1827 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
1828
1829 s = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN) & 0xffff;
1830 s <<= 32;
1831 s += ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
1832 ns = ocelot_read_rix(ocelot, PTP_PIN_TOD_NSEC, TOD_ACC_PIN);
1833
1834 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
1835
1836 /* Deal with negative values */
1837 if (ns >= 0x3ffffff0 && ns <= 0x3fffffff) {
1838 s--;
1839 ns &= 0xf;
1840 ns += 999999984;
1841 }
1842
1843 set_normalized_timespec64(ts, s, ns);
1844 return 0;
1845}
1846EXPORT_SYMBOL(ocelot_ptp_gettime64);
1847
1848static int ocelot_ptp_settime64(struct ptp_clock_info *ptp,
1849 const struct timespec64 *ts)
1850{
1851 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info);
1852 unsigned long flags;
1853 u32 val;
1854
1855 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
1856
1857 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
1858 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
1859 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE);
1860
1861 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
1862
1863 ocelot_write_rix(ocelot, lower_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_LSB,
1864 TOD_ACC_PIN);
1865 ocelot_write_rix(ocelot, upper_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_MSB,
1866 TOD_ACC_PIN);
1867 ocelot_write_rix(ocelot, ts->tv_nsec, PTP_PIN_TOD_NSEC, TOD_ACC_PIN);
1868
1869 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
1870 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
1871 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_LOAD);
1872
1873 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
1874
1875 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
1876 return 0;
1877}
1878
1879static int ocelot_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
1880{
1881 if (delta > -(NSEC_PER_SEC / 2) && delta < (NSEC_PER_SEC / 2)) {
1882 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info);
1883 unsigned long flags;
1884 u32 val;
1885
1886 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
1887
1888 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
1889 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
1890 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE);
1891
1892 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
1893
1894 ocelot_write_rix(ocelot, 0, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
1895 ocelot_write_rix(ocelot, 0, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN);
1896 ocelot_write_rix(ocelot, delta, PTP_PIN_TOD_NSEC, TOD_ACC_PIN);
1897
1898 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
1899 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
1900 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_DELTA);
1901
1902 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
1903
1904 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
1905 } else {
1906 /* Fall back using ocelot_ptp_settime64 which is not exact. */
1907 struct timespec64 ts;
1908 u64 now;
1909
1910 ocelot_ptp_gettime64(ptp, &ts);
1911
1912 now = ktime_to_ns(timespec64_to_ktime(ts));
1913 ts = ns_to_timespec64(now + delta);
1914
1915 ocelot_ptp_settime64(ptp, &ts);
1916 }
1917 return 0;
1918}
1919
1920static int ocelot_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
1921{
1922 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info);
1923 u32 unit = 0, direction = 0;
1924 unsigned long flags;
1925 u64 adj = 0;
1926
1927 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
1928
1929 if (!scaled_ppm)
1930 goto disable_adj;
1931
1932 if (scaled_ppm < 0) {
1933 direction = PTP_CFG_CLK_ADJ_CFG_DIR;
1934 scaled_ppm = -scaled_ppm;
1935 }
1936
1937 adj = PSEC_PER_SEC << 16;
1938 do_div(adj, scaled_ppm);
1939 do_div(adj, 1000);
1940
1941 /* If the adjustment value is too large, use ns instead */
1942 if (adj >= (1L << 30)) {
1943 unit = PTP_CFG_CLK_ADJ_FREQ_NS;
1944 do_div(adj, 1000);
1945 }
1946
1947 /* Still too big */
1948 if (adj >= (1L << 30))
1949 goto disable_adj;
1950
1951 ocelot_write(ocelot, unit | adj, PTP_CLK_CFG_ADJ_FREQ);
1952 ocelot_write(ocelot, PTP_CFG_CLK_ADJ_CFG_ENA | direction,
1953 PTP_CLK_CFG_ADJ_CFG);
1954
1955 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
1956 return 0;
1957
1958disable_adj:
1959 ocelot_write(ocelot, 0, PTP_CLK_CFG_ADJ_CFG);
1960
1961 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
1962 return 0;
1963}
1964
1965static struct ptp_clock_info ocelot_ptp_clock_info = {
1966 .owner = THIS_MODULE,
1967 .name = "ocelot ptp",
1968 .max_adj = 0x7fffffff,
1969 .n_alarm = 0,
1970 .n_ext_ts = 0,
1971 .n_per_out = 0,
1972 .n_pins = 0,
1973 .pps = 0,
1974 .gettime64 = ocelot_ptp_gettime64,
1975 .settime64 = ocelot_ptp_settime64,
1976 .adjtime = ocelot_ptp_adjtime,
1977 .adjfine = ocelot_ptp_adjfine,
1978};
1979
1980static int ocelot_init_timestamp(struct ocelot *ocelot)
1981{
1982 ocelot->ptp_info = ocelot_ptp_clock_info;
1983 ocelot->ptp_clock = ptp_clock_register(&ocelot->ptp_info, ocelot->dev);
1984 if (IS_ERR(ocelot->ptp_clock))
1985 return PTR_ERR(ocelot->ptp_clock);
1986 /* Check if PHC support is missing at the configuration level */
1987 if (!ocelot->ptp_clock)
1988 return 0;
1989
1990 ocelot_write(ocelot, SYS_PTP_CFG_PTP_STAMP_WID(30), SYS_PTP_CFG);
1991 ocelot_write(ocelot, 0xffffffff, ANA_TABLES_PTP_ID_LOW);
1992 ocelot_write(ocelot, 0xffffffff, ANA_TABLES_PTP_ID_HIGH);
1993
1994 ocelot_write(ocelot, PTP_CFG_MISC_PTP_EN, PTP_CFG_MISC);
1995
1996 /* There is no device reconfiguration, PTP Rx stamping is always
1997 * enabled.
1998 */
1999 ocelot->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
2000
2001 return 0;
2002}
2003
2004int ocelot_probe_port(struct ocelot *ocelot, u8 port,
2005 void __iomem *regs,
2006 struct phy_device *phy)
2007{
2008 struct ocelot_port *ocelot_port;
2009 struct net_device *dev;
2010 int err;
2011
2012 dev = alloc_etherdev(sizeof(struct ocelot_port));
2013 if (!dev)
2014 return -ENOMEM;
2015 SET_NETDEV_DEV(dev, ocelot->dev);
2016 ocelot_port = netdev_priv(dev);
2017 ocelot_port->dev = dev;
2018 ocelot_port->ocelot = ocelot;
2019 ocelot_port->regs = regs;
2020 ocelot_port->chip_port = port;
2021 ocelot_port->phy = phy;
2022 ocelot->ports[port] = ocelot_port;
2023
2024 dev->netdev_ops = &ocelot_port_netdev_ops;
2025 dev->ethtool_ops = &ocelot_ethtool_ops;
2026
2027 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS |
2028 NETIF_F_HW_TC;
2029 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2030
2031 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN);
2032 dev->dev_addr[ETH_ALEN - 1] += port;
2033 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid,
2034 ENTRYTYPE_LOCKED);
2035
2036 INIT_LIST_HEAD(&ocelot_port->skbs);
2037
2038 err = register_netdev(dev);
2039 if (err) {
2040 dev_err(ocelot->dev, "register_netdev failed\n");
2041 goto err_register_netdev;
2042 }
2043
2044 /* Basic L2 initialization */
2045 ocelot_vlan_port_apply(ocelot, ocelot_port);
2046
2047 /* Enable vcap lookups */
2048 ocelot_vcap_enable(ocelot, ocelot_port);
2049
2050 return 0;
2051
2052err_register_netdev:
2053 free_netdev(dev);
2054 return err;
2055}
2056EXPORT_SYMBOL(ocelot_probe_port);
2057
2058int ocelot_init(struct ocelot *ocelot)
2059{
2060 u32 port;
2061 int i, ret, cpu = ocelot->num_phys_ports;
2062 char queue_name[32];
2063
2064 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,
2065 sizeof(u32), GFP_KERNEL);
2066 if (!ocelot->lags)
2067 return -ENOMEM;
2068
2069 ocelot->stats = devm_kcalloc(ocelot->dev,
2070 ocelot->num_phys_ports * ocelot->num_stats,
2071 sizeof(u64), GFP_KERNEL);
2072 if (!ocelot->stats)
2073 return -ENOMEM;
2074
2075 mutex_init(&ocelot->stats_lock);
2076 mutex_init(&ocelot->ptp_lock);
2077 spin_lock_init(&ocelot->ptp_clock_lock);
2078 snprintf(queue_name, sizeof(queue_name), "%s-stats",
2079 dev_name(ocelot->dev));
2080 ocelot->stats_queue = create_singlethread_workqueue(queue_name);
2081 if (!ocelot->stats_queue)
2082 return -ENOMEM;
2083
2084 ocelot_mact_init(ocelot);
2085 ocelot_vlan_init(ocelot);
2086 ocelot_ace_init(ocelot);
2087
2088 for (port = 0; port < ocelot->num_phys_ports; port++) {
2089 /* Clear all counters (5 groups) */
2090 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
2091 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
2092 SYS_STAT_CFG);
2093 }
2094
2095 /* Only use S-Tag */
2096 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
2097
2098 /* Aggregation mode */
2099 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
2100 ANA_AGGR_CFG_AC_DMAC_ENA |
2101 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
2102 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG);
2103
2104 /* Set MAC age time to default value. The entry is aged after
2105 * 2*AGE_PERIOD
2106 */
2107 ocelot_write(ocelot,
2108 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
2109 ANA_AUTOAGE);
2110
2111 /* Disable learning for frames discarded by VLAN ingress filtering */
2112 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
2113
2114 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
2115 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
2116 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
2117
2118 /* Setup flooding PGIDs */
2119 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
2120 ANA_FLOODING_FLD_BROADCAST(PGID_MC) |
2121 ANA_FLOODING_FLD_UNICAST(PGID_UC),
2122 ANA_FLOODING, 0);
2123 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
2124 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
2125 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
2126 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
2127 ANA_FLOODING_IPMC);
2128
2129 for (port = 0; port < ocelot->num_phys_ports; port++) {
2130 /* Transmit the frame to the local port. */
2131 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
2132 /* Do not forward BPDU frames to the front ports. */
2133 ocelot_write_gix(ocelot,
2134 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
2135 ANA_PORT_CPU_FWD_BPDU_CFG,
2136 port);
2137 /* Ensure bridging is disabled */
2138 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
2139 }
2140
2141 /* Configure and enable the CPU port. */
2142 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
2143 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
2144 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
2145 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
2146 ANA_PORT_PORT_CFG, cpu);
2147
2148 /* Allow broadcast MAC frames. */
2149 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) {
2150 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
2151
2152 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
2153 }
2154 ocelot_write_rix(ocelot,
2155 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
2156 ANA_PGID_PGID, PGID_MC);
2157 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
2158 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
2159
2160 /* CPU port Injection/Extraction configuration */
2161 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
2162 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
2163 QSYS_SWITCH_PORT_MODE_PORT_ENA,
2164 QSYS_SWITCH_PORT_MODE, cpu);
2165 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(1) |
2166 SYS_PORT_MODE_INCL_INJ_HDR(1), SYS_PORT_MODE, cpu);
2167 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
2168 * registers endianness.
2169 */
2170 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
2171 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
2172 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
2173 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
2174 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
2175 ANA_CPUQ_CFG_CPUQ_LRN(2) |
2176 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
2177 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
2178 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
2179 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
2180 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
2181 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
2182 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
2183 for (i = 0; i < 16; i++)
2184 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
2185 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
2186 ANA_CPUQ_8021_CFG, i);
2187
2188 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work);
2189 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
2190 OCELOT_STATS_CHECK_DELAY);
2191
2192 if (ocelot->ptp) {
2193 ret = ocelot_init_timestamp(ocelot);
2194 if (ret) {
2195 dev_err(ocelot->dev,
2196 "Timestamp initialization failed\n");
2197 return ret;
2198 }
2199 }
2200
2201 return 0;
2202}
2203EXPORT_SYMBOL(ocelot_init);
2204
2205void ocelot_deinit(struct ocelot *ocelot)
2206{
2207 struct list_head *pos, *tmp;
2208 struct ocelot_port *port;
2209 struct ocelot_skb *entry;
2210 int i;
2211
2212 cancel_delayed_work(&ocelot->stats_work);
2213 destroy_workqueue(ocelot->stats_queue);
2214 mutex_destroy(&ocelot->stats_lock);
2215 ocelot_ace_deinit();
2216
2217 for (i = 0; i < ocelot->num_phys_ports; i++) {
2218 port = ocelot->ports[i];
2219
2220 list_for_each_safe(pos, tmp, &port->skbs) {
2221 entry = list_entry(pos, struct ocelot_skb, head);
2222
2223 list_del(pos);
2224 dev_kfree_skb_any(entry->skb);
2225 kfree(entry);
2226 }
2227 }
2228}
2229EXPORT_SYMBOL(ocelot_deinit);
2230
2231MODULE_LICENSE("Dual MIT/GPL");