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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
7 */
8
9#include <linux/of_device.h>
10#include <linux/of_mdio.h>
11#include <linux/of_net.h>
12#include <linux/mfd/syscon.h>
13#include <linux/regmap.h>
14#include <linux/clk.h>
15#include <linux/pm_runtime.h>
16#include <linux/if_vlan.h>
17#include <linux/reset.h>
18#include <linux/tcp.h>
19#include <linux/interrupt.h>
20#include <linux/pinctrl/devinfo.h>
21#include <linux/phylink.h>
22
23#include "mtk_eth_soc.h"
24
25static int mtk_msg_level = -1;
26module_param_named(msg_level, mtk_msg_level, int, 0);
27MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
28
29#define MTK_ETHTOOL_STAT(x) { #x, \
30 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
31
32/* strings used by ethtool */
33static const struct mtk_ethtool_stats {
34 char str[ETH_GSTRING_LEN];
35 u32 offset;
36} mtk_ethtool_stats[] = {
37 MTK_ETHTOOL_STAT(tx_bytes),
38 MTK_ETHTOOL_STAT(tx_packets),
39 MTK_ETHTOOL_STAT(tx_skip),
40 MTK_ETHTOOL_STAT(tx_collisions),
41 MTK_ETHTOOL_STAT(rx_bytes),
42 MTK_ETHTOOL_STAT(rx_packets),
43 MTK_ETHTOOL_STAT(rx_overflow),
44 MTK_ETHTOOL_STAT(rx_fcs_errors),
45 MTK_ETHTOOL_STAT(rx_short_errors),
46 MTK_ETHTOOL_STAT(rx_long_errors),
47 MTK_ETHTOOL_STAT(rx_checksum_errors),
48 MTK_ETHTOOL_STAT(rx_flow_control_packets),
49};
50
51static const char * const mtk_clks_source_name[] = {
52 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
53 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
54 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
55 "sgmii_ck", "eth2pll",
56};
57
58void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
59{
60 __raw_writel(val, eth->base + reg);
61}
62
63u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
64{
65 return __raw_readl(eth->base + reg);
66}
67
68static int mtk_mdio_busy_wait(struct mtk_eth *eth)
69{
70 unsigned long t_start = jiffies;
71
72 while (1) {
73 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
74 return 0;
75 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
76 break;
77 usleep_range(10, 20);
78 }
79
80 dev_err(eth->dev, "mdio: MDIO timeout\n");
81 return -1;
82}
83
84static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
85 u32 phy_register, u32 write_data)
86{
87 if (mtk_mdio_busy_wait(eth))
88 return -1;
89
90 write_data &= 0xffff;
91
92 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
93 (phy_register << PHY_IAC_REG_SHIFT) |
94 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
95 MTK_PHY_IAC);
96
97 if (mtk_mdio_busy_wait(eth))
98 return -1;
99
100 return 0;
101}
102
103static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
104{
105 u32 d;
106
107 if (mtk_mdio_busy_wait(eth))
108 return 0xffff;
109
110 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
111 (phy_reg << PHY_IAC_REG_SHIFT) |
112 (phy_addr << PHY_IAC_ADDR_SHIFT),
113 MTK_PHY_IAC);
114
115 if (mtk_mdio_busy_wait(eth))
116 return 0xffff;
117
118 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
119
120 return d;
121}
122
123static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
124 int phy_reg, u16 val)
125{
126 struct mtk_eth *eth = bus->priv;
127
128 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
129}
130
131static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
132{
133 struct mtk_eth *eth = bus->priv;
134
135 return _mtk_mdio_read(eth, phy_addr, phy_reg);
136}
137
138static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth,
139 phy_interface_t interface)
140{
141 u32 val;
142
143 /* Check DDR memory type.
144 * Currently TRGMII mode with DDR2 memory is not supported.
145 */
146 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val);
147 if (interface == PHY_INTERFACE_MODE_TRGMII &&
148 val & SYSCFG_DRAM_TYPE_DDR2) {
149 dev_err(eth->dev,
150 "TRGMII mode with DDR2 memory is not supported!\n");
151 return -EOPNOTSUPP;
152 }
153
154 val = (interface == PHY_INTERFACE_MODE_TRGMII) ?
155 ETHSYS_TRGMII_MT7621_DDR_PLL : 0;
156
157 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
158 ETHSYS_TRGMII_MT7621_MASK, val);
159
160 return 0;
161}
162
163static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
164{
165 u32 val;
166 int ret;
167
168 val = (speed == SPEED_1000) ?
169 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
170 mtk_w32(eth, val, INTF_MODE);
171
172 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
173 ETHSYS_TRGMII_CLK_SEL362_5,
174 ETHSYS_TRGMII_CLK_SEL362_5);
175
176 val = (speed == SPEED_1000) ? 250000000 : 500000000;
177 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
178 if (ret)
179 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
180
181 val = (speed == SPEED_1000) ?
182 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
183 mtk_w32(eth, val, TRGMII_RCK_CTRL);
184
185 val = (speed == SPEED_1000) ?
186 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
187 mtk_w32(eth, val, TRGMII_TCK_CTRL);
188}
189
190static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
191 const struct phylink_link_state *state)
192{
193 struct mtk_mac *mac = container_of(config, struct mtk_mac,
194 phylink_config);
195 struct mtk_eth *eth = mac->hw;
196 u32 mcr_cur, mcr_new, sid;
197 int val, ge_mode, err;
198
199 /* MT76x8 has no hardware settings between for the MAC */
200 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
201 mac->interface != state->interface) {
202 /* Setup soc pin functions */
203 switch (state->interface) {
204 case PHY_INTERFACE_MODE_TRGMII:
205 if (mac->id)
206 goto err_phy;
207 if (!MTK_HAS_CAPS(mac->hw->soc->caps,
208 MTK_GMAC1_TRGMII))
209 goto err_phy;
210 /* fall through */
211 case PHY_INTERFACE_MODE_RGMII_TXID:
212 case PHY_INTERFACE_MODE_RGMII_RXID:
213 case PHY_INTERFACE_MODE_RGMII_ID:
214 case PHY_INTERFACE_MODE_RGMII:
215 case PHY_INTERFACE_MODE_MII:
216 case PHY_INTERFACE_MODE_REVMII:
217 case PHY_INTERFACE_MODE_RMII:
218 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) {
219 err = mtk_gmac_rgmii_path_setup(eth, mac->id);
220 if (err)
221 goto init_err;
222 }
223 break;
224 case PHY_INTERFACE_MODE_1000BASEX:
225 case PHY_INTERFACE_MODE_2500BASEX:
226 case PHY_INTERFACE_MODE_SGMII:
227 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
228 err = mtk_gmac_sgmii_path_setup(eth, mac->id);
229 if (err)
230 goto init_err;
231 }
232 break;
233 case PHY_INTERFACE_MODE_GMII:
234 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) {
235 err = mtk_gmac_gephy_path_setup(eth, mac->id);
236 if (err)
237 goto init_err;
238 }
239 break;
240 default:
241 goto err_phy;
242 }
243
244 /* Setup clock for 1st gmac */
245 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII &&
246 !phy_interface_mode_is_8023z(state->interface) &&
247 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) {
248 if (MTK_HAS_CAPS(mac->hw->soc->caps,
249 MTK_TRGMII_MT7621_CLK)) {
250 if (mt7621_gmac0_rgmii_adjust(mac->hw,
251 state->interface))
252 goto err_phy;
253 } else {
254 if (state->interface !=
255 PHY_INTERFACE_MODE_TRGMII)
256 mtk_gmac0_rgmii_adjust(mac->hw,
257 state->speed);
258 }
259 }
260
261 ge_mode = 0;
262 switch (state->interface) {
263 case PHY_INTERFACE_MODE_MII:
264 case PHY_INTERFACE_MODE_GMII:
265 ge_mode = 1;
266 break;
267 case PHY_INTERFACE_MODE_REVMII:
268 ge_mode = 2;
269 break;
270 case PHY_INTERFACE_MODE_RMII:
271 if (mac->id)
272 goto err_phy;
273 ge_mode = 3;
274 break;
275 default:
276 break;
277 }
278
279 /* put the gmac into the right mode */
280 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
281 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
282 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
283 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
284
285 mac->interface = state->interface;
286 }
287
288 /* SGMII */
289 if (state->interface == PHY_INTERFACE_MODE_SGMII ||
290 phy_interface_mode_is_8023z(state->interface)) {
291 /* The path GMAC to SGMII will be enabled once the SGMIISYS is
292 * being setup done.
293 */
294 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
295
296 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
297 SYSCFG0_SGMII_MASK,
298 ~(u32)SYSCFG0_SGMII_MASK);
299
300 /* Decide how GMAC and SGMIISYS be mapped */
301 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
302 0 : mac->id;
303
304 /* Setup SGMIISYS with the determined property */
305 if (state->interface != PHY_INTERFACE_MODE_SGMII)
306 err = mtk_sgmii_setup_mode_force(eth->sgmii, sid,
307 state);
308 else if (phylink_autoneg_inband(mode))
309 err = mtk_sgmii_setup_mode_an(eth->sgmii, sid);
310
311 if (err)
312 goto init_err;
313
314 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
315 SYSCFG0_SGMII_MASK, val);
316 } else if (phylink_autoneg_inband(mode)) {
317 dev_err(eth->dev,
318 "In-band mode not supported in non SGMII mode!\n");
319 return;
320 }
321
322 /* Setup gmac */
323 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
324 mcr_new = mcr_cur;
325 mcr_new &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 |
326 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC |
327 MAC_MCR_FORCE_RX_FC);
328 mcr_new |= MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE |
329 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK;
330
331 switch (state->speed) {
332 case SPEED_2500:
333 case SPEED_1000:
334 mcr_new |= MAC_MCR_SPEED_1000;
335 break;
336 case SPEED_100:
337 mcr_new |= MAC_MCR_SPEED_100;
338 break;
339 }
340 if (state->duplex == DUPLEX_FULL) {
341 mcr_new |= MAC_MCR_FORCE_DPX;
342 if (state->pause & MLO_PAUSE_TX)
343 mcr_new |= MAC_MCR_FORCE_TX_FC;
344 if (state->pause & MLO_PAUSE_RX)
345 mcr_new |= MAC_MCR_FORCE_RX_FC;
346 }
347
348 /* Only update control register when needed! */
349 if (mcr_new != mcr_cur)
350 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
351
352 return;
353
354err_phy:
355 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__,
356 mac->id, phy_modes(state->interface));
357 return;
358
359init_err:
360 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__,
361 mac->id, phy_modes(state->interface), err);
362}
363
364static int mtk_mac_link_state(struct phylink_config *config,
365 struct phylink_link_state *state)
366{
367 struct mtk_mac *mac = container_of(config, struct mtk_mac,
368 phylink_config);
369 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id));
370
371 state->link = (pmsr & MAC_MSR_LINK);
372 state->duplex = (pmsr & MAC_MSR_DPX) >> 1;
373
374 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) {
375 case 0:
376 state->speed = SPEED_10;
377 break;
378 case MAC_MSR_SPEED_100:
379 state->speed = SPEED_100;
380 break;
381 case MAC_MSR_SPEED_1000:
382 state->speed = SPEED_1000;
383 break;
384 default:
385 state->speed = SPEED_UNKNOWN;
386 break;
387 }
388
389 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
390 if (pmsr & MAC_MSR_RX_FC)
391 state->pause |= MLO_PAUSE_RX;
392 if (pmsr & MAC_MSR_TX_FC)
393 state->pause |= MLO_PAUSE_TX;
394
395 return 1;
396}
397
398static void mtk_mac_an_restart(struct phylink_config *config)
399{
400 struct mtk_mac *mac = container_of(config, struct mtk_mac,
401 phylink_config);
402
403 mtk_sgmii_restart_an(mac->hw, mac->id);
404}
405
406static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
407 phy_interface_t interface)
408{
409 struct mtk_mac *mac = container_of(config, struct mtk_mac,
410 phylink_config);
411 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
412
413 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
414 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
415}
416
417static void mtk_mac_link_up(struct phylink_config *config, unsigned int mode,
418 phy_interface_t interface,
419 struct phy_device *phy)
420{
421 struct mtk_mac *mac = container_of(config, struct mtk_mac,
422 phylink_config);
423 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
424
425 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN;
426 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
427}
428
429static void mtk_validate(struct phylink_config *config,
430 unsigned long *supported,
431 struct phylink_link_state *state)
432{
433 struct mtk_mac *mac = container_of(config, struct mtk_mac,
434 phylink_config);
435 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
436
437 if (state->interface != PHY_INTERFACE_MODE_NA &&
438 state->interface != PHY_INTERFACE_MODE_MII &&
439 state->interface != PHY_INTERFACE_MODE_GMII &&
440 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII) &&
441 phy_interface_mode_is_rgmii(state->interface)) &&
442 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) &&
443 !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII) &&
444 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII) &&
445 (state->interface == PHY_INTERFACE_MODE_SGMII ||
446 phy_interface_mode_is_8023z(state->interface)))) {
447 linkmode_zero(supported);
448 return;
449 }
450
451 phylink_set_port_modes(mask);
452 phylink_set(mask, Autoneg);
453
454 switch (state->interface) {
455 case PHY_INTERFACE_MODE_TRGMII:
456 phylink_set(mask, 1000baseT_Full);
457 break;
458 case PHY_INTERFACE_MODE_1000BASEX:
459 case PHY_INTERFACE_MODE_2500BASEX:
460 phylink_set(mask, 1000baseX_Full);
461 phylink_set(mask, 2500baseX_Full);
462 break;
463 case PHY_INTERFACE_MODE_GMII:
464 case PHY_INTERFACE_MODE_RGMII:
465 case PHY_INTERFACE_MODE_RGMII_ID:
466 case PHY_INTERFACE_MODE_RGMII_RXID:
467 case PHY_INTERFACE_MODE_RGMII_TXID:
468 phylink_set(mask, 1000baseT_Half);
469 /* fall through */
470 case PHY_INTERFACE_MODE_SGMII:
471 phylink_set(mask, 1000baseT_Full);
472 phylink_set(mask, 1000baseX_Full);
473 /* fall through */
474 case PHY_INTERFACE_MODE_MII:
475 case PHY_INTERFACE_MODE_RMII:
476 case PHY_INTERFACE_MODE_REVMII:
477 case PHY_INTERFACE_MODE_NA:
478 default:
479 phylink_set(mask, 10baseT_Half);
480 phylink_set(mask, 10baseT_Full);
481 phylink_set(mask, 100baseT_Half);
482 phylink_set(mask, 100baseT_Full);
483 break;
484 }
485
486 if (state->interface == PHY_INTERFACE_MODE_NA) {
487 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) {
488 phylink_set(mask, 1000baseT_Full);
489 phylink_set(mask, 1000baseX_Full);
490 phylink_set(mask, 2500baseX_Full);
491 }
492 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) {
493 phylink_set(mask, 1000baseT_Full);
494 phylink_set(mask, 1000baseT_Half);
495 phylink_set(mask, 1000baseX_Full);
496 }
497 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GEPHY)) {
498 phylink_set(mask, 1000baseT_Full);
499 phylink_set(mask, 1000baseT_Half);
500 }
501 }
502
503 phylink_set(mask, Pause);
504 phylink_set(mask, Asym_Pause);
505
506 linkmode_and(supported, supported, mask);
507 linkmode_and(state->advertising, state->advertising, mask);
508
509 /* We can only operate at 2500BaseX or 1000BaseX. If requested
510 * to advertise both, only report advertising at 2500BaseX.
511 */
512 phylink_helper_basex_speed(state);
513}
514
515static const struct phylink_mac_ops mtk_phylink_ops = {
516 .validate = mtk_validate,
517 .mac_link_state = mtk_mac_link_state,
518 .mac_an_restart = mtk_mac_an_restart,
519 .mac_config = mtk_mac_config,
520 .mac_link_down = mtk_mac_link_down,
521 .mac_link_up = mtk_mac_link_up,
522};
523
524static int mtk_mdio_init(struct mtk_eth *eth)
525{
526 struct device_node *mii_np;
527 int ret;
528
529 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
530 if (!mii_np) {
531 dev_err(eth->dev, "no %s child node found", "mdio-bus");
532 return -ENODEV;
533 }
534
535 if (!of_device_is_available(mii_np)) {
536 ret = -ENODEV;
537 goto err_put_node;
538 }
539
540 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
541 if (!eth->mii_bus) {
542 ret = -ENOMEM;
543 goto err_put_node;
544 }
545
546 eth->mii_bus->name = "mdio";
547 eth->mii_bus->read = mtk_mdio_read;
548 eth->mii_bus->write = mtk_mdio_write;
549 eth->mii_bus->priv = eth;
550 eth->mii_bus->parent = eth->dev;
551
552 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
553 ret = of_mdiobus_register(eth->mii_bus, mii_np);
554
555err_put_node:
556 of_node_put(mii_np);
557 return ret;
558}
559
560static void mtk_mdio_cleanup(struct mtk_eth *eth)
561{
562 if (!eth->mii_bus)
563 return;
564
565 mdiobus_unregister(eth->mii_bus);
566}
567
568static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
569{
570 unsigned long flags;
571 u32 val;
572
573 spin_lock_irqsave(ð->tx_irq_lock, flags);
574 val = mtk_r32(eth, eth->tx_int_mask_reg);
575 mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg);
576 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
577}
578
579static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
580{
581 unsigned long flags;
582 u32 val;
583
584 spin_lock_irqsave(ð->tx_irq_lock, flags);
585 val = mtk_r32(eth, eth->tx_int_mask_reg);
586 mtk_w32(eth, val | mask, eth->tx_int_mask_reg);
587 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
588}
589
590static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
591{
592 unsigned long flags;
593 u32 val;
594
595 spin_lock_irqsave(ð->rx_irq_lock, flags);
596 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
597 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK);
598 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
599}
600
601static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
602{
603 unsigned long flags;
604 u32 val;
605
606 spin_lock_irqsave(ð->rx_irq_lock, flags);
607 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
608 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK);
609 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
610}
611
612static int mtk_set_mac_address(struct net_device *dev, void *p)
613{
614 int ret = eth_mac_addr(dev, p);
615 struct mtk_mac *mac = netdev_priv(dev);
616 struct mtk_eth *eth = mac->hw;
617 const char *macaddr = dev->dev_addr;
618
619 if (ret)
620 return ret;
621
622 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
623 return -EBUSY;
624
625 spin_lock_bh(&mac->hw->page_lock);
626 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
627 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
628 MT7628_SDM_MAC_ADRH);
629 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
630 (macaddr[4] << 8) | macaddr[5],
631 MT7628_SDM_MAC_ADRL);
632 } else {
633 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
634 MTK_GDMA_MAC_ADRH(mac->id));
635 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
636 (macaddr[4] << 8) | macaddr[5],
637 MTK_GDMA_MAC_ADRL(mac->id));
638 }
639 spin_unlock_bh(&mac->hw->page_lock);
640
641 return 0;
642}
643
644void mtk_stats_update_mac(struct mtk_mac *mac)
645{
646 struct mtk_hw_stats *hw_stats = mac->hw_stats;
647 unsigned int base = MTK_GDM1_TX_GBCNT;
648 u64 stats;
649
650 base += hw_stats->reg_offset;
651
652 u64_stats_update_begin(&hw_stats->syncp);
653
654 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
655 stats = mtk_r32(mac->hw, base + 0x04);
656 if (stats)
657 hw_stats->rx_bytes += (stats << 32);
658 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
659 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
660 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
661 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
662 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
663 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
664 hw_stats->rx_flow_control_packets +=
665 mtk_r32(mac->hw, base + 0x24);
666 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
667 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
668 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
669 stats = mtk_r32(mac->hw, base + 0x34);
670 if (stats)
671 hw_stats->tx_bytes += (stats << 32);
672 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
673 u64_stats_update_end(&hw_stats->syncp);
674}
675
676static void mtk_stats_update(struct mtk_eth *eth)
677{
678 int i;
679
680 for (i = 0; i < MTK_MAC_COUNT; i++) {
681 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
682 continue;
683 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) {
684 mtk_stats_update_mac(eth->mac[i]);
685 spin_unlock(ð->mac[i]->hw_stats->stats_lock);
686 }
687 }
688}
689
690static void mtk_get_stats64(struct net_device *dev,
691 struct rtnl_link_stats64 *storage)
692{
693 struct mtk_mac *mac = netdev_priv(dev);
694 struct mtk_hw_stats *hw_stats = mac->hw_stats;
695 unsigned int start;
696
697 if (netif_running(dev) && netif_device_present(dev)) {
698 if (spin_trylock_bh(&hw_stats->stats_lock)) {
699 mtk_stats_update_mac(mac);
700 spin_unlock_bh(&hw_stats->stats_lock);
701 }
702 }
703
704 do {
705 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
706 storage->rx_packets = hw_stats->rx_packets;
707 storage->tx_packets = hw_stats->tx_packets;
708 storage->rx_bytes = hw_stats->rx_bytes;
709 storage->tx_bytes = hw_stats->tx_bytes;
710 storage->collisions = hw_stats->tx_collisions;
711 storage->rx_length_errors = hw_stats->rx_short_errors +
712 hw_stats->rx_long_errors;
713 storage->rx_over_errors = hw_stats->rx_overflow;
714 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
715 storage->rx_errors = hw_stats->rx_checksum_errors;
716 storage->tx_aborted_errors = hw_stats->tx_skip;
717 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
718
719 storage->tx_errors = dev->stats.tx_errors;
720 storage->rx_dropped = dev->stats.rx_dropped;
721 storage->tx_dropped = dev->stats.tx_dropped;
722}
723
724static inline int mtk_max_frag_size(int mtu)
725{
726 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
727 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
728 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
729
730 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
731 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
732}
733
734static inline int mtk_max_buf_size(int frag_size)
735{
736 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
737 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
738
739 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
740
741 return buf_size;
742}
743
744static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
745 struct mtk_rx_dma *dma_rxd)
746{
747 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
748 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
749 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
750 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
751}
752
753/* the qdma core needs scratch memory to be setup */
754static int mtk_init_fq_dma(struct mtk_eth *eth)
755{
756 dma_addr_t phy_ring_tail;
757 int cnt = MTK_DMA_SIZE;
758 dma_addr_t dma_addr;
759 int i;
760
761 eth->scratch_ring = dma_alloc_coherent(eth->dev,
762 cnt * sizeof(struct mtk_tx_dma),
763 ð->phy_scratch_ring,
764 GFP_ATOMIC);
765 if (unlikely(!eth->scratch_ring))
766 return -ENOMEM;
767
768 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
769 GFP_KERNEL);
770 if (unlikely(!eth->scratch_head))
771 return -ENOMEM;
772
773 dma_addr = dma_map_single(eth->dev,
774 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
775 DMA_FROM_DEVICE);
776 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
777 return -ENOMEM;
778
779 phy_ring_tail = eth->phy_scratch_ring +
780 (sizeof(struct mtk_tx_dma) * (cnt - 1));
781
782 for (i = 0; i < cnt; i++) {
783 eth->scratch_ring[i].txd1 =
784 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
785 if (i < cnt - 1)
786 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
787 ((i + 1) * sizeof(struct mtk_tx_dma)));
788 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
789 }
790
791 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
792 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
793 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
794 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
795
796 return 0;
797}
798
799static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
800{
801 void *ret = ring->dma;
802
803 return ret + (desc - ring->phys);
804}
805
806static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
807 struct mtk_tx_dma *txd)
808{
809 int idx = txd - ring->dma;
810
811 return &ring->buf[idx];
812}
813
814static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring,
815 struct mtk_tx_dma *dma)
816{
817 return ring->dma_pdma - ring->dma + dma;
818}
819
820static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma)
821{
822 return ((void *)dma - (void *)ring->dma) / sizeof(*dma);
823}
824
825static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
826{
827 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
828 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
829 dma_unmap_single(eth->dev,
830 dma_unmap_addr(tx_buf, dma_addr0),
831 dma_unmap_len(tx_buf, dma_len0),
832 DMA_TO_DEVICE);
833 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
834 dma_unmap_page(eth->dev,
835 dma_unmap_addr(tx_buf, dma_addr0),
836 dma_unmap_len(tx_buf, dma_len0),
837 DMA_TO_DEVICE);
838 }
839 } else {
840 if (dma_unmap_len(tx_buf, dma_len0)) {
841 dma_unmap_page(eth->dev,
842 dma_unmap_addr(tx_buf, dma_addr0),
843 dma_unmap_len(tx_buf, dma_len0),
844 DMA_TO_DEVICE);
845 }
846
847 if (dma_unmap_len(tx_buf, dma_len1)) {
848 dma_unmap_page(eth->dev,
849 dma_unmap_addr(tx_buf, dma_addr1),
850 dma_unmap_len(tx_buf, dma_len1),
851 DMA_TO_DEVICE);
852 }
853 }
854
855 tx_buf->flags = 0;
856 if (tx_buf->skb &&
857 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
858 dev_kfree_skb_any(tx_buf->skb);
859 tx_buf->skb = NULL;
860}
861
862static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
863 struct mtk_tx_dma *txd, dma_addr_t mapped_addr,
864 size_t size, int idx)
865{
866 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
867 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
868 dma_unmap_len_set(tx_buf, dma_len0, size);
869 } else {
870 if (idx & 1) {
871 txd->txd3 = mapped_addr;
872 txd->txd2 |= TX_DMA_PLEN1(size);
873 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
874 dma_unmap_len_set(tx_buf, dma_len1, size);
875 } else {
876 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
877 txd->txd1 = mapped_addr;
878 txd->txd2 = TX_DMA_PLEN0(size);
879 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
880 dma_unmap_len_set(tx_buf, dma_len0, size);
881 }
882 }
883}
884
885static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
886 int tx_num, struct mtk_tx_ring *ring, bool gso)
887{
888 struct mtk_mac *mac = netdev_priv(dev);
889 struct mtk_eth *eth = mac->hw;
890 struct mtk_tx_dma *itxd, *txd;
891 struct mtk_tx_dma *itxd_pdma, *txd_pdma;
892 struct mtk_tx_buf *itx_buf, *tx_buf;
893 dma_addr_t mapped_addr;
894 unsigned int nr_frags;
895 int i, n_desc = 1;
896 u32 txd4 = 0, fport;
897 int k = 0;
898
899 itxd = ring->next_free;
900 itxd_pdma = qdma_to_pdma(ring, itxd);
901 if (itxd == ring->last_free)
902 return -ENOMEM;
903
904 /* set the forward port */
905 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
906 txd4 |= fport;
907
908 itx_buf = mtk_desc_to_tx_buf(ring, itxd);
909 memset(itx_buf, 0, sizeof(*itx_buf));
910
911 if (gso)
912 txd4 |= TX_DMA_TSO;
913
914 /* TX Checksum offload */
915 if (skb->ip_summed == CHECKSUM_PARTIAL)
916 txd4 |= TX_DMA_CHKSUM;
917
918 /* VLAN header offload */
919 if (skb_vlan_tag_present(skb))
920 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
921
922 mapped_addr = dma_map_single(eth->dev, skb->data,
923 skb_headlen(skb), DMA_TO_DEVICE);
924 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
925 return -ENOMEM;
926
927 WRITE_ONCE(itxd->txd1, mapped_addr);
928 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
929 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
930 MTK_TX_FLAGS_FPORT1;
931 setup_tx_buf(eth, itx_buf, itxd_pdma, mapped_addr, skb_headlen(skb),
932 k++);
933
934 /* TX SG offload */
935 txd = itxd;
936 txd_pdma = qdma_to_pdma(ring, txd);
937 nr_frags = skb_shinfo(skb)->nr_frags;
938
939 for (i = 0; i < nr_frags; i++) {
940 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
941 unsigned int offset = 0;
942 int frag_size = skb_frag_size(frag);
943
944 while (frag_size) {
945 bool last_frag = false;
946 unsigned int frag_map_size;
947 bool new_desc = true;
948
949 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA) ||
950 (i & 0x1)) {
951 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
952 txd_pdma = qdma_to_pdma(ring, txd);
953 if (txd == ring->last_free)
954 goto err_dma;
955
956 n_desc++;
957 } else {
958 new_desc = false;
959 }
960
961
962 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
963 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
964 frag_map_size,
965 DMA_TO_DEVICE);
966 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
967 goto err_dma;
968
969 if (i == nr_frags - 1 &&
970 (frag_size - frag_map_size) == 0)
971 last_frag = true;
972
973 WRITE_ONCE(txd->txd1, mapped_addr);
974 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
975 TX_DMA_PLEN0(frag_map_size) |
976 last_frag * TX_DMA_LS0));
977 WRITE_ONCE(txd->txd4, fport);
978
979 tx_buf = mtk_desc_to_tx_buf(ring, txd);
980 if (new_desc)
981 memset(tx_buf, 0, sizeof(*tx_buf));
982 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
983 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
984 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
985 MTK_TX_FLAGS_FPORT1;
986
987 setup_tx_buf(eth, tx_buf, txd_pdma, mapped_addr,
988 frag_map_size, k++);
989
990 frag_size -= frag_map_size;
991 offset += frag_map_size;
992 }
993 }
994
995 /* store skb to cleanup */
996 itx_buf->skb = skb;
997
998 WRITE_ONCE(itxd->txd4, txd4);
999 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
1000 (!nr_frags * TX_DMA_LS0)));
1001 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1002 if (k & 0x1)
1003 txd_pdma->txd2 |= TX_DMA_LS0;
1004 else
1005 txd_pdma->txd2 |= TX_DMA_LS1;
1006 }
1007
1008 netdev_sent_queue(dev, skb->len);
1009 skb_tx_timestamp(skb);
1010
1011 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1012 atomic_sub(n_desc, &ring->free_count);
1013
1014 /* make sure that all changes to the dma ring are flushed before we
1015 * continue
1016 */
1017 wmb();
1018
1019 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1020 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) ||
1021 !netdev_xmit_more())
1022 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
1023 } else {
1024 int next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd),
1025 ring->dma_size);
1026 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
1027 }
1028
1029 return 0;
1030
1031err_dma:
1032 do {
1033 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
1034
1035 /* unmap dma */
1036 mtk_tx_unmap(eth, tx_buf);
1037
1038 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1039 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
1040 itxd_pdma->txd2 = TX_DMA_DESP2_DEF;
1041
1042 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
1043 itxd_pdma = qdma_to_pdma(ring, itxd);
1044 } while (itxd != txd);
1045
1046 return -ENOMEM;
1047}
1048
1049static inline int mtk_cal_txd_req(struct sk_buff *skb)
1050{
1051 int i, nfrags;
1052 skb_frag_t *frag;
1053
1054 nfrags = 1;
1055 if (skb_is_gso(skb)) {
1056 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1057 frag = &skb_shinfo(skb)->frags[i];
1058 nfrags += DIV_ROUND_UP(skb_frag_size(frag),
1059 MTK_TX_DMA_BUF_LEN);
1060 }
1061 } else {
1062 nfrags += skb_shinfo(skb)->nr_frags;
1063 }
1064
1065 return nfrags;
1066}
1067
1068static int mtk_queue_stopped(struct mtk_eth *eth)
1069{
1070 int i;
1071
1072 for (i = 0; i < MTK_MAC_COUNT; i++) {
1073 if (!eth->netdev[i])
1074 continue;
1075 if (netif_queue_stopped(eth->netdev[i]))
1076 return 1;
1077 }
1078
1079 return 0;
1080}
1081
1082static void mtk_wake_queue(struct mtk_eth *eth)
1083{
1084 int i;
1085
1086 for (i = 0; i < MTK_MAC_COUNT; i++) {
1087 if (!eth->netdev[i])
1088 continue;
1089 netif_wake_queue(eth->netdev[i]);
1090 }
1091}
1092
1093static void mtk_stop_queue(struct mtk_eth *eth)
1094{
1095 int i;
1096
1097 for (i = 0; i < MTK_MAC_COUNT; i++) {
1098 if (!eth->netdev[i])
1099 continue;
1100 netif_stop_queue(eth->netdev[i]);
1101 }
1102}
1103
1104static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
1105{
1106 struct mtk_mac *mac = netdev_priv(dev);
1107 struct mtk_eth *eth = mac->hw;
1108 struct mtk_tx_ring *ring = ð->tx_ring;
1109 struct net_device_stats *stats = &dev->stats;
1110 bool gso = false;
1111 int tx_num;
1112
1113 /* normally we can rely on the stack not calling this more than once,
1114 * however we have 2 queues running on the same ring so we need to lock
1115 * the ring access
1116 */
1117 spin_lock(ð->page_lock);
1118
1119 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1120 goto drop;
1121
1122 tx_num = mtk_cal_txd_req(skb);
1123 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
1124 mtk_stop_queue(eth);
1125 netif_err(eth, tx_queued, dev,
1126 "Tx Ring full when queue awake!\n");
1127 spin_unlock(ð->page_lock);
1128 return NETDEV_TX_BUSY;
1129 }
1130
1131 /* TSO: fill MSS info in tcp checksum field */
1132 if (skb_is_gso(skb)) {
1133 if (skb_cow_head(skb, 0)) {
1134 netif_warn(eth, tx_err, dev,
1135 "GSO expand head fail.\n");
1136 goto drop;
1137 }
1138
1139 if (skb_shinfo(skb)->gso_type &
1140 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1141 gso = true;
1142 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
1143 }
1144 }
1145
1146 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
1147 goto drop;
1148
1149 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
1150 mtk_stop_queue(eth);
1151
1152 spin_unlock(ð->page_lock);
1153
1154 return NETDEV_TX_OK;
1155
1156drop:
1157 spin_unlock(ð->page_lock);
1158 stats->tx_dropped++;
1159 dev_kfree_skb_any(skb);
1160 return NETDEV_TX_OK;
1161}
1162
1163static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
1164{
1165 int i;
1166 struct mtk_rx_ring *ring;
1167 int idx;
1168
1169 if (!eth->hwlro)
1170 return ð->rx_ring[0];
1171
1172 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1173 ring = ð->rx_ring[i];
1174 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
1175 if (ring->dma[idx].rxd2 & RX_DMA_DONE) {
1176 ring->calc_idx_update = true;
1177 return ring;
1178 }
1179 }
1180
1181 return NULL;
1182}
1183
1184static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
1185{
1186 struct mtk_rx_ring *ring;
1187 int i;
1188
1189 if (!eth->hwlro) {
1190 ring = ð->rx_ring[0];
1191 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1192 } else {
1193 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1194 ring = ð->rx_ring[i];
1195 if (ring->calc_idx_update) {
1196 ring->calc_idx_update = false;
1197 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1198 }
1199 }
1200 }
1201}
1202
1203static int mtk_poll_rx(struct napi_struct *napi, int budget,
1204 struct mtk_eth *eth)
1205{
1206 struct mtk_rx_ring *ring;
1207 int idx;
1208 struct sk_buff *skb;
1209 u8 *data, *new_data;
1210 struct mtk_rx_dma *rxd, trxd;
1211 int done = 0;
1212
1213 while (done < budget) {
1214 struct net_device *netdev;
1215 unsigned int pktlen;
1216 dma_addr_t dma_addr;
1217 int mac;
1218
1219 ring = mtk_get_rx_ring(eth);
1220 if (unlikely(!ring))
1221 goto rx_done;
1222
1223 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
1224 rxd = &ring->dma[idx];
1225 data = ring->data[idx];
1226
1227 mtk_rx_get_desc(&trxd, rxd);
1228 if (!(trxd.rxd2 & RX_DMA_DONE))
1229 break;
1230
1231 /* find out which mac the packet come from. values start at 1 */
1232 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
1233 mac = 0;
1234 } else {
1235 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
1236 RX_DMA_FPORT_MASK;
1237 mac--;
1238 }
1239
1240 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
1241 !eth->netdev[mac]))
1242 goto release_desc;
1243
1244 netdev = eth->netdev[mac];
1245
1246 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1247 goto release_desc;
1248
1249 /* alloc new buffer */
1250 new_data = napi_alloc_frag(ring->frag_size);
1251 if (unlikely(!new_data)) {
1252 netdev->stats.rx_dropped++;
1253 goto release_desc;
1254 }
1255 dma_addr = dma_map_single(eth->dev,
1256 new_data + NET_SKB_PAD +
1257 eth->ip_align,
1258 ring->buf_size,
1259 DMA_FROM_DEVICE);
1260 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
1261 skb_free_frag(new_data);
1262 netdev->stats.rx_dropped++;
1263 goto release_desc;
1264 }
1265
1266 /* receive data */
1267 skb = build_skb(data, ring->frag_size);
1268 if (unlikely(!skb)) {
1269 skb_free_frag(new_data);
1270 netdev->stats.rx_dropped++;
1271 goto release_desc;
1272 }
1273 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
1274
1275 dma_unmap_single(eth->dev, trxd.rxd1,
1276 ring->buf_size, DMA_FROM_DEVICE);
1277 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
1278 skb->dev = netdev;
1279 skb_put(skb, pktlen);
1280 if (trxd.rxd4 & eth->rx_dma_l4_valid)
1281 skb->ip_summed = CHECKSUM_UNNECESSARY;
1282 else
1283 skb_checksum_none_assert(skb);
1284 skb->protocol = eth_type_trans(skb, netdev);
1285
1286 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
1287 RX_DMA_VID(trxd.rxd3))
1288 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1289 RX_DMA_VID(trxd.rxd3));
1290 skb_record_rx_queue(skb, 0);
1291 napi_gro_receive(napi, skb);
1292
1293 ring->data[idx] = new_data;
1294 rxd->rxd1 = (unsigned int)dma_addr;
1295
1296release_desc:
1297 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
1298 rxd->rxd2 = RX_DMA_LSO;
1299 else
1300 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
1301
1302 ring->calc_idx = idx;
1303
1304 done++;
1305 }
1306
1307rx_done:
1308 if (done) {
1309 /* make sure that all changes to the dma ring are flushed before
1310 * we continue
1311 */
1312 wmb();
1313 mtk_update_rx_cpu_idx(eth);
1314 }
1315
1316 return done;
1317}
1318
1319static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget,
1320 unsigned int *done, unsigned int *bytes)
1321{
1322 struct mtk_tx_ring *ring = ð->tx_ring;
1323 struct mtk_tx_dma *desc;
1324 struct sk_buff *skb;
1325 struct mtk_tx_buf *tx_buf;
1326 u32 cpu, dma;
1327
1328 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
1329 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
1330
1331 desc = mtk_qdma_phys_to_virt(ring, cpu);
1332
1333 while ((cpu != dma) && budget) {
1334 u32 next_cpu = desc->txd2;
1335 int mac = 0;
1336
1337 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
1338 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
1339 break;
1340
1341 tx_buf = mtk_desc_to_tx_buf(ring, desc);
1342 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
1343 mac = 1;
1344
1345 skb = tx_buf->skb;
1346 if (!skb)
1347 break;
1348
1349 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1350 bytes[mac] += skb->len;
1351 done[mac]++;
1352 budget--;
1353 }
1354 mtk_tx_unmap(eth, tx_buf);
1355
1356 ring->last_free = desc;
1357 atomic_inc(&ring->free_count);
1358
1359 cpu = next_cpu;
1360 }
1361
1362 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
1363
1364 return budget;
1365}
1366
1367static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget,
1368 unsigned int *done, unsigned int *bytes)
1369{
1370 struct mtk_tx_ring *ring = ð->tx_ring;
1371 struct mtk_tx_dma *desc;
1372 struct sk_buff *skb;
1373 struct mtk_tx_buf *tx_buf;
1374 u32 cpu, dma;
1375
1376 cpu = ring->cpu_idx;
1377 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0);
1378
1379 while ((cpu != dma) && budget) {
1380 tx_buf = &ring->buf[cpu];
1381 skb = tx_buf->skb;
1382 if (!skb)
1383 break;
1384
1385 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1386 bytes[0] += skb->len;
1387 done[0]++;
1388 budget--;
1389 }
1390
1391 mtk_tx_unmap(eth, tx_buf);
1392
1393 desc = &ring->dma[cpu];
1394 ring->last_free = desc;
1395 atomic_inc(&ring->free_count);
1396
1397 cpu = NEXT_DESP_IDX(cpu, ring->dma_size);
1398 }
1399
1400 ring->cpu_idx = cpu;
1401
1402 return budget;
1403}
1404
1405static int mtk_poll_tx(struct mtk_eth *eth, int budget)
1406{
1407 struct mtk_tx_ring *ring = ð->tx_ring;
1408 unsigned int done[MTK_MAX_DEVS];
1409 unsigned int bytes[MTK_MAX_DEVS];
1410 int total = 0, i;
1411
1412 memset(done, 0, sizeof(done));
1413 memset(bytes, 0, sizeof(bytes));
1414
1415 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
1416 budget = mtk_poll_tx_qdma(eth, budget, done, bytes);
1417 else
1418 budget = mtk_poll_tx_pdma(eth, budget, done, bytes);
1419
1420 for (i = 0; i < MTK_MAC_COUNT; i++) {
1421 if (!eth->netdev[i] || !done[i])
1422 continue;
1423 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
1424 total += done[i];
1425 }
1426
1427 if (mtk_queue_stopped(eth) &&
1428 (atomic_read(&ring->free_count) > ring->thresh))
1429 mtk_wake_queue(eth);
1430
1431 return total;
1432}
1433
1434static void mtk_handle_status_irq(struct mtk_eth *eth)
1435{
1436 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
1437
1438 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
1439 mtk_stats_update(eth);
1440 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
1441 MTK_INT_STATUS2);
1442 }
1443}
1444
1445static int mtk_napi_tx(struct napi_struct *napi, int budget)
1446{
1447 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
1448 u32 status, mask;
1449 int tx_done = 0;
1450
1451 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
1452 mtk_handle_status_irq(eth);
1453 mtk_w32(eth, MTK_TX_DONE_INT, eth->tx_int_status_reg);
1454 tx_done = mtk_poll_tx(eth, budget);
1455
1456 if (unlikely(netif_msg_intr(eth))) {
1457 status = mtk_r32(eth, eth->tx_int_status_reg);
1458 mask = mtk_r32(eth, eth->tx_int_mask_reg);
1459 dev_info(eth->dev,
1460 "done tx %d, intr 0x%08x/0x%x\n",
1461 tx_done, status, mask);
1462 }
1463
1464 if (tx_done == budget)
1465 return budget;
1466
1467 status = mtk_r32(eth, eth->tx_int_status_reg);
1468 if (status & MTK_TX_DONE_INT)
1469 return budget;
1470
1471 napi_complete(napi);
1472 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1473
1474 return tx_done;
1475}
1476
1477static int mtk_napi_rx(struct napi_struct *napi, int budget)
1478{
1479 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1480 u32 status, mask;
1481 int rx_done = 0;
1482 int remain_budget = budget;
1483
1484 mtk_handle_status_irq(eth);
1485
1486poll_again:
1487 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
1488 rx_done = mtk_poll_rx(napi, remain_budget, eth);
1489
1490 if (unlikely(netif_msg_intr(eth))) {
1491 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1492 mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
1493 dev_info(eth->dev,
1494 "done rx %d, intr 0x%08x/0x%x\n",
1495 rx_done, status, mask);
1496 }
1497 if (rx_done == remain_budget)
1498 return budget;
1499
1500 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1501 if (status & MTK_RX_DONE_INT) {
1502 remain_budget -= rx_done;
1503 goto poll_again;
1504 }
1505 napi_complete(napi);
1506 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1507
1508 return rx_done + budget - remain_budget;
1509}
1510
1511static int mtk_tx_alloc(struct mtk_eth *eth)
1512{
1513 struct mtk_tx_ring *ring = ð->tx_ring;
1514 int i, sz = sizeof(*ring->dma);
1515
1516 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1517 GFP_KERNEL);
1518 if (!ring->buf)
1519 goto no_tx_mem;
1520
1521 ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz,
1522 &ring->phys, GFP_ATOMIC);
1523 if (!ring->dma)
1524 goto no_tx_mem;
1525
1526 for (i = 0; i < MTK_DMA_SIZE; i++) {
1527 int next = (i + 1) % MTK_DMA_SIZE;
1528 u32 next_ptr = ring->phys + next * sz;
1529
1530 ring->dma[i].txd2 = next_ptr;
1531 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1532 }
1533
1534 /* On MT7688 (PDMA only) this driver uses the ring->dma structs
1535 * only as the framework. The real HW descriptors are the PDMA
1536 * descriptors in ring->dma_pdma.
1537 */
1538 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1539 ring->dma_pdma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz,
1540 &ring->phys_pdma,
1541 GFP_ATOMIC);
1542 if (!ring->dma_pdma)
1543 goto no_tx_mem;
1544
1545 for (i = 0; i < MTK_DMA_SIZE; i++) {
1546 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF;
1547 ring->dma_pdma[i].txd4 = 0;
1548 }
1549 }
1550
1551 ring->dma_size = MTK_DMA_SIZE;
1552 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1553 ring->next_free = &ring->dma[0];
1554 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
1555 ring->thresh = MAX_SKB_FRAGS;
1556
1557 /* make sure that all changes to the dma ring are flushed before we
1558 * continue
1559 */
1560 wmb();
1561
1562 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1563 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1564 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1565 mtk_w32(eth,
1566 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1567 MTK_QTX_CRX_PTR);
1568 mtk_w32(eth,
1569 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1570 MTK_QTX_DRX_PTR);
1571 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES,
1572 MTK_QTX_CFG(0));
1573 } else {
1574 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
1575 mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0);
1576 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);
1577 mtk_w32(eth, MT7628_PST_DTX_IDX0, MTK_PDMA_RST_IDX);
1578 }
1579
1580 return 0;
1581
1582no_tx_mem:
1583 return -ENOMEM;
1584}
1585
1586static void mtk_tx_clean(struct mtk_eth *eth)
1587{
1588 struct mtk_tx_ring *ring = ð->tx_ring;
1589 int i;
1590
1591 if (ring->buf) {
1592 for (i = 0; i < MTK_DMA_SIZE; i++)
1593 mtk_tx_unmap(eth, &ring->buf[i]);
1594 kfree(ring->buf);
1595 ring->buf = NULL;
1596 }
1597
1598 if (ring->dma) {
1599 dma_free_coherent(eth->dev,
1600 MTK_DMA_SIZE * sizeof(*ring->dma),
1601 ring->dma,
1602 ring->phys);
1603 ring->dma = NULL;
1604 }
1605
1606 if (ring->dma_pdma) {
1607 dma_free_coherent(eth->dev,
1608 MTK_DMA_SIZE * sizeof(*ring->dma_pdma),
1609 ring->dma_pdma,
1610 ring->phys_pdma);
1611 ring->dma_pdma = NULL;
1612 }
1613}
1614
1615static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
1616{
1617 struct mtk_rx_ring *ring;
1618 int rx_data_len, rx_dma_size;
1619 int i;
1620 u32 offset = 0;
1621
1622 if (rx_flag == MTK_RX_FLAGS_QDMA) {
1623 if (ring_no)
1624 return -EINVAL;
1625 ring = ð->rx_ring_qdma;
1626 offset = 0x1000;
1627 } else {
1628 ring = ð->rx_ring[ring_no];
1629 }
1630
1631 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
1632 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
1633 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
1634 } else {
1635 rx_data_len = ETH_DATA_LEN;
1636 rx_dma_size = MTK_DMA_SIZE;
1637 }
1638
1639 ring->frag_size = mtk_max_frag_size(rx_data_len);
1640 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1641 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
1642 GFP_KERNEL);
1643 if (!ring->data)
1644 return -ENOMEM;
1645
1646 for (i = 0; i < rx_dma_size; i++) {
1647 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1648 if (!ring->data[i])
1649 return -ENOMEM;
1650 }
1651
1652 ring->dma = dma_alloc_coherent(eth->dev,
1653 rx_dma_size * sizeof(*ring->dma),
1654 &ring->phys, GFP_ATOMIC);
1655 if (!ring->dma)
1656 return -ENOMEM;
1657
1658 for (i = 0; i < rx_dma_size; i++) {
1659 dma_addr_t dma_addr = dma_map_single(eth->dev,
1660 ring->data[i] + NET_SKB_PAD + eth->ip_align,
1661 ring->buf_size,
1662 DMA_FROM_DEVICE);
1663 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1664 return -ENOMEM;
1665 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1666
1667 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
1668 ring->dma[i].rxd2 = RX_DMA_LSO;
1669 else
1670 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1671 }
1672 ring->dma_size = rx_dma_size;
1673 ring->calc_idx_update = false;
1674 ring->calc_idx = rx_dma_size - 1;
1675 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no);
1676 /* make sure that all changes to the dma ring are flushed before we
1677 * continue
1678 */
1679 wmb();
1680
1681 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset);
1682 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset);
1683 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset);
1684 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset);
1685
1686 return 0;
1687}
1688
1689static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
1690{
1691 int i;
1692
1693 if (ring->data && ring->dma) {
1694 for (i = 0; i < ring->dma_size; i++) {
1695 if (!ring->data[i])
1696 continue;
1697 if (!ring->dma[i].rxd1)
1698 continue;
1699 dma_unmap_single(eth->dev,
1700 ring->dma[i].rxd1,
1701 ring->buf_size,
1702 DMA_FROM_DEVICE);
1703 skb_free_frag(ring->data[i]);
1704 }
1705 kfree(ring->data);
1706 ring->data = NULL;
1707 }
1708
1709 if (ring->dma) {
1710 dma_free_coherent(eth->dev,
1711 ring->dma_size * sizeof(*ring->dma),
1712 ring->dma,
1713 ring->phys);
1714 ring->dma = NULL;
1715 }
1716}
1717
1718static int mtk_hwlro_rx_init(struct mtk_eth *eth)
1719{
1720 int i;
1721 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
1722 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
1723
1724 /* set LRO rings to auto-learn modes */
1725 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
1726
1727 /* validate LRO ring */
1728 ring_ctrl_dw2 |= MTK_RING_VLD;
1729
1730 /* set AGE timer (unit: 20us) */
1731 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
1732 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
1733
1734 /* set max AGG timer (unit: 20us) */
1735 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
1736
1737 /* set max LRO AGG count */
1738 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
1739 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
1740
1741 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1742 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
1743 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
1744 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
1745 }
1746
1747 /* IPv4 checksum update enable */
1748 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
1749
1750 /* switch priority comparison to packet count mode */
1751 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
1752
1753 /* bandwidth threshold setting */
1754 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
1755
1756 /* auto-learn score delta setting */
1757 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
1758
1759 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
1760 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
1761 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
1762
1763 /* set HW LRO mode & the max aggregation count for rx packets */
1764 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
1765
1766 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
1767 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
1768
1769 /* enable HW LRO */
1770 lro_ctrl_dw0 |= MTK_LRO_EN;
1771
1772 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
1773 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
1774
1775 return 0;
1776}
1777
1778static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
1779{
1780 int i;
1781 u32 val;
1782
1783 /* relinquish lro rings, flush aggregated packets */
1784 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
1785
1786 /* wait for relinquishments done */
1787 for (i = 0; i < 10; i++) {
1788 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
1789 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
1790 msleep(20);
1791 continue;
1792 }
1793 break;
1794 }
1795
1796 /* invalidate lro rings */
1797 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1798 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
1799
1800 /* disable HW LRO */
1801 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
1802}
1803
1804static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
1805{
1806 u32 reg_val;
1807
1808 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1809
1810 /* invalidate the IP setting */
1811 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1812
1813 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
1814
1815 /* validate the IP setting */
1816 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1817}
1818
1819static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
1820{
1821 u32 reg_val;
1822
1823 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1824
1825 /* invalidate the IP setting */
1826 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1827
1828 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
1829}
1830
1831static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
1832{
1833 int cnt = 0;
1834 int i;
1835
1836 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1837 if (mac->hwlro_ip[i])
1838 cnt++;
1839 }
1840
1841 return cnt;
1842}
1843
1844static int mtk_hwlro_add_ipaddr(struct net_device *dev,
1845 struct ethtool_rxnfc *cmd)
1846{
1847 struct ethtool_rx_flow_spec *fsp =
1848 (struct ethtool_rx_flow_spec *)&cmd->fs;
1849 struct mtk_mac *mac = netdev_priv(dev);
1850 struct mtk_eth *eth = mac->hw;
1851 int hwlro_idx;
1852
1853 if ((fsp->flow_type != TCP_V4_FLOW) ||
1854 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
1855 (fsp->location > 1))
1856 return -EINVAL;
1857
1858 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
1859 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1860
1861 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1862
1863 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
1864
1865 return 0;
1866}
1867
1868static int mtk_hwlro_del_ipaddr(struct net_device *dev,
1869 struct ethtool_rxnfc *cmd)
1870{
1871 struct ethtool_rx_flow_spec *fsp =
1872 (struct ethtool_rx_flow_spec *)&cmd->fs;
1873 struct mtk_mac *mac = netdev_priv(dev);
1874 struct mtk_eth *eth = mac->hw;
1875 int hwlro_idx;
1876
1877 if (fsp->location > 1)
1878 return -EINVAL;
1879
1880 mac->hwlro_ip[fsp->location] = 0;
1881 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1882
1883 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1884
1885 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1886
1887 return 0;
1888}
1889
1890static void mtk_hwlro_netdev_disable(struct net_device *dev)
1891{
1892 struct mtk_mac *mac = netdev_priv(dev);
1893 struct mtk_eth *eth = mac->hw;
1894 int i, hwlro_idx;
1895
1896 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1897 mac->hwlro_ip[i] = 0;
1898 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
1899
1900 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1901 }
1902
1903 mac->hwlro_ip_cnt = 0;
1904}
1905
1906static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
1907 struct ethtool_rxnfc *cmd)
1908{
1909 struct mtk_mac *mac = netdev_priv(dev);
1910 struct ethtool_rx_flow_spec *fsp =
1911 (struct ethtool_rx_flow_spec *)&cmd->fs;
1912
1913 /* only tcp dst ipv4 is meaningful, others are meaningless */
1914 fsp->flow_type = TCP_V4_FLOW;
1915 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
1916 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
1917
1918 fsp->h_u.tcp_ip4_spec.ip4src = 0;
1919 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
1920 fsp->h_u.tcp_ip4_spec.psrc = 0;
1921 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
1922 fsp->h_u.tcp_ip4_spec.pdst = 0;
1923 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
1924 fsp->h_u.tcp_ip4_spec.tos = 0;
1925 fsp->m_u.tcp_ip4_spec.tos = 0xff;
1926
1927 return 0;
1928}
1929
1930static int mtk_hwlro_get_fdir_all(struct net_device *dev,
1931 struct ethtool_rxnfc *cmd,
1932 u32 *rule_locs)
1933{
1934 struct mtk_mac *mac = netdev_priv(dev);
1935 int cnt = 0;
1936 int i;
1937
1938 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1939 if (mac->hwlro_ip[i]) {
1940 rule_locs[cnt] = i;
1941 cnt++;
1942 }
1943 }
1944
1945 cmd->rule_cnt = cnt;
1946
1947 return 0;
1948}
1949
1950static netdev_features_t mtk_fix_features(struct net_device *dev,
1951 netdev_features_t features)
1952{
1953 if (!(features & NETIF_F_LRO)) {
1954 struct mtk_mac *mac = netdev_priv(dev);
1955 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1956
1957 if (ip_cnt) {
1958 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
1959
1960 features |= NETIF_F_LRO;
1961 }
1962 }
1963
1964 return features;
1965}
1966
1967static int mtk_set_features(struct net_device *dev, netdev_features_t features)
1968{
1969 int err = 0;
1970
1971 if (!((dev->features ^ features) & NETIF_F_LRO))
1972 return 0;
1973
1974 if (!(features & NETIF_F_LRO))
1975 mtk_hwlro_netdev_disable(dev);
1976
1977 return err;
1978}
1979
1980/* wait for DMA to finish whatever it is doing before we start using it again */
1981static int mtk_dma_busy_wait(struct mtk_eth *eth)
1982{
1983 unsigned long t_start = jiffies;
1984
1985 while (1) {
1986 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1987 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1988 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1989 return 0;
1990 } else {
1991 if (!(mtk_r32(eth, MTK_PDMA_GLO_CFG) &
1992 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1993 return 0;
1994 }
1995
1996 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1997 break;
1998 }
1999
2000 dev_err(eth->dev, "DMA init timeout\n");
2001 return -1;
2002}
2003
2004static int mtk_dma_init(struct mtk_eth *eth)
2005{
2006 int err;
2007 u32 i;
2008
2009 if (mtk_dma_busy_wait(eth))
2010 return -EBUSY;
2011
2012 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2013 /* QDMA needs scratch memory for internal reordering of the
2014 * descriptors
2015 */
2016 err = mtk_init_fq_dma(eth);
2017 if (err)
2018 return err;
2019 }
2020
2021 err = mtk_tx_alloc(eth);
2022 if (err)
2023 return err;
2024
2025 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2026 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
2027 if (err)
2028 return err;
2029 }
2030
2031 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
2032 if (err)
2033 return err;
2034
2035 if (eth->hwlro) {
2036 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
2037 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
2038 if (err)
2039 return err;
2040 }
2041 err = mtk_hwlro_rx_init(eth);
2042 if (err)
2043 return err;
2044 }
2045
2046 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2047 /* Enable random early drop and set drop threshold
2048 * automatically
2049 */
2050 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN |
2051 FC_THRES_MIN, MTK_QDMA_FC_THRES);
2052 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
2053 }
2054
2055 return 0;
2056}
2057
2058static void mtk_dma_free(struct mtk_eth *eth)
2059{
2060 int i;
2061
2062 for (i = 0; i < MTK_MAC_COUNT; i++)
2063 if (eth->netdev[i])
2064 netdev_reset_queue(eth->netdev[i]);
2065 if (eth->scratch_ring) {
2066 dma_free_coherent(eth->dev,
2067 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
2068 eth->scratch_ring,
2069 eth->phy_scratch_ring);
2070 eth->scratch_ring = NULL;
2071 eth->phy_scratch_ring = 0;
2072 }
2073 mtk_tx_clean(eth);
2074 mtk_rx_clean(eth, ð->rx_ring[0]);
2075 mtk_rx_clean(eth, ð->rx_ring_qdma);
2076
2077 if (eth->hwlro) {
2078 mtk_hwlro_rx_uninit(eth);
2079 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
2080 mtk_rx_clean(eth, ð->rx_ring[i]);
2081 }
2082
2083 kfree(eth->scratch_head);
2084}
2085
2086static void mtk_tx_timeout(struct net_device *dev)
2087{
2088 struct mtk_mac *mac = netdev_priv(dev);
2089 struct mtk_eth *eth = mac->hw;
2090
2091 eth->netdev[mac->id]->stats.tx_errors++;
2092 netif_err(eth, tx_err, dev,
2093 "transmit timed out\n");
2094 schedule_work(ð->pending_work);
2095}
2096
2097static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
2098{
2099 struct mtk_eth *eth = _eth;
2100
2101 if (likely(napi_schedule_prep(ð->rx_napi))) {
2102 __napi_schedule(ð->rx_napi);
2103 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
2104 }
2105
2106 return IRQ_HANDLED;
2107}
2108
2109static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
2110{
2111 struct mtk_eth *eth = _eth;
2112
2113 if (likely(napi_schedule_prep(ð->tx_napi))) {
2114 __napi_schedule(ð->tx_napi);
2115 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
2116 }
2117
2118 return IRQ_HANDLED;
2119}
2120
2121static irqreturn_t mtk_handle_irq(int irq, void *_eth)
2122{
2123 struct mtk_eth *eth = _eth;
2124
2125 if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) {
2126 if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT)
2127 mtk_handle_irq_rx(irq, _eth);
2128 }
2129 if (mtk_r32(eth, eth->tx_int_mask_reg) & MTK_TX_DONE_INT) {
2130 if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT)
2131 mtk_handle_irq_tx(irq, _eth);
2132 }
2133
2134 return IRQ_HANDLED;
2135}
2136
2137#ifdef CONFIG_NET_POLL_CONTROLLER
2138static void mtk_poll_controller(struct net_device *dev)
2139{
2140 struct mtk_mac *mac = netdev_priv(dev);
2141 struct mtk_eth *eth = mac->hw;
2142
2143 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
2144 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
2145 mtk_handle_irq_rx(eth->irq[2], dev);
2146 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
2147 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
2148}
2149#endif
2150
2151static int mtk_start_dma(struct mtk_eth *eth)
2152{
2153 u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;
2154 int err;
2155
2156 err = mtk_dma_init(eth);
2157 if (err) {
2158 mtk_dma_free(eth);
2159 return err;
2160 }
2161
2162 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2163 mtk_w32(eth,
2164 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
2165 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO |
2166 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
2167 MTK_RX_BT_32DWORDS,
2168 MTK_QDMA_GLO_CFG);
2169
2170 mtk_w32(eth,
2171 MTK_RX_DMA_EN | rx_2b_offset |
2172 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
2173 MTK_PDMA_GLO_CFG);
2174 } else {
2175 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN |
2176 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS,
2177 MTK_PDMA_GLO_CFG);
2178 }
2179
2180 return 0;
2181}
2182
2183static int mtk_open(struct net_device *dev)
2184{
2185 struct mtk_mac *mac = netdev_priv(dev);
2186 struct mtk_eth *eth = mac->hw;
2187 int err;
2188
2189 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
2190 if (err) {
2191 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
2192 err);
2193 return err;
2194 }
2195
2196 /* we run 2 netdevs on the same dma ring so we only bring it up once */
2197 if (!refcount_read(ð->dma_refcnt)) {
2198 int err = mtk_start_dma(eth);
2199
2200 if (err)
2201 return err;
2202
2203 napi_enable(ð->tx_napi);
2204 napi_enable(ð->rx_napi);
2205 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
2206 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
2207 refcount_set(ð->dma_refcnt, 1);
2208 }
2209 else
2210 refcount_inc(ð->dma_refcnt);
2211
2212 phylink_start(mac->phylink);
2213 netif_start_queue(dev);
2214 return 0;
2215}
2216
2217static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
2218{
2219 u32 val;
2220 int i;
2221
2222 /* stop the dma engine */
2223 spin_lock_bh(ð->page_lock);
2224 val = mtk_r32(eth, glo_cfg);
2225 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
2226 glo_cfg);
2227 spin_unlock_bh(ð->page_lock);
2228
2229 /* wait for dma stop */
2230 for (i = 0; i < 10; i++) {
2231 val = mtk_r32(eth, glo_cfg);
2232 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
2233 msleep(20);
2234 continue;
2235 }
2236 break;
2237 }
2238}
2239
2240static int mtk_stop(struct net_device *dev)
2241{
2242 struct mtk_mac *mac = netdev_priv(dev);
2243 struct mtk_eth *eth = mac->hw;
2244
2245 phylink_stop(mac->phylink);
2246
2247 netif_tx_disable(dev);
2248
2249 phylink_disconnect_phy(mac->phylink);
2250
2251 /* only shutdown DMA if this is the last user */
2252 if (!refcount_dec_and_test(ð->dma_refcnt))
2253 return 0;
2254
2255 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
2256 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
2257 napi_disable(ð->tx_napi);
2258 napi_disable(ð->rx_napi);
2259
2260 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2261 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
2262 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG);
2263
2264 mtk_dma_free(eth);
2265
2266 return 0;
2267}
2268
2269static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
2270{
2271 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
2272 reset_bits,
2273 reset_bits);
2274
2275 usleep_range(1000, 1100);
2276 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
2277 reset_bits,
2278 ~reset_bits);
2279 mdelay(10);
2280}
2281
2282static void mtk_clk_disable(struct mtk_eth *eth)
2283{
2284 int clk;
2285
2286 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)
2287 clk_disable_unprepare(eth->clks[clk]);
2288}
2289
2290static int mtk_clk_enable(struct mtk_eth *eth)
2291{
2292 int clk, ret;
2293
2294 for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
2295 ret = clk_prepare_enable(eth->clks[clk]);
2296 if (ret)
2297 goto err_disable_clks;
2298 }
2299
2300 return 0;
2301
2302err_disable_clks:
2303 while (--clk >= 0)
2304 clk_disable_unprepare(eth->clks[clk]);
2305
2306 return ret;
2307}
2308
2309static int mtk_hw_init(struct mtk_eth *eth)
2310{
2311 int i, val, ret;
2312
2313 if (test_and_set_bit(MTK_HW_INIT, ð->state))
2314 return 0;
2315
2316 pm_runtime_enable(eth->dev);
2317 pm_runtime_get_sync(eth->dev);
2318
2319 ret = mtk_clk_enable(eth);
2320 if (ret)
2321 goto err_disable_pm;
2322
2323 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
2324 ret = device_reset(eth->dev);
2325 if (ret) {
2326 dev_err(eth->dev, "MAC reset failed!\n");
2327 goto err_disable_pm;
2328 }
2329
2330 /* enable interrupt delay for RX */
2331 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
2332
2333 /* disable delay and normal interrupt */
2334 mtk_tx_irq_disable(eth, ~0);
2335 mtk_rx_irq_disable(eth, ~0);
2336
2337 return 0;
2338 }
2339
2340 /* Non-MT7628 handling... */
2341 ethsys_reset(eth, RSTCTRL_FE);
2342 ethsys_reset(eth, RSTCTRL_PPE);
2343
2344 if (eth->pctl) {
2345 /* Set GE2 driving and slew rate */
2346 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
2347
2348 /* set GE2 TDSEL */
2349 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
2350
2351 /* set GE2 TUNE */
2352 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
2353 }
2354
2355 /* Set linkdown as the default for each GMAC. Its own MCR would be set
2356 * up with the more appropriate value when mtk_mac_config call is being
2357 * invoked.
2358 */
2359 for (i = 0; i < MTK_MAC_COUNT; i++)
2360 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
2361
2362 /* Indicates CDM to parse the MTK special tag from CPU
2363 * which also is working out for untag packets.
2364 */
2365 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
2366 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
2367
2368 /* Enable RX VLan Offloading */
2369 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
2370
2371 /* enable interrupt delay for RX */
2372 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
2373
2374 /* disable delay and normal interrupt */
2375 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
2376 mtk_tx_irq_disable(eth, ~0);
2377 mtk_rx_irq_disable(eth, ~0);
2378 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
2379 mtk_w32(eth, 0, MTK_RST_GL);
2380
2381 /* FE int grouping */
2382 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
2383 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
2384 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
2385 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
2386 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
2387
2388 for (i = 0; i < MTK_MAC_COUNT; i++) {
2389 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
2390
2391 /* setup the forward port to send frame to PDMA */
2392 val &= ~0xffff;
2393
2394 /* Enable RX checksum */
2395 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
2396
2397 /* setup the mac dma */
2398 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
2399 }
2400
2401 return 0;
2402
2403err_disable_pm:
2404 pm_runtime_put_sync(eth->dev);
2405 pm_runtime_disable(eth->dev);
2406
2407 return ret;
2408}
2409
2410static int mtk_hw_deinit(struct mtk_eth *eth)
2411{
2412 if (!test_and_clear_bit(MTK_HW_INIT, ð->state))
2413 return 0;
2414
2415 mtk_clk_disable(eth);
2416
2417 pm_runtime_put_sync(eth->dev);
2418 pm_runtime_disable(eth->dev);
2419
2420 return 0;
2421}
2422
2423static int __init mtk_init(struct net_device *dev)
2424{
2425 struct mtk_mac *mac = netdev_priv(dev);
2426 struct mtk_eth *eth = mac->hw;
2427 const char *mac_addr;
2428
2429 mac_addr = of_get_mac_address(mac->of_node);
2430 if (!IS_ERR(mac_addr))
2431 ether_addr_copy(dev->dev_addr, mac_addr);
2432
2433 /* If the mac address is invalid, use random mac address */
2434 if (!is_valid_ether_addr(dev->dev_addr)) {
2435 eth_hw_addr_random(dev);
2436 dev_err(eth->dev, "generated random MAC address %pM\n",
2437 dev->dev_addr);
2438 }
2439
2440 return 0;
2441}
2442
2443static void mtk_uninit(struct net_device *dev)
2444{
2445 struct mtk_mac *mac = netdev_priv(dev);
2446 struct mtk_eth *eth = mac->hw;
2447
2448 phylink_disconnect_phy(mac->phylink);
2449 mtk_tx_irq_disable(eth, ~0);
2450 mtk_rx_irq_disable(eth, ~0);
2451}
2452
2453static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2454{
2455 struct mtk_mac *mac = netdev_priv(dev);
2456
2457 switch (cmd) {
2458 case SIOCGMIIPHY:
2459 case SIOCGMIIREG:
2460 case SIOCSMIIREG:
2461 return phylink_mii_ioctl(mac->phylink, ifr, cmd);
2462 default:
2463 break;
2464 }
2465
2466 return -EOPNOTSUPP;
2467}
2468
2469static void mtk_pending_work(struct work_struct *work)
2470{
2471 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
2472 int err, i;
2473 unsigned long restart = 0;
2474
2475 rtnl_lock();
2476
2477 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
2478
2479 while (test_and_set_bit_lock(MTK_RESETTING, ð->state))
2480 cpu_relax();
2481
2482 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__);
2483 /* stop all devices to make sure that dma is properly shut down */
2484 for (i = 0; i < MTK_MAC_COUNT; i++) {
2485 if (!eth->netdev[i])
2486 continue;
2487 mtk_stop(eth->netdev[i]);
2488 __set_bit(i, &restart);
2489 }
2490 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
2491
2492 /* restart underlying hardware such as power, clock, pin mux
2493 * and the connected phy
2494 */
2495 mtk_hw_deinit(eth);
2496
2497 if (eth->dev->pins)
2498 pinctrl_select_state(eth->dev->pins->p,
2499 eth->dev->pins->default_state);
2500 mtk_hw_init(eth);
2501
2502 /* restart DMA and enable IRQs */
2503 for (i = 0; i < MTK_MAC_COUNT; i++) {
2504 if (!test_bit(i, &restart))
2505 continue;
2506 err = mtk_open(eth->netdev[i]);
2507 if (err) {
2508 netif_alert(eth, ifup, eth->netdev[i],
2509 "Driver up/down cycle failed, closing device.\n");
2510 dev_close(eth->netdev[i]);
2511 }
2512 }
2513
2514 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
2515
2516 clear_bit_unlock(MTK_RESETTING, ð->state);
2517
2518 rtnl_unlock();
2519}
2520
2521static int mtk_free_dev(struct mtk_eth *eth)
2522{
2523 int i;
2524
2525 for (i = 0; i < MTK_MAC_COUNT; i++) {
2526 if (!eth->netdev[i])
2527 continue;
2528 free_netdev(eth->netdev[i]);
2529 }
2530
2531 return 0;
2532}
2533
2534static int mtk_unreg_dev(struct mtk_eth *eth)
2535{
2536 int i;
2537
2538 for (i = 0; i < MTK_MAC_COUNT; i++) {
2539 if (!eth->netdev[i])
2540 continue;
2541 unregister_netdev(eth->netdev[i]);
2542 }
2543
2544 return 0;
2545}
2546
2547static int mtk_cleanup(struct mtk_eth *eth)
2548{
2549 mtk_unreg_dev(eth);
2550 mtk_free_dev(eth);
2551 cancel_work_sync(ð->pending_work);
2552
2553 return 0;
2554}
2555
2556static int mtk_get_link_ksettings(struct net_device *ndev,
2557 struct ethtool_link_ksettings *cmd)
2558{
2559 struct mtk_mac *mac = netdev_priv(ndev);
2560
2561 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2562 return -EBUSY;
2563
2564 return phylink_ethtool_ksettings_get(mac->phylink, cmd);
2565}
2566
2567static int mtk_set_link_ksettings(struct net_device *ndev,
2568 const struct ethtool_link_ksettings *cmd)
2569{
2570 struct mtk_mac *mac = netdev_priv(ndev);
2571
2572 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2573 return -EBUSY;
2574
2575 return phylink_ethtool_ksettings_set(mac->phylink, cmd);
2576}
2577
2578static void mtk_get_drvinfo(struct net_device *dev,
2579 struct ethtool_drvinfo *info)
2580{
2581 struct mtk_mac *mac = netdev_priv(dev);
2582
2583 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
2584 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
2585 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
2586}
2587
2588static u32 mtk_get_msglevel(struct net_device *dev)
2589{
2590 struct mtk_mac *mac = netdev_priv(dev);
2591
2592 return mac->hw->msg_enable;
2593}
2594
2595static void mtk_set_msglevel(struct net_device *dev, u32 value)
2596{
2597 struct mtk_mac *mac = netdev_priv(dev);
2598
2599 mac->hw->msg_enable = value;
2600}
2601
2602static int mtk_nway_reset(struct net_device *dev)
2603{
2604 struct mtk_mac *mac = netdev_priv(dev);
2605
2606 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2607 return -EBUSY;
2608
2609 if (!mac->phylink)
2610 return -ENOTSUPP;
2611
2612 return phylink_ethtool_nway_reset(mac->phylink);
2613}
2614
2615static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2616{
2617 int i;
2618
2619 switch (stringset) {
2620 case ETH_SS_STATS:
2621 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
2622 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
2623 data += ETH_GSTRING_LEN;
2624 }
2625 break;
2626 }
2627}
2628
2629static int mtk_get_sset_count(struct net_device *dev, int sset)
2630{
2631 switch (sset) {
2632 case ETH_SS_STATS:
2633 return ARRAY_SIZE(mtk_ethtool_stats);
2634 default:
2635 return -EOPNOTSUPP;
2636 }
2637}
2638
2639static void mtk_get_ethtool_stats(struct net_device *dev,
2640 struct ethtool_stats *stats, u64 *data)
2641{
2642 struct mtk_mac *mac = netdev_priv(dev);
2643 struct mtk_hw_stats *hwstats = mac->hw_stats;
2644 u64 *data_src, *data_dst;
2645 unsigned int start;
2646 int i;
2647
2648 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2649 return;
2650
2651 if (netif_running(dev) && netif_device_present(dev)) {
2652 if (spin_trylock_bh(&hwstats->stats_lock)) {
2653 mtk_stats_update_mac(mac);
2654 spin_unlock_bh(&hwstats->stats_lock);
2655 }
2656 }
2657
2658 data_src = (u64 *)hwstats;
2659
2660 do {
2661 data_dst = data;
2662 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
2663
2664 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
2665 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
2666 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
2667}
2668
2669static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2670 u32 *rule_locs)
2671{
2672 int ret = -EOPNOTSUPP;
2673
2674 switch (cmd->cmd) {
2675 case ETHTOOL_GRXRINGS:
2676 if (dev->hw_features & NETIF_F_LRO) {
2677 cmd->data = MTK_MAX_RX_RING_NUM;
2678 ret = 0;
2679 }
2680 break;
2681 case ETHTOOL_GRXCLSRLCNT:
2682 if (dev->hw_features & NETIF_F_LRO) {
2683 struct mtk_mac *mac = netdev_priv(dev);
2684
2685 cmd->rule_cnt = mac->hwlro_ip_cnt;
2686 ret = 0;
2687 }
2688 break;
2689 case ETHTOOL_GRXCLSRULE:
2690 if (dev->hw_features & NETIF_F_LRO)
2691 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
2692 break;
2693 case ETHTOOL_GRXCLSRLALL:
2694 if (dev->hw_features & NETIF_F_LRO)
2695 ret = mtk_hwlro_get_fdir_all(dev, cmd,
2696 rule_locs);
2697 break;
2698 default:
2699 break;
2700 }
2701
2702 return ret;
2703}
2704
2705static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2706{
2707 int ret = -EOPNOTSUPP;
2708
2709 switch (cmd->cmd) {
2710 case ETHTOOL_SRXCLSRLINS:
2711 if (dev->hw_features & NETIF_F_LRO)
2712 ret = mtk_hwlro_add_ipaddr(dev, cmd);
2713 break;
2714 case ETHTOOL_SRXCLSRLDEL:
2715 if (dev->hw_features & NETIF_F_LRO)
2716 ret = mtk_hwlro_del_ipaddr(dev, cmd);
2717 break;
2718 default:
2719 break;
2720 }
2721
2722 return ret;
2723}
2724
2725static const struct ethtool_ops mtk_ethtool_ops = {
2726 .get_link_ksettings = mtk_get_link_ksettings,
2727 .set_link_ksettings = mtk_set_link_ksettings,
2728 .get_drvinfo = mtk_get_drvinfo,
2729 .get_msglevel = mtk_get_msglevel,
2730 .set_msglevel = mtk_set_msglevel,
2731 .nway_reset = mtk_nway_reset,
2732 .get_link = ethtool_op_get_link,
2733 .get_strings = mtk_get_strings,
2734 .get_sset_count = mtk_get_sset_count,
2735 .get_ethtool_stats = mtk_get_ethtool_stats,
2736 .get_rxnfc = mtk_get_rxnfc,
2737 .set_rxnfc = mtk_set_rxnfc,
2738};
2739
2740static const struct net_device_ops mtk_netdev_ops = {
2741 .ndo_init = mtk_init,
2742 .ndo_uninit = mtk_uninit,
2743 .ndo_open = mtk_open,
2744 .ndo_stop = mtk_stop,
2745 .ndo_start_xmit = mtk_start_xmit,
2746 .ndo_set_mac_address = mtk_set_mac_address,
2747 .ndo_validate_addr = eth_validate_addr,
2748 .ndo_do_ioctl = mtk_do_ioctl,
2749 .ndo_tx_timeout = mtk_tx_timeout,
2750 .ndo_get_stats64 = mtk_get_stats64,
2751 .ndo_fix_features = mtk_fix_features,
2752 .ndo_set_features = mtk_set_features,
2753#ifdef CONFIG_NET_POLL_CONTROLLER
2754 .ndo_poll_controller = mtk_poll_controller,
2755#endif
2756};
2757
2758static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
2759{
2760 const __be32 *_id = of_get_property(np, "reg", NULL);
2761 struct phylink *phylink;
2762 int phy_mode, id, err;
2763 struct mtk_mac *mac;
2764
2765 if (!_id) {
2766 dev_err(eth->dev, "missing mac id\n");
2767 return -EINVAL;
2768 }
2769
2770 id = be32_to_cpup(_id);
2771 if (id >= MTK_MAC_COUNT) {
2772 dev_err(eth->dev, "%d is not a valid mac id\n", id);
2773 return -EINVAL;
2774 }
2775
2776 if (eth->netdev[id]) {
2777 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
2778 return -EINVAL;
2779 }
2780
2781 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
2782 if (!eth->netdev[id]) {
2783 dev_err(eth->dev, "alloc_etherdev failed\n");
2784 return -ENOMEM;
2785 }
2786 mac = netdev_priv(eth->netdev[id]);
2787 eth->mac[id] = mac;
2788 mac->id = id;
2789 mac->hw = eth;
2790 mac->of_node = np;
2791
2792 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
2793 mac->hwlro_ip_cnt = 0;
2794
2795 mac->hw_stats = devm_kzalloc(eth->dev,
2796 sizeof(*mac->hw_stats),
2797 GFP_KERNEL);
2798 if (!mac->hw_stats) {
2799 dev_err(eth->dev, "failed to allocate counter memory\n");
2800 err = -ENOMEM;
2801 goto free_netdev;
2802 }
2803 spin_lock_init(&mac->hw_stats->stats_lock);
2804 u64_stats_init(&mac->hw_stats->syncp);
2805 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
2806
2807 /* phylink create */
2808 phy_mode = of_get_phy_mode(np);
2809 if (phy_mode < 0) {
2810 dev_err(eth->dev, "incorrect phy-mode\n");
2811 err = -EINVAL;
2812 goto free_netdev;
2813 }
2814
2815 /* mac config is not set */
2816 mac->interface = PHY_INTERFACE_MODE_NA;
2817 mac->mode = MLO_AN_PHY;
2818 mac->speed = SPEED_UNKNOWN;
2819
2820 mac->phylink_config.dev = ð->netdev[id]->dev;
2821 mac->phylink_config.type = PHYLINK_NETDEV;
2822
2823 phylink = phylink_create(&mac->phylink_config,
2824 of_fwnode_handle(mac->of_node),
2825 phy_mode, &mtk_phylink_ops);
2826 if (IS_ERR(phylink)) {
2827 err = PTR_ERR(phylink);
2828 goto free_netdev;
2829 }
2830
2831 mac->phylink = phylink;
2832
2833 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
2834 eth->netdev[id]->watchdog_timeo = 5 * HZ;
2835 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
2836 eth->netdev[id]->base_addr = (unsigned long)eth->base;
2837
2838 eth->netdev[id]->hw_features = eth->soc->hw_features;
2839 if (eth->hwlro)
2840 eth->netdev[id]->hw_features |= NETIF_F_LRO;
2841
2842 eth->netdev[id]->vlan_features = eth->soc->hw_features &
2843 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
2844 eth->netdev[id]->features |= eth->soc->hw_features;
2845 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
2846
2847 eth->netdev[id]->irq = eth->irq[0];
2848 eth->netdev[id]->dev.of_node = np;
2849
2850 return 0;
2851
2852free_netdev:
2853 free_netdev(eth->netdev[id]);
2854 return err;
2855}
2856
2857static int mtk_probe(struct platform_device *pdev)
2858{
2859 struct device_node *mac_np;
2860 struct mtk_eth *eth;
2861 int err, i;
2862
2863 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2864 if (!eth)
2865 return -ENOMEM;
2866
2867 eth->soc = of_device_get_match_data(&pdev->dev);
2868
2869 eth->dev = &pdev->dev;
2870 eth->base = devm_platform_ioremap_resource(pdev, 0);
2871 if (IS_ERR(eth->base))
2872 return PTR_ERR(eth->base);
2873
2874 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2875 eth->tx_int_mask_reg = MTK_QDMA_INT_MASK;
2876 eth->tx_int_status_reg = MTK_QDMA_INT_STATUS;
2877 } else {
2878 eth->tx_int_mask_reg = MTK_PDMA_INT_MASK;
2879 eth->tx_int_status_reg = MTK_PDMA_INT_STATUS;
2880 }
2881
2882 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
2883 eth->rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA;
2884 eth->ip_align = NET_IP_ALIGN;
2885 } else {
2886 eth->rx_dma_l4_valid = RX_DMA_L4_VALID;
2887 }
2888
2889 spin_lock_init(ð->page_lock);
2890 spin_lock_init(ð->tx_irq_lock);
2891 spin_lock_init(ð->rx_irq_lock);
2892
2893 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
2894 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2895 "mediatek,ethsys");
2896 if (IS_ERR(eth->ethsys)) {
2897 dev_err(&pdev->dev, "no ethsys regmap found\n");
2898 return PTR_ERR(eth->ethsys);
2899 }
2900 }
2901
2902 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) {
2903 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2904 "mediatek,infracfg");
2905 if (IS_ERR(eth->infra)) {
2906 dev_err(&pdev->dev, "no infracfg regmap found\n");
2907 return PTR_ERR(eth->infra);
2908 }
2909 }
2910
2911 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
2912 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),
2913 GFP_KERNEL);
2914 if (!eth->sgmii)
2915 return -ENOMEM;
2916
2917 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node,
2918 eth->soc->ana_rgc3);
2919
2920 if (err)
2921 return err;
2922 }
2923
2924 if (eth->soc->required_pctl) {
2925 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2926 "mediatek,pctl");
2927 if (IS_ERR(eth->pctl)) {
2928 dev_err(&pdev->dev, "no pctl regmap found\n");
2929 return PTR_ERR(eth->pctl);
2930 }
2931 }
2932
2933 for (i = 0; i < 3; i++) {
2934 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)
2935 eth->irq[i] = eth->irq[0];
2936 else
2937 eth->irq[i] = platform_get_irq(pdev, i);
2938 if (eth->irq[i] < 0) {
2939 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
2940 return -ENXIO;
2941 }
2942 }
2943 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
2944 eth->clks[i] = devm_clk_get(eth->dev,
2945 mtk_clks_source_name[i]);
2946 if (IS_ERR(eth->clks[i])) {
2947 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
2948 return -EPROBE_DEFER;
2949 if (eth->soc->required_clks & BIT(i)) {
2950 dev_err(&pdev->dev, "clock %s not found\n",
2951 mtk_clks_source_name[i]);
2952 return -EINVAL;
2953 }
2954 eth->clks[i] = NULL;
2955 }
2956 }
2957
2958 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
2959 INIT_WORK(ð->pending_work, mtk_pending_work);
2960
2961 err = mtk_hw_init(eth);
2962 if (err)
2963 return err;
2964
2965 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO);
2966
2967 for_each_child_of_node(pdev->dev.of_node, mac_np) {
2968 if (!of_device_is_compatible(mac_np,
2969 "mediatek,eth-mac"))
2970 continue;
2971
2972 if (!of_device_is_available(mac_np))
2973 continue;
2974
2975 err = mtk_add_mac(eth, mac_np);
2976 if (err) {
2977 of_node_put(mac_np);
2978 goto err_deinit_hw;
2979 }
2980 }
2981
2982 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
2983 err = devm_request_irq(eth->dev, eth->irq[0],
2984 mtk_handle_irq, 0,
2985 dev_name(eth->dev), eth);
2986 } else {
2987 err = devm_request_irq(eth->dev, eth->irq[1],
2988 mtk_handle_irq_tx, 0,
2989 dev_name(eth->dev), eth);
2990 if (err)
2991 goto err_free_dev;
2992
2993 err = devm_request_irq(eth->dev, eth->irq[2],
2994 mtk_handle_irq_rx, 0,
2995 dev_name(eth->dev), eth);
2996 }
2997 if (err)
2998 goto err_free_dev;
2999
3000 /* No MT7628/88 support yet */
3001 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
3002 err = mtk_mdio_init(eth);
3003 if (err)
3004 goto err_free_dev;
3005 }
3006
3007 for (i = 0; i < MTK_MAX_DEVS; i++) {
3008 if (!eth->netdev[i])
3009 continue;
3010
3011 err = register_netdev(eth->netdev[i]);
3012 if (err) {
3013 dev_err(eth->dev, "error bringing up device\n");
3014 goto err_deinit_mdio;
3015 } else
3016 netif_info(eth, probe, eth->netdev[i],
3017 "mediatek frame engine at 0x%08lx, irq %d\n",
3018 eth->netdev[i]->base_addr, eth->irq[0]);
3019 }
3020
3021 /* we run 2 devices on the same DMA ring so we need a dummy device
3022 * for NAPI to work
3023 */
3024 init_dummy_netdev(ð->dummy_dev);
3025 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx,
3026 MTK_NAPI_WEIGHT);
3027 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx,
3028 MTK_NAPI_WEIGHT);
3029
3030 platform_set_drvdata(pdev, eth);
3031
3032 return 0;
3033
3034err_deinit_mdio:
3035 mtk_mdio_cleanup(eth);
3036err_free_dev:
3037 mtk_free_dev(eth);
3038err_deinit_hw:
3039 mtk_hw_deinit(eth);
3040
3041 return err;
3042}
3043
3044static int mtk_remove(struct platform_device *pdev)
3045{
3046 struct mtk_eth *eth = platform_get_drvdata(pdev);
3047 struct mtk_mac *mac;
3048 int i;
3049
3050 /* stop all devices to make sure that dma is properly shut down */
3051 for (i = 0; i < MTK_MAC_COUNT; i++) {
3052 if (!eth->netdev[i])
3053 continue;
3054 mtk_stop(eth->netdev[i]);
3055 mac = netdev_priv(eth->netdev[i]);
3056 phylink_disconnect_phy(mac->phylink);
3057 }
3058
3059 mtk_hw_deinit(eth);
3060
3061 netif_napi_del(ð->tx_napi);
3062 netif_napi_del(ð->rx_napi);
3063 mtk_cleanup(eth);
3064 mtk_mdio_cleanup(eth);
3065
3066 return 0;
3067}
3068
3069static const struct mtk_soc_data mt2701_data = {
3070 .caps = MT7623_CAPS | MTK_HWLRO,
3071 .hw_features = MTK_HW_FEATURES,
3072 .required_clks = MT7623_CLKS_BITMAP,
3073 .required_pctl = true,
3074};
3075
3076static const struct mtk_soc_data mt7621_data = {
3077 .caps = MT7621_CAPS,
3078 .hw_features = MTK_HW_FEATURES,
3079 .required_clks = MT7621_CLKS_BITMAP,
3080 .required_pctl = false,
3081};
3082
3083static const struct mtk_soc_data mt7622_data = {
3084 .ana_rgc3 = 0x2028,
3085 .caps = MT7622_CAPS | MTK_HWLRO,
3086 .hw_features = MTK_HW_FEATURES,
3087 .required_clks = MT7622_CLKS_BITMAP,
3088 .required_pctl = false,
3089};
3090
3091static const struct mtk_soc_data mt7623_data = {
3092 .caps = MT7623_CAPS | MTK_HWLRO,
3093 .hw_features = MTK_HW_FEATURES,
3094 .required_clks = MT7623_CLKS_BITMAP,
3095 .required_pctl = true,
3096};
3097
3098static const struct mtk_soc_data mt7629_data = {
3099 .ana_rgc3 = 0x128,
3100 .caps = MT7629_CAPS | MTK_HWLRO,
3101 .hw_features = MTK_HW_FEATURES,
3102 .required_clks = MT7629_CLKS_BITMAP,
3103 .required_pctl = false,
3104};
3105
3106static const struct mtk_soc_data rt5350_data = {
3107 .caps = MT7628_CAPS,
3108 .hw_features = MTK_HW_FEATURES_MT7628,
3109 .required_clks = MT7628_CLKS_BITMAP,
3110 .required_pctl = false,
3111};
3112
3113const struct of_device_id of_mtk_match[] = {
3114 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
3115 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data},
3116 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
3117 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
3118 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
3119 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
3120 {},
3121};
3122MODULE_DEVICE_TABLE(of, of_mtk_match);
3123
3124static struct platform_driver mtk_driver = {
3125 .probe = mtk_probe,
3126 .remove = mtk_remove,
3127 .driver = {
3128 .name = "mtk_soc_eth",
3129 .of_match_table = of_mtk_match,
3130 },
3131};
3132
3133module_platform_driver(mtk_driver);
3134
3135MODULE_LICENSE("GPL");
3136MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
3137MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");