1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright(c) 2015 EZchip Technologies.
  4 */
  5
  6#ifndef _NPS_ENET_H
  7#define _NPS_ENET_H
  8
  9/* default values */
 10#define NPS_ENET_NAPI_POLL_WEIGHT		0x2
 11#define NPS_ENET_MAX_FRAME_LENGTH		0x3FFF
 12#define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR	0x7
 13#define NPS_ENET_GE_MAC_CFG_0_RX_IFG		0x5
 14#define NPS_ENET_GE_MAC_CFG_0_TX_IFG		0xC
 15#define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN		0x7
 16#define NPS_ENET_GE_MAC_CFG_2_STAT_EN		0x3
 17#define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH		0x14
 18#define NPS_ENET_GE_MAC_CFG_3_MAX_LEN		0x3FFC
 19#define NPS_ENET_ENABLE				1
 20#define NPS_ENET_DISABLE			0
 21
 22/* register definitions  */
 23#define NPS_ENET_REG_TX_CTL		0x800
 24#define NPS_ENET_REG_TX_BUF		0x808
 25#define NPS_ENET_REG_RX_CTL		0x810
 26#define NPS_ENET_REG_RX_BUF		0x818
 27#define NPS_ENET_REG_BUF_INT_ENABLE	0x8C0
 28#define NPS_ENET_REG_GE_MAC_CFG_0	0x1000
 29#define NPS_ENET_REG_GE_MAC_CFG_1	0x1004
 30#define NPS_ENET_REG_GE_MAC_CFG_2	0x1008
 31#define NPS_ENET_REG_GE_MAC_CFG_3	0x100C
 32#define NPS_ENET_REG_GE_RST		0x1400
 33#define NPS_ENET_REG_PHASE_FIFO_CTL	0x1404
 34
 35/* Tx control register masks and shifts */
 36#define TX_CTL_NT_MASK 0x7FF
 37#define TX_CTL_NT_SHIFT 0
 38#define TX_CTL_ET_MASK 0x4000
 39#define TX_CTL_ET_SHIFT 14
 40#define TX_CTL_CT_MASK 0x8000
 41#define TX_CTL_CT_SHIFT 15
 42
 43/* Rx control register masks and shifts */
 44#define RX_CTL_NR_MASK 0x7FF
 45#define RX_CTL_NR_SHIFT 0
 46#define RX_CTL_CRC_MASK 0x2000
 47#define RX_CTL_CRC_SHIFT 13
 48#define RX_CTL_ER_MASK 0x4000
 49#define RX_CTL_ER_SHIFT 14
 50#define RX_CTL_CR_MASK 0x8000
 51#define RX_CTL_CR_SHIFT 15
 52
 53/* Interrupt enable for data buffer events register masks and shifts */
 54#define RX_RDY_MASK 0x1
 55#define RX_RDY_SHIFT 0
 56#define TX_DONE_MASK 0x2
 57#define TX_DONE_SHIFT 1
 58
 59/* Gbps Eth MAC Configuration 0 register masks and shifts */
 60#define CFG_0_RX_EN_MASK 0x1
 61#define CFG_0_RX_EN_SHIFT 0
 62#define CFG_0_TX_EN_MASK 0x2
 63#define CFG_0_TX_EN_SHIFT 1
 64#define CFG_0_TX_FC_EN_MASK 0x4
 65#define CFG_0_TX_FC_EN_SHIFT 2
 66#define CFG_0_TX_PAD_EN_MASK 0x8
 67#define CFG_0_TX_PAD_EN_SHIFT 3
 68#define CFG_0_TX_CRC_EN_MASK 0x10
 69#define CFG_0_TX_CRC_EN_SHIFT 4
 70#define CFG_0_RX_FC_EN_MASK 0x20
 71#define CFG_0_RX_FC_EN_SHIFT 5
 72#define CFG_0_RX_CRC_STRIP_MASK 0x40
 73#define CFG_0_RX_CRC_STRIP_SHIFT 6
 74#define CFG_0_RX_CRC_IGNORE_MASK 0x80
 75#define CFG_0_RX_CRC_IGNORE_SHIFT 7
 76#define CFG_0_RX_LENGTH_CHECK_EN_MASK 0x100
 77#define CFG_0_RX_LENGTH_CHECK_EN_SHIFT 8
 78#define CFG_0_TX_FC_RETR_MASK 0xE00
 79#define CFG_0_TX_FC_RETR_SHIFT 9
 80#define CFG_0_RX_IFG_MASK 0xF000
 81#define CFG_0_RX_IFG_SHIFT 12
 82#define CFG_0_TX_IFG_MASK 0x3F0000
 83#define CFG_0_TX_IFG_SHIFT 16
 84#define CFG_0_RX_PR_CHECK_EN_MASK 0x400000
 85#define CFG_0_RX_PR_CHECK_EN_SHIFT 22
 86#define CFG_0_NIB_MODE_MASK 0x800000
 87#define CFG_0_NIB_MODE_SHIFT 23
 88#define CFG_0_TX_IFG_NIB_MASK 0xF000000
 89#define CFG_0_TX_IFG_NIB_SHIFT 24
 90#define CFG_0_TX_PR_LEN_MASK 0xF0000000
 91#define CFG_0_TX_PR_LEN_SHIFT 28
 92
 93/* Gbps Eth MAC Configuration 1 register masks and shifts */
 94#define CFG_1_OCTET_0_MASK 0x000000FF
 95#define CFG_1_OCTET_0_SHIFT 0
 96#define CFG_1_OCTET_1_MASK 0x0000FF00
 97#define CFG_1_OCTET_1_SHIFT 8
 98#define CFG_1_OCTET_2_MASK 0x00FF0000
 99#define CFG_1_OCTET_2_SHIFT 16
100#define CFG_1_OCTET_3_MASK 0xFF000000
101#define CFG_1_OCTET_3_SHIFT 24
102
103/* Gbps Eth MAC Configuration 2 register masks and shifts */
104#define CFG_2_OCTET_4_MASK 0x000000FF
105#define CFG_2_OCTET_4_SHIFT 0
106#define CFG_2_OCTET_5_MASK 0x0000FF00
107#define CFG_2_OCTET_5_SHIFT 8
108#define CFG_2_DISK_MC_MASK 0x00100000
109#define CFG_2_DISK_MC_SHIFT 20
110#define CFG_2_DISK_BC_MASK 0x00200000
111#define CFG_2_DISK_BC_SHIFT 21
112#define CFG_2_DISK_DA_MASK 0x00400000
113#define CFG_2_DISK_DA_SHIFT 22
114#define CFG_2_STAT_EN_MASK 0x3000000
115#define CFG_2_STAT_EN_SHIFT 24
116#define CFG_2_TRANSMIT_FLUSH_EN_MASK 0x80000000
117#define CFG_2_TRANSMIT_FLUSH_EN_SHIFT 31
118
119/* Gbps Eth MAC Configuration 3 register masks and shifts */
120#define CFG_3_TM_HD_MODE_MASK 0x1
121#define CFG_3_TM_HD_MODE_SHIFT 0
122#define CFG_3_RX_CBFC_EN_MASK 0x2
123#define CFG_3_RX_CBFC_EN_SHIFT 1
124#define CFG_3_RX_CBFC_REDIR_EN_MASK 0x4
125#define CFG_3_RX_CBFC_REDIR_EN_SHIFT 2
126#define CFG_3_REDIRECT_CBFC_SEL_MASK 0x18
127#define CFG_3_REDIRECT_CBFC_SEL_SHIFT 3
128#define CFG_3_CF_DROP_MASK 0x20
129#define CFG_3_CF_DROP_SHIFT 5
130#define CFG_3_CF_TIMEOUT_MASK 0x3C0
131#define CFG_3_CF_TIMEOUT_SHIFT 6
132#define CFG_3_RX_IFG_TH_MASK 0x7C00
133#define CFG_3_RX_IFG_TH_SHIFT 10
134#define CFG_3_TX_CBFC_EN_MASK 0x8000
135#define CFG_3_TX_CBFC_EN_SHIFT 15
136#define CFG_3_MAX_LEN_MASK 0x3FFF0000
137#define CFG_3_MAX_LEN_SHIFT 16
138#define CFG_3_EXT_OOB_CBFC_SEL_MASK 0xC0000000
139#define CFG_3_EXT_OOB_CBFC_SEL_SHIFT 30
140
141/* GE MAC, PCS reset control register masks and shifts */
142#define RST_SPCS_MASK 0x1
143#define RST_SPCS_SHIFT 0
144#define RST_GMAC_0_MASK 0x100
145#define RST_GMAC_0_SHIFT 8
146
147/* Tx phase sync FIFO control register masks and shifts */
148#define PHASE_FIFO_CTL_RST_MASK 0x1
149#define PHASE_FIFO_CTL_RST_SHIFT 0
150#define PHASE_FIFO_CTL_INIT_MASK 0x2
151#define PHASE_FIFO_CTL_INIT_SHIFT 1
152
153/**
154 * struct nps_enet_priv - Storage of ENET's private information.
155 * @regs_base:      Base address of ENET memory-mapped control registers.
156 * @irq:            For RX/TX IRQ number.
157 * @tx_skb:         socket buffer of sent frame.
158 * @napi:           Structure for NAPI.
159 */
160struct nps_enet_priv {
161	void __iomem *regs_base;
162	s32 irq;
163	struct sk_buff *tx_skb;
164	struct napi_struct napi;
165	u32 ge_mac_cfg_2_value;
166	u32 ge_mac_cfg_3_value;
167};
168
169/**
170 * nps_enet_reg_set - Sets ENET register with provided value.
171 * @priv:       Pointer to EZchip ENET private data structure.
172 * @reg:        Register offset from base address.
173 * @value:      Value to set in register.
174 */
175static inline void nps_enet_reg_set(struct nps_enet_priv *priv,
176				    s32 reg, s32 value)
177{
178	iowrite32be(value, priv->regs_base + reg);
179}
180
181/**
182 * nps_enet_reg_get - Gets value of specified ENET register.
183 * @priv:       Pointer to EZchip ENET private data structure.
184 * @reg:        Register offset from base address.
185 *
186 * returns:     Value of requested register.
187 */
188static inline u32 nps_enet_reg_get(struct nps_enet_priv *priv, s32 reg)
189{
190	return ioread32be(priv->regs_base + reg);
191}
192
193#endif /* _NPS_ENET_H */