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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2016 John Crispin <john@phrozen.org>
7 */
8
9#include <linux/module.h>
10#include <linux/phy.h>
11#include <linux/netdevice.h>
12#include <net/dsa.h>
13#include <linux/of_net.h>
14#include <linux/of_platform.h>
15#include <linux/if_bridge.h>
16#include <linux/mdio.h>
17#include <linux/gpio/consumer.h>
18#include <linux/etherdevice.h>
19
20#include "qca8k.h"
21
22#define MIB_DESC(_s, _o, _n) \
23 { \
24 .size = (_s), \
25 .offset = (_o), \
26 .name = (_n), \
27 }
28
29static const struct qca8k_mib_desc ar8327_mib[] = {
30 MIB_DESC(1, 0x00, "RxBroad"),
31 MIB_DESC(1, 0x04, "RxPause"),
32 MIB_DESC(1, 0x08, "RxMulti"),
33 MIB_DESC(1, 0x0c, "RxFcsErr"),
34 MIB_DESC(1, 0x10, "RxAlignErr"),
35 MIB_DESC(1, 0x14, "RxRunt"),
36 MIB_DESC(1, 0x18, "RxFragment"),
37 MIB_DESC(1, 0x1c, "Rx64Byte"),
38 MIB_DESC(1, 0x20, "Rx128Byte"),
39 MIB_DESC(1, 0x24, "Rx256Byte"),
40 MIB_DESC(1, 0x28, "Rx512Byte"),
41 MIB_DESC(1, 0x2c, "Rx1024Byte"),
42 MIB_DESC(1, 0x30, "Rx1518Byte"),
43 MIB_DESC(1, 0x34, "RxMaxByte"),
44 MIB_DESC(1, 0x38, "RxTooLong"),
45 MIB_DESC(2, 0x3c, "RxGoodByte"),
46 MIB_DESC(2, 0x44, "RxBadByte"),
47 MIB_DESC(1, 0x4c, "RxOverFlow"),
48 MIB_DESC(1, 0x50, "Filtered"),
49 MIB_DESC(1, 0x54, "TxBroad"),
50 MIB_DESC(1, 0x58, "TxPause"),
51 MIB_DESC(1, 0x5c, "TxMulti"),
52 MIB_DESC(1, 0x60, "TxUnderRun"),
53 MIB_DESC(1, 0x64, "Tx64Byte"),
54 MIB_DESC(1, 0x68, "Tx128Byte"),
55 MIB_DESC(1, 0x6c, "Tx256Byte"),
56 MIB_DESC(1, 0x70, "Tx512Byte"),
57 MIB_DESC(1, 0x74, "Tx1024Byte"),
58 MIB_DESC(1, 0x78, "Tx1518Byte"),
59 MIB_DESC(1, 0x7c, "TxMaxByte"),
60 MIB_DESC(1, 0x80, "TxOverSize"),
61 MIB_DESC(2, 0x84, "TxByte"),
62 MIB_DESC(1, 0x8c, "TxCollision"),
63 MIB_DESC(1, 0x90, "TxAbortCol"),
64 MIB_DESC(1, 0x94, "TxMultiCol"),
65 MIB_DESC(1, 0x98, "TxSingleCol"),
66 MIB_DESC(1, 0x9c, "TxExcDefer"),
67 MIB_DESC(1, 0xa0, "TxDefer"),
68 MIB_DESC(1, 0xa4, "TxLateCol"),
69};
70
71/* The 32bit switch registers are accessed indirectly. To achieve this we need
72 * to set the page of the register. Track the last page that was set to reduce
73 * mdio writes
74 */
75static u16 qca8k_current_page = 0xffff;
76
77static void
78qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
79{
80 regaddr >>= 1;
81 *r1 = regaddr & 0x1e;
82
83 regaddr >>= 5;
84 *r2 = regaddr & 0x7;
85
86 regaddr >>= 3;
87 *page = regaddr & 0x3ff;
88}
89
90static u32
91qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum)
92{
93 u32 val;
94 int ret;
95
96 ret = bus->read(bus, phy_id, regnum);
97 if (ret >= 0) {
98 val = ret;
99 ret = bus->read(bus, phy_id, regnum + 1);
100 val |= ret << 16;
101 }
102
103 if (ret < 0) {
104 dev_err_ratelimited(&bus->dev,
105 "failed to read qca8k 32bit register\n");
106 return ret;
107 }
108
109 return val;
110}
111
112static void
113qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
114{
115 u16 lo, hi;
116 int ret;
117
118 lo = val & 0xffff;
119 hi = (u16)(val >> 16);
120
121 ret = bus->write(bus, phy_id, regnum, lo);
122 if (ret >= 0)
123 ret = bus->write(bus, phy_id, regnum + 1, hi);
124 if (ret < 0)
125 dev_err_ratelimited(&bus->dev,
126 "failed to write qca8k 32bit register\n");
127}
128
129static void
130qca8k_set_page(struct mii_bus *bus, u16 page)
131{
132 if (page == qca8k_current_page)
133 return;
134
135 if (bus->write(bus, 0x18, 0, page) < 0)
136 dev_err_ratelimited(&bus->dev,
137 "failed to set qca8k page\n");
138 qca8k_current_page = page;
139}
140
141static u32
142qca8k_read(struct qca8k_priv *priv, u32 reg)
143{
144 u16 r1, r2, page;
145 u32 val;
146
147 qca8k_split_addr(reg, &r1, &r2, &page);
148
149 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
150
151 qca8k_set_page(priv->bus, page);
152 val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
153
154 mutex_unlock(&priv->bus->mdio_lock);
155
156 return val;
157}
158
159static void
160qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
161{
162 u16 r1, r2, page;
163
164 qca8k_split_addr(reg, &r1, &r2, &page);
165
166 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
167
168 qca8k_set_page(priv->bus, page);
169 qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);
170
171 mutex_unlock(&priv->bus->mdio_lock);
172}
173
174static u32
175qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val)
176{
177 u16 r1, r2, page;
178 u32 ret;
179
180 qca8k_split_addr(reg, &r1, &r2, &page);
181
182 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
183
184 qca8k_set_page(priv->bus, page);
185 ret = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
186 ret &= ~mask;
187 ret |= val;
188 qca8k_mii_write32(priv->bus, 0x10 | r2, r1, ret);
189
190 mutex_unlock(&priv->bus->mdio_lock);
191
192 return ret;
193}
194
195static void
196qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
197{
198 qca8k_rmw(priv, reg, 0, val);
199}
200
201static void
202qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
203{
204 qca8k_rmw(priv, reg, val, 0);
205}
206
207static int
208qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
209{
210 struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
211
212 *val = qca8k_read(priv, reg);
213
214 return 0;
215}
216
217static int
218qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
219{
220 struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
221
222 qca8k_write(priv, reg, val);
223
224 return 0;
225}
226
227static const struct regmap_range qca8k_readable_ranges[] = {
228 regmap_reg_range(0x0000, 0x00e4), /* Global control */
229 regmap_reg_range(0x0100, 0x0168), /* EEE control */
230 regmap_reg_range(0x0200, 0x0270), /* Parser control */
231 regmap_reg_range(0x0400, 0x0454), /* ACL */
232 regmap_reg_range(0x0600, 0x0718), /* Lookup */
233 regmap_reg_range(0x0800, 0x0b70), /* QM */
234 regmap_reg_range(0x0c00, 0x0c80), /* PKT */
235 regmap_reg_range(0x0e00, 0x0e98), /* L3 */
236 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
237 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
238 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
239 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
240 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
241 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
242 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
243
244};
245
246static const struct regmap_access_table qca8k_readable_table = {
247 .yes_ranges = qca8k_readable_ranges,
248 .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
249};
250
251static struct regmap_config qca8k_regmap_config = {
252 .reg_bits = 16,
253 .val_bits = 32,
254 .reg_stride = 4,
255 .max_register = 0x16ac, /* end MIB - Port6 range */
256 .reg_read = qca8k_regmap_read,
257 .reg_write = qca8k_regmap_write,
258 .rd_table = &qca8k_readable_table,
259};
260
261static int
262qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
263{
264 unsigned long timeout;
265
266 timeout = jiffies + msecs_to_jiffies(20);
267
268 /* loop until the busy flag has cleared */
269 do {
270 u32 val = qca8k_read(priv, reg);
271 int busy = val & mask;
272
273 if (!busy)
274 break;
275 cond_resched();
276 } while (!time_after_eq(jiffies, timeout));
277
278 return time_after_eq(jiffies, timeout);
279}
280
281static void
282qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
283{
284 u32 reg[4];
285 int i;
286
287 /* load the ARL table into an array */
288 for (i = 0; i < 4; i++)
289 reg[i] = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4));
290
291 /* vid - 83:72 */
292 fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
293 /* aging - 67:64 */
294 fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
295 /* portmask - 54:48 */
296 fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
297 /* mac - 47:0 */
298 fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
299 fdb->mac[1] = reg[1] & 0xff;
300 fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
301 fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
302 fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
303 fdb->mac[5] = reg[0] & 0xff;
304}
305
306static void
307qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
308 u8 aging)
309{
310 u32 reg[3] = { 0 };
311 int i;
312
313 /* vid - 83:72 */
314 reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
315 /* aging - 67:64 */
316 reg[2] |= aging & QCA8K_ATU_STATUS_M;
317 /* portmask - 54:48 */
318 reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
319 /* mac - 47:0 */
320 reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
321 reg[1] |= mac[1];
322 reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
323 reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
324 reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
325 reg[0] |= mac[5];
326
327 /* load the array into the ARL table */
328 for (i = 0; i < 3; i++)
329 qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
330}
331
332static int
333qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
334{
335 u32 reg;
336
337 /* Set the command and FDB index */
338 reg = QCA8K_ATU_FUNC_BUSY;
339 reg |= cmd;
340 if (port >= 0) {
341 reg |= QCA8K_ATU_FUNC_PORT_EN;
342 reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
343 }
344
345 /* Write the function register triggering the table access */
346 qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
347
348 /* wait for completion */
349 if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY))
350 return -1;
351
352 /* Check for table full violation when adding an entry */
353 if (cmd == QCA8K_FDB_LOAD) {
354 reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC);
355 if (reg & QCA8K_ATU_FUNC_FULL)
356 return -1;
357 }
358
359 return 0;
360}
361
362static int
363qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
364{
365 int ret;
366
367 qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
368 ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
369 if (ret >= 0)
370 qca8k_fdb_read(priv, fdb);
371
372 return ret;
373}
374
375static int
376qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
377 u16 vid, u8 aging)
378{
379 int ret;
380
381 mutex_lock(&priv->reg_mutex);
382 qca8k_fdb_write(priv, vid, port_mask, mac, aging);
383 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
384 mutex_unlock(&priv->reg_mutex);
385
386 return ret;
387}
388
389static int
390qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
391{
392 int ret;
393
394 mutex_lock(&priv->reg_mutex);
395 qca8k_fdb_write(priv, vid, port_mask, mac, 0);
396 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
397 mutex_unlock(&priv->reg_mutex);
398
399 return ret;
400}
401
402static void
403qca8k_fdb_flush(struct qca8k_priv *priv)
404{
405 mutex_lock(&priv->reg_mutex);
406 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
407 mutex_unlock(&priv->reg_mutex);
408}
409
410static void
411qca8k_mib_init(struct qca8k_priv *priv)
412{
413 mutex_lock(&priv->reg_mutex);
414 qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
415 qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
416 qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
417 qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
418 mutex_unlock(&priv->reg_mutex);
419}
420
421static int
422qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
423{
424 u32 reg, val;
425
426 switch (port) {
427 case 0:
428 reg = QCA8K_REG_PORT0_PAD_CTRL;
429 break;
430 case 6:
431 reg = QCA8K_REG_PORT6_PAD_CTRL;
432 break;
433 default:
434 pr_err("Can't set PAD_CTRL on port %d\n", port);
435 return -EINVAL;
436 }
437
438 /* Configure a port to be directly connected to an external
439 * PHY or MAC.
440 */
441 switch (mode) {
442 case PHY_INTERFACE_MODE_RGMII:
443 /* RGMII mode means no delay so don't enable the delay */
444 val = QCA8K_PORT_PAD_RGMII_EN;
445 qca8k_write(priv, reg, val);
446 break;
447 case PHY_INTERFACE_MODE_RGMII_ID:
448 /* RGMII_ID needs internal delay. This is enabled through
449 * PORT5_PAD_CTRL for all ports, rather than individual port
450 * registers
451 */
452 qca8k_write(priv, reg,
453 QCA8K_PORT_PAD_RGMII_EN |
454 QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) |
455 QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY));
456 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
457 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
458 break;
459 case PHY_INTERFACE_MODE_SGMII:
460 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
461 break;
462 default:
463 pr_err("xMII mode %d not supported\n", mode);
464 return -EINVAL;
465 }
466
467 return 0;
468}
469
470static void
471qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
472{
473 u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
474
475 /* Port 0 and 6 have no internal PHY */
476 if (port > 0 && port < 6)
477 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
478
479 if (enable)
480 qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);
481 else
482 qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
483}
484
485static u32
486qca8k_port_to_phy(int port)
487{
488 /* From Andrew Lunn:
489 * Port 0 has no internal phy.
490 * Port 1 has an internal PHY at MDIO address 0.
491 * Port 2 has an internal PHY at MDIO address 1.
492 * ...
493 * Port 5 has an internal PHY at MDIO address 4.
494 * Port 6 has no internal PHY.
495 */
496
497 return port - 1;
498}
499
500static int
501qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data)
502{
503 u32 phy, val;
504
505 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
506 return -EINVAL;
507
508 /* callee is responsible for not passing bad ports,
509 * but we still would like to make spills impossible.
510 */
511 phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
512 val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
513 QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
514 QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
515 QCA8K_MDIO_MASTER_DATA(data);
516
517 qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
518
519 return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
520 QCA8K_MDIO_MASTER_BUSY);
521}
522
523static int
524qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum)
525{
526 u32 phy, val;
527
528 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
529 return -EINVAL;
530
531 /* callee is responsible for not passing bad ports,
532 * but we still would like to make spills impossible.
533 */
534 phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
535 val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
536 QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
537 QCA8K_MDIO_MASTER_REG_ADDR(regnum);
538
539 qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
540
541 if (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
542 QCA8K_MDIO_MASTER_BUSY))
543 return -ETIMEDOUT;
544
545 val = (qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL) &
546 QCA8K_MDIO_MASTER_DATA_MASK);
547
548 return val;
549}
550
551static int
552qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data)
553{
554 struct qca8k_priv *priv = ds->priv;
555
556 return qca8k_mdio_write(priv, port, regnum, data);
557}
558
559static int
560qca8k_phy_read(struct dsa_switch *ds, int port, int regnum)
561{
562 struct qca8k_priv *priv = ds->priv;
563 int ret;
564
565 ret = qca8k_mdio_read(priv, port, regnum);
566
567 if (ret < 0)
568 return 0xffff;
569
570 return ret;
571}
572
573static int
574qca8k_setup_mdio_bus(struct qca8k_priv *priv)
575{
576 u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg;
577 struct device_node *ports, *port;
578 int err;
579
580 ports = of_get_child_by_name(priv->dev->of_node, "ports");
581 if (!ports)
582 return -EINVAL;
583
584 for_each_available_child_of_node(ports, port) {
585 err = of_property_read_u32(port, "reg", ®);
586 if (err) {
587 of_node_put(port);
588 of_node_put(ports);
589 return err;
590 }
591
592 if (!dsa_is_user_port(priv->ds, reg))
593 continue;
594
595 if (of_property_read_bool(port, "phy-handle"))
596 external_mdio_mask |= BIT(reg);
597 else
598 internal_mdio_mask |= BIT(reg);
599 }
600
601 of_node_put(ports);
602 if (!external_mdio_mask && !internal_mdio_mask) {
603 dev_err(priv->dev, "no PHYs are defined.\n");
604 return -EINVAL;
605 }
606
607 /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through
608 * the MDIO_MASTER register also _disconnects_ the external MDC
609 * passthrough to the internal PHYs. It's not possible to use both
610 * configurations at the same time!
611 *
612 * Because this came up during the review process:
613 * If the external mdio-bus driver is capable magically disabling
614 * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's
615 * accessors for the time being, it would be possible to pull this
616 * off.
617 */
618 if (!!external_mdio_mask && !!internal_mdio_mask) {
619 dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n");
620 return -EINVAL;
621 }
622
623 if (external_mdio_mask) {
624 /* Make sure to disable the internal mdio bus in cases
625 * a dt-overlay and driver reload changed the configuration
626 */
627
628 qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,
629 QCA8K_MDIO_MASTER_EN);
630 return 0;
631 }
632
633 priv->ops.phy_read = qca8k_phy_read;
634 priv->ops.phy_write = qca8k_phy_write;
635 return 0;
636}
637
638static int
639qca8k_setup(struct dsa_switch *ds)
640{
641 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
642 int ret, i, phy_mode = -1;
643 u32 mask;
644
645 /* Make sure that port 0 is the cpu port */
646 if (!dsa_is_cpu_port(ds, 0)) {
647 pr_err("port 0 is not the CPU port\n");
648 return -EINVAL;
649 }
650
651 mutex_init(&priv->reg_mutex);
652
653 /* Start by setting up the register mapping */
654 priv->regmap = devm_regmap_init(ds->dev, NULL, priv,
655 &qca8k_regmap_config);
656 if (IS_ERR(priv->regmap))
657 pr_warn("regmap initialization failed");
658
659 ret = qca8k_setup_mdio_bus(priv);
660 if (ret)
661 return ret;
662
663 /* Initialize CPU port pad mode (xMII type, delays...) */
664 phy_mode = of_get_phy_mode(ds->ports[QCA8K_CPU_PORT].dn);
665 if (phy_mode < 0) {
666 pr_err("Can't find phy-mode for master device\n");
667 return phy_mode;
668 }
669 ret = qca8k_set_pad_ctrl(priv, QCA8K_CPU_PORT, phy_mode);
670 if (ret < 0)
671 return ret;
672
673 /* Enable CPU Port, force it to maximum bandwidth and full-duplex */
674 mask = QCA8K_PORT_STATUS_SPEED_1000 | QCA8K_PORT_STATUS_TXFLOW |
675 QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_DUPLEX;
676 qca8k_write(priv, QCA8K_REG_PORT_STATUS(QCA8K_CPU_PORT), mask);
677 qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
678 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
679 qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1);
680 priv->port_sts[QCA8K_CPU_PORT].enabled = 1;
681
682 /* Enable MIB counters */
683 qca8k_mib_init(priv);
684
685 /* Enable QCA header mode on the cpu port */
686 qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
687 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
688 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
689
690 /* Disable forwarding by default on all ports */
691 for (i = 0; i < QCA8K_NUM_PORTS; i++)
692 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
693 QCA8K_PORT_LOOKUP_MEMBER, 0);
694
695 /* Disable MAC by default on all user ports */
696 for (i = 1; i < QCA8K_NUM_PORTS; i++)
697 if (dsa_is_user_port(ds, i))
698 qca8k_port_set_status(priv, i, 0);
699
700 /* Forward all unknown frames to CPU port for Linux processing */
701 qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
702 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
703 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
704 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
705 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
706
707 /* Setup connection between CPU port & user ports */
708 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
709 /* CPU port gets connected to all user ports of the switch */
710 if (dsa_is_cpu_port(ds, i)) {
711 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
712 QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
713 }
714
715 /* Invividual user ports get connected to CPU port only */
716 if (dsa_is_user_port(ds, i)) {
717 int shift = 16 * (i % 2);
718
719 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
720 QCA8K_PORT_LOOKUP_MEMBER,
721 BIT(QCA8K_CPU_PORT));
722
723 /* Enable ARP Auto-learning by default */
724 qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
725 QCA8K_PORT_LOOKUP_LEARN);
726
727 /* For port based vlans to work we need to set the
728 * default egress vid
729 */
730 qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
731 0xffff << shift, 1 << shift);
732 qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
733 QCA8K_PORT_VLAN_CVID(1) |
734 QCA8K_PORT_VLAN_SVID(1));
735 }
736 }
737
738 /* Flush the FDB table */
739 qca8k_fdb_flush(priv);
740
741 return 0;
742}
743
744static void
745qca8k_adjust_link(struct dsa_switch *ds, int port, struct phy_device *phy)
746{
747 struct qca8k_priv *priv = ds->priv;
748 u32 reg;
749
750 /* Force fixed-link setting for CPU port, skip others. */
751 if (!phy_is_pseudo_fixed_link(phy))
752 return;
753
754 /* Set port speed */
755 switch (phy->speed) {
756 case 10:
757 reg = QCA8K_PORT_STATUS_SPEED_10;
758 break;
759 case 100:
760 reg = QCA8K_PORT_STATUS_SPEED_100;
761 break;
762 case 1000:
763 reg = QCA8K_PORT_STATUS_SPEED_1000;
764 break;
765 default:
766 dev_dbg(priv->dev, "port%d link speed %dMbps not supported.\n",
767 port, phy->speed);
768 return;
769 }
770
771 /* Set duplex mode */
772 if (phy->duplex == DUPLEX_FULL)
773 reg |= QCA8K_PORT_STATUS_DUPLEX;
774
775 /* Force flow control */
776 if (dsa_is_cpu_port(ds, port))
777 reg |= QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_TXFLOW;
778
779 /* Force link down before changing MAC options */
780 qca8k_port_set_status(priv, port, 0);
781 qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
782 qca8k_port_set_status(priv, port, 1);
783}
784
785static void
786qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
787{
788 int i;
789
790 if (stringset != ETH_SS_STATS)
791 return;
792
793 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
794 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
795 ETH_GSTRING_LEN);
796}
797
798static void
799qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
800 uint64_t *data)
801{
802 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
803 const struct qca8k_mib_desc *mib;
804 u32 reg, i;
805 u64 hi;
806
807 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
808 mib = &ar8327_mib[i];
809 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
810
811 data[i] = qca8k_read(priv, reg);
812 if (mib->size == 2) {
813 hi = qca8k_read(priv, reg + 4);
814 data[i] |= hi << 32;
815 }
816 }
817}
818
819static int
820qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
821{
822 if (sset != ETH_SS_STATS)
823 return 0;
824
825 return ARRAY_SIZE(ar8327_mib);
826}
827
828static int
829qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
830{
831 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
832 u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
833 u32 reg;
834
835 mutex_lock(&priv->reg_mutex);
836 reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);
837 if (eee->eee_enabled)
838 reg |= lpi_en;
839 else
840 reg &= ~lpi_en;
841 qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
842 mutex_unlock(&priv->reg_mutex);
843
844 return 0;
845}
846
847static int
848qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
849{
850 /* Nothing to do on the port's MAC */
851 return 0;
852}
853
854static void
855qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
856{
857 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
858 u32 stp_state;
859
860 switch (state) {
861 case BR_STATE_DISABLED:
862 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
863 break;
864 case BR_STATE_BLOCKING:
865 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
866 break;
867 case BR_STATE_LISTENING:
868 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
869 break;
870 case BR_STATE_LEARNING:
871 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
872 break;
873 case BR_STATE_FORWARDING:
874 default:
875 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
876 break;
877 }
878
879 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
880 QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
881}
882
883static int
884qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
885{
886 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
887 int port_mask = BIT(QCA8K_CPU_PORT);
888 int i;
889
890 for (i = 1; i < QCA8K_NUM_PORTS; i++) {
891 if (dsa_to_port(ds, i)->bridge_dev != br)
892 continue;
893 /* Add this port to the portvlan mask of the other ports
894 * in the bridge
895 */
896 qca8k_reg_set(priv,
897 QCA8K_PORT_LOOKUP_CTRL(i),
898 BIT(port));
899 if (i != port)
900 port_mask |= BIT(i);
901 }
902 /* Add all other ports to this ports portvlan mask */
903 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
904 QCA8K_PORT_LOOKUP_MEMBER, port_mask);
905
906 return 0;
907}
908
909static void
910qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
911{
912 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
913 int i;
914
915 for (i = 1; i < QCA8K_NUM_PORTS; i++) {
916 if (dsa_to_port(ds, i)->bridge_dev != br)
917 continue;
918 /* Remove this port to the portvlan mask of the other ports
919 * in the bridge
920 */
921 qca8k_reg_clear(priv,
922 QCA8K_PORT_LOOKUP_CTRL(i),
923 BIT(port));
924 }
925
926 /* Set the cpu port to be the only one in the portvlan mask of
927 * this port
928 */
929 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
930 QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT));
931}
932
933static int
934qca8k_port_enable(struct dsa_switch *ds, int port,
935 struct phy_device *phy)
936{
937 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
938
939 if (!dsa_is_user_port(ds, port))
940 return 0;
941
942 qca8k_port_set_status(priv, port, 1);
943 priv->port_sts[port].enabled = 1;
944
945 phy_support_asym_pause(phy);
946
947 return 0;
948}
949
950static void
951qca8k_port_disable(struct dsa_switch *ds, int port)
952{
953 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
954
955 qca8k_port_set_status(priv, port, 0);
956 priv->port_sts[port].enabled = 0;
957}
958
959static int
960qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
961 u16 port_mask, u16 vid)
962{
963 /* Set the vid to the port vlan id if no vid is set */
964 if (!vid)
965 vid = 1;
966
967 return qca8k_fdb_add(priv, addr, port_mask, vid,
968 QCA8K_ATU_STATUS_STATIC);
969}
970
971static int
972qca8k_port_fdb_add(struct dsa_switch *ds, int port,
973 const unsigned char *addr, u16 vid)
974{
975 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
976 u16 port_mask = BIT(port);
977
978 return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
979}
980
981static int
982qca8k_port_fdb_del(struct dsa_switch *ds, int port,
983 const unsigned char *addr, u16 vid)
984{
985 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
986 u16 port_mask = BIT(port);
987
988 if (!vid)
989 vid = 1;
990
991 return qca8k_fdb_del(priv, addr, port_mask, vid);
992}
993
994static int
995qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
996 dsa_fdb_dump_cb_t *cb, void *data)
997{
998 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
999 struct qca8k_fdb _fdb = { 0 };
1000 int cnt = QCA8K_NUM_FDB_RECORDS;
1001 bool is_static;
1002 int ret = 0;
1003
1004 mutex_lock(&priv->reg_mutex);
1005 while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
1006 if (!_fdb.aging)
1007 break;
1008 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
1009 ret = cb(_fdb.mac, _fdb.vid, is_static, data);
1010 if (ret)
1011 break;
1012 }
1013 mutex_unlock(&priv->reg_mutex);
1014
1015 return 0;
1016}
1017
1018static enum dsa_tag_protocol
1019qca8k_get_tag_protocol(struct dsa_switch *ds, int port)
1020{
1021 return DSA_TAG_PROTO_QCA;
1022}
1023
1024static const struct dsa_switch_ops qca8k_switch_ops = {
1025 .get_tag_protocol = qca8k_get_tag_protocol,
1026 .setup = qca8k_setup,
1027 .adjust_link = qca8k_adjust_link,
1028 .get_strings = qca8k_get_strings,
1029 .get_ethtool_stats = qca8k_get_ethtool_stats,
1030 .get_sset_count = qca8k_get_sset_count,
1031 .get_mac_eee = qca8k_get_mac_eee,
1032 .set_mac_eee = qca8k_set_mac_eee,
1033 .port_enable = qca8k_port_enable,
1034 .port_disable = qca8k_port_disable,
1035 .port_stp_state_set = qca8k_port_stp_state_set,
1036 .port_bridge_join = qca8k_port_bridge_join,
1037 .port_bridge_leave = qca8k_port_bridge_leave,
1038 .port_fdb_add = qca8k_port_fdb_add,
1039 .port_fdb_del = qca8k_port_fdb_del,
1040 .port_fdb_dump = qca8k_port_fdb_dump,
1041};
1042
1043static int
1044qca8k_sw_probe(struct mdio_device *mdiodev)
1045{
1046 struct qca8k_priv *priv;
1047 u32 id;
1048
1049 /* allocate the private data struct so that we can probe the switches
1050 * ID register
1051 */
1052 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1053 if (!priv)
1054 return -ENOMEM;
1055
1056 priv->bus = mdiodev->bus;
1057 priv->dev = &mdiodev->dev;
1058
1059 priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset",
1060 GPIOD_ASIS);
1061 if (IS_ERR(priv->reset_gpio))
1062 return PTR_ERR(priv->reset_gpio);
1063
1064 if (priv->reset_gpio) {
1065 gpiod_set_value_cansleep(priv->reset_gpio, 1);
1066 /* The active low duration must be greater than 10 ms
1067 * and checkpatch.pl wants 20 ms.
1068 */
1069 msleep(20);
1070 gpiod_set_value_cansleep(priv->reset_gpio, 0);
1071 }
1072
1073 /* read the switches ID register */
1074 id = qca8k_read(priv, QCA8K_REG_MASK_CTRL);
1075 id >>= QCA8K_MASK_CTRL_ID_S;
1076 id &= QCA8K_MASK_CTRL_ID_M;
1077 if (id != QCA8K_ID_QCA8337)
1078 return -ENODEV;
1079
1080 priv->ds = dsa_switch_alloc(&mdiodev->dev, QCA8K_NUM_PORTS);
1081 if (!priv->ds)
1082 return -ENOMEM;
1083
1084 priv->ds->priv = priv;
1085 priv->ops = qca8k_switch_ops;
1086 priv->ds->ops = &priv->ops;
1087 mutex_init(&priv->reg_mutex);
1088 dev_set_drvdata(&mdiodev->dev, priv);
1089
1090 return dsa_register_switch(priv->ds);
1091}
1092
1093static void
1094qca8k_sw_remove(struct mdio_device *mdiodev)
1095{
1096 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
1097 int i;
1098
1099 for (i = 0; i < QCA8K_NUM_PORTS; i++)
1100 qca8k_port_set_status(priv, i, 0);
1101
1102 dsa_unregister_switch(priv->ds);
1103}
1104
1105#ifdef CONFIG_PM_SLEEP
1106static void
1107qca8k_set_pm(struct qca8k_priv *priv, int enable)
1108{
1109 int i;
1110
1111 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1112 if (!priv->port_sts[i].enabled)
1113 continue;
1114
1115 qca8k_port_set_status(priv, i, enable);
1116 }
1117}
1118
1119static int qca8k_suspend(struct device *dev)
1120{
1121 struct qca8k_priv *priv = dev_get_drvdata(dev);
1122
1123 qca8k_set_pm(priv, 0);
1124
1125 return dsa_switch_suspend(priv->ds);
1126}
1127
1128static int qca8k_resume(struct device *dev)
1129{
1130 struct qca8k_priv *priv = dev_get_drvdata(dev);
1131
1132 qca8k_set_pm(priv, 1);
1133
1134 return dsa_switch_resume(priv->ds);
1135}
1136#endif /* CONFIG_PM_SLEEP */
1137
1138static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
1139 qca8k_suspend, qca8k_resume);
1140
1141static const struct of_device_id qca8k_of_match[] = {
1142 { .compatible = "qca,qca8334" },
1143 { .compatible = "qca,qca8337" },
1144 { /* sentinel */ },
1145};
1146
1147static struct mdio_driver qca8kmdio_driver = {
1148 .probe = qca8k_sw_probe,
1149 .remove = qca8k_sw_remove,
1150 .mdiodrv.driver = {
1151 .name = "qca8k",
1152 .of_match_table = qca8k_of_match,
1153 .pm = &qca8k_pm_ops,
1154 },
1155};
1156
1157mdio_module_driver(qca8kmdio_driver);
1158
1159MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
1160MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
1161MODULE_LICENSE("GPL v2");
1162MODULE_ALIAS("platform:qca8k");