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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
4 */
5
6#ifndef __MT7530_H
7#define __MT7530_H
8
9#define MT7530_NUM_PORTS 7
10#define MT7530_CPU_PORT 6
11#define MT7530_NUM_FDB_RECORDS 2048
12#define MT7530_ALL_MEMBERS 0xff
13
14enum {
15 ID_MT7530 = 0,
16 ID_MT7621 = 1,
17};
18
19#define NUM_TRGMII_CTRL 5
20
21#define TRGMII_BASE(x) (0x10000 + (x))
22
23/* Registers to ethsys access */
24#define ETHSYS_CLKCFG0 0x2c
25#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
26
27#define SYSC_REG_RSTCTRL 0x34
28#define RESET_MCM BIT(2)
29
30/* Registers to mac forward control for unknown frames */
31#define MT7530_MFC 0x10
32#define BC_FFP(x) (((x) & 0xff) << 24)
33#define UNM_FFP(x) (((x) & 0xff) << 16)
34#define UNU_FFP(x) (((x) & 0xff) << 8)
35#define UNU_FFP_MASK UNU_FFP(~0)
36#define CPU_EN BIT(7)
37#define CPU_PORT(x) ((x) << 4)
38#define CPU_MASK (0xf << 4)
39
40/* Registers for address table access */
41#define MT7530_ATA1 0x74
42#define STATIC_EMP 0
43#define STATIC_ENT 3
44#define MT7530_ATA2 0x78
45
46/* Register for address table write data */
47#define MT7530_ATWD 0x7c
48
49/* Register for address table control */
50#define MT7530_ATC 0x80
51#define ATC_HASH (((x) & 0xfff) << 16)
52#define ATC_BUSY BIT(15)
53#define ATC_SRCH_END BIT(14)
54#define ATC_SRCH_HIT BIT(13)
55#define ATC_INVALID BIT(12)
56#define ATC_MAT(x) (((x) & 0xf) << 8)
57#define ATC_MAT_MACTAB ATC_MAT(0)
58
59enum mt7530_fdb_cmd {
60 MT7530_FDB_READ = 0,
61 MT7530_FDB_WRITE = 1,
62 MT7530_FDB_FLUSH = 2,
63 MT7530_FDB_START = 4,
64 MT7530_FDB_NEXT = 5,
65};
66
67/* Registers for table search read address */
68#define MT7530_TSRA1 0x84
69#define MAC_BYTE_0 24
70#define MAC_BYTE_1 16
71#define MAC_BYTE_2 8
72#define MAC_BYTE_3 0
73#define MAC_BYTE_MASK 0xff
74
75#define MT7530_TSRA2 0x88
76#define MAC_BYTE_4 24
77#define MAC_BYTE_5 16
78#define CVID 0
79#define CVID_MASK 0xfff
80
81#define MT7530_ATRD 0x8C
82#define AGE_TIMER 24
83#define AGE_TIMER_MASK 0xff
84#define PORT_MAP 4
85#define PORT_MAP_MASK 0xff
86#define ENT_STATUS 2
87#define ENT_STATUS_MASK 0x3
88
89/* Register for vlan table control */
90#define MT7530_VTCR 0x90
91#define VTCR_BUSY BIT(31)
92#define VTCR_INVALID BIT(16)
93#define VTCR_FUNC(x) (((x) & 0xf) << 12)
94#define VTCR_VID ((x) & 0xfff)
95
96enum mt7530_vlan_cmd {
97 /* Read/Write the specified VID entry from VAWD register based
98 * on VID.
99 */
100 MT7530_VTCR_RD_VID = 0,
101 MT7530_VTCR_WR_VID = 1,
102};
103
104/* Register for setup vlan and acl write data */
105#define MT7530_VAWD1 0x94
106#define PORT_STAG BIT(31)
107/* Independent VLAN Learning */
108#define IVL_MAC BIT(30)
109/* Per VLAN Egress Tag Control */
110#define VTAG_EN BIT(28)
111/* VLAN Member Control */
112#define PORT_MEM(x) (((x) & 0xff) << 16)
113/* VLAN Entry Valid */
114#define VLAN_VALID BIT(0)
115#define PORT_MEM_SHFT 16
116#define PORT_MEM_MASK 0xff
117
118#define MT7530_VAWD2 0x98
119/* Egress Tag Control */
120#define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
121#define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3)
122
123enum mt7530_vlan_egress_attr {
124 MT7530_VLAN_EGRESS_UNTAG = 0,
125 MT7530_VLAN_EGRESS_TAG = 2,
126 MT7530_VLAN_EGRESS_STACK = 3,
127};
128
129/* Register for port STP state control */
130#define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
131#define FID_PST(x) ((x) & 0x3)
132#define FID_PST_MASK FID_PST(0x3)
133
134enum mt7530_stp_state {
135 MT7530_STP_DISABLED = 0,
136 MT7530_STP_BLOCKING = 1,
137 MT7530_STP_LISTENING = 1,
138 MT7530_STP_LEARNING = 2,
139 MT7530_STP_FORWARDING = 3
140};
141
142/* Register for port control */
143#define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
144#define PORT_VLAN(x) ((x) & 0x3)
145
146enum mt7530_port_mode {
147 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
148 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
149
150 /* Security Mode: Discard any frame due to ingress membership
151 * violation or VID missed on the VLAN table.
152 */
153 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3),
154};
155
156#define PCR_MATRIX(x) (((x) & 0xff) << 16)
157#define PORT_PRI(x) (((x) & 0x7) << 24)
158#define EG_TAG(x) (((x) & 0x3) << 28)
159#define PCR_MATRIX_MASK PCR_MATRIX(0xff)
160#define PCR_MATRIX_CLR PCR_MATRIX(0)
161#define PCR_PORT_VLAN_MASK PORT_VLAN(3)
162
163/* Register for port security control */
164#define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
165#define SA_DIS BIT(4)
166
167/* Register for port vlan control */
168#define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
169#define PORT_SPEC_TAG BIT(5)
170#define VLAN_ATTR(x) (((x) & 0x3) << 6)
171#define VLAN_ATTR_MASK VLAN_ATTR(3)
172
173enum mt7530_vlan_port_attr {
174 MT7530_VLAN_USER = 0,
175 MT7530_VLAN_TRANSPARENT = 3,
176};
177
178#define STAG_VPID (((x) & 0xffff) << 16)
179
180/* Register for port port-and-protocol based vlan 1 control */
181#define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
182#define G0_PORT_VID(x) (((x) & 0xfff) << 0)
183#define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
184#define G0_PORT_VID_DEF G0_PORT_VID(1)
185
186/* Register for port MAC control register */
187#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
188#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
189#define PMCR_EXT_PHY BIT(17)
190#define PMCR_MAC_MODE BIT(16)
191#define PMCR_FORCE_MODE BIT(15)
192#define PMCR_TX_EN BIT(14)
193#define PMCR_RX_EN BIT(13)
194#define PMCR_BACKOFF_EN BIT(9)
195#define PMCR_BACKPR_EN BIT(8)
196#define PMCR_TX_FC_EN BIT(5)
197#define PMCR_RX_FC_EN BIT(4)
198#define PMCR_FORCE_SPEED_1000 BIT(3)
199#define PMCR_FORCE_SPEED_100 BIT(2)
200#define PMCR_FORCE_FDX BIT(1)
201#define PMCR_FORCE_LNK BIT(0)
202#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
203 PMCR_FORCE_SPEED_1000)
204
205#define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
206#define PMSR_EEE1G BIT(7)
207#define PMSR_EEE100M BIT(6)
208#define PMSR_RX_FC BIT(5)
209#define PMSR_TX_FC BIT(4)
210#define PMSR_SPEED_1000 BIT(3)
211#define PMSR_SPEED_100 BIT(2)
212#define PMSR_SPEED_10 0x00
213#define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000)
214#define PMSR_DPX BIT(1)
215#define PMSR_LINK BIT(0)
216
217/* Register for MIB */
218#define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
219#define MT7530_MIB_CCR 0x4fe0
220#define CCR_MIB_ENABLE BIT(31)
221#define CCR_RX_OCT_CNT_GOOD BIT(7)
222#define CCR_RX_OCT_CNT_BAD BIT(6)
223#define CCR_TX_OCT_CNT_GOOD BIT(5)
224#define CCR_TX_OCT_CNT_BAD BIT(4)
225#define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \
226 CCR_RX_OCT_CNT_BAD | \
227 CCR_TX_OCT_CNT_GOOD | \
228 CCR_TX_OCT_CNT_BAD)
229#define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \
230 CCR_RX_OCT_CNT_GOOD | \
231 CCR_RX_OCT_CNT_BAD | \
232 CCR_TX_OCT_CNT_GOOD | \
233 CCR_TX_OCT_CNT_BAD)
234/* Register for system reset */
235#define MT7530_SYS_CTRL 0x7000
236#define SYS_CTRL_PHY_RST BIT(2)
237#define SYS_CTRL_SW_RST BIT(1)
238#define SYS_CTRL_REG_RST BIT(0)
239
240/* Register for hw trap status */
241#define MT7530_HWTRAP 0x7800
242#define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
243#define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9))
244#define HWTRAP_XTAL_40MHZ (BIT(10))
245#define HWTRAP_XTAL_20MHZ (BIT(9))
246
247/* Register for hw trap modification */
248#define MT7530_MHWTRAP 0x7804
249#define MHWTRAP_PHY0_SEL BIT(20)
250#define MHWTRAP_MANUAL BIT(16)
251#define MHWTRAP_P5_MAC_SEL BIT(13)
252#define MHWTRAP_P6_DIS BIT(8)
253#define MHWTRAP_P5_RGMII_MODE BIT(7)
254#define MHWTRAP_P5_DIS BIT(6)
255#define MHWTRAP_PHY_ACCESS BIT(5)
256
257/* Register for TOP signal control */
258#define MT7530_TOP_SIG_CTRL 0x7808
259#define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
260
261#define MT7530_IO_DRV_CR 0x7810
262#define P5_IO_CLK_DRV(x) ((x) & 0x3)
263#define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
264
265#define MT7530_P6ECR 0x7830
266#define P6_INTF_MODE_MASK 0x3
267#define P6_INTF_MODE(x) ((x) & 0x3)
268
269/* Registers for TRGMII on the both side */
270#define MT7530_TRGMII_RCK_CTRL 0x7a00
271#define GSW_TRGMII_RCK_CTRL 0x300
272#define RX_RST BIT(31)
273#define RXC_DQSISEL BIT(30)
274#define DQSI1_TAP_MASK (0x7f << 8)
275#define DQSI0_TAP_MASK 0x7f
276#define DQSI1_TAP(x) (((x) & 0x7f) << 8)
277#define DQSI0_TAP(x) ((x) & 0x7f)
278
279#define MT7530_TRGMII_RCK_RTT 0x7a04
280#define GSW_TRGMII_RCK_RTT 0x304
281#define DQS1_GATE BIT(31)
282#define DQS0_GATE BIT(30)
283
284#define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
285#define GSW_TRGMII_RD(x) (0x310 + (x) * 8)
286#define BSLIP_EN BIT(31)
287#define EDGE_CHK BIT(30)
288#define RD_TAP_MASK 0x7f
289#define RD_TAP(x) ((x) & 0x7f)
290
291#define GSW_TRGMII_TXCTRL 0x340
292#define MT7530_TRGMII_TXCTRL 0x7a40
293#define TRAIN_TXEN BIT(31)
294#define TXC_INV BIT(30)
295#define TX_RST BIT(28)
296
297#define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
298#define GSW_TRGMII_TD_ODT(i) (0x354 + 8 * (i))
299#define TD_DM_DRVP(x) ((x) & 0xf)
300#define TD_DM_DRVN(x) (((x) & 0xf) << 4)
301
302#define GSW_INTF_MODE 0x390
303#define INTF_MODE_TRGMII BIT(1)
304
305#define MT7530_TRGMII_TCK_CTRL 0x7a78
306#define TCK_TAP(x) (((x) & 0xf) << 8)
307
308#define MT7530_P5RGMIIRXCR 0x7b00
309#define CSR_RGMII_EDGE_ALIGN BIT(8)
310#define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf)
311
312#define MT7530_P5RGMIITXCR 0x7b04
313#define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
314
315#define MT7530_CREV 0x7ffc
316#define CHIP_NAME_SHIFT 16
317#define MT7530_ID 0x7530
318
319/* Registers for core PLL access through mmd indirect */
320#define CORE_PLL_GROUP2 0x401
321#define RG_SYSPLL_EN_NORMAL BIT(15)
322#define RG_SYSPLL_VODEN BIT(14)
323#define RG_SYSPLL_LF BIT(13)
324#define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12)
325#define RG_SYSPLL_LVROD_EN BIT(10)
326#define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8)
327#define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5)
328#define RG_SYSPLL_FBKSEL BIT(4)
329#define RT_SYSPLL_EN_AFE_OLT BIT(0)
330
331#define CORE_PLL_GROUP4 0x403
332#define RG_SYSPLL_DDSFBK_EN BIT(12)
333#define RG_SYSPLL_BIAS_EN BIT(11)
334#define RG_SYSPLL_BIAS_LPF_EN BIT(10)
335
336#define CORE_PLL_GROUP5 0x404
337#define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
338
339#define CORE_PLL_GROUP6 0x405
340#define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff)
341
342#define CORE_PLL_GROUP7 0x406
343#define RG_LCDDS_PWDB BIT(15)
344#define RG_LCDDS_ISO_EN BIT(13)
345#define RG_LCCDS_C(x) (((x) & 0x7) << 4)
346#define RG_LCDDS_PCW_NCPO_CHG BIT(3)
347
348#define CORE_PLL_GROUP10 0x409
349#define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff)
350
351#define CORE_PLL_GROUP11 0x40a
352#define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff)
353
354#define CORE_GSWPLL_GRP1 0x40d
355#define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14)
356#define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12)
357#define RG_GSWPLL_EN_PRE BIT(11)
358#define RG_GSWPLL_FBKSEL BIT(10)
359#define RG_GSWPLL_BP BIT(9)
360#define RG_GSWPLL_BR BIT(8)
361#define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff)
362
363#define CORE_GSWPLL_GRP2 0x40e
364#define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8)
365#define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff)
366
367#define CORE_TRGMII_GSW_CLK_CG 0x410
368#define REG_GSWCK_EN BIT(0)
369#define REG_TRGMIICK_EN BIT(1)
370
371#define MIB_DESC(_s, _o, _n) \
372 { \
373 .size = (_s), \
374 .offset = (_o), \
375 .name = (_n), \
376 }
377
378struct mt7530_mib_desc {
379 unsigned int size;
380 unsigned int offset;
381 const char *name;
382};
383
384struct mt7530_fdb {
385 u16 vid;
386 u8 port_mask;
387 u8 aging;
388 u8 mac[6];
389 bool noarp;
390};
391
392/* struct mt7530_port - This is the main data structure for holding the state
393 * of the port.
394 * @enable: The status used for show port is enabled or not.
395 * @pm: The matrix used to show all connections with the port.
396 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any
397 * untagged frames will be assigned to the related VLAN.
398 * @vlan_filtering: The flags indicating whether the port that can recognize
399 * VLAN-tagged frames.
400 */
401struct mt7530_port {
402 bool enable;
403 u32 pm;
404 u16 pvid;
405};
406
407/* Port 5 interface select definitions */
408enum p5_interface_select {
409 P5_DISABLED = 0,
410 P5_INTF_SEL_PHY_P0,
411 P5_INTF_SEL_PHY_P4,
412 P5_INTF_SEL_GMAC5,
413};
414
415static const char *p5_intf_modes(unsigned int p5_interface)
416{
417 switch (p5_interface) {
418 case P5_DISABLED:
419 return "DISABLED";
420 case P5_INTF_SEL_PHY_P0:
421 return "PHY P0";
422 case P5_INTF_SEL_PHY_P4:
423 return "PHY P4";
424 case P5_INTF_SEL_GMAC5:
425 return "GMAC5";
426 default:
427 return "unknown";
428 }
429}
430
431/* struct mt7530_priv - This is the main data structure for holding the state
432 * of the driver
433 * @dev: The device pointer
434 * @ds: The pointer to the dsa core structure
435 * @bus: The bus used for the device and built-in PHY
436 * @rstc: The pointer to reset control used by MCM
437 * @ethernet: The regmap used for access TRGMII-based registers
438 * @core_pwr: The power supplied into the core
439 * @io_pwr: The power supplied into the I/O
440 * @reset: The descriptor for GPIO line tied to its reset pin
441 * @mcm: Flag for distinguishing if standalone IC or module
442 * coupling
443 * @ports: Holding the state among ports
444 * @reg_mutex: The lock for protecting among process accessing
445 * registers
446 * @p6_interface Holding the current port 6 interface
447 * @p5_intf_sel: Holding the current port 5 interface select
448 */
449struct mt7530_priv {
450 struct device *dev;
451 struct dsa_switch *ds;
452 struct mii_bus *bus;
453 struct reset_control *rstc;
454 struct regmap *ethernet;
455 struct regulator *core_pwr;
456 struct regulator *io_pwr;
457 struct gpio_desc *reset;
458 unsigned int id;
459 bool mcm;
460 phy_interface_t p6_interface;
461 phy_interface_t p5_interface;
462 unsigned int p5_intf_sel;
463
464 struct mt7530_port ports[MT7530_NUM_PORTS];
465 /* protect among processes for registers access*/
466 struct mutex reg_mutex;
467};
468
469struct mt7530_hw_vlan_entry {
470 int port;
471 u8 old_members;
472 bool untagged;
473};
474
475static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
476 int port, bool untagged)
477{
478 e->port = port;
479 e->untagged = untagged;
480}
481
482typedef void (*mt7530_vlan_op)(struct mt7530_priv *,
483 struct mt7530_hw_vlan_entry *);
484
485struct mt7530_hw_stats {
486 const char *string;
487 u16 reg;
488 u8 sizeof_stat;
489};
490
491struct mt7530_dummy_poll {
492 struct mt7530_priv *priv;
493 u32 reg;
494};
495
496static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p,
497 struct mt7530_priv *priv, u32 reg)
498{
499 p->priv = priv;
500 p->reg = reg;
501}
502
503#endif /* __MT7530_H */