1/*
 2 * Code specific to PKUnity SoC and UniCore ISA
 3 *
 4 *	Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn>
 5 *	Copyright (C) 2001-2011 Guan Xuetao
 6 *
 7 * This program is free software; you can redistribute it and/or modify
 8 * it under the terms of the GNU General Public License version 2 as
 9 * published by the Free Software Foundation.
10 */
11#ifndef _I8042_UNICORE32_H
12#define _I8042_UNICORE32_H
13
14#include <mach/hardware.h>
15
16/*
17 * Names.
18 */
19#define I8042_KBD_PHYS_DESC "isa0060/serio0"
20#define I8042_AUX_PHYS_DESC "isa0060/serio1"
21#define I8042_MUX_PHYS_DESC "isa0060/serio%d"
22
23/*
24 * IRQs.
25 */
26#define I8042_KBD_IRQ           IRQ_PS2_KBD
27#define I8042_AUX_IRQ           IRQ_PS2_AUX
28
29/*
30 * Register numbers.
31 */
32#define I8042_COMMAND_REG	PS2_COMMAND
33#define I8042_STATUS_REG	PS2_STATUS
34#define I8042_DATA_REG		PS2_DATA
35
36#define I8042_REGION_START	(resource_size_t)(PS2_DATA)
37#define I8042_REGION_SIZE	(resource_size_t)(16)
38
39static inline int i8042_read_data(void)
40{
41	return readb(I8042_DATA_REG);
42}
43
44static inline int i8042_read_status(void)
45{
46	return readb(I8042_STATUS_REG);
47}
48
49static inline void i8042_write_data(int val)
50{
51	writeb(val, I8042_DATA_REG);
52}
53
54static inline void i8042_write_command(int val)
55{
56	writeb(val, I8042_COMMAND_REG);
57}
58
59static inline int i8042_platform_init(void)
60{
61	if (!request_mem_region(I8042_REGION_START, I8042_REGION_SIZE, "i8042"))
62		return -EBUSY;
63
64	i8042_reset = 1;
65	return 0;
66}
67
68static inline void i8042_platform_exit(void)
69{
70	release_mem_region(I8042_REGION_START, I8042_REGION_SIZE);
71}
72
73#endif /* _I8042_UNICORE32_H */

 1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Code specific to PKUnity SoC and UniCore ISA
 4 *
 5 *	Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn>
 6 *	Copyright (C) 2001-2011 Guan Xuetao
 
 
 
 
 7 */
 8#ifndef _I8042_UNICORE32_H
 9#define _I8042_UNICORE32_H
10
11#include <mach/hardware.h>
12
13/*
14 * Names.
15 */
16#define I8042_KBD_PHYS_DESC "isa0060/serio0"
17#define I8042_AUX_PHYS_DESC "isa0060/serio1"
18#define I8042_MUX_PHYS_DESC "isa0060/serio%d"
19
20/*
21 * IRQs.
22 */
23#define I8042_KBD_IRQ           IRQ_PS2_KBD
24#define I8042_AUX_IRQ           IRQ_PS2_AUX
25
26/*
27 * Register numbers.
28 */
29#define I8042_COMMAND_REG	PS2_COMMAND
30#define I8042_STATUS_REG	PS2_STATUS
31#define I8042_DATA_REG		PS2_DATA
32
33#define I8042_REGION_START	(resource_size_t)(PS2_DATA)
34#define I8042_REGION_SIZE	(resource_size_t)(16)
35
36static inline int i8042_read_data(void)
37{
38	return readb(I8042_DATA_REG);
39}
40
41static inline int i8042_read_status(void)
42{
43	return readb(I8042_STATUS_REG);
44}
45
46static inline void i8042_write_data(int val)
47{
48	writeb(val, I8042_DATA_REG);
49}
50
51static inline void i8042_write_command(int val)
52{
53	writeb(val, I8042_COMMAND_REG);
54}
55
56static inline int i8042_platform_init(void)
57{
58	if (!request_mem_region(I8042_REGION_START, I8042_REGION_SIZE, "i8042"))
59		return -EBUSY;
60
61	i8042_reset = I8042_RESET_ALWAYS;
62	return 0;
63}
64
65static inline void i8042_platform_exit(void)
66{
67	release_mem_region(I8042_REGION_START, I8042_REGION_SIZE);
68}
69
70#endif /* _I8042_UNICORE32_H */