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1/*
2 * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
3 *
4 * Copyright (C) 2010 Extreme Engineering Solutions.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/gpio.h>
26#include <linux/platform_device.h>
27#include <linux/mfd/lpc_ich.h>
28
29#define DRV_NAME "gpio_ich"
30
31/*
32 * GPIO register offsets in GPIO I/O space.
33 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
34 * LVLx registers. Logic in the read/write functions takes a register and
35 * an absolute bit number and determines the proper register offset and bit
36 * number in that register. For example, to read the value of GPIO bit 50
37 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
38 * bit 18 (50%32).
39 */
40enum GPIO_REG {
41 GPIO_USE_SEL = 0,
42 GPIO_IO_SEL,
43 GPIO_LVL,
44 GPO_BLINK
45};
46
47static const u8 ichx_regs[4][3] = {
48 {0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
49 {0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
50 {0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
51 {0x18, 0x18, 0x18}, /* BLINK offset */
52};
53
54static const u8 ichx_reglen[3] = {
55 0x30, 0x10, 0x10,
56};
57
58static const u8 avoton_regs[4][3] = {
59 {0x00, 0x80, 0x00},
60 {0x04, 0x84, 0x00},
61 {0x08, 0x88, 0x00},
62};
63
64static const u8 avoton_reglen[3] = {
65 0x10, 0x10, 0x00,
66};
67
68#define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
69#define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
70
71struct ichx_desc {
72 /* Max GPIO pins the chipset can have */
73 uint ngpio;
74
75 /* chipset registers */
76 const u8 (*regs)[3];
77 const u8 *reglen;
78
79 /* GPO_BLINK is available on this chipset */
80 bool have_blink;
81
82 /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
83 bool uses_gpe0;
84
85 /* USE_SEL is bogus on some chipsets, eg 3100 */
86 u32 use_sel_ignore[3];
87
88 /* Some chipsets have quirks, let these use their own request/get */
89 int (*request)(struct gpio_chip *chip, unsigned offset);
90 int (*get)(struct gpio_chip *chip, unsigned offset);
91
92 /*
93 * Some chipsets don't let reading output values on GPIO_LVL register
94 * this option allows driver caching written output values
95 */
96 bool use_outlvl_cache;
97};
98
99static struct {
100 spinlock_t lock;
101 struct platform_device *dev;
102 struct gpio_chip chip;
103 struct resource *gpio_base; /* GPIO IO base */
104 struct resource *pm_base; /* Power Mangagment IO base */
105 struct ichx_desc *desc; /* Pointer to chipset-specific description */
106 u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */
107 u8 use_gpio; /* Which GPIO groups are usable */
108 int outlvl_cache[3]; /* cached output values */
109} ichx_priv;
110
111static int modparam_gpiobase = -1; /* dynamic */
112module_param_named(gpiobase, modparam_gpiobase, int, 0444);
113MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
114 "which is the default.");
115
116static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
117{
118 unsigned long flags;
119 u32 data, tmp;
120 int reg_nr = nr / 32;
121 int bit = nr & 0x1f;
122 int ret = 0;
123
124 spin_lock_irqsave(&ichx_priv.lock, flags);
125
126 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
127 data = ichx_priv.outlvl_cache[reg_nr];
128 else
129 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
130 ichx_priv.gpio_base);
131
132 if (val)
133 data |= 1 << bit;
134 else
135 data &= ~(1 << bit);
136 ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
137 ichx_priv.gpio_base);
138 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
139 ichx_priv.outlvl_cache[reg_nr] = data;
140
141 tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
142 ichx_priv.gpio_base);
143 if (verify && data != tmp)
144 ret = -EPERM;
145
146 spin_unlock_irqrestore(&ichx_priv.lock, flags);
147
148 return ret;
149}
150
151static int ichx_read_bit(int reg, unsigned nr)
152{
153 unsigned long flags;
154 u32 data;
155 int reg_nr = nr / 32;
156 int bit = nr & 0x1f;
157
158 spin_lock_irqsave(&ichx_priv.lock, flags);
159
160 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
161 ichx_priv.gpio_base);
162
163 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
164 data = ichx_priv.outlvl_cache[reg_nr] | data;
165
166 spin_unlock_irqrestore(&ichx_priv.lock, flags);
167
168 return data & (1 << bit) ? 1 : 0;
169}
170
171static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
172{
173 return !!(ichx_priv.use_gpio & (1 << (nr / 32)));
174}
175
176static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
177{
178 /*
179 * Try setting pin as an input and verify it worked since many pins
180 * are output-only.
181 */
182 if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
183 return -EINVAL;
184
185 return 0;
186}
187
188static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
189 int val)
190{
191 /* Disable blink hardware which is available for GPIOs from 0 to 31. */
192 if (nr < 32 && ichx_priv.desc->have_blink)
193 ichx_write_bit(GPO_BLINK, nr, 0, 0);
194
195 /* Set GPIO output value. */
196 ichx_write_bit(GPIO_LVL, nr, val, 0);
197
198 /*
199 * Try setting pin as an output and verify it worked since many pins
200 * are input-only.
201 */
202 if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
203 return -EINVAL;
204
205 return 0;
206}
207
208static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
209{
210 return ichx_read_bit(GPIO_LVL, nr);
211}
212
213static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
214{
215 unsigned long flags;
216 u32 data;
217
218 /*
219 * GPI 0 - 15 need to be read from the power management registers on
220 * a ICH6/3100 bridge.
221 */
222 if (nr < 16) {
223 if (!ichx_priv.pm_base)
224 return -ENXIO;
225
226 spin_lock_irqsave(&ichx_priv.lock, flags);
227
228 /* GPI 0 - 15 are latched, write 1 to clear*/
229 ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);
230 data = ICHX_READ(0, ichx_priv.pm_base);
231
232 spin_unlock_irqrestore(&ichx_priv.lock, flags);
233
234 return (data >> 16) & (1 << nr) ? 1 : 0;
235 } else {
236 return ichx_gpio_get(chip, nr);
237 }
238}
239
240static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
241{
242 if (!ichx_gpio_check_available(chip, nr))
243 return -ENXIO;
244
245 /*
246 * Note we assume the BIOS properly set a bridge's USE value. Some
247 * chips (eg Intel 3100) have bogus USE values though, so first see if
248 * the chipset's USE value can be trusted for this specific bit.
249 * If it can't be trusted, assume that the pin can be used as a GPIO.
250 */
251 if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
252 return 0;
253
254 return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
255}
256
257static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
258{
259 /*
260 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
261 * bridge as they are controlled by USE register bits 0 and 1. See
262 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
263 * additional info.
264 */
265 if (nr == 16 || nr == 17)
266 nr -= 16;
267
268 return ichx_gpio_request(chip, nr);
269}
270
271static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
272{
273 ichx_write_bit(GPIO_LVL, nr, val, 0);
274}
275
276static void ichx_gpiolib_setup(struct gpio_chip *chip)
277{
278 chip->owner = THIS_MODULE;
279 chip->label = DRV_NAME;
280 chip->dev = &ichx_priv.dev->dev;
281
282 /* Allow chip-specific overrides of request()/get() */
283 chip->request = ichx_priv.desc->request ?
284 ichx_priv.desc->request : ichx_gpio_request;
285 chip->get = ichx_priv.desc->get ?
286 ichx_priv.desc->get : ichx_gpio_get;
287
288 chip->set = ichx_gpio_set;
289 chip->direction_input = ichx_gpio_direction_input;
290 chip->direction_output = ichx_gpio_direction_output;
291 chip->base = modparam_gpiobase;
292 chip->ngpio = ichx_priv.desc->ngpio;
293 chip->can_sleep = false;
294 chip->dbg_show = NULL;
295}
296
297/* ICH6-based, 631xesb-based */
298static struct ichx_desc ich6_desc = {
299 /* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
300 .request = ich6_gpio_request,
301 .get = ich6_gpio_get,
302
303 /* GPIO 0-15 are read in the GPE0_STS PM register */
304 .uses_gpe0 = true,
305
306 .ngpio = 50,
307 .have_blink = true,
308 .regs = ichx_regs,
309 .reglen = ichx_reglen,
310};
311
312/* Intel 3100 */
313static struct ichx_desc i3100_desc = {
314 /*
315 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
316 * the Intel 3100. See "Table 712. GPIO Summary Table" of 3100
317 * Datasheet for more info.
318 */
319 .use_sel_ignore = {0x00130000, 0x00010000, 0x0},
320
321 /* The 3100 needs fixups for GPIO 0 - 17 */
322 .request = ich6_gpio_request,
323 .get = ich6_gpio_get,
324
325 /* GPIO 0-15 are read in the GPE0_STS PM register */
326 .uses_gpe0 = true,
327
328 .ngpio = 50,
329 .regs = ichx_regs,
330 .reglen = ichx_reglen,
331};
332
333/* ICH7 and ICH8-based */
334static struct ichx_desc ich7_desc = {
335 .ngpio = 50,
336 .have_blink = true,
337 .regs = ichx_regs,
338 .reglen = ichx_reglen,
339};
340
341/* ICH9-based */
342static struct ichx_desc ich9_desc = {
343 .ngpio = 61,
344 .have_blink = true,
345 .regs = ichx_regs,
346 .reglen = ichx_reglen,
347};
348
349/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
350static struct ichx_desc ich10_cons_desc = {
351 .ngpio = 61,
352 .have_blink = true,
353 .regs = ichx_regs,
354 .reglen = ichx_reglen,
355};
356static struct ichx_desc ich10_corp_desc = {
357 .ngpio = 72,
358 .have_blink = true,
359 .regs = ichx_regs,
360 .reglen = ichx_reglen,
361};
362
363/* Intel 5 series, 6 series, 3400 series, and C200 series */
364static struct ichx_desc intel5_desc = {
365 .ngpio = 76,
366 .regs = ichx_regs,
367 .reglen = ichx_reglen,
368};
369
370/* Avoton */
371static struct ichx_desc avoton_desc = {
372 /* Avoton has only 59 GPIOs, but we assume the first set of register
373 * (Core) has 32 instead of 31 to keep gpio-ich compliance
374 */
375 .ngpio = 60,
376 .regs = avoton_regs,
377 .reglen = avoton_reglen,
378 .use_outlvl_cache = true,
379};
380
381static int ichx_gpio_request_regions(struct resource *res_base,
382 const char *name, u8 use_gpio)
383{
384 int i;
385
386 if (!res_base || !res_base->start || !res_base->end)
387 return -ENODEV;
388
389 for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
390 if (!(use_gpio & (1 << i)))
391 continue;
392 if (!request_region(
393 res_base->start + ichx_priv.desc->regs[0][i],
394 ichx_priv.desc->reglen[i], name))
395 goto request_err;
396 }
397 return 0;
398
399request_err:
400 /* Clean up: release already requested regions, if any */
401 for (i--; i >= 0; i--) {
402 if (!(use_gpio & (1 << i)))
403 continue;
404 release_region(res_base->start + ichx_priv.desc->regs[0][i],
405 ichx_priv.desc->reglen[i]);
406 }
407 return -EBUSY;
408}
409
410static void ichx_gpio_release_regions(struct resource *res_base, u8 use_gpio)
411{
412 int i;
413
414 for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
415 if (!(use_gpio & (1 << i)))
416 continue;
417 release_region(res_base->start + ichx_priv.desc->regs[0][i],
418 ichx_priv.desc->reglen[i]);
419 }
420}
421
422static int ichx_gpio_probe(struct platform_device *pdev)
423{
424 struct resource *res_base, *res_pm;
425 int err;
426 struct lpc_ich_info *ich_info = dev_get_platdata(&pdev->dev);
427
428 if (!ich_info)
429 return -ENODEV;
430
431 ichx_priv.dev = pdev;
432
433 switch (ich_info->gpio_version) {
434 case ICH_I3100_GPIO:
435 ichx_priv.desc = &i3100_desc;
436 break;
437 case ICH_V5_GPIO:
438 ichx_priv.desc = &intel5_desc;
439 break;
440 case ICH_V6_GPIO:
441 ichx_priv.desc = &ich6_desc;
442 break;
443 case ICH_V7_GPIO:
444 ichx_priv.desc = &ich7_desc;
445 break;
446 case ICH_V9_GPIO:
447 ichx_priv.desc = &ich9_desc;
448 break;
449 case ICH_V10CORP_GPIO:
450 ichx_priv.desc = &ich10_corp_desc;
451 break;
452 case ICH_V10CONS_GPIO:
453 ichx_priv.desc = &ich10_cons_desc;
454 break;
455 case AVOTON_GPIO:
456 ichx_priv.desc = &avoton_desc;
457 break;
458 default:
459 return -ENODEV;
460 }
461
462 spin_lock_init(&ichx_priv.lock);
463 res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
464 ichx_priv.use_gpio = ich_info->use_gpio;
465 err = ichx_gpio_request_regions(res_base, pdev->name,
466 ichx_priv.use_gpio);
467 if (err)
468 return err;
469
470 ichx_priv.gpio_base = res_base;
471
472 /*
473 * If necessary, determine the I/O address of ACPI/power management
474 * registers which are needed to read the the GPE0 register for GPI pins
475 * 0 - 15 on some chipsets.
476 */
477 if (!ichx_priv.desc->uses_gpe0)
478 goto init;
479
480 res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
481 if (!res_pm) {
482 pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
483 goto init;
484 }
485
486 if (!request_region(res_pm->start, resource_size(res_pm),
487 pdev->name)) {
488 pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
489 goto init;
490 }
491
492 ichx_priv.pm_base = res_pm;
493
494init:
495 ichx_gpiolib_setup(&ichx_priv.chip);
496 err = gpiochip_add(&ichx_priv.chip);
497 if (err) {
498 pr_err("Failed to register GPIOs\n");
499 goto add_err;
500 }
501
502 pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
503 ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);
504
505 return 0;
506
507add_err:
508 ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
509 if (ichx_priv.pm_base)
510 release_region(ichx_priv.pm_base->start,
511 resource_size(ichx_priv.pm_base));
512 return err;
513}
514
515static int ichx_gpio_remove(struct platform_device *pdev)
516{
517 int err;
518
519 err = gpiochip_remove(&ichx_priv.chip);
520 if (err) {
521 dev_err(&pdev->dev, "%s failed, %d\n",
522 "gpiochip_remove()", err);
523 return err;
524 }
525
526 ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
527 if (ichx_priv.pm_base)
528 release_region(ichx_priv.pm_base->start,
529 resource_size(ichx_priv.pm_base));
530
531 return 0;
532}
533
534static struct platform_driver ichx_gpio_driver = {
535 .driver = {
536 .owner = THIS_MODULE,
537 .name = DRV_NAME,
538 },
539 .probe = ichx_gpio_probe,
540 .remove = ichx_gpio_remove,
541};
542
543module_platform_driver(ichx_gpio_driver);
544
545MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
546MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
547MODULE_LICENSE("GPL");
548MODULE_ALIAS("platform:"DRV_NAME);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
4 *
5 * Copyright (C) 2010 Extreme Engineering Solutions.
6 */
7
8
9#include <linux/bitops.h>
10#include <linux/gpio/driver.h>
11#include <linux/ioport.h>
12#include <linux/mfd/lpc_ich.h>
13#include <linux/module.h>
14#include <linux/pci.h>
15#include <linux/platform_device.h>
16
17#define DRV_NAME "gpio_ich"
18
19/*
20 * GPIO register offsets in GPIO I/O space.
21 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
22 * LVLx registers. Logic in the read/write functions takes a register and
23 * an absolute bit number and determines the proper register offset and bit
24 * number in that register. For example, to read the value of GPIO bit 50
25 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
26 * bit 18 (50%32).
27 */
28enum GPIO_REG {
29 GPIO_USE_SEL = 0,
30 GPIO_IO_SEL,
31 GPIO_LVL,
32 GPO_BLINK
33};
34
35static const u8 ichx_regs[4][3] = {
36 {0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
37 {0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
38 {0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
39 {0x18, 0x18, 0x18}, /* BLINK offset */
40};
41
42static const u8 ichx_reglen[3] = {
43 0x30, 0x10, 0x10,
44};
45
46static const u8 avoton_regs[4][3] = {
47 {0x00, 0x80, 0x00},
48 {0x04, 0x84, 0x00},
49 {0x08, 0x88, 0x00},
50};
51
52static const u8 avoton_reglen[3] = {
53 0x10, 0x10, 0x00,
54};
55
56#define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
57#define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
58
59struct ichx_desc {
60 /* Max GPIO pins the chipset can have */
61 uint ngpio;
62
63 /* chipset registers */
64 const u8 (*regs)[3];
65 const u8 *reglen;
66
67 /* GPO_BLINK is available on this chipset */
68 bool have_blink;
69
70 /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
71 bool uses_gpe0;
72
73 /* USE_SEL is bogus on some chipsets, eg 3100 */
74 u32 use_sel_ignore[3];
75
76 /* Some chipsets have quirks, let these use their own request/get */
77 int (*request)(struct gpio_chip *chip, unsigned offset);
78 int (*get)(struct gpio_chip *chip, unsigned offset);
79
80 /*
81 * Some chipsets don't let reading output values on GPIO_LVL register
82 * this option allows driver caching written output values
83 */
84 bool use_outlvl_cache;
85};
86
87static struct {
88 spinlock_t lock;
89 struct device *dev;
90 struct gpio_chip chip;
91 struct resource *gpio_base; /* GPIO IO base */
92 struct resource *pm_base; /* Power Mangagment IO base */
93 struct ichx_desc *desc; /* Pointer to chipset-specific description */
94 u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */
95 u8 use_gpio; /* Which GPIO groups are usable */
96 int outlvl_cache[3]; /* cached output values */
97} ichx_priv;
98
99static int modparam_gpiobase = -1; /* dynamic */
100module_param_named(gpiobase, modparam_gpiobase, int, 0444);
101MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, which is the default.");
102
103static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
104{
105 unsigned long flags;
106 u32 data, tmp;
107 int reg_nr = nr / 32;
108 int bit = nr & 0x1f;
109
110 spin_lock_irqsave(&ichx_priv.lock, flags);
111
112 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
113 data = ichx_priv.outlvl_cache[reg_nr];
114 else
115 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
116 ichx_priv.gpio_base);
117
118 if (val)
119 data |= BIT(bit);
120 else
121 data &= ~BIT(bit);
122 ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
123 ichx_priv.gpio_base);
124 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
125 ichx_priv.outlvl_cache[reg_nr] = data;
126
127 tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
128 ichx_priv.gpio_base);
129
130 spin_unlock_irqrestore(&ichx_priv.lock, flags);
131
132 return (verify && data != tmp) ? -EPERM : 0;
133}
134
135static int ichx_read_bit(int reg, unsigned nr)
136{
137 unsigned long flags;
138 u32 data;
139 int reg_nr = nr / 32;
140 int bit = nr & 0x1f;
141
142 spin_lock_irqsave(&ichx_priv.lock, flags);
143
144 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
145 ichx_priv.gpio_base);
146
147 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
148 data = ichx_priv.outlvl_cache[reg_nr] | data;
149
150 spin_unlock_irqrestore(&ichx_priv.lock, flags);
151
152 return !!(data & BIT(bit));
153}
154
155static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
156{
157 return !!(ichx_priv.use_gpio & BIT(nr / 32));
158}
159
160static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned nr)
161{
162 return ichx_read_bit(GPIO_IO_SEL, nr);
163}
164
165static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
166{
167 /*
168 * Try setting pin as an input and verify it worked since many pins
169 * are output-only.
170 */
171 return ichx_write_bit(GPIO_IO_SEL, nr, 1, 1);
172}
173
174static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
175 int val)
176{
177 /* Disable blink hardware which is available for GPIOs from 0 to 31. */
178 if (nr < 32 && ichx_priv.desc->have_blink)
179 ichx_write_bit(GPO_BLINK, nr, 0, 0);
180
181 /* Set GPIO output value. */
182 ichx_write_bit(GPIO_LVL, nr, val, 0);
183
184 /*
185 * Try setting pin as an output and verify it worked since many pins
186 * are input-only.
187 */
188 return ichx_write_bit(GPIO_IO_SEL, nr, 0, 1);
189}
190
191static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
192{
193 return ichx_read_bit(GPIO_LVL, nr);
194}
195
196static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
197{
198 unsigned long flags;
199 u32 data;
200
201 /*
202 * GPI 0 - 15 need to be read from the power management registers on
203 * a ICH6/3100 bridge.
204 */
205 if (nr < 16) {
206 if (!ichx_priv.pm_base)
207 return -ENXIO;
208
209 spin_lock_irqsave(&ichx_priv.lock, flags);
210
211 /* GPI 0 - 15 are latched, write 1 to clear*/
212 ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base);
213 data = ICHX_READ(0, ichx_priv.pm_base);
214
215 spin_unlock_irqrestore(&ichx_priv.lock, flags);
216
217 return !!((data >> 16) & BIT(nr));
218 } else {
219 return ichx_gpio_get(chip, nr);
220 }
221}
222
223static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
224{
225 if (!ichx_gpio_check_available(chip, nr))
226 return -ENXIO;
227
228 /*
229 * Note we assume the BIOS properly set a bridge's USE value. Some
230 * chips (eg Intel 3100) have bogus USE values though, so first see if
231 * the chipset's USE value can be trusted for this specific bit.
232 * If it can't be trusted, assume that the pin can be used as a GPIO.
233 */
234 if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f))
235 return 0;
236
237 return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
238}
239
240static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
241{
242 /*
243 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
244 * bridge as they are controlled by USE register bits 0 and 1. See
245 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
246 * additional info.
247 */
248 if (nr == 16 || nr == 17)
249 nr -= 16;
250
251 return ichx_gpio_request(chip, nr);
252}
253
254static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
255{
256 ichx_write_bit(GPIO_LVL, nr, val, 0);
257}
258
259static void ichx_gpiolib_setup(struct gpio_chip *chip)
260{
261 chip->owner = THIS_MODULE;
262 chip->label = DRV_NAME;
263 chip->parent = ichx_priv.dev;
264
265 /* Allow chip-specific overrides of request()/get() */
266 chip->request = ichx_priv.desc->request ?
267 ichx_priv.desc->request : ichx_gpio_request;
268 chip->get = ichx_priv.desc->get ?
269 ichx_priv.desc->get : ichx_gpio_get;
270
271 chip->set = ichx_gpio_set;
272 chip->get_direction = ichx_gpio_get_direction;
273 chip->direction_input = ichx_gpio_direction_input;
274 chip->direction_output = ichx_gpio_direction_output;
275 chip->base = modparam_gpiobase;
276 chip->ngpio = ichx_priv.desc->ngpio;
277 chip->can_sleep = false;
278 chip->dbg_show = NULL;
279}
280
281/* ICH6-based, 631xesb-based */
282static struct ichx_desc ich6_desc = {
283 /* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
284 .request = ich6_gpio_request,
285 .get = ich6_gpio_get,
286
287 /* GPIO 0-15 are read in the GPE0_STS PM register */
288 .uses_gpe0 = true,
289
290 .ngpio = 50,
291 .have_blink = true,
292 .regs = ichx_regs,
293 .reglen = ichx_reglen,
294};
295
296/* Intel 3100 */
297static struct ichx_desc i3100_desc = {
298 /*
299 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
300 * the Intel 3100. See "Table 712. GPIO Summary Table" of 3100
301 * Datasheet for more info.
302 */
303 .use_sel_ignore = {0x00130000, 0x00010000, 0x0},
304
305 /* The 3100 needs fixups for GPIO 0 - 17 */
306 .request = ich6_gpio_request,
307 .get = ich6_gpio_get,
308
309 /* GPIO 0-15 are read in the GPE0_STS PM register */
310 .uses_gpe0 = true,
311
312 .ngpio = 50,
313 .regs = ichx_regs,
314 .reglen = ichx_reglen,
315};
316
317/* ICH7 and ICH8-based */
318static struct ichx_desc ich7_desc = {
319 .ngpio = 50,
320 .have_blink = true,
321 .regs = ichx_regs,
322 .reglen = ichx_reglen,
323};
324
325/* ICH9-based */
326static struct ichx_desc ich9_desc = {
327 .ngpio = 61,
328 .have_blink = true,
329 .regs = ichx_regs,
330 .reglen = ichx_reglen,
331};
332
333/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
334static struct ichx_desc ich10_cons_desc = {
335 .ngpio = 61,
336 .have_blink = true,
337 .regs = ichx_regs,
338 .reglen = ichx_reglen,
339};
340static struct ichx_desc ich10_corp_desc = {
341 .ngpio = 72,
342 .have_blink = true,
343 .regs = ichx_regs,
344 .reglen = ichx_reglen,
345};
346
347/* Intel 5 series, 6 series, 3400 series, and C200 series */
348static struct ichx_desc intel5_desc = {
349 .ngpio = 76,
350 .regs = ichx_regs,
351 .reglen = ichx_reglen,
352};
353
354/* Avoton */
355static struct ichx_desc avoton_desc = {
356 /* Avoton has only 59 GPIOs, but we assume the first set of register
357 * (Core) has 32 instead of 31 to keep gpio-ich compliance
358 */
359 .ngpio = 60,
360 .regs = avoton_regs,
361 .reglen = avoton_reglen,
362 .use_outlvl_cache = true,
363};
364
365static int ichx_gpio_request_regions(struct device *dev,
366 struct resource *res_base, const char *name, u8 use_gpio)
367{
368 int i;
369
370 if (!res_base || !res_base->start || !res_base->end)
371 return -ENODEV;
372
373 for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
374 if (!(use_gpio & BIT(i)))
375 continue;
376 if (!devm_request_region(dev,
377 res_base->start + ichx_priv.desc->regs[0][i],
378 ichx_priv.desc->reglen[i], name))
379 return -EBUSY;
380 }
381 return 0;
382}
383
384static int ichx_gpio_probe(struct platform_device *pdev)
385{
386 struct device *dev = &pdev->dev;
387 struct lpc_ich_info *ich_info = dev_get_platdata(dev);
388 struct resource *res_base, *res_pm;
389 int err;
390
391 if (!ich_info)
392 return -ENODEV;
393
394 switch (ich_info->gpio_version) {
395 case ICH_I3100_GPIO:
396 ichx_priv.desc = &i3100_desc;
397 break;
398 case ICH_V5_GPIO:
399 ichx_priv.desc = &intel5_desc;
400 break;
401 case ICH_V6_GPIO:
402 ichx_priv.desc = &ich6_desc;
403 break;
404 case ICH_V7_GPIO:
405 ichx_priv.desc = &ich7_desc;
406 break;
407 case ICH_V9_GPIO:
408 ichx_priv.desc = &ich9_desc;
409 break;
410 case ICH_V10CORP_GPIO:
411 ichx_priv.desc = &ich10_corp_desc;
412 break;
413 case ICH_V10CONS_GPIO:
414 ichx_priv.desc = &ich10_cons_desc;
415 break;
416 case AVOTON_GPIO:
417 ichx_priv.desc = &avoton_desc;
418 break;
419 default:
420 return -ENODEV;
421 }
422
423 ichx_priv.dev = dev;
424 spin_lock_init(&ichx_priv.lock);
425
426 res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
427 err = ichx_gpio_request_regions(dev, res_base, pdev->name,
428 ich_info->use_gpio);
429 if (err)
430 return err;
431
432 ichx_priv.gpio_base = res_base;
433 ichx_priv.use_gpio = ich_info->use_gpio;
434
435 /*
436 * If necessary, determine the I/O address of ACPI/power management
437 * registers which are needed to read the GPE0 register for GPI pins
438 * 0 - 15 on some chipsets.
439 */
440 if (!ichx_priv.desc->uses_gpe0)
441 goto init;
442
443 res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
444 if (!res_pm) {
445 dev_warn(dev, "ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
446 goto init;
447 }
448
449 if (!devm_request_region(dev, res_pm->start, resource_size(res_pm),
450 pdev->name)) {
451 dev_warn(dev, "ACPI BAR is busy, GPI 0 - 15 unavailable\n");
452 goto init;
453 }
454
455 ichx_priv.pm_base = res_pm;
456
457init:
458 ichx_gpiolib_setup(&ichx_priv.chip);
459 err = gpiochip_add_data(&ichx_priv.chip, NULL);
460 if (err) {
461 dev_err(dev, "Failed to register GPIOs\n");
462 return err;
463 }
464
465 dev_info(dev, "GPIO from %d to %d\n", ichx_priv.chip.base,
466 ichx_priv.chip.base + ichx_priv.chip.ngpio - 1);
467
468 return 0;
469}
470
471static int ichx_gpio_remove(struct platform_device *pdev)
472{
473 gpiochip_remove(&ichx_priv.chip);
474
475 return 0;
476}
477
478static struct platform_driver ichx_gpio_driver = {
479 .driver = {
480 .name = DRV_NAME,
481 },
482 .probe = ichx_gpio_probe,
483 .remove = ichx_gpio_remove,
484};
485
486module_platform_driver(ichx_gpio_driver);
487
488MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
489MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
490MODULE_LICENSE("GPL");
491MODULE_ALIAS("platform:"DRV_NAME);