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1/*
2 * Low-Level PCI Support for PC -- Routing of Interrupts
3 *
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
5 */
6
7#include <linux/types.h>
8#include <linux/kernel.h>
9#include <linux/pci.h>
10#include <linux/init.h>
11#include <linux/interrupt.h>
12#include <linux/dmi.h>
13#include <linux/io.h>
14#include <linux/smp.h>
15#include <asm/io_apic.h>
16#include <linux/irq.h>
17#include <linux/acpi.h>
18#include <asm/pci_x86.h>
19
20#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
21#define PIRQ_VERSION 0x0100
22
23static int broken_hp_bios_irq9;
24static int acer_tm360_irqrouting;
25
26static struct irq_routing_table *pirq_table;
27
28static int pirq_enable_irq(struct pci_dev *dev);
29
30/*
31 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
32 * Avoid using: 13, 14 and 15 (FP error and IDE).
33 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
34 */
35unsigned int pcibios_irq_mask = 0xfff8;
36
37static int pirq_penalty[16] = {
38 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
39 0, 0, 0, 0, 1000, 100000, 100000, 100000
40};
41
42struct irq_router {
43 char *name;
44 u16 vendor, device;
45 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
46 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq,
47 int new);
48};
49
50struct irq_router_handler {
51 u16 vendor;
52 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
53};
54
55int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq;
56void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL;
57
58/*
59 * Check passed address for the PCI IRQ Routing Table signature
60 * and perform checksum verification.
61 */
62
63static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr)
64{
65 struct irq_routing_table *rt;
66 int i;
67 u8 sum;
68
69 rt = (struct irq_routing_table *) addr;
70 if (rt->signature != PIRQ_SIGNATURE ||
71 rt->version != PIRQ_VERSION ||
72 rt->size % 16 ||
73 rt->size < sizeof(struct irq_routing_table))
74 return NULL;
75 sum = 0;
76 for (i = 0; i < rt->size; i++)
77 sum += addr[i];
78 if (!sum) {
79 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n",
80 rt);
81 return rt;
82 }
83 return NULL;
84}
85
86
87
88/*
89 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
90 */
91
92static struct irq_routing_table * __init pirq_find_routing_table(void)
93{
94 u8 *addr;
95 struct irq_routing_table *rt;
96
97 if (pirq_table_addr) {
98 rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr));
99 if (rt)
100 return rt;
101 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n");
102 }
103 for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
104 rt = pirq_check_routing_table(addr);
105 if (rt)
106 return rt;
107 }
108 return NULL;
109}
110
111/*
112 * If we have a IRQ routing table, use it to search for peer host
113 * bridges. It's a gross hack, but since there are no other known
114 * ways how to get a list of buses, we have to go this way.
115 */
116
117static void __init pirq_peer_trick(void)
118{
119 struct irq_routing_table *rt = pirq_table;
120 u8 busmap[256];
121 int i;
122 struct irq_info *e;
123
124 memset(busmap, 0, sizeof(busmap));
125 for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
126 e = &rt->slots[i];
127#ifdef DEBUG
128 {
129 int j;
130 DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
131 for (j = 0; j < 4; j++)
132 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
133 DBG("\n");
134 }
135#endif
136 busmap[e->bus] = 1;
137 }
138 for (i = 1; i < 256; i++) {
139 if (!busmap[i] || pci_find_bus(0, i))
140 continue;
141 pcibios_scan_root(i);
142 }
143 pcibios_last_bus = -1;
144}
145
146/*
147 * Code for querying and setting of IRQ routes on various interrupt routers.
148 */
149
150void eisa_set_level_irq(unsigned int irq)
151{
152 unsigned char mask = 1 << (irq & 7);
153 unsigned int port = 0x4d0 + (irq >> 3);
154 unsigned char val;
155 static u16 eisa_irq_mask;
156
157 if (irq >= 16 || (1 << irq) & eisa_irq_mask)
158 return;
159
160 eisa_irq_mask |= (1 << irq);
161 printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq);
162 val = inb(port);
163 if (!(val & mask)) {
164 DBG(KERN_DEBUG " -> edge");
165 outb(val | mask, port);
166 }
167}
168
169/*
170 * Common IRQ routing practice: nibbles in config space,
171 * offset by some magic constant.
172 */
173static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
174{
175 u8 x;
176 unsigned reg = offset + (nr >> 1);
177
178 pci_read_config_byte(router, reg, &x);
179 return (nr & 1) ? (x >> 4) : (x & 0xf);
180}
181
182static void write_config_nybble(struct pci_dev *router, unsigned offset,
183 unsigned nr, unsigned int val)
184{
185 u8 x;
186 unsigned reg = offset + (nr >> 1);
187
188 pci_read_config_byte(router, reg, &x);
189 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
190 pci_write_config_byte(router, reg, x);
191}
192
193/*
194 * ALI pirq entries are damn ugly, and completely undocumented.
195 * This has been figured out from pirq tables, and it's not a pretty
196 * picture.
197 */
198static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
199{
200 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
201
202 WARN_ON_ONCE(pirq > 16);
203 return irqmap[read_config_nybble(router, 0x48, pirq-1)];
204}
205
206static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
207{
208 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
209 unsigned int val = irqmap[irq];
210
211 WARN_ON_ONCE(pirq > 16);
212 if (val) {
213 write_config_nybble(router, 0x48, pirq-1, val);
214 return 1;
215 }
216 return 0;
217}
218
219/*
220 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
221 * just a pointer to the config space.
222 */
223static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
224{
225 u8 x;
226
227 pci_read_config_byte(router, pirq, &x);
228 return (x < 16) ? x : 0;
229}
230
231static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
232{
233 pci_write_config_byte(router, pirq, irq);
234 return 1;
235}
236
237/*
238 * The VIA pirq rules are nibble-based, like ALI,
239 * but without the ugly irq number munging.
240 * However, PIRQD is in the upper instead of lower 4 bits.
241 */
242static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
243{
244 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
245}
246
247static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
248{
249 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
250 return 1;
251}
252
253/*
254 * The VIA pirq rules are nibble-based, like ALI,
255 * but without the ugly irq number munging.
256 * However, for 82C586, nibble map is different .
257 */
258static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
259{
260 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
261
262 WARN_ON_ONCE(pirq > 5);
263 return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
264}
265
266static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
267{
268 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
269
270 WARN_ON_ONCE(pirq > 5);
271 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
272 return 1;
273}
274
275/*
276 * ITE 8330G pirq rules are nibble-based
277 * FIXME: pirqmap may be { 1, 0, 3, 2 },
278 * 2+3 are both mapped to irq 9 on my system
279 */
280static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
281{
282 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
283
284 WARN_ON_ONCE(pirq > 4);
285 return read_config_nybble(router, 0x43, pirqmap[pirq-1]);
286}
287
288static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
289{
290 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
291
292 WARN_ON_ONCE(pirq > 4);
293 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
294 return 1;
295}
296
297/*
298 * OPTI: high four bits are nibble pointer..
299 * I wonder what the low bits do?
300 */
301static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
302{
303 return read_config_nybble(router, 0xb8, pirq >> 4);
304}
305
306static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
307{
308 write_config_nybble(router, 0xb8, pirq >> 4, irq);
309 return 1;
310}
311
312/*
313 * Cyrix: nibble offset 0x5C
314 * 0x5C bits 7:4 is INTB bits 3:0 is INTA
315 * 0x5D bits 7:4 is INTD bits 3:0 is INTC
316 */
317static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
318{
319 return read_config_nybble(router, 0x5C, (pirq-1)^1);
320}
321
322static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
323{
324 write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
325 return 1;
326}
327
328/*
329 * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
330 * We have to deal with the following issues here:
331 * - vendors have different ideas about the meaning of link values
332 * - some onboard devices (integrated in the chipset) have special
333 * links and are thus routed differently (i.e. not via PCI INTA-INTD)
334 * - different revision of the router have a different layout for
335 * the routing registers, particularly for the onchip devices
336 *
337 * For all routing registers the common thing is we have one byte
338 * per routeable link which is defined as:
339 * bit 7 IRQ mapping enabled (0) or disabled (1)
340 * bits [6:4] reserved (sometimes used for onchip devices)
341 * bits [3:0] IRQ to map to
342 * allowed: 3-7, 9-12, 14-15
343 * reserved: 0, 1, 2, 8, 13
344 *
345 * The config-space registers located at 0x41/0x42/0x43/0x44 are
346 * always used to route the normal PCI INT A/B/C/D respectively.
347 * Apparently there are systems implementing PCI routing table using
348 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
349 * We try our best to handle both link mappings.
350 *
351 * Currently (2003-05-21) it appears most SiS chipsets follow the
352 * definition of routing registers from the SiS-5595 southbridge.
353 * According to the SiS 5595 datasheets the revision id's of the
354 * router (ISA-bridge) should be 0x01 or 0xb0.
355 *
356 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
357 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
358 * They seem to work with the current routing code. However there is
359 * some concern because of the two USB-OHCI HCs (original SiS 5595
360 * had only one). YMMV.
361 *
362 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
363 *
364 * 0x61: IDEIRQ:
365 * bits [6:5] must be written 01
366 * bit 4 channel-select primary (0), secondary (1)
367 *
368 * 0x62: USBIRQ:
369 * bit 6 OHCI function disabled (0), enabled (1)
370 *
371 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
372 *
373 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
374 *
375 * We support USBIRQ (in addition to INTA-INTD) and keep the
376 * IDE, ACPI and DAQ routing untouched as set by the BIOS.
377 *
378 * Currently the only reported exception is the new SiS 65x chipset
379 * which includes the SiS 69x southbridge. Here we have the 85C503
380 * router revision 0x04 and there are changes in the register layout
381 * mostly related to the different USB HCs with USB 2.0 support.
382 *
383 * Onchip routing for router rev-id 0x04 (try-and-error observation)
384 *
385 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
386 * bit 6-4 are probably unused, not like 5595
387 */
388
389#define PIRQ_SIS_IRQ_MASK 0x0f
390#define PIRQ_SIS_IRQ_DISABLE 0x80
391#define PIRQ_SIS_USB_ENABLE 0x40
392
393static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
394{
395 u8 x;
396 int reg;
397
398 reg = pirq;
399 if (reg >= 0x01 && reg <= 0x04)
400 reg += 0x40;
401 pci_read_config_byte(router, reg, &x);
402 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
403}
404
405static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
406{
407 u8 x;
408 int reg;
409
410 reg = pirq;
411 if (reg >= 0x01 && reg <= 0x04)
412 reg += 0x40;
413 pci_read_config_byte(router, reg, &x);
414 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
415 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
416 pci_write_config_byte(router, reg, x);
417 return 1;
418}
419
420
421/*
422 * VLSI: nibble offset 0x74 - educated guess due to routing table and
423 * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
424 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
425 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
426 * for the busbridge to the docking station.
427 */
428
429static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
430{
431 WARN_ON_ONCE(pirq >= 9);
432 if (pirq > 8) {
433 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
434 return 0;
435 }
436 return read_config_nybble(router, 0x74, pirq-1);
437}
438
439static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
440{
441 WARN_ON_ONCE(pirq >= 9);
442 if (pirq > 8) {
443 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
444 return 0;
445 }
446 write_config_nybble(router, 0x74, pirq-1, irq);
447 return 1;
448}
449
450/*
451 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
452 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
453 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
454 * register is a straight binary coding of desired PIC IRQ (low nibble).
455 *
456 * The 'link' value in the PIRQ table is already in the correct format
457 * for the Index register. There are some special index values:
458 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
459 * and 0x03 for SMBus.
460 */
461static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
462{
463 outb(pirq, 0xc00);
464 return inb(0xc01) & 0xf;
465}
466
467static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev,
468 int pirq, int irq)
469{
470 outb(pirq, 0xc00);
471 outb(irq, 0xc01);
472 return 1;
473}
474
475/* Support for AMD756 PCI IRQ Routing
476 * Jhon H. Caicedo <jhcaiced@osso.org.co>
477 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
478 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
479 * The AMD756 pirq rules are nibble-based
480 * offset 0x56 0-3 PIRQA 4-7 PIRQB
481 * offset 0x57 0-3 PIRQC 4-7 PIRQD
482 */
483static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
484{
485 u8 irq;
486 irq = 0;
487 if (pirq <= 4)
488 irq = read_config_nybble(router, 0x56, pirq - 1);
489 dev_info(&dev->dev,
490 "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n",
491 dev->vendor, dev->device, pirq, irq);
492 return irq;
493}
494
495static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
496{
497 dev_info(&dev->dev,
498 "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n",
499 dev->vendor, dev->device, pirq, irq);
500 if (pirq <= 4)
501 write_config_nybble(router, 0x56, pirq - 1, irq);
502 return 1;
503}
504
505/*
506 * PicoPower PT86C523
507 */
508static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
509{
510 outb(0x10 + ((pirq - 1) >> 1), 0x24);
511 return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf);
512}
513
514static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
515 int irq)
516{
517 unsigned int x;
518 outb(0x10 + ((pirq - 1) >> 1), 0x24);
519 x = inb(0x26);
520 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq));
521 outb(x, 0x26);
522 return 1;
523}
524
525#ifdef CONFIG_PCI_BIOS
526
527static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
528{
529 struct pci_dev *bridge;
530 int pin = pci_get_interrupt_pin(dev, &bridge);
531 return pcibios_set_irq_routing(bridge, pin - 1, irq);
532}
533
534#endif
535
536static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
537{
538 static struct pci_device_id __initdata pirq_440gx[] = {
539 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
540 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
541 { },
542 };
543
544 /* 440GX has a proprietary PIRQ router -- don't use it */
545 if (pci_dev_present(pirq_440gx))
546 return 0;
547
548 switch (device) {
549 case PCI_DEVICE_ID_INTEL_82371FB_0:
550 case PCI_DEVICE_ID_INTEL_82371SB_0:
551 case PCI_DEVICE_ID_INTEL_82371AB_0:
552 case PCI_DEVICE_ID_INTEL_82371MX:
553 case PCI_DEVICE_ID_INTEL_82443MX_0:
554 case PCI_DEVICE_ID_INTEL_82801AA_0:
555 case PCI_DEVICE_ID_INTEL_82801AB_0:
556 case PCI_DEVICE_ID_INTEL_82801BA_0:
557 case PCI_DEVICE_ID_INTEL_82801BA_10:
558 case PCI_DEVICE_ID_INTEL_82801CA_0:
559 case PCI_DEVICE_ID_INTEL_82801CA_12:
560 case PCI_DEVICE_ID_INTEL_82801DB_0:
561 case PCI_DEVICE_ID_INTEL_82801E_0:
562 case PCI_DEVICE_ID_INTEL_82801EB_0:
563 case PCI_DEVICE_ID_INTEL_ESB_1:
564 case PCI_DEVICE_ID_INTEL_ICH6_0:
565 case PCI_DEVICE_ID_INTEL_ICH6_1:
566 case PCI_DEVICE_ID_INTEL_ICH7_0:
567 case PCI_DEVICE_ID_INTEL_ICH7_1:
568 case PCI_DEVICE_ID_INTEL_ICH7_30:
569 case PCI_DEVICE_ID_INTEL_ICH7_31:
570 case PCI_DEVICE_ID_INTEL_TGP_LPC:
571 case PCI_DEVICE_ID_INTEL_ESB2_0:
572 case PCI_DEVICE_ID_INTEL_ICH8_0:
573 case PCI_DEVICE_ID_INTEL_ICH8_1:
574 case PCI_DEVICE_ID_INTEL_ICH8_2:
575 case PCI_DEVICE_ID_INTEL_ICH8_3:
576 case PCI_DEVICE_ID_INTEL_ICH8_4:
577 case PCI_DEVICE_ID_INTEL_ICH9_0:
578 case PCI_DEVICE_ID_INTEL_ICH9_1:
579 case PCI_DEVICE_ID_INTEL_ICH9_2:
580 case PCI_DEVICE_ID_INTEL_ICH9_3:
581 case PCI_DEVICE_ID_INTEL_ICH9_4:
582 case PCI_DEVICE_ID_INTEL_ICH9_5:
583 case PCI_DEVICE_ID_INTEL_EP80579_0:
584 case PCI_DEVICE_ID_INTEL_ICH10_0:
585 case PCI_DEVICE_ID_INTEL_ICH10_1:
586 case PCI_DEVICE_ID_INTEL_ICH10_2:
587 case PCI_DEVICE_ID_INTEL_ICH10_3:
588 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0:
589 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1:
590 r->name = "PIIX/ICH";
591 r->get = pirq_piix_get;
592 r->set = pirq_piix_set;
593 return 1;
594 }
595
596 if ((device >= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN &&
597 device <= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX)
598 || (device >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
599 device <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX)
600 || (device >= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN &&
601 device <= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX)
602 || (device >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
603 device <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) {
604 r->name = "PIIX/ICH";
605 r->get = pirq_piix_get;
606 r->set = pirq_piix_set;
607 return 1;
608 }
609
610 return 0;
611}
612
613static __init int via_router_probe(struct irq_router *r,
614 struct pci_dev *router, u16 device)
615{
616 /* FIXME: We should move some of the quirk fixup stuff here */
617
618 /*
619 * workarounds for some buggy BIOSes
620 */
621 if (device == PCI_DEVICE_ID_VIA_82C586_0) {
622 switch (router->device) {
623 case PCI_DEVICE_ID_VIA_82C686:
624 /*
625 * Asus k7m bios wrongly reports 82C686A
626 * as 586-compatible
627 */
628 device = PCI_DEVICE_ID_VIA_82C686;
629 break;
630 case PCI_DEVICE_ID_VIA_8235:
631 /**
632 * Asus a7v-x bios wrongly reports 8235
633 * as 586-compatible
634 */
635 device = PCI_DEVICE_ID_VIA_8235;
636 break;
637 case PCI_DEVICE_ID_VIA_8237:
638 /**
639 * Asus a7v600 bios wrongly reports 8237
640 * as 586-compatible
641 */
642 device = PCI_DEVICE_ID_VIA_8237;
643 break;
644 }
645 }
646
647 switch (device) {
648 case PCI_DEVICE_ID_VIA_82C586_0:
649 r->name = "VIA";
650 r->get = pirq_via586_get;
651 r->set = pirq_via586_set;
652 return 1;
653 case PCI_DEVICE_ID_VIA_82C596:
654 case PCI_DEVICE_ID_VIA_82C686:
655 case PCI_DEVICE_ID_VIA_8231:
656 case PCI_DEVICE_ID_VIA_8233A:
657 case PCI_DEVICE_ID_VIA_8235:
658 case PCI_DEVICE_ID_VIA_8237:
659 /* FIXME: add new ones for 8233/5 */
660 r->name = "VIA";
661 r->get = pirq_via_get;
662 r->set = pirq_via_set;
663 return 1;
664 }
665 return 0;
666}
667
668static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
669{
670 switch (device) {
671 case PCI_DEVICE_ID_VLSI_82C534:
672 r->name = "VLSI 82C534";
673 r->get = pirq_vlsi_get;
674 r->set = pirq_vlsi_set;
675 return 1;
676 }
677 return 0;
678}
679
680
681static __init int serverworks_router_probe(struct irq_router *r,
682 struct pci_dev *router, u16 device)
683{
684 switch (device) {
685 case PCI_DEVICE_ID_SERVERWORKS_OSB4:
686 case PCI_DEVICE_ID_SERVERWORKS_CSB5:
687 r->name = "ServerWorks";
688 r->get = pirq_serverworks_get;
689 r->set = pirq_serverworks_set;
690 return 1;
691 }
692 return 0;
693}
694
695static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
696{
697 if (device != PCI_DEVICE_ID_SI_503)
698 return 0;
699
700 r->name = "SIS";
701 r->get = pirq_sis_get;
702 r->set = pirq_sis_set;
703 return 1;
704}
705
706static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
707{
708 switch (device) {
709 case PCI_DEVICE_ID_CYRIX_5520:
710 r->name = "NatSemi";
711 r->get = pirq_cyrix_get;
712 r->set = pirq_cyrix_set;
713 return 1;
714 }
715 return 0;
716}
717
718static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
719{
720 switch (device) {
721 case PCI_DEVICE_ID_OPTI_82C700:
722 r->name = "OPTI";
723 r->get = pirq_opti_get;
724 r->set = pirq_opti_set;
725 return 1;
726 }
727 return 0;
728}
729
730static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
731{
732 switch (device) {
733 case PCI_DEVICE_ID_ITE_IT8330G_0:
734 r->name = "ITE";
735 r->get = pirq_ite_get;
736 r->set = pirq_ite_set;
737 return 1;
738 }
739 return 0;
740}
741
742static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
743{
744 switch (device) {
745 case PCI_DEVICE_ID_AL_M1533:
746 case PCI_DEVICE_ID_AL_M1563:
747 r->name = "ALI";
748 r->get = pirq_ali_get;
749 r->set = pirq_ali_set;
750 return 1;
751 }
752 return 0;
753}
754
755static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
756{
757 switch (device) {
758 case PCI_DEVICE_ID_AMD_VIPER_740B:
759 r->name = "AMD756";
760 break;
761 case PCI_DEVICE_ID_AMD_VIPER_7413:
762 r->name = "AMD766";
763 break;
764 case PCI_DEVICE_ID_AMD_VIPER_7443:
765 r->name = "AMD768";
766 break;
767 default:
768 return 0;
769 }
770 r->get = pirq_amd756_get;
771 r->set = pirq_amd756_set;
772 return 1;
773}
774
775static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
776{
777 switch (device) {
778 case PCI_DEVICE_ID_PICOPOWER_PT86C523:
779 r->name = "PicoPower PT86C523";
780 r->get = pirq_pico_get;
781 r->set = pirq_pico_set;
782 return 1;
783
784 case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP:
785 r->name = "PicoPower PT86C523 rev. BB+";
786 r->get = pirq_pico_get;
787 r->set = pirq_pico_set;
788 return 1;
789 }
790 return 0;
791}
792
793static __initdata struct irq_router_handler pirq_routers[] = {
794 { PCI_VENDOR_ID_INTEL, intel_router_probe },
795 { PCI_VENDOR_ID_AL, ali_router_probe },
796 { PCI_VENDOR_ID_ITE, ite_router_probe },
797 { PCI_VENDOR_ID_VIA, via_router_probe },
798 { PCI_VENDOR_ID_OPTI, opti_router_probe },
799 { PCI_VENDOR_ID_SI, sis_router_probe },
800 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
801 { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
802 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
803 { PCI_VENDOR_ID_AMD, amd_router_probe },
804 { PCI_VENDOR_ID_PICOPOWER, pico_router_probe },
805 /* Someone with docs needs to add the ATI Radeon IGP */
806 { 0, NULL }
807};
808static struct irq_router pirq_router;
809static struct pci_dev *pirq_router_dev;
810
811
812/*
813 * FIXME: should we have an option to say "generic for
814 * chipset" ?
815 */
816
817static void __init pirq_find_router(struct irq_router *r)
818{
819 struct irq_routing_table *rt = pirq_table;
820 struct irq_router_handler *h;
821
822#ifdef CONFIG_PCI_BIOS
823 if (!rt->signature) {
824 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
825 r->set = pirq_bios_set;
826 r->name = "BIOS";
827 return;
828 }
829#endif
830
831 /* Default unless a driver reloads it */
832 r->name = "default";
833 r->get = NULL;
834 r->set = NULL;
835
836 DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n",
837 rt->rtr_vendor, rt->rtr_device);
838
839 pirq_router_dev = pci_get_bus_and_slot(rt->rtr_bus, rt->rtr_devfn);
840 if (!pirq_router_dev) {
841 DBG(KERN_DEBUG "PCI: Interrupt router not found at "
842 "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
843 return;
844 }
845
846 for (h = pirq_routers; h->vendor; h++) {
847 /* First look for a router match */
848 if (rt->rtr_vendor == h->vendor &&
849 h->probe(r, pirq_router_dev, rt->rtr_device))
850 break;
851 /* Fall back to a device match */
852 if (pirq_router_dev->vendor == h->vendor &&
853 h->probe(r, pirq_router_dev, pirq_router_dev->device))
854 break;
855 }
856 dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n",
857 pirq_router.name,
858 pirq_router_dev->vendor, pirq_router_dev->device);
859
860 /* The device remains referenced for the kernel lifetime */
861}
862
863static struct irq_info *pirq_get_info(struct pci_dev *dev)
864{
865 struct irq_routing_table *rt = pirq_table;
866 int entries = (rt->size - sizeof(struct irq_routing_table)) /
867 sizeof(struct irq_info);
868 struct irq_info *info;
869
870 for (info = rt->slots; entries--; info++)
871 if (info->bus == dev->bus->number &&
872 PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
873 return info;
874 return NULL;
875}
876
877static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
878{
879 u8 pin;
880 struct irq_info *info;
881 int i, pirq, newirq;
882 int irq = 0;
883 u32 mask;
884 struct irq_router *r = &pirq_router;
885 struct pci_dev *dev2 = NULL;
886 char *msg = NULL;
887
888 /* Find IRQ pin */
889 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
890 if (!pin) {
891 dev_dbg(&dev->dev, "no interrupt pin\n");
892 return 0;
893 }
894
895 if (io_apic_assign_pci_irqs)
896 return 0;
897
898 /* Find IRQ routing entry */
899
900 if (!pirq_table)
901 return 0;
902
903 info = pirq_get_info(dev);
904 if (!info) {
905 dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n",
906 'A' + pin - 1);
907 return 0;
908 }
909 pirq = info->irq[pin - 1].link;
910 mask = info->irq[pin - 1].bitmap;
911 if (!pirq) {
912 dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin - 1);
913 return 0;
914 }
915 dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x",
916 'A' + pin - 1, pirq, mask, pirq_table->exclusive_irqs);
917 mask &= pcibios_irq_mask;
918
919 /* Work around broken HP Pavilion Notebooks which assign USB to
920 IRQ 9 even though it is actually wired to IRQ 11 */
921
922 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
923 dev->irq = 11;
924 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
925 r->set(pirq_router_dev, dev, pirq, 11);
926 }
927
928 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
929 if (acer_tm360_irqrouting && dev->irq == 11 &&
930 dev->vendor == PCI_VENDOR_ID_O2) {
931 pirq = 0x68;
932 mask = 0x400;
933 dev->irq = r->get(pirq_router_dev, dev, pirq);
934 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
935 }
936
937 /*
938 * Find the best IRQ to assign: use the one
939 * reported by the device if possible.
940 */
941 newirq = dev->irq;
942 if (newirq && !((1 << newirq) & mask)) {
943 if (pci_probe & PCI_USE_PIRQ_MASK)
944 newirq = 0;
945 else
946 dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask "
947 "%#x; try pci=usepirqmask\n", newirq, mask);
948 }
949 if (!newirq && assign) {
950 for (i = 0; i < 16; i++) {
951 if (!(mask & (1 << i)))
952 continue;
953 if (pirq_penalty[i] < pirq_penalty[newirq] &&
954 can_request_irq(i, IRQF_SHARED))
955 newirq = i;
956 }
957 }
958 dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin - 1, newirq);
959
960 /* Check if it is hardcoded */
961 if ((pirq & 0xf0) == 0xf0) {
962 irq = pirq & 0xf;
963 msg = "hardcoded";
964 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
965 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) {
966 msg = "found";
967 eisa_set_level_irq(irq);
968 } else if (newirq && r->set &&
969 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
970 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
971 eisa_set_level_irq(newirq);
972 msg = "assigned";
973 irq = newirq;
974 }
975 }
976
977 if (!irq) {
978 if (newirq && mask == (1 << newirq)) {
979 msg = "guessed";
980 irq = newirq;
981 } else {
982 dev_dbg(&dev->dev, "can't route interrupt\n");
983 return 0;
984 }
985 }
986 dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin - 1, irq);
987
988 /* Update IRQ for all devices with the same pirq value */
989 for_each_pci_dev(dev2) {
990 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
991 if (!pin)
992 continue;
993
994 info = pirq_get_info(dev2);
995 if (!info)
996 continue;
997 if (info->irq[pin - 1].link == pirq) {
998 /*
999 * We refuse to override the dev->irq
1000 * information. Give a warning!
1001 */
1002 if (dev2->irq && dev2->irq != irq && \
1003 (!(pci_probe & PCI_USE_PIRQ_MASK) || \
1004 ((1 << dev2->irq) & mask))) {
1005#ifndef CONFIG_PCI_MSI
1006 dev_info(&dev2->dev, "IRQ routing conflict: "
1007 "have IRQ %d, want IRQ %d\n",
1008 dev2->irq, irq);
1009#endif
1010 continue;
1011 }
1012 dev2->irq = irq;
1013 pirq_penalty[irq]++;
1014 if (dev != dev2)
1015 dev_info(&dev->dev, "sharing IRQ %d with %s\n",
1016 irq, pci_name(dev2));
1017 }
1018 }
1019 return 1;
1020}
1021
1022void __init pcibios_fixup_irqs(void)
1023{
1024 struct pci_dev *dev = NULL;
1025 u8 pin;
1026
1027 DBG(KERN_DEBUG "PCI: IRQ fixup\n");
1028 for_each_pci_dev(dev) {
1029 /*
1030 * If the BIOS has set an out of range IRQ number, just
1031 * ignore it. Also keep track of which IRQ's are
1032 * already in use.
1033 */
1034 if (dev->irq >= 16) {
1035 dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq);
1036 dev->irq = 0;
1037 }
1038 /*
1039 * If the IRQ is already assigned to a PCI device,
1040 * ignore its ISA use penalty
1041 */
1042 if (pirq_penalty[dev->irq] >= 100 &&
1043 pirq_penalty[dev->irq] < 100000)
1044 pirq_penalty[dev->irq] = 0;
1045 pirq_penalty[dev->irq]++;
1046 }
1047
1048 if (io_apic_assign_pci_irqs)
1049 return;
1050
1051 dev = NULL;
1052 for_each_pci_dev(dev) {
1053 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1054 if (!pin)
1055 continue;
1056
1057 /*
1058 * Still no IRQ? Try to lookup one...
1059 */
1060 if (!dev->irq)
1061 pcibios_lookup_irq(dev, 0);
1062 }
1063}
1064
1065/*
1066 * Work around broken HP Pavilion Notebooks which assign USB to
1067 * IRQ 9 even though it is actually wired to IRQ 11
1068 */
1069static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d)
1070{
1071 if (!broken_hp_bios_irq9) {
1072 broken_hp_bios_irq9 = 1;
1073 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1074 d->ident);
1075 }
1076 return 0;
1077}
1078
1079/*
1080 * Work around broken Acer TravelMate 360 Notebooks which assign
1081 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
1082 */
1083static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d)
1084{
1085 if (!acer_tm360_irqrouting) {
1086 acer_tm360_irqrouting = 1;
1087 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1088 d->ident);
1089 }
1090 return 0;
1091}
1092
1093static struct dmi_system_id __initdata pciirq_dmi_table[] = {
1094 {
1095 .callback = fix_broken_hp_bios_irq9,
1096 .ident = "HP Pavilion N5400 Series Laptop",
1097 .matches = {
1098 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1099 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
1100 DMI_MATCH(DMI_PRODUCT_VERSION,
1101 "HP Pavilion Notebook Model GE"),
1102 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
1103 },
1104 },
1105 {
1106 .callback = fix_acer_tm360_irqrouting,
1107 .ident = "Acer TravelMate 36x Laptop",
1108 .matches = {
1109 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1110 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
1111 },
1112 },
1113 { }
1114};
1115
1116void __init pcibios_irq_init(void)
1117{
1118 DBG(KERN_DEBUG "PCI: IRQ init\n");
1119
1120 if (raw_pci_ops == NULL)
1121 return;
1122
1123 dmi_check_system(pciirq_dmi_table);
1124
1125 pirq_table = pirq_find_routing_table();
1126
1127#ifdef CONFIG_PCI_BIOS
1128 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
1129 pirq_table = pcibios_get_irq_routing_table();
1130#endif
1131 if (pirq_table) {
1132 pirq_peer_trick();
1133 pirq_find_router(&pirq_router);
1134 if (pirq_table->exclusive_irqs) {
1135 int i;
1136 for (i = 0; i < 16; i++)
1137 if (!(pirq_table->exclusive_irqs & (1 << i)))
1138 pirq_penalty[i] += 100;
1139 }
1140 /*
1141 * If we're using the I/O APIC, avoid using the PCI IRQ
1142 * routing table
1143 */
1144 if (io_apic_assign_pci_irqs)
1145 pirq_table = NULL;
1146 }
1147
1148 x86_init.pci.fixup_irqs();
1149
1150 if (io_apic_assign_pci_irqs && pci_routeirq) {
1151 struct pci_dev *dev = NULL;
1152 /*
1153 * PCI IRQ routing is set up by pci_enable_device(), but we
1154 * also do it here in case there are still broken drivers that
1155 * don't use pci_enable_device().
1156 */
1157 printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n");
1158 for_each_pci_dev(dev)
1159 pirq_enable_irq(dev);
1160 }
1161}
1162
1163static void pirq_penalize_isa_irq(int irq, int active)
1164{
1165 /*
1166 * If any ISAPnP device reports an IRQ in its list of possible
1167 * IRQ's, we try to avoid assigning it to PCI devices.
1168 */
1169 if (irq < 16) {
1170 if (active)
1171 pirq_penalty[irq] += 1000;
1172 else
1173 pirq_penalty[irq] += 100;
1174 }
1175}
1176
1177void pcibios_penalize_isa_irq(int irq, int active)
1178{
1179#ifdef CONFIG_ACPI
1180 if (!acpi_noirq)
1181 acpi_penalize_isa_irq(irq, active);
1182 else
1183#endif
1184 pirq_penalize_isa_irq(irq, active);
1185}
1186
1187static int pirq_enable_irq(struct pci_dev *dev)
1188{
1189 u8 pin;
1190
1191 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1192 if (pin && !pcibios_lookup_irq(dev, 1)) {
1193 char *msg = "";
1194
1195 if (!io_apic_assign_pci_irqs && dev->irq)
1196 return 0;
1197
1198 if (io_apic_assign_pci_irqs) {
1199#ifdef CONFIG_X86_IO_APIC
1200 struct pci_dev *temp_dev;
1201 int irq;
1202 struct io_apic_irq_attr irq_attr;
1203
1204 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number,
1205 PCI_SLOT(dev->devfn),
1206 pin - 1, &irq_attr);
1207 /*
1208 * Busses behind bridges are typically not listed in the MP-table.
1209 * In this case we have to look up the IRQ based on the parent bus,
1210 * parent slot, and pin number. The SMP code detects such bridged
1211 * busses itself so we should get into this branch reliably.
1212 */
1213 temp_dev = dev;
1214 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1215 struct pci_dev *bridge = dev->bus->self;
1216
1217 pin = pci_swizzle_interrupt_pin(dev, pin);
1218 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1219 PCI_SLOT(bridge->devfn),
1220 pin - 1, &irq_attr);
1221 if (irq >= 0)
1222 dev_warn(&dev->dev, "using bridge %s "
1223 "INT %c to get IRQ %d\n",
1224 pci_name(bridge), 'A' + pin - 1,
1225 irq);
1226 dev = bridge;
1227 }
1228 dev = temp_dev;
1229 if (irq >= 0) {
1230 io_apic_set_pci_routing(&dev->dev, irq,
1231 &irq_attr);
1232 dev->irq = irq;
1233 dev_info(&dev->dev, "PCI->APIC IRQ transform: "
1234 "INT %c -> IRQ %d\n", 'A' + pin - 1, irq);
1235 return 0;
1236 } else
1237 msg = "; probably buggy MP table";
1238#endif
1239 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1240 msg = "";
1241 else
1242 msg = "; please try using pci=biosirq";
1243
1244 /*
1245 * With IDE legacy devices the IRQ lookup failure is not
1246 * a problem..
1247 */
1248 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE &&
1249 !(dev->class & 0x5))
1250 return 0;
1251
1252 dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n",
1253 'A' + pin - 1, msg);
1254 }
1255 return 0;
1256}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Low-Level PCI Support for PC -- Routing of Interrupts
4 *
5 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
6 */
7
8#include <linux/types.h>
9#include <linux/kernel.h>
10#include <linux/pci.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/dmi.h>
14#include <linux/io.h>
15#include <linux/smp.h>
16#include <asm/io_apic.h>
17#include <linux/irq.h>
18#include <linux/acpi.h>
19#include <asm/pci_x86.h>
20
21#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
22#define PIRQ_VERSION 0x0100
23
24static int broken_hp_bios_irq9;
25static int acer_tm360_irqrouting;
26
27static struct irq_routing_table *pirq_table;
28
29static int pirq_enable_irq(struct pci_dev *dev);
30static void pirq_disable_irq(struct pci_dev *dev);
31
32/*
33 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
34 * Avoid using: 13, 14 and 15 (FP error and IDE).
35 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
36 */
37unsigned int pcibios_irq_mask = 0xfff8;
38
39static int pirq_penalty[16] = {
40 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
41 0, 0, 0, 0, 1000, 100000, 100000, 100000
42};
43
44struct irq_router {
45 char *name;
46 u16 vendor, device;
47 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
48 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq,
49 int new);
50};
51
52struct irq_router_handler {
53 u16 vendor;
54 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
55};
56
57int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq;
58void (*pcibios_disable_irq)(struct pci_dev *dev) = pirq_disable_irq;
59
60/*
61 * Check passed address for the PCI IRQ Routing Table signature
62 * and perform checksum verification.
63 */
64
65static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr)
66{
67 struct irq_routing_table *rt;
68 int i;
69 u8 sum;
70
71 rt = (struct irq_routing_table *) addr;
72 if (rt->signature != PIRQ_SIGNATURE ||
73 rt->version != PIRQ_VERSION ||
74 rt->size % 16 ||
75 rt->size < sizeof(struct irq_routing_table))
76 return NULL;
77 sum = 0;
78 for (i = 0; i < rt->size; i++)
79 sum += addr[i];
80 if (!sum) {
81 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n",
82 rt);
83 return rt;
84 }
85 return NULL;
86}
87
88
89
90/*
91 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
92 */
93
94static struct irq_routing_table * __init pirq_find_routing_table(void)
95{
96 u8 *addr;
97 struct irq_routing_table *rt;
98
99 if (pirq_table_addr) {
100 rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr));
101 if (rt)
102 return rt;
103 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n");
104 }
105 for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
106 rt = pirq_check_routing_table(addr);
107 if (rt)
108 return rt;
109 }
110 return NULL;
111}
112
113/*
114 * If we have a IRQ routing table, use it to search for peer host
115 * bridges. It's a gross hack, but since there are no other known
116 * ways how to get a list of buses, we have to go this way.
117 */
118
119static void __init pirq_peer_trick(void)
120{
121 struct irq_routing_table *rt = pirq_table;
122 u8 busmap[256];
123 int i;
124 struct irq_info *e;
125
126 memset(busmap, 0, sizeof(busmap));
127 for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
128 e = &rt->slots[i];
129#ifdef DEBUG
130 {
131 int j;
132 DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
133 for (j = 0; j < 4; j++)
134 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
135 DBG("\n");
136 }
137#endif
138 busmap[e->bus] = 1;
139 }
140 for (i = 1; i < 256; i++) {
141 if (!busmap[i] || pci_find_bus(0, i))
142 continue;
143 pcibios_scan_root(i);
144 }
145 pcibios_last_bus = -1;
146}
147
148/*
149 * Code for querying and setting of IRQ routes on various interrupt routers.
150 * PIC Edge/Level Control Registers (ELCR) 0x4d0 & 0x4d1.
151 */
152
153void elcr_set_level_irq(unsigned int irq)
154{
155 unsigned char mask = 1 << (irq & 7);
156 unsigned int port = 0x4d0 + (irq >> 3);
157 unsigned char val;
158 static u16 elcr_irq_mask;
159
160 if (irq >= 16 || (1 << irq) & elcr_irq_mask)
161 return;
162
163 elcr_irq_mask |= (1 << irq);
164 printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq);
165 val = inb(port);
166 if (!(val & mask)) {
167 DBG(KERN_DEBUG " -> edge");
168 outb(val | mask, port);
169 }
170}
171
172/*
173 * Common IRQ routing practice: nibbles in config space,
174 * offset by some magic constant.
175 */
176static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
177{
178 u8 x;
179 unsigned reg = offset + (nr >> 1);
180
181 pci_read_config_byte(router, reg, &x);
182 return (nr & 1) ? (x >> 4) : (x & 0xf);
183}
184
185static void write_config_nybble(struct pci_dev *router, unsigned offset,
186 unsigned nr, unsigned int val)
187{
188 u8 x;
189 unsigned reg = offset + (nr >> 1);
190
191 pci_read_config_byte(router, reg, &x);
192 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
193 pci_write_config_byte(router, reg, x);
194}
195
196/*
197 * ALI pirq entries are damn ugly, and completely undocumented.
198 * This has been figured out from pirq tables, and it's not a pretty
199 * picture.
200 */
201static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
202{
203 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
204
205 WARN_ON_ONCE(pirq > 16);
206 return irqmap[read_config_nybble(router, 0x48, pirq-1)];
207}
208
209static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
210{
211 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
212 unsigned int val = irqmap[irq];
213
214 WARN_ON_ONCE(pirq > 16);
215 if (val) {
216 write_config_nybble(router, 0x48, pirq-1, val);
217 return 1;
218 }
219 return 0;
220}
221
222/*
223 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
224 * just a pointer to the config space.
225 */
226static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
227{
228 u8 x;
229
230 pci_read_config_byte(router, pirq, &x);
231 return (x < 16) ? x : 0;
232}
233
234static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
235{
236 pci_write_config_byte(router, pirq, irq);
237 return 1;
238}
239
240/*
241 * The VIA pirq rules are nibble-based, like ALI,
242 * but without the ugly irq number munging.
243 * However, PIRQD is in the upper instead of lower 4 bits.
244 */
245static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
246{
247 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
248}
249
250static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
251{
252 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
253 return 1;
254}
255
256/*
257 * The VIA pirq rules are nibble-based, like ALI,
258 * but without the ugly irq number munging.
259 * However, for 82C586, nibble map is different .
260 */
261static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
262{
263 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
264
265 WARN_ON_ONCE(pirq > 5);
266 return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
267}
268
269static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
270{
271 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
272
273 WARN_ON_ONCE(pirq > 5);
274 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
275 return 1;
276}
277
278/*
279 * ITE 8330G pirq rules are nibble-based
280 * FIXME: pirqmap may be { 1, 0, 3, 2 },
281 * 2+3 are both mapped to irq 9 on my system
282 */
283static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
284{
285 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
286
287 WARN_ON_ONCE(pirq > 4);
288 return read_config_nybble(router, 0x43, pirqmap[pirq-1]);
289}
290
291static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
292{
293 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
294
295 WARN_ON_ONCE(pirq > 4);
296 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
297 return 1;
298}
299
300/*
301 * OPTI: high four bits are nibble pointer..
302 * I wonder what the low bits do?
303 */
304static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
305{
306 return read_config_nybble(router, 0xb8, pirq >> 4);
307}
308
309static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
310{
311 write_config_nybble(router, 0xb8, pirq >> 4, irq);
312 return 1;
313}
314
315/*
316 * Cyrix: nibble offset 0x5C
317 * 0x5C bits 7:4 is INTB bits 3:0 is INTA
318 * 0x5D bits 7:4 is INTD bits 3:0 is INTC
319 */
320static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
321{
322 return read_config_nybble(router, 0x5C, (pirq-1)^1);
323}
324
325static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
326{
327 write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
328 return 1;
329}
330
331/*
332 * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
333 * We have to deal with the following issues here:
334 * - vendors have different ideas about the meaning of link values
335 * - some onboard devices (integrated in the chipset) have special
336 * links and are thus routed differently (i.e. not via PCI INTA-INTD)
337 * - different revision of the router have a different layout for
338 * the routing registers, particularly for the onchip devices
339 *
340 * For all routing registers the common thing is we have one byte
341 * per routeable link which is defined as:
342 * bit 7 IRQ mapping enabled (0) or disabled (1)
343 * bits [6:4] reserved (sometimes used for onchip devices)
344 * bits [3:0] IRQ to map to
345 * allowed: 3-7, 9-12, 14-15
346 * reserved: 0, 1, 2, 8, 13
347 *
348 * The config-space registers located at 0x41/0x42/0x43/0x44 are
349 * always used to route the normal PCI INT A/B/C/D respectively.
350 * Apparently there are systems implementing PCI routing table using
351 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
352 * We try our best to handle both link mappings.
353 *
354 * Currently (2003-05-21) it appears most SiS chipsets follow the
355 * definition of routing registers from the SiS-5595 southbridge.
356 * According to the SiS 5595 datasheets the revision id's of the
357 * router (ISA-bridge) should be 0x01 or 0xb0.
358 *
359 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
360 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
361 * They seem to work with the current routing code. However there is
362 * some concern because of the two USB-OHCI HCs (original SiS 5595
363 * had only one). YMMV.
364 *
365 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
366 *
367 * 0x61: IDEIRQ:
368 * bits [6:5] must be written 01
369 * bit 4 channel-select primary (0), secondary (1)
370 *
371 * 0x62: USBIRQ:
372 * bit 6 OHCI function disabled (0), enabled (1)
373 *
374 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
375 *
376 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
377 *
378 * We support USBIRQ (in addition to INTA-INTD) and keep the
379 * IDE, ACPI and DAQ routing untouched as set by the BIOS.
380 *
381 * Currently the only reported exception is the new SiS 65x chipset
382 * which includes the SiS 69x southbridge. Here we have the 85C503
383 * router revision 0x04 and there are changes in the register layout
384 * mostly related to the different USB HCs with USB 2.0 support.
385 *
386 * Onchip routing for router rev-id 0x04 (try-and-error observation)
387 *
388 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
389 * bit 6-4 are probably unused, not like 5595
390 */
391
392#define PIRQ_SIS_IRQ_MASK 0x0f
393#define PIRQ_SIS_IRQ_DISABLE 0x80
394#define PIRQ_SIS_USB_ENABLE 0x40
395
396static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
397{
398 u8 x;
399 int reg;
400
401 reg = pirq;
402 if (reg >= 0x01 && reg <= 0x04)
403 reg += 0x40;
404 pci_read_config_byte(router, reg, &x);
405 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
406}
407
408static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
409{
410 u8 x;
411 int reg;
412
413 reg = pirq;
414 if (reg >= 0x01 && reg <= 0x04)
415 reg += 0x40;
416 pci_read_config_byte(router, reg, &x);
417 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
418 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
419 pci_write_config_byte(router, reg, x);
420 return 1;
421}
422
423
424/*
425 * VLSI: nibble offset 0x74 - educated guess due to routing table and
426 * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
427 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
428 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
429 * for the busbridge to the docking station.
430 */
431
432static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
433{
434 WARN_ON_ONCE(pirq >= 9);
435 if (pirq > 8) {
436 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
437 return 0;
438 }
439 return read_config_nybble(router, 0x74, pirq-1);
440}
441
442static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
443{
444 WARN_ON_ONCE(pirq >= 9);
445 if (pirq > 8) {
446 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
447 return 0;
448 }
449 write_config_nybble(router, 0x74, pirq-1, irq);
450 return 1;
451}
452
453/*
454 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
455 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
456 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
457 * register is a straight binary coding of desired PIC IRQ (low nibble).
458 *
459 * The 'link' value in the PIRQ table is already in the correct format
460 * for the Index register. There are some special index values:
461 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
462 * and 0x03 for SMBus.
463 */
464static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
465{
466 outb(pirq, 0xc00);
467 return inb(0xc01) & 0xf;
468}
469
470static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev,
471 int pirq, int irq)
472{
473 outb(pirq, 0xc00);
474 outb(irq, 0xc01);
475 return 1;
476}
477
478/* Support for AMD756 PCI IRQ Routing
479 * Jhon H. Caicedo <jhcaiced@osso.org.co>
480 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
481 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
482 * The AMD756 pirq rules are nibble-based
483 * offset 0x56 0-3 PIRQA 4-7 PIRQB
484 * offset 0x57 0-3 PIRQC 4-7 PIRQD
485 */
486static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
487{
488 u8 irq;
489 irq = 0;
490 if (pirq <= 4)
491 irq = read_config_nybble(router, 0x56, pirq - 1);
492 dev_info(&dev->dev,
493 "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n",
494 dev->vendor, dev->device, pirq, irq);
495 return irq;
496}
497
498static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
499{
500 dev_info(&dev->dev,
501 "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n",
502 dev->vendor, dev->device, pirq, irq);
503 if (pirq <= 4)
504 write_config_nybble(router, 0x56, pirq - 1, irq);
505 return 1;
506}
507
508/*
509 * PicoPower PT86C523
510 */
511static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
512{
513 outb(0x10 + ((pirq - 1) >> 1), 0x24);
514 return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf);
515}
516
517static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
518 int irq)
519{
520 unsigned int x;
521 outb(0x10 + ((pirq - 1) >> 1), 0x24);
522 x = inb(0x26);
523 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq));
524 outb(x, 0x26);
525 return 1;
526}
527
528#ifdef CONFIG_PCI_BIOS
529
530static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
531{
532 struct pci_dev *bridge;
533 int pin = pci_get_interrupt_pin(dev, &bridge);
534 return pcibios_set_irq_routing(bridge, pin - 1, irq);
535}
536
537#endif
538
539static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
540{
541 static struct pci_device_id __initdata pirq_440gx[] = {
542 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
543 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
544 { },
545 };
546
547 /* 440GX has a proprietary PIRQ router -- don't use it */
548 if (pci_dev_present(pirq_440gx))
549 return 0;
550
551 switch (device) {
552 case PCI_DEVICE_ID_INTEL_82371FB_0:
553 case PCI_DEVICE_ID_INTEL_82371SB_0:
554 case PCI_DEVICE_ID_INTEL_82371AB_0:
555 case PCI_DEVICE_ID_INTEL_82371MX:
556 case PCI_DEVICE_ID_INTEL_82443MX_0:
557 case PCI_DEVICE_ID_INTEL_82801AA_0:
558 case PCI_DEVICE_ID_INTEL_82801AB_0:
559 case PCI_DEVICE_ID_INTEL_82801BA_0:
560 case PCI_DEVICE_ID_INTEL_82801BA_10:
561 case PCI_DEVICE_ID_INTEL_82801CA_0:
562 case PCI_DEVICE_ID_INTEL_82801CA_12:
563 case PCI_DEVICE_ID_INTEL_82801DB_0:
564 case PCI_DEVICE_ID_INTEL_82801E_0:
565 case PCI_DEVICE_ID_INTEL_82801EB_0:
566 case PCI_DEVICE_ID_INTEL_ESB_1:
567 case PCI_DEVICE_ID_INTEL_ICH6_0:
568 case PCI_DEVICE_ID_INTEL_ICH6_1:
569 case PCI_DEVICE_ID_INTEL_ICH7_0:
570 case PCI_DEVICE_ID_INTEL_ICH7_1:
571 case PCI_DEVICE_ID_INTEL_ICH7_30:
572 case PCI_DEVICE_ID_INTEL_ICH7_31:
573 case PCI_DEVICE_ID_INTEL_TGP_LPC:
574 case PCI_DEVICE_ID_INTEL_ESB2_0:
575 case PCI_DEVICE_ID_INTEL_ICH8_0:
576 case PCI_DEVICE_ID_INTEL_ICH8_1:
577 case PCI_DEVICE_ID_INTEL_ICH8_2:
578 case PCI_DEVICE_ID_INTEL_ICH8_3:
579 case PCI_DEVICE_ID_INTEL_ICH8_4:
580 case PCI_DEVICE_ID_INTEL_ICH9_0:
581 case PCI_DEVICE_ID_INTEL_ICH9_1:
582 case PCI_DEVICE_ID_INTEL_ICH9_2:
583 case PCI_DEVICE_ID_INTEL_ICH9_3:
584 case PCI_DEVICE_ID_INTEL_ICH9_4:
585 case PCI_DEVICE_ID_INTEL_ICH9_5:
586 case PCI_DEVICE_ID_INTEL_EP80579_0:
587 case PCI_DEVICE_ID_INTEL_ICH10_0:
588 case PCI_DEVICE_ID_INTEL_ICH10_1:
589 case PCI_DEVICE_ID_INTEL_ICH10_2:
590 case PCI_DEVICE_ID_INTEL_ICH10_3:
591 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0:
592 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1:
593 r->name = "PIIX/ICH";
594 r->get = pirq_piix_get;
595 r->set = pirq_piix_set;
596 return 1;
597 }
598
599 if ((device >= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN &&
600 device <= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX)
601 || (device >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
602 device <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX)
603 || (device >= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN &&
604 device <= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX)
605 || (device >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
606 device <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) {
607 r->name = "PIIX/ICH";
608 r->get = pirq_piix_get;
609 r->set = pirq_piix_set;
610 return 1;
611 }
612
613 return 0;
614}
615
616static __init int via_router_probe(struct irq_router *r,
617 struct pci_dev *router, u16 device)
618{
619 /* FIXME: We should move some of the quirk fixup stuff here */
620
621 /*
622 * workarounds for some buggy BIOSes
623 */
624 if (device == PCI_DEVICE_ID_VIA_82C586_0) {
625 switch (router->device) {
626 case PCI_DEVICE_ID_VIA_82C686:
627 /*
628 * Asus k7m bios wrongly reports 82C686A
629 * as 586-compatible
630 */
631 device = PCI_DEVICE_ID_VIA_82C686;
632 break;
633 case PCI_DEVICE_ID_VIA_8235:
634 /**
635 * Asus a7v-x bios wrongly reports 8235
636 * as 586-compatible
637 */
638 device = PCI_DEVICE_ID_VIA_8235;
639 break;
640 case PCI_DEVICE_ID_VIA_8237:
641 /**
642 * Asus a7v600 bios wrongly reports 8237
643 * as 586-compatible
644 */
645 device = PCI_DEVICE_ID_VIA_8237;
646 break;
647 }
648 }
649
650 switch (device) {
651 case PCI_DEVICE_ID_VIA_82C586_0:
652 r->name = "VIA";
653 r->get = pirq_via586_get;
654 r->set = pirq_via586_set;
655 return 1;
656 case PCI_DEVICE_ID_VIA_82C596:
657 case PCI_DEVICE_ID_VIA_82C686:
658 case PCI_DEVICE_ID_VIA_8231:
659 case PCI_DEVICE_ID_VIA_8233A:
660 case PCI_DEVICE_ID_VIA_8235:
661 case PCI_DEVICE_ID_VIA_8237:
662 /* FIXME: add new ones for 8233/5 */
663 r->name = "VIA";
664 r->get = pirq_via_get;
665 r->set = pirq_via_set;
666 return 1;
667 }
668 return 0;
669}
670
671static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
672{
673 switch (device) {
674 case PCI_DEVICE_ID_VLSI_82C534:
675 r->name = "VLSI 82C534";
676 r->get = pirq_vlsi_get;
677 r->set = pirq_vlsi_set;
678 return 1;
679 }
680 return 0;
681}
682
683
684static __init int serverworks_router_probe(struct irq_router *r,
685 struct pci_dev *router, u16 device)
686{
687 switch (device) {
688 case PCI_DEVICE_ID_SERVERWORKS_OSB4:
689 case PCI_DEVICE_ID_SERVERWORKS_CSB5:
690 r->name = "ServerWorks";
691 r->get = pirq_serverworks_get;
692 r->set = pirq_serverworks_set;
693 return 1;
694 }
695 return 0;
696}
697
698static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
699{
700 if (device != PCI_DEVICE_ID_SI_503)
701 return 0;
702
703 r->name = "SIS";
704 r->get = pirq_sis_get;
705 r->set = pirq_sis_set;
706 return 1;
707}
708
709static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
710{
711 switch (device) {
712 case PCI_DEVICE_ID_CYRIX_5520:
713 r->name = "NatSemi";
714 r->get = pirq_cyrix_get;
715 r->set = pirq_cyrix_set;
716 return 1;
717 }
718 return 0;
719}
720
721static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
722{
723 switch (device) {
724 case PCI_DEVICE_ID_OPTI_82C700:
725 r->name = "OPTI";
726 r->get = pirq_opti_get;
727 r->set = pirq_opti_set;
728 return 1;
729 }
730 return 0;
731}
732
733static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
734{
735 switch (device) {
736 case PCI_DEVICE_ID_ITE_IT8330G_0:
737 r->name = "ITE";
738 r->get = pirq_ite_get;
739 r->set = pirq_ite_set;
740 return 1;
741 }
742 return 0;
743}
744
745static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
746{
747 switch (device) {
748 case PCI_DEVICE_ID_AL_M1533:
749 case PCI_DEVICE_ID_AL_M1563:
750 r->name = "ALI";
751 r->get = pirq_ali_get;
752 r->set = pirq_ali_set;
753 return 1;
754 }
755 return 0;
756}
757
758static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
759{
760 switch (device) {
761 case PCI_DEVICE_ID_AMD_VIPER_740B:
762 r->name = "AMD756";
763 break;
764 case PCI_DEVICE_ID_AMD_VIPER_7413:
765 r->name = "AMD766";
766 break;
767 case PCI_DEVICE_ID_AMD_VIPER_7443:
768 r->name = "AMD768";
769 break;
770 default:
771 return 0;
772 }
773 r->get = pirq_amd756_get;
774 r->set = pirq_amd756_set;
775 return 1;
776}
777
778static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
779{
780 switch (device) {
781 case PCI_DEVICE_ID_PICOPOWER_PT86C523:
782 r->name = "PicoPower PT86C523";
783 r->get = pirq_pico_get;
784 r->set = pirq_pico_set;
785 return 1;
786
787 case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP:
788 r->name = "PicoPower PT86C523 rev. BB+";
789 r->get = pirq_pico_get;
790 r->set = pirq_pico_set;
791 return 1;
792 }
793 return 0;
794}
795
796static __initdata struct irq_router_handler pirq_routers[] = {
797 { PCI_VENDOR_ID_INTEL, intel_router_probe },
798 { PCI_VENDOR_ID_AL, ali_router_probe },
799 { PCI_VENDOR_ID_ITE, ite_router_probe },
800 { PCI_VENDOR_ID_VIA, via_router_probe },
801 { PCI_VENDOR_ID_OPTI, opti_router_probe },
802 { PCI_VENDOR_ID_SI, sis_router_probe },
803 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
804 { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
805 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
806 { PCI_VENDOR_ID_AMD, amd_router_probe },
807 { PCI_VENDOR_ID_PICOPOWER, pico_router_probe },
808 /* Someone with docs needs to add the ATI Radeon IGP */
809 { 0, NULL }
810};
811static struct irq_router pirq_router;
812static struct pci_dev *pirq_router_dev;
813
814
815/*
816 * FIXME: should we have an option to say "generic for
817 * chipset" ?
818 */
819
820static void __init pirq_find_router(struct irq_router *r)
821{
822 struct irq_routing_table *rt = pirq_table;
823 struct irq_router_handler *h;
824
825#ifdef CONFIG_PCI_BIOS
826 if (!rt->signature) {
827 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
828 r->set = pirq_bios_set;
829 r->name = "BIOS";
830 return;
831 }
832#endif
833
834 /* Default unless a driver reloads it */
835 r->name = "default";
836 r->get = NULL;
837 r->set = NULL;
838
839 DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n",
840 rt->rtr_vendor, rt->rtr_device);
841
842 pirq_router_dev = pci_get_domain_bus_and_slot(0, rt->rtr_bus,
843 rt->rtr_devfn);
844 if (!pirq_router_dev) {
845 DBG(KERN_DEBUG "PCI: Interrupt router not found at "
846 "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
847 return;
848 }
849
850 for (h = pirq_routers; h->vendor; h++) {
851 /* First look for a router match */
852 if (rt->rtr_vendor == h->vendor &&
853 h->probe(r, pirq_router_dev, rt->rtr_device))
854 break;
855 /* Fall back to a device match */
856 if (pirq_router_dev->vendor == h->vendor &&
857 h->probe(r, pirq_router_dev, pirq_router_dev->device))
858 break;
859 }
860 dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n",
861 pirq_router.name,
862 pirq_router_dev->vendor, pirq_router_dev->device);
863
864 /* The device remains referenced for the kernel lifetime */
865}
866
867static struct irq_info *pirq_get_info(struct pci_dev *dev)
868{
869 struct irq_routing_table *rt = pirq_table;
870 int entries = (rt->size - sizeof(struct irq_routing_table)) /
871 sizeof(struct irq_info);
872 struct irq_info *info;
873
874 for (info = rt->slots; entries--; info++)
875 if (info->bus == dev->bus->number &&
876 PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
877 return info;
878 return NULL;
879}
880
881static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
882{
883 u8 pin;
884 struct irq_info *info;
885 int i, pirq, newirq;
886 int irq = 0;
887 u32 mask;
888 struct irq_router *r = &pirq_router;
889 struct pci_dev *dev2 = NULL;
890 char *msg = NULL;
891
892 /* Find IRQ pin */
893 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
894 if (!pin) {
895 dev_dbg(&dev->dev, "no interrupt pin\n");
896 return 0;
897 }
898
899 if (io_apic_assign_pci_irqs)
900 return 0;
901
902 /* Find IRQ routing entry */
903
904 if (!pirq_table)
905 return 0;
906
907 info = pirq_get_info(dev);
908 if (!info) {
909 dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n",
910 'A' + pin - 1);
911 return 0;
912 }
913 pirq = info->irq[pin - 1].link;
914 mask = info->irq[pin - 1].bitmap;
915 if (!pirq) {
916 dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin - 1);
917 return 0;
918 }
919 dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x",
920 'A' + pin - 1, pirq, mask, pirq_table->exclusive_irqs);
921 mask &= pcibios_irq_mask;
922
923 /* Work around broken HP Pavilion Notebooks which assign USB to
924 IRQ 9 even though it is actually wired to IRQ 11 */
925
926 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
927 dev->irq = 11;
928 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
929 r->set(pirq_router_dev, dev, pirq, 11);
930 }
931
932 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
933 if (acer_tm360_irqrouting && dev->irq == 11 &&
934 dev->vendor == PCI_VENDOR_ID_O2) {
935 pirq = 0x68;
936 mask = 0x400;
937 dev->irq = r->get(pirq_router_dev, dev, pirq);
938 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
939 }
940
941 /*
942 * Find the best IRQ to assign: use the one
943 * reported by the device if possible.
944 */
945 newirq = dev->irq;
946 if (newirq && !((1 << newirq) & mask)) {
947 if (pci_probe & PCI_USE_PIRQ_MASK)
948 newirq = 0;
949 else
950 dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask "
951 "%#x; try pci=usepirqmask\n", newirq, mask);
952 }
953 if (!newirq && assign) {
954 for (i = 0; i < 16; i++) {
955 if (!(mask & (1 << i)))
956 continue;
957 if (pirq_penalty[i] < pirq_penalty[newirq] &&
958 can_request_irq(i, IRQF_SHARED))
959 newirq = i;
960 }
961 }
962 dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin - 1, newirq);
963
964 /* Check if it is hardcoded */
965 if ((pirq & 0xf0) == 0xf0) {
966 irq = pirq & 0xf;
967 msg = "hardcoded";
968 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
969 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) {
970 msg = "found";
971 elcr_set_level_irq(irq);
972 } else if (newirq && r->set &&
973 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
974 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
975 elcr_set_level_irq(newirq);
976 msg = "assigned";
977 irq = newirq;
978 }
979 }
980
981 if (!irq) {
982 if (newirq && mask == (1 << newirq)) {
983 msg = "guessed";
984 irq = newirq;
985 } else {
986 dev_dbg(&dev->dev, "can't route interrupt\n");
987 return 0;
988 }
989 }
990 dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin - 1, irq);
991
992 /* Update IRQ for all devices with the same pirq value */
993 for_each_pci_dev(dev2) {
994 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
995 if (!pin)
996 continue;
997
998 info = pirq_get_info(dev2);
999 if (!info)
1000 continue;
1001 if (info->irq[pin - 1].link == pirq) {
1002 /*
1003 * We refuse to override the dev->irq
1004 * information. Give a warning!
1005 */
1006 if (dev2->irq && dev2->irq != irq && \
1007 (!(pci_probe & PCI_USE_PIRQ_MASK) || \
1008 ((1 << dev2->irq) & mask))) {
1009#ifndef CONFIG_PCI_MSI
1010 dev_info(&dev2->dev, "IRQ routing conflict: "
1011 "have IRQ %d, want IRQ %d\n",
1012 dev2->irq, irq);
1013#endif
1014 continue;
1015 }
1016 dev2->irq = irq;
1017 pirq_penalty[irq]++;
1018 if (dev != dev2)
1019 dev_info(&dev->dev, "sharing IRQ %d with %s\n",
1020 irq, pci_name(dev2));
1021 }
1022 }
1023 return 1;
1024}
1025
1026void __init pcibios_fixup_irqs(void)
1027{
1028 struct pci_dev *dev = NULL;
1029 u8 pin;
1030
1031 DBG(KERN_DEBUG "PCI: IRQ fixup\n");
1032 for_each_pci_dev(dev) {
1033 /*
1034 * If the BIOS has set an out of range IRQ number, just
1035 * ignore it. Also keep track of which IRQ's are
1036 * already in use.
1037 */
1038 if (dev->irq >= 16) {
1039 dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq);
1040 dev->irq = 0;
1041 }
1042 /*
1043 * If the IRQ is already assigned to a PCI device,
1044 * ignore its ISA use penalty
1045 */
1046 if (pirq_penalty[dev->irq] >= 100 &&
1047 pirq_penalty[dev->irq] < 100000)
1048 pirq_penalty[dev->irq] = 0;
1049 pirq_penalty[dev->irq]++;
1050 }
1051
1052 if (io_apic_assign_pci_irqs)
1053 return;
1054
1055 dev = NULL;
1056 for_each_pci_dev(dev) {
1057 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1058 if (!pin)
1059 continue;
1060
1061 /*
1062 * Still no IRQ? Try to lookup one...
1063 */
1064 if (!dev->irq)
1065 pcibios_lookup_irq(dev, 0);
1066 }
1067}
1068
1069/*
1070 * Work around broken HP Pavilion Notebooks which assign USB to
1071 * IRQ 9 even though it is actually wired to IRQ 11
1072 */
1073static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d)
1074{
1075 if (!broken_hp_bios_irq9) {
1076 broken_hp_bios_irq9 = 1;
1077 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1078 d->ident);
1079 }
1080 return 0;
1081}
1082
1083/*
1084 * Work around broken Acer TravelMate 360 Notebooks which assign
1085 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
1086 */
1087static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d)
1088{
1089 if (!acer_tm360_irqrouting) {
1090 acer_tm360_irqrouting = 1;
1091 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1092 d->ident);
1093 }
1094 return 0;
1095}
1096
1097static const struct dmi_system_id pciirq_dmi_table[] __initconst = {
1098 {
1099 .callback = fix_broken_hp_bios_irq9,
1100 .ident = "HP Pavilion N5400 Series Laptop",
1101 .matches = {
1102 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1103 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
1104 DMI_MATCH(DMI_PRODUCT_VERSION,
1105 "HP Pavilion Notebook Model GE"),
1106 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
1107 },
1108 },
1109 {
1110 .callback = fix_acer_tm360_irqrouting,
1111 .ident = "Acer TravelMate 36x Laptop",
1112 .matches = {
1113 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1114 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
1115 },
1116 },
1117 { }
1118};
1119
1120void __init pcibios_irq_init(void)
1121{
1122 struct irq_routing_table *rtable = NULL;
1123
1124 DBG(KERN_DEBUG "PCI: IRQ init\n");
1125
1126 if (raw_pci_ops == NULL)
1127 return;
1128
1129 dmi_check_system(pciirq_dmi_table);
1130
1131 pirq_table = pirq_find_routing_table();
1132
1133#ifdef CONFIG_PCI_BIOS
1134 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) {
1135 pirq_table = pcibios_get_irq_routing_table();
1136 rtable = pirq_table;
1137 }
1138#endif
1139 if (pirq_table) {
1140 pirq_peer_trick();
1141 pirq_find_router(&pirq_router);
1142 if (pirq_table->exclusive_irqs) {
1143 int i;
1144 for (i = 0; i < 16; i++)
1145 if (!(pirq_table->exclusive_irqs & (1 << i)))
1146 pirq_penalty[i] += 100;
1147 }
1148 /*
1149 * If we're using the I/O APIC, avoid using the PCI IRQ
1150 * routing table
1151 */
1152 if (io_apic_assign_pci_irqs) {
1153 kfree(rtable);
1154 pirq_table = NULL;
1155 }
1156 }
1157
1158 x86_init.pci.fixup_irqs();
1159
1160 if (io_apic_assign_pci_irqs && pci_routeirq) {
1161 struct pci_dev *dev = NULL;
1162 /*
1163 * PCI IRQ routing is set up by pci_enable_device(), but we
1164 * also do it here in case there are still broken drivers that
1165 * don't use pci_enable_device().
1166 */
1167 printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n");
1168 for_each_pci_dev(dev)
1169 pirq_enable_irq(dev);
1170 }
1171}
1172
1173static void pirq_penalize_isa_irq(int irq, int active)
1174{
1175 /*
1176 * If any ISAPnP device reports an IRQ in its list of possible
1177 * IRQ's, we try to avoid assigning it to PCI devices.
1178 */
1179 if (irq < 16) {
1180 if (active)
1181 pirq_penalty[irq] += 1000;
1182 else
1183 pirq_penalty[irq] += 100;
1184 }
1185}
1186
1187void pcibios_penalize_isa_irq(int irq, int active)
1188{
1189#ifdef CONFIG_ACPI
1190 if (!acpi_noirq)
1191 acpi_penalize_isa_irq(irq, active);
1192 else
1193#endif
1194 pirq_penalize_isa_irq(irq, active);
1195}
1196
1197static int pirq_enable_irq(struct pci_dev *dev)
1198{
1199 u8 pin = 0;
1200
1201 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1202 if (pin && !pcibios_lookup_irq(dev, 1)) {
1203 char *msg = "";
1204
1205 if (!io_apic_assign_pci_irqs && dev->irq)
1206 return 0;
1207
1208 if (io_apic_assign_pci_irqs) {
1209#ifdef CONFIG_X86_IO_APIC
1210 struct pci_dev *temp_dev;
1211 int irq;
1212
1213 if (dev->irq_managed && dev->irq > 0)
1214 return 0;
1215
1216 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number,
1217 PCI_SLOT(dev->devfn), pin - 1);
1218 /*
1219 * Busses behind bridges are typically not listed in the MP-table.
1220 * In this case we have to look up the IRQ based on the parent bus,
1221 * parent slot, and pin number. The SMP code detects such bridged
1222 * busses itself so we should get into this branch reliably.
1223 */
1224 temp_dev = dev;
1225 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1226 struct pci_dev *bridge = dev->bus->self;
1227
1228 pin = pci_swizzle_interrupt_pin(dev, pin);
1229 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1230 PCI_SLOT(bridge->devfn),
1231 pin - 1);
1232 if (irq >= 0)
1233 dev_warn(&dev->dev, "using bridge %s "
1234 "INT %c to get IRQ %d\n",
1235 pci_name(bridge), 'A' + pin - 1,
1236 irq);
1237 dev = bridge;
1238 }
1239 dev = temp_dev;
1240 if (irq >= 0) {
1241 dev->irq_managed = 1;
1242 dev->irq = irq;
1243 dev_info(&dev->dev, "PCI->APIC IRQ transform: "
1244 "INT %c -> IRQ %d\n", 'A' + pin - 1, irq);
1245 return 0;
1246 } else
1247 msg = "; probably buggy MP table";
1248#endif
1249 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1250 msg = "";
1251 else
1252 msg = "; please try using pci=biosirq";
1253
1254 /*
1255 * With IDE legacy devices the IRQ lookup failure is not
1256 * a problem..
1257 */
1258 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE &&
1259 !(dev->class & 0x5))
1260 return 0;
1261
1262 dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n",
1263 'A' + pin - 1, msg);
1264 }
1265 return 0;
1266}
1267
1268bool mp_should_keep_irq(struct device *dev)
1269{
1270 if (dev->power.is_prepared)
1271 return true;
1272#ifdef CONFIG_PM
1273 if (dev->power.runtime_status == RPM_SUSPENDING)
1274 return true;
1275#endif
1276
1277 return false;
1278}
1279
1280static void pirq_disable_irq(struct pci_dev *dev)
1281{
1282 if (io_apic_assign_pci_irqs && !mp_should_keep_irq(&dev->dev) &&
1283 dev->irq_managed && dev->irq) {
1284 mp_unmap_irq(dev->irq);
1285 dev->irq = 0;
1286 dev->irq_managed = 0;
1287 }
1288}