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1/*
2 * Atheros AR71XX/AR724X/AR913X SoC register definitions
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 */
14
15#ifndef __ASM_MACH_AR71XX_REGS_H
16#define __ASM_MACH_AR71XX_REGS_H
17
18#include <linux/types.h>
19#include <linux/io.h>
20#include <linux/bitops.h>
21
22#define AR71XX_APB_BASE 0x18000000
23#define AR71XX_EHCI_BASE 0x1b000000
24#define AR71XX_EHCI_SIZE 0x1000
25#define AR71XX_OHCI_BASE 0x1c000000
26#define AR71XX_OHCI_SIZE 0x1000
27#define AR71XX_SPI_BASE 0x1f000000
28#define AR71XX_SPI_SIZE 0x01000000
29
30#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
31#define AR71XX_DDR_CTRL_SIZE 0x100
32#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
33#define AR71XX_UART_SIZE 0x100
34#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
35#define AR71XX_USB_CTRL_SIZE 0x100
36#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
37#define AR71XX_GPIO_SIZE 0x100
38#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
39#define AR71XX_PLL_SIZE 0x100
40#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
41#define AR71XX_RESET_SIZE 0x100
42
43#define AR71XX_PCI_MEM_BASE 0x10000000
44#define AR71XX_PCI_MEM_SIZE 0x07000000
45
46#define AR71XX_PCI_WIN0_OFFS 0x10000000
47#define AR71XX_PCI_WIN1_OFFS 0x11000000
48#define AR71XX_PCI_WIN2_OFFS 0x12000000
49#define AR71XX_PCI_WIN3_OFFS 0x13000000
50#define AR71XX_PCI_WIN4_OFFS 0x14000000
51#define AR71XX_PCI_WIN5_OFFS 0x15000000
52#define AR71XX_PCI_WIN6_OFFS 0x16000000
53#define AR71XX_PCI_WIN7_OFFS 0x07000000
54
55#define AR71XX_PCI_CFG_BASE \
56 (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
57#define AR71XX_PCI_CFG_SIZE 0x100
58
59#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
60#define AR7240_USB_CTRL_SIZE 0x100
61#define AR7240_OHCI_BASE 0x1b000000
62#define AR7240_OHCI_SIZE 0x1000
63
64#define AR724X_PCI_MEM_BASE 0x10000000
65#define AR724X_PCI_MEM_SIZE 0x04000000
66
67#define AR724X_PCI_CFG_BASE 0x14000000
68#define AR724X_PCI_CFG_SIZE 0x1000
69#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000)
70#define AR724X_PCI_CRP_SIZE 0x1000
71#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
72#define AR724X_PCI_CTRL_SIZE 0x100
73
74#define AR724X_EHCI_BASE 0x1b000000
75#define AR724X_EHCI_SIZE 0x1000
76
77#define AR913X_EHCI_BASE 0x1b000000
78#define AR913X_EHCI_SIZE 0x1000
79#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
80#define AR913X_WMAC_SIZE 0x30000
81
82#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
83#define AR933X_UART_SIZE 0x14
84#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
85#define AR933X_WMAC_SIZE 0x20000
86#define AR933X_EHCI_BASE 0x1b000000
87#define AR933X_EHCI_SIZE 0x1000
88
89#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
90#define AR934X_WMAC_SIZE 0x20000
91#define AR934X_EHCI_BASE 0x1b000000
92#define AR934X_EHCI_SIZE 0x200
93#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
94#define AR934X_SRIF_SIZE 0x1000
95
96#define QCA955X_PCI_MEM_BASE0 0x10000000
97#define QCA955X_PCI_MEM_BASE1 0x12000000
98#define QCA955X_PCI_MEM_SIZE 0x02000000
99#define QCA955X_PCI_CFG_BASE0 0x14000000
100#define QCA955X_PCI_CFG_BASE1 0x16000000
101#define QCA955X_PCI_CFG_SIZE 0x1000
102#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
103#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
104#define QCA955X_PCI_CRP_SIZE 0x1000
105#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
106#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
107#define QCA955X_PCI_CTRL_SIZE 0x100
108
109#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
110#define QCA955X_WMAC_SIZE 0x20000
111#define QCA955X_EHCI0_BASE 0x1b000000
112#define QCA955X_EHCI1_BASE 0x1b400000
113#define QCA955X_EHCI_SIZE 0x1000
114
115/*
116 * DDR_CTRL block
117 */
118#define AR71XX_DDR_REG_PCI_WIN0 0x7c
119#define AR71XX_DDR_REG_PCI_WIN1 0x80
120#define AR71XX_DDR_REG_PCI_WIN2 0x84
121#define AR71XX_DDR_REG_PCI_WIN3 0x88
122#define AR71XX_DDR_REG_PCI_WIN4 0x8c
123#define AR71XX_DDR_REG_PCI_WIN5 0x90
124#define AR71XX_DDR_REG_PCI_WIN6 0x94
125#define AR71XX_DDR_REG_PCI_WIN7 0x98
126#define AR71XX_DDR_REG_FLUSH_GE0 0x9c
127#define AR71XX_DDR_REG_FLUSH_GE1 0xa0
128#define AR71XX_DDR_REG_FLUSH_USB 0xa4
129#define AR71XX_DDR_REG_FLUSH_PCI 0xa8
130
131#define AR724X_DDR_REG_FLUSH_GE0 0x7c
132#define AR724X_DDR_REG_FLUSH_GE1 0x80
133#define AR724X_DDR_REG_FLUSH_USB 0x84
134#define AR724X_DDR_REG_FLUSH_PCIE 0x88
135
136#define AR913X_DDR_REG_FLUSH_GE0 0x7c
137#define AR913X_DDR_REG_FLUSH_GE1 0x80
138#define AR913X_DDR_REG_FLUSH_USB 0x84
139#define AR913X_DDR_REG_FLUSH_WMAC 0x88
140
141#define AR933X_DDR_REG_FLUSH_GE0 0x7c
142#define AR933X_DDR_REG_FLUSH_GE1 0x80
143#define AR933X_DDR_REG_FLUSH_USB 0x84
144#define AR933X_DDR_REG_FLUSH_WMAC 0x88
145
146#define AR934X_DDR_REG_FLUSH_GE0 0x9c
147#define AR934X_DDR_REG_FLUSH_GE1 0xa0
148#define AR934X_DDR_REG_FLUSH_USB 0xa4
149#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
150#define AR934X_DDR_REG_FLUSH_WMAC 0xac
151
152/*
153 * PLL block
154 */
155#define AR71XX_PLL_REG_CPU_CONFIG 0x00
156#define AR71XX_PLL_REG_SEC_CONFIG 0x04
157#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
158#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
159
160#define AR71XX_PLL_DIV_SHIFT 3
161#define AR71XX_PLL_DIV_MASK 0x1f
162#define AR71XX_CPU_DIV_SHIFT 16
163#define AR71XX_CPU_DIV_MASK 0x3
164#define AR71XX_DDR_DIV_SHIFT 18
165#define AR71XX_DDR_DIV_MASK 0x3
166#define AR71XX_AHB_DIV_SHIFT 20
167#define AR71XX_AHB_DIV_MASK 0x7
168
169#define AR724X_PLL_REG_CPU_CONFIG 0x00
170#define AR724X_PLL_REG_PCIE_CONFIG 0x18
171
172#define AR724X_PLL_DIV_SHIFT 0
173#define AR724X_PLL_DIV_MASK 0x3ff
174#define AR724X_PLL_REF_DIV_SHIFT 10
175#define AR724X_PLL_REF_DIV_MASK 0xf
176#define AR724X_AHB_DIV_SHIFT 19
177#define AR724X_AHB_DIV_MASK 0x1
178#define AR724X_DDR_DIV_SHIFT 22
179#define AR724X_DDR_DIV_MASK 0x3
180
181#define AR913X_PLL_REG_CPU_CONFIG 0x00
182#define AR913X_PLL_REG_ETH_CONFIG 0x04
183#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
184#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18
185
186#define AR913X_PLL_DIV_SHIFT 0
187#define AR913X_PLL_DIV_MASK 0x3ff
188#define AR913X_DDR_DIV_SHIFT 22
189#define AR913X_DDR_DIV_MASK 0x3
190#define AR913X_AHB_DIV_SHIFT 19
191#define AR913X_AHB_DIV_MASK 0x1
192
193#define AR933X_PLL_CPU_CONFIG_REG 0x00
194#define AR933X_PLL_CLOCK_CTRL_REG 0x08
195
196#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
197#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
198#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
199#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
200#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
201#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
202
203#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
204#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
205#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
206#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
207#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
208#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
209#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
210
211#define AR934X_PLL_CPU_CONFIG_REG 0x00
212#define AR934X_PLL_DDR_CONFIG_REG 0x04
213#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
214
215#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
216#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
217#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
218#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
219#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
220#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
221#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
222#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
223
224#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
225#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
226#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
227#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
228#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
229#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
230#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
231#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
232
233#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
234#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
235#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
236#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
237#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
238#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
239#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
240#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
241#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
242#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
243#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
244#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
245
246#define QCA955X_PLL_CPU_CONFIG_REG 0x00
247#define QCA955X_PLL_DDR_CONFIG_REG 0x04
248#define QCA955X_PLL_CLK_CTRL_REG 0x08
249
250#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
251#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
252#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6
253#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f
254#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
255#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
256#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
257#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
258
259#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
260#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
261#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10
262#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f
263#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
264#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
265#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
266#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
267
268#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
269#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
270#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
271#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
272#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
273#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
274#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
275#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
276#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
277#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
278#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
279#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
280
281/*
282 * USB_CONFIG block
283 */
284#define AR71XX_USB_CTRL_REG_FLADJ 0x00
285#define AR71XX_USB_CTRL_REG_CONFIG 0x04
286
287/*
288 * RESET block
289 */
290#define AR71XX_RESET_REG_TIMER 0x00
291#define AR71XX_RESET_REG_TIMER_RELOAD 0x04
292#define AR71XX_RESET_REG_WDOG_CTRL 0x08
293#define AR71XX_RESET_REG_WDOG 0x0c
294#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
295#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
296#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
297#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
298#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
299#define AR71XX_RESET_REG_RESET_MODULE 0x24
300#define AR71XX_RESET_REG_PERFC_CTRL 0x2c
301#define AR71XX_RESET_REG_PERFC0 0x30
302#define AR71XX_RESET_REG_PERFC1 0x34
303#define AR71XX_RESET_REG_REV_ID 0x90
304
305#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18
306#define AR913X_RESET_REG_RESET_MODULE 0x1c
307#define AR913X_RESET_REG_PERF_CTRL 0x20
308#define AR913X_RESET_REG_PERFC0 0x24
309#define AR913X_RESET_REG_PERFC1 0x28
310
311#define AR724X_RESET_REG_RESET_MODULE 0x1c
312
313#define AR933X_RESET_REG_RESET_MODULE 0x1c
314#define AR933X_RESET_REG_BOOTSTRAP 0xac
315
316#define AR934X_RESET_REG_RESET_MODULE 0x1c
317#define AR934X_RESET_REG_BOOTSTRAP 0xb0
318#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
319
320#define QCA955X_RESET_REG_RESET_MODULE 0x1c
321#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
322#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
323
324#define MISC_INT_ETHSW BIT(12)
325#define MISC_INT_TIMER4 BIT(10)
326#define MISC_INT_TIMER3 BIT(9)
327#define MISC_INT_TIMER2 BIT(8)
328#define MISC_INT_DMA BIT(7)
329#define MISC_INT_OHCI BIT(6)
330#define MISC_INT_PERFC BIT(5)
331#define MISC_INT_WDOG BIT(4)
332#define MISC_INT_UART BIT(3)
333#define MISC_INT_GPIO BIT(2)
334#define MISC_INT_ERROR BIT(1)
335#define MISC_INT_TIMER BIT(0)
336
337#define AR71XX_RESET_EXTERNAL BIT(28)
338#define AR71XX_RESET_FULL_CHIP BIT(24)
339#define AR71XX_RESET_CPU_NMI BIT(21)
340#define AR71XX_RESET_CPU_COLD BIT(20)
341#define AR71XX_RESET_DMA BIT(19)
342#define AR71XX_RESET_SLIC BIT(18)
343#define AR71XX_RESET_STEREO BIT(17)
344#define AR71XX_RESET_DDR BIT(16)
345#define AR71XX_RESET_GE1_MAC BIT(13)
346#define AR71XX_RESET_GE1_PHY BIT(12)
347#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10)
348#define AR71XX_RESET_GE0_MAC BIT(9)
349#define AR71XX_RESET_GE0_PHY BIT(8)
350#define AR71XX_RESET_USB_OHCI_DLL BIT(6)
351#define AR71XX_RESET_USB_HOST BIT(5)
352#define AR71XX_RESET_USB_PHY BIT(4)
353#define AR71XX_RESET_PCI_BUS BIT(1)
354#define AR71XX_RESET_PCI_CORE BIT(0)
355
356#define AR7240_RESET_USB_HOST BIT(5)
357#define AR7240_RESET_OHCI_DLL BIT(3)
358
359#define AR724X_RESET_GE1_MDIO BIT(23)
360#define AR724X_RESET_GE0_MDIO BIT(22)
361#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
362#define AR724X_RESET_PCIE_PHY BIT(7)
363#define AR724X_RESET_PCIE BIT(6)
364#define AR724X_RESET_USB_HOST BIT(5)
365#define AR724X_RESET_USB_PHY BIT(4)
366#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
367
368#define AR913X_RESET_AMBA2WMAC BIT(22)
369#define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
370#define AR913X_RESET_USB_HOST BIT(5)
371#define AR913X_RESET_USB_PHY BIT(4)
372
373#define AR933X_RESET_WMAC BIT(11)
374#define AR933X_RESET_USB_HOST BIT(5)
375#define AR933X_RESET_USB_PHY BIT(4)
376#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
377
378#define AR934X_RESET_USB_PHY_ANALOG BIT(11)
379#define AR934X_RESET_USB_HOST BIT(5)
380#define AR934X_RESET_USB_PHY BIT(4)
381#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
382
383#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
384
385#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
386#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
387#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
388#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
389#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
390#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
391#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
392#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
393#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
394#define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
395#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
396#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
397#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
398#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
399#define AR934X_BOOTSTRAP_DDR1 BIT(0)
400
401#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
402
403#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
404#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
405#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
406#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
407#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
408#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
409#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
410#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
411#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
412#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
413 (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
414 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
415
416#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
417 (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
418 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
419 AR934X_PCIE_WMAC_INT_PCIE_RC3)
420
421#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
422#define QCA955X_EXT_INT_WMAC_TX BIT(1)
423#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
424#define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
425#define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
426#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
427#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
428#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
429#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
430#define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
431#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
432#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
433#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
434#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
435#define QCA955X_EXT_INT_USB1 BIT(24)
436#define QCA955X_EXT_INT_USB2 BIT(28)
437
438#define QCA955X_EXT_INT_WMAC_ALL \
439 (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
440 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
441
442#define QCA955X_EXT_INT_PCIE_RC1_ALL \
443 (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
444 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
445 QCA955X_EXT_INT_PCIE_RC1_INT3)
446
447#define QCA955X_EXT_INT_PCIE_RC2_ALL \
448 (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
449 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
450 QCA955X_EXT_INT_PCIE_RC2_INT3)
451
452#define REV_ID_MAJOR_MASK 0xfff0
453#define REV_ID_MAJOR_AR71XX 0x00a0
454#define REV_ID_MAJOR_AR913X 0x00b0
455#define REV_ID_MAJOR_AR7240 0x00c0
456#define REV_ID_MAJOR_AR7241 0x0100
457#define REV_ID_MAJOR_AR7242 0x1100
458#define REV_ID_MAJOR_AR9330 0x0110
459#define REV_ID_MAJOR_AR9331 0x1110
460#define REV_ID_MAJOR_AR9341 0x0120
461#define REV_ID_MAJOR_AR9342 0x1120
462#define REV_ID_MAJOR_AR9344 0x2120
463#define REV_ID_MAJOR_QCA9556 0x0130
464#define REV_ID_MAJOR_QCA9558 0x1130
465
466#define AR71XX_REV_ID_MINOR_MASK 0x3
467#define AR71XX_REV_ID_MINOR_AR7130 0x0
468#define AR71XX_REV_ID_MINOR_AR7141 0x1
469#define AR71XX_REV_ID_MINOR_AR7161 0x2
470#define AR71XX_REV_ID_REVISION_MASK 0x3
471#define AR71XX_REV_ID_REVISION_SHIFT 2
472
473#define AR913X_REV_ID_MINOR_MASK 0x3
474#define AR913X_REV_ID_MINOR_AR9130 0x0
475#define AR913X_REV_ID_MINOR_AR9132 0x1
476#define AR913X_REV_ID_REVISION_MASK 0x3
477#define AR913X_REV_ID_REVISION_SHIFT 2
478
479#define AR933X_REV_ID_REVISION_MASK 0x3
480
481#define AR724X_REV_ID_REVISION_MASK 0x3
482
483#define AR934X_REV_ID_REVISION_MASK 0xf
484
485#define QCA955X_REV_ID_REVISION_MASK 0xf
486
487/*
488 * SPI block
489 */
490#define AR71XX_SPI_REG_FS 0x00 /* Function Select */
491#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
492#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
493#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
494
495#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
496
497#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */
498#define AR71XX_SPI_CTRL_DIV_MASK 0x3f
499
500#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
501#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
502#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
503#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0)
504#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1)
505#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2)
506#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
507 AR71XX_SPI_IOC_CS2)
508
509/*
510 * GPIO block
511 */
512#define AR71XX_GPIO_REG_OE 0x00
513#define AR71XX_GPIO_REG_IN 0x04
514#define AR71XX_GPIO_REG_OUT 0x08
515#define AR71XX_GPIO_REG_SET 0x0c
516#define AR71XX_GPIO_REG_CLEAR 0x10
517#define AR71XX_GPIO_REG_INT_MODE 0x14
518#define AR71XX_GPIO_REG_INT_TYPE 0x18
519#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
520#define AR71XX_GPIO_REG_INT_PENDING 0x20
521#define AR71XX_GPIO_REG_INT_ENABLE 0x24
522#define AR71XX_GPIO_REG_FUNC 0x28
523
524#define AR934X_GPIO_REG_FUNC 0x6c
525
526#define AR71XX_GPIO_COUNT 16
527#define AR7240_GPIO_COUNT 18
528#define AR7241_GPIO_COUNT 20
529#define AR913X_GPIO_COUNT 22
530#define AR933X_GPIO_COUNT 30
531#define AR934X_GPIO_COUNT 23
532#define QCA955X_GPIO_COUNT 24
533
534/*
535 * SRIF block
536 */
537#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0
538#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4
539#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8
540
541#define AR934X_SRIF_DDR_DPLL1_REG 0x240
542#define AR934X_SRIF_DDR_DPLL2_REG 0x244
543#define AR934X_SRIF_DDR_DPLL3_REG 0x248
544
545#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27
546#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f
547#define AR934X_SRIF_DPLL1_NINT_SHIFT 18
548#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff
549#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
550
551#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30)
552#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
553#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
554
555#endif /* __ASM_MACH_AR71XX_REGS_H */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Atheros AR71XX/AR724X/AR913X SoC register definitions
4 *
5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
6 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 *
9 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
10 */
11
12#ifndef __ASM_MACH_AR71XX_REGS_H
13#define __ASM_MACH_AR71XX_REGS_H
14
15#include <linux/types.h>
16#include <linux/io.h>
17#include <linux/bitops.h>
18
19#define AR71XX_APB_BASE 0x18000000
20#define AR71XX_GE0_BASE 0x19000000
21#define AR71XX_GE0_SIZE 0x10000
22#define AR71XX_GE1_BASE 0x1a000000
23#define AR71XX_GE1_SIZE 0x10000
24#define AR71XX_EHCI_BASE 0x1b000000
25#define AR71XX_EHCI_SIZE 0x1000
26#define AR71XX_OHCI_BASE 0x1c000000
27#define AR71XX_OHCI_SIZE 0x1000
28#define AR71XX_SPI_BASE 0x1f000000
29#define AR71XX_SPI_SIZE 0x01000000
30
31#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
32#define AR71XX_DDR_CTRL_SIZE 0x100
33#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
34#define AR71XX_UART_SIZE 0x100
35#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
36#define AR71XX_USB_CTRL_SIZE 0x100
37#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
38#define AR71XX_GPIO_SIZE 0x100
39#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
40#define AR71XX_PLL_SIZE 0x100
41#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
42#define AR71XX_RESET_SIZE 0x100
43#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
44#define AR71XX_MII_SIZE 0x100
45
46#define AR71XX_PCI_MEM_BASE 0x10000000
47#define AR71XX_PCI_MEM_SIZE 0x07000000
48
49#define AR71XX_PCI_WIN0_OFFS 0x10000000
50#define AR71XX_PCI_WIN1_OFFS 0x11000000
51#define AR71XX_PCI_WIN2_OFFS 0x12000000
52#define AR71XX_PCI_WIN3_OFFS 0x13000000
53#define AR71XX_PCI_WIN4_OFFS 0x14000000
54#define AR71XX_PCI_WIN5_OFFS 0x15000000
55#define AR71XX_PCI_WIN6_OFFS 0x16000000
56#define AR71XX_PCI_WIN7_OFFS 0x07000000
57
58#define AR71XX_PCI_CFG_BASE \
59 (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
60#define AR71XX_PCI_CFG_SIZE 0x100
61
62#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
63#define AR7240_USB_CTRL_SIZE 0x100
64#define AR7240_OHCI_BASE 0x1b000000
65#define AR7240_OHCI_SIZE 0x1000
66
67#define AR724X_PCI_MEM_BASE 0x10000000
68#define AR724X_PCI_MEM_SIZE 0x04000000
69
70#define AR724X_PCI_CFG_BASE 0x14000000
71#define AR724X_PCI_CFG_SIZE 0x1000
72#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000)
73#define AR724X_PCI_CRP_SIZE 0x1000
74#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
75#define AR724X_PCI_CTRL_SIZE 0x100
76
77#define AR724X_EHCI_BASE 0x1b000000
78#define AR724X_EHCI_SIZE 0x1000
79
80#define AR913X_EHCI_BASE 0x1b000000
81#define AR913X_EHCI_SIZE 0x1000
82#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
83#define AR913X_WMAC_SIZE 0x30000
84
85#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
86#define AR933X_UART_SIZE 0x14
87#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
88#define AR933X_GMAC_SIZE 0x04
89#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
90#define AR933X_WMAC_SIZE 0x20000
91#define AR933X_EHCI_BASE 0x1b000000
92#define AR933X_EHCI_SIZE 0x1000
93
94#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
95#define AR934X_GMAC_SIZE 0x14
96#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
97#define AR934X_WMAC_SIZE 0x20000
98#define AR934X_EHCI_BASE 0x1b000000
99#define AR934X_EHCI_SIZE 0x200
100#define AR934X_NFC_BASE 0x1b000200
101#define AR934X_NFC_SIZE 0xb8
102#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
103#define AR934X_SRIF_SIZE 0x1000
104
105#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
106#define QCA953X_GMAC_SIZE 0x14
107#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
108#define QCA953X_WMAC_SIZE 0x20000
109#define QCA953X_EHCI_BASE 0x1b000000
110#define QCA953X_EHCI_SIZE 0x200
111#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
112#define QCA953X_SRIF_SIZE 0x1000
113
114#define QCA953X_PCI_CFG_BASE0 0x14000000
115#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
116#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
117#define QCA953X_PCI_MEM_BASE0 0x10000000
118#define QCA953X_PCI_MEM_SIZE 0x02000000
119
120#define QCA955X_PCI_MEM_BASE0 0x10000000
121#define QCA955X_PCI_MEM_BASE1 0x12000000
122#define QCA955X_PCI_MEM_SIZE 0x02000000
123#define QCA955X_PCI_CFG_BASE0 0x14000000
124#define QCA955X_PCI_CFG_BASE1 0x16000000
125#define QCA955X_PCI_CFG_SIZE 0x1000
126#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
127#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
128#define QCA955X_PCI_CRP_SIZE 0x1000
129#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
130#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
131#define QCA955X_PCI_CTRL_SIZE 0x100
132
133#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
134#define QCA955X_GMAC_SIZE 0x40
135#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
136#define QCA955X_WMAC_SIZE 0x20000
137#define QCA955X_EHCI0_BASE 0x1b000000
138#define QCA955X_EHCI1_BASE 0x1b400000
139#define QCA955X_EHCI_SIZE 0x1000
140#define QCA955X_NFC_BASE 0x1b800200
141#define QCA955X_NFC_SIZE 0xb8
142
143#define QCA956X_PCI_MEM_BASE1 0x12000000
144#define QCA956X_PCI_MEM_SIZE 0x02000000
145#define QCA956X_PCI_CFG_BASE1 0x16000000
146#define QCA956X_PCI_CFG_SIZE 0x1000
147#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
148#define QCA956X_PCI_CRP_SIZE 0x1000
149#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
150#define QCA956X_PCI_CTRL_SIZE 0x100
151
152#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
153#define QCA956X_WMAC_SIZE 0x20000
154#define QCA956X_EHCI0_BASE 0x1b000000
155#define QCA956X_EHCI1_BASE 0x1b400000
156#define QCA956X_EHCI_SIZE 0x200
157#define QCA956X_GMAC_SGMII_BASE (AR71XX_APB_BASE + 0x00070000)
158#define QCA956X_GMAC_SGMII_SIZE 0x64
159#define QCA956X_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
160#define QCA956X_PLL_SIZE 0x50
161#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
162#define QCA956X_GMAC_SIZE 0x64
163
164/*
165 * Hidden Registers
166 */
167#define QCA956X_MAC_CFG_BASE 0xb9000000
168#define QCA956X_MAC_CFG_SIZE 0x64
169
170#define QCA956X_MAC_CFG1_REG 0x00
171#define QCA956X_MAC_CFG1_SOFT_RST BIT(31)
172#define QCA956X_MAC_CFG1_RX_RST BIT(19)
173#define QCA956X_MAC_CFG1_TX_RST BIT(18)
174#define QCA956X_MAC_CFG1_LOOPBACK BIT(8)
175#define QCA956X_MAC_CFG1_RX_EN BIT(2)
176#define QCA956X_MAC_CFG1_TX_EN BIT(0)
177
178#define QCA956X_MAC_CFG2_REG 0x04
179#define QCA956X_MAC_CFG2_IF_1000 BIT(9)
180#define QCA956X_MAC_CFG2_IF_10_100 BIT(8)
181#define QCA956X_MAC_CFG2_HUGE_FRAME_EN BIT(5)
182#define QCA956X_MAC_CFG2_LEN_CHECK BIT(4)
183#define QCA956X_MAC_CFG2_PAD_CRC_EN BIT(2)
184#define QCA956X_MAC_CFG2_FDX BIT(0)
185
186#define QCA956X_MAC_MII_MGMT_CFG_REG 0x20
187#define QCA956X_MGMT_CFG_CLK_DIV_20 0x07
188
189#define QCA956X_MAC_FIFO_CFG0_REG 0x48
190#define QCA956X_MAC_FIFO_CFG1_REG 0x4c
191#define QCA956X_MAC_FIFO_CFG2_REG 0x50
192#define QCA956X_MAC_FIFO_CFG3_REG 0x54
193#define QCA956X_MAC_FIFO_CFG4_REG 0x58
194#define QCA956X_MAC_FIFO_CFG5_REG 0x5c
195
196#define QCA956X_DAM_RESET_OFFSET 0xb90001bc
197#define QCA956X_DAM_RESET_SIZE 0x4
198#define QCA956X_INLINE_CHKSUM_ENG BIT(27)
199
200/*
201 * DDR_CTRL block
202 */
203#define AR71XX_DDR_REG_PCI_WIN0 0x7c
204#define AR71XX_DDR_REG_PCI_WIN1 0x80
205#define AR71XX_DDR_REG_PCI_WIN2 0x84
206#define AR71XX_DDR_REG_PCI_WIN3 0x88
207#define AR71XX_DDR_REG_PCI_WIN4 0x8c
208#define AR71XX_DDR_REG_PCI_WIN5 0x90
209#define AR71XX_DDR_REG_PCI_WIN6 0x94
210#define AR71XX_DDR_REG_PCI_WIN7 0x98
211#define AR71XX_DDR_REG_FLUSH_GE0 0x9c
212#define AR71XX_DDR_REG_FLUSH_GE1 0xa0
213#define AR71XX_DDR_REG_FLUSH_USB 0xa4
214#define AR71XX_DDR_REG_FLUSH_PCI 0xa8
215
216#define AR724X_DDR_REG_FLUSH_GE0 0x7c
217#define AR724X_DDR_REG_FLUSH_GE1 0x80
218#define AR724X_DDR_REG_FLUSH_USB 0x84
219#define AR724X_DDR_REG_FLUSH_PCIE 0x88
220
221#define AR913X_DDR_REG_FLUSH_GE0 0x7c
222#define AR913X_DDR_REG_FLUSH_GE1 0x80
223#define AR913X_DDR_REG_FLUSH_USB 0x84
224#define AR913X_DDR_REG_FLUSH_WMAC 0x88
225
226#define AR933X_DDR_REG_FLUSH_GE0 0x7c
227#define AR933X_DDR_REG_FLUSH_GE1 0x80
228#define AR933X_DDR_REG_FLUSH_USB 0x84
229#define AR933X_DDR_REG_FLUSH_WMAC 0x88
230
231#define AR934X_DDR_REG_FLUSH_GE0 0x9c
232#define AR934X_DDR_REG_FLUSH_GE1 0xa0
233#define AR934X_DDR_REG_FLUSH_USB 0xa4
234#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
235#define AR934X_DDR_REG_FLUSH_WMAC 0xac
236
237#define QCA953X_DDR_REG_FLUSH_GE0 0x9c
238#define QCA953X_DDR_REG_FLUSH_GE1 0xa0
239#define QCA953X_DDR_REG_FLUSH_USB 0xa4
240#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
241#define QCA953X_DDR_REG_FLUSH_WMAC 0xac
242
243/*
244 * PLL block
245 */
246#define AR71XX_PLL_REG_CPU_CONFIG 0x00
247#define AR71XX_PLL_REG_SEC_CONFIG 0x04
248#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
249#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
250
251#define AR71XX_PLL_FB_SHIFT 3
252#define AR71XX_PLL_FB_MASK 0x1f
253#define AR71XX_CPU_DIV_SHIFT 16
254#define AR71XX_CPU_DIV_MASK 0x3
255#define AR71XX_DDR_DIV_SHIFT 18
256#define AR71XX_DDR_DIV_MASK 0x3
257#define AR71XX_AHB_DIV_SHIFT 20
258#define AR71XX_AHB_DIV_MASK 0x7
259
260#define AR71XX_ETH0_PLL_SHIFT 17
261#define AR71XX_ETH1_PLL_SHIFT 19
262
263#define AR724X_PLL_REG_CPU_CONFIG 0x00
264#define AR724X_PLL_REG_PCIE_CONFIG 0x10
265
266#define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS BIT(16)
267#define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET BIT(25)
268
269#define AR724X_PLL_FB_SHIFT 0
270#define AR724X_PLL_FB_MASK 0x3ff
271#define AR724X_PLL_REF_DIV_SHIFT 10
272#define AR724X_PLL_REF_DIV_MASK 0xf
273#define AR724X_AHB_DIV_SHIFT 19
274#define AR724X_AHB_DIV_MASK 0x1
275#define AR724X_DDR_DIV_SHIFT 22
276#define AR724X_DDR_DIV_MASK 0x3
277
278#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
279
280#define AR913X_PLL_REG_CPU_CONFIG 0x00
281#define AR913X_PLL_REG_ETH_CONFIG 0x04
282#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
283#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18
284
285#define AR913X_PLL_FB_SHIFT 0
286#define AR913X_PLL_FB_MASK 0x3ff
287#define AR913X_DDR_DIV_SHIFT 22
288#define AR913X_DDR_DIV_MASK 0x3
289#define AR913X_AHB_DIV_SHIFT 19
290#define AR913X_AHB_DIV_MASK 0x1
291
292#define AR913X_ETH0_PLL_SHIFT 20
293#define AR913X_ETH1_PLL_SHIFT 22
294
295#define AR933X_PLL_CPU_CONFIG_REG 0x00
296#define AR933X_PLL_CLOCK_CTRL_REG 0x08
297
298#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
299#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
300#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
301#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
302#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
303#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
304
305#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
306#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
307#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
308#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
309#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
310#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
311#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
312
313#define AR934X_PLL_CPU_CONFIG_REG 0x00
314#define AR934X_PLL_DDR_CONFIG_REG 0x04
315#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
316#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
317#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
318
319#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
320#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
321#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
322#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
323#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
324#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
325#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
326#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
327
328#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
329#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
330#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
331#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
332#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
333#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
334#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
335#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
336
337#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
338#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
339#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
340#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
341#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
342#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
343#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
344#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
345#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
346#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
347#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
348#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
349
350#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
351
352#define QCA953X_PLL_CPU_CONFIG_REG 0x00
353#define QCA953X_PLL_DDR_CONFIG_REG 0x04
354#define QCA953X_PLL_CLK_CTRL_REG 0x08
355#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
356#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
357#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48
358
359#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
360#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
361#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
362#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
363#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
364#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
365#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
366#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
367
368#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
369#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
370#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
371#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
372#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
373#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
374#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
375#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
376
377#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
378#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
379#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
380#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
381#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
382#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
383#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
384#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
385#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
386#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
387#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
388#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
389
390#define QCA955X_PLL_CPU_CONFIG_REG 0x00
391#define QCA955X_PLL_DDR_CONFIG_REG 0x04
392#define QCA955X_PLL_CLK_CTRL_REG 0x08
393#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
394#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
395#define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c
396
397#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
398#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
399#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6
400#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f
401#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
402#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
403#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
404#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
405
406#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
407#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
408#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10
409#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f
410#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
411#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
412#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
413#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
414
415#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
416#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
417#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
418#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
419#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
420#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
421#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
422#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
423#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
424#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
425#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
426#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
427
428#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2)
429#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1)
430#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0)
431
432#define QCA956X_PLL_CPU_CONFIG_REG 0x00
433#define QCA956X_PLL_CPU_CONFIG1_REG 0x04
434#define QCA956X_PLL_DDR_CONFIG_REG 0x08
435#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
436#define QCA956X_PLL_CLK_CTRL_REG 0x10
437#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG 0x28
438#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30
439#define QCA956X_PLL_ETH_SGMII_SERDES_REG 0x4c
440
441#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
442#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
443#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
444#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
445
446#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
447#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
448#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
449#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff
450#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
451#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
452
453#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
454#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
455#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
456#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
457
458#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
459#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
460#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
461#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff
462#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
463#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
464
465#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
466#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
467#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
468#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
469#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
470#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
471#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
472#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
473#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
474#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20)
475#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
476#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
477
478#define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB BIT(5)
479#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1 BIT(6)
480#define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL BIT(7)
481#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SHIFT 8
482#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0xf
483#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EN_PLL_TOP BIT(12)
484#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2 BIT(13)
485#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1 BIT(14)
486#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2 BIT(15)
487#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE BIT(16)
488#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EEE_ENABLE BIT(17)
489#define QCA956X_PLL_SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL BIT(18)
490#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCHCLK_SEL BIT(19)
491
492#define QCA956X_PLL_ETH_XMII_TX_INVERT BIT(1)
493#define QCA956X_PLL_ETH_XMII_GIGE BIT(25)
494#define QCA956X_PLL_ETH_XMII_RX_DELAY_SHIFT 28
495#define QCA956X_PLL_ETH_XMII_RX_DELAY_MASK 0x3
496#define QCA956X_PLL_ETH_XMII_TX_DELAY_SHIFT 26
497#define QCA956X_PLL_ETH_XMII_TX_DELAY_MASK 3
498
499#define QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2)
500#define QCA956X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1)
501#define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0)
502
503/*
504 * USB_CONFIG block
505 */
506#define AR71XX_USB_CTRL_REG_FLADJ 0x00
507#define AR71XX_USB_CTRL_REG_CONFIG 0x04
508
509/*
510 * RESET block
511 */
512#define AR71XX_RESET_REG_TIMER 0x00
513#define AR71XX_RESET_REG_TIMER_RELOAD 0x04
514#define AR71XX_RESET_REG_WDOG_CTRL 0x08
515#define AR71XX_RESET_REG_WDOG 0x0c
516#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
517#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
518#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
519#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
520#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
521#define AR71XX_RESET_REG_RESET_MODULE 0x24
522#define AR71XX_RESET_REG_PERFC_CTRL 0x2c
523#define AR71XX_RESET_REG_PERFC0 0x30
524#define AR71XX_RESET_REG_PERFC1 0x34
525#define AR71XX_RESET_REG_REV_ID 0x90
526
527#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18
528#define AR913X_RESET_REG_RESET_MODULE 0x1c
529#define AR913X_RESET_REG_PERF_CTRL 0x20
530#define AR913X_RESET_REG_PERFC0 0x24
531#define AR913X_RESET_REG_PERFC1 0x28
532
533#define AR724X_RESET_REG_RESET_MODULE 0x1c
534
535#define AR933X_RESET_REG_RESET_MODULE 0x1c
536#define AR933X_RESET_REG_BOOTSTRAP 0xac
537
538#define AR934X_RESET_REG_RESET_MODULE 0x1c
539#define AR934X_RESET_REG_BOOTSTRAP 0xb0
540#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
541
542#define QCA953X_RESET_REG_RESET_MODULE 0x1c
543#define QCA953X_RESET_REG_BOOTSTRAP 0xb0
544#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
545
546#define QCA955X_RESET_REG_RESET_MODULE 0x1c
547#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
548#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
549
550#define QCA956X_RESET_REG_RESET_MODULE 0x1c
551#define QCA956X_RESET_REG_BOOTSTRAP 0xb0
552#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac
553
554#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
555#define MISC_INT_ETHSW BIT(12)
556#define MISC_INT_TIMER4 BIT(10)
557#define MISC_INT_TIMER3 BIT(9)
558#define MISC_INT_TIMER2 BIT(8)
559#define MISC_INT_DMA BIT(7)
560#define MISC_INT_OHCI BIT(6)
561#define MISC_INT_PERFC BIT(5)
562#define MISC_INT_WDOG BIT(4)
563#define MISC_INT_UART BIT(3)
564#define MISC_INT_GPIO BIT(2)
565#define MISC_INT_ERROR BIT(1)
566#define MISC_INT_TIMER BIT(0)
567
568#define AR71XX_RESET_EXTERNAL BIT(28)
569#define AR71XX_RESET_FULL_CHIP BIT(24)
570#define AR71XX_RESET_CPU_NMI BIT(21)
571#define AR71XX_RESET_CPU_COLD BIT(20)
572#define AR71XX_RESET_DMA BIT(19)
573#define AR71XX_RESET_SLIC BIT(18)
574#define AR71XX_RESET_STEREO BIT(17)
575#define AR71XX_RESET_DDR BIT(16)
576#define AR71XX_RESET_GE1_MAC BIT(13)
577#define AR71XX_RESET_GE1_PHY BIT(12)
578#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10)
579#define AR71XX_RESET_GE0_MAC BIT(9)
580#define AR71XX_RESET_GE0_PHY BIT(8)
581#define AR71XX_RESET_USB_OHCI_DLL BIT(6)
582#define AR71XX_RESET_USB_HOST BIT(5)
583#define AR71XX_RESET_USB_PHY BIT(4)
584#define AR71XX_RESET_PCI_BUS BIT(1)
585#define AR71XX_RESET_PCI_CORE BIT(0)
586
587#define AR7240_RESET_USB_HOST BIT(5)
588#define AR7240_RESET_OHCI_DLL BIT(3)
589
590#define AR724X_RESET_GE1_MDIO BIT(23)
591#define AR724X_RESET_GE0_MDIO BIT(22)
592#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
593#define AR724X_RESET_PCIE_PHY BIT(7)
594#define AR724X_RESET_PCIE BIT(6)
595#define AR724X_RESET_USB_HOST BIT(5)
596#define AR724X_RESET_USB_PHY BIT(4)
597#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
598
599#define AR913X_RESET_AMBA2WMAC BIT(22)
600#define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
601#define AR913X_RESET_USB_HOST BIT(5)
602#define AR913X_RESET_USB_PHY BIT(4)
603
604#define AR933X_RESET_GE1_MDIO BIT(23)
605#define AR933X_RESET_GE0_MDIO BIT(22)
606#define AR933X_RESET_GE1_MAC BIT(13)
607#define AR933X_RESET_WMAC BIT(11)
608#define AR933X_RESET_GE0_MAC BIT(9)
609#define AR933X_RESET_USB_HOST BIT(5)
610#define AR933X_RESET_USB_PHY BIT(4)
611#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
612
613#define AR934X_RESET_HOST BIT(31)
614#define AR934X_RESET_SLIC BIT(30)
615#define AR934X_RESET_HDMA BIT(29)
616#define AR934X_RESET_EXTERNAL BIT(28)
617#define AR934X_RESET_RTC BIT(27)
618#define AR934X_RESET_PCIE_EP_INT BIT(26)
619#define AR934X_RESET_CHKSUM_ACC BIT(25)
620#define AR934X_RESET_FULL_CHIP BIT(24)
621#define AR934X_RESET_GE1_MDIO BIT(23)
622#define AR934X_RESET_GE0_MDIO BIT(22)
623#define AR934X_RESET_CPU_NMI BIT(21)
624#define AR934X_RESET_CPU_COLD BIT(20)
625#define AR934X_RESET_HOST_RESET_INT BIT(19)
626#define AR934X_RESET_PCIE_EP BIT(18)
627#define AR934X_RESET_UART1 BIT(17)
628#define AR934X_RESET_DDR BIT(16)
629#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
630#define AR934X_RESET_NANDF BIT(14)
631#define AR934X_RESET_GE1_MAC BIT(13)
632#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
633#define AR934X_RESET_USB_PHY_ANALOG BIT(11)
634#define AR934X_RESET_HOST_DMA_INT BIT(10)
635#define AR934X_RESET_GE0_MAC BIT(9)
636#define AR934X_RESET_ETH_SWITCH BIT(8)
637#define AR934X_RESET_PCIE_PHY BIT(7)
638#define AR934X_RESET_PCIE BIT(6)
639#define AR934X_RESET_USB_HOST BIT(5)
640#define AR934X_RESET_USB_PHY BIT(4)
641#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
642#define AR934X_RESET_LUT BIT(2)
643#define AR934X_RESET_MBOX BIT(1)
644#define AR934X_RESET_I2S BIT(0)
645
646#define QCA953X_RESET_USB_EXT_PWR BIT(29)
647#define QCA953X_RESET_EXTERNAL BIT(28)
648#define QCA953X_RESET_RTC BIT(27)
649#define QCA953X_RESET_FULL_CHIP BIT(24)
650#define QCA953X_RESET_GE1_MDIO BIT(23)
651#define QCA953X_RESET_GE0_MDIO BIT(22)
652#define QCA953X_RESET_CPU_NMI BIT(21)
653#define QCA953X_RESET_CPU_COLD BIT(20)
654#define QCA953X_RESET_DDR BIT(16)
655#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
656#define QCA953X_RESET_GE1_MAC BIT(13)
657#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
658#define QCA953X_RESET_USB_PHY_ANALOG BIT(11)
659#define QCA953X_RESET_GE0_MAC BIT(9)
660#define QCA953X_RESET_ETH_SWITCH BIT(8)
661#define QCA953X_RESET_PCIE_PHY BIT(7)
662#define QCA953X_RESET_PCIE BIT(6)
663#define QCA953X_RESET_USB_HOST BIT(5)
664#define QCA953X_RESET_USB_PHY BIT(4)
665#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
666
667#define QCA955X_RESET_HOST BIT(31)
668#define QCA955X_RESET_SLIC BIT(30)
669#define QCA955X_RESET_HDMA BIT(29)
670#define QCA955X_RESET_EXTERNAL BIT(28)
671#define QCA955X_RESET_RTC BIT(27)
672#define QCA955X_RESET_PCIE_EP_INT BIT(26)
673#define QCA955X_RESET_CHKSUM_ACC BIT(25)
674#define QCA955X_RESET_FULL_CHIP BIT(24)
675#define QCA955X_RESET_GE1_MDIO BIT(23)
676#define QCA955X_RESET_GE0_MDIO BIT(22)
677#define QCA955X_RESET_CPU_NMI BIT(21)
678#define QCA955X_RESET_CPU_COLD BIT(20)
679#define QCA955X_RESET_HOST_RESET_INT BIT(19)
680#define QCA955X_RESET_PCIE_EP BIT(18)
681#define QCA955X_RESET_UART1 BIT(17)
682#define QCA955X_RESET_DDR BIT(16)
683#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
684#define QCA955X_RESET_NANDF BIT(14)
685#define QCA955X_RESET_GE1_MAC BIT(13)
686#define QCA955X_RESET_SGMII_ANALOG BIT(12)
687#define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
688#define QCA955X_RESET_HOST_DMA_INT BIT(10)
689#define QCA955X_RESET_GE0_MAC BIT(9)
690#define QCA955X_RESET_SGMII BIT(8)
691#define QCA955X_RESET_PCIE_PHY BIT(7)
692#define QCA955X_RESET_PCIE BIT(6)
693#define QCA955X_RESET_USB_HOST BIT(5)
694#define QCA955X_RESET_USB_PHY BIT(4)
695#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
696#define QCA955X_RESET_LUT BIT(2)
697#define QCA955X_RESET_MBOX BIT(1)
698#define QCA955X_RESET_I2S BIT(0)
699
700#define QCA956X_RESET_EXTERNAL BIT(28)
701#define QCA956X_RESET_FULL_CHIP BIT(24)
702#define QCA956X_RESET_GE1_MDIO BIT(23)
703#define QCA956X_RESET_GE0_MDIO BIT(22)
704#define QCA956X_RESET_CPU_NMI BIT(21)
705#define QCA956X_RESET_CPU_COLD BIT(20)
706#define QCA956X_RESET_DMA BIT(19)
707#define QCA956X_RESET_DDR BIT(16)
708#define QCA956X_RESET_GE1_MAC BIT(13)
709#define QCA956X_RESET_SGMII_ANALOG BIT(12)
710#define QCA956X_RESET_USB_PHY_ANALOG BIT(11)
711#define QCA956X_RESET_GE0_MAC BIT(9)
712#define QCA956X_RESET_SGMII BIT(8)
713#define QCA956X_RESET_USB_HOST BIT(5)
714#define QCA956X_RESET_USB_PHY BIT(4)
715#define QCA956X_RESET_USBSUS_OVERRIDE BIT(3)
716#define QCA956X_RESET_SWITCH_ANALOG BIT(2)
717#define QCA956X_RESET_SWITCH BIT(0)
718
719#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
720#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
721#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
722
723#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
724#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
725#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
726#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
727#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
728#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
729#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
730#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
731#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
732#define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
733#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
734#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
735#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
736#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
737#define AR934X_BOOTSTRAP_DDR1 BIT(0)
738
739#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
740#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
741#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
742#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
743#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
744#define QCA953X_BOOTSTRAP_DDR1 BIT(0)
745
746#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
747
748#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)
749
750#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
751#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
752#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
753#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
754#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
755#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
756#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
757#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
758#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
759#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
760 (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
761 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
762
763#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
764 (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
765 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
766 AR934X_PCIE_WMAC_INT_PCIE_RC3)
767
768#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
769#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1)
770#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
771#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
772#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4)
773#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
774#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
775#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
776#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
777#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
778 (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
779 QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
780
781#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
782 (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
783 QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
784 QCA953X_PCIE_WMAC_INT_PCIE_RC3)
785
786#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
787#define QCA955X_EXT_INT_WMAC_TX BIT(1)
788#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
789#define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
790#define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
791#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
792#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
793#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
794#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
795#define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
796#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
797#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
798#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
799#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
800#define QCA955X_EXT_INT_USB1 BIT(24)
801#define QCA955X_EXT_INT_USB2 BIT(28)
802
803#define QCA955X_EXT_INT_WMAC_ALL \
804 (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
805 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
806
807#define QCA955X_EXT_INT_PCIE_RC1_ALL \
808 (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
809 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
810 QCA955X_EXT_INT_PCIE_RC1_INT3)
811
812#define QCA955X_EXT_INT_PCIE_RC2_ALL \
813 (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
814 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
815 QCA955X_EXT_INT_PCIE_RC2_INT3)
816
817#define QCA956X_EXT_INT_WMAC_MISC BIT(0)
818#define QCA956X_EXT_INT_WMAC_TX BIT(1)
819#define QCA956X_EXT_INT_WMAC_RXLP BIT(2)
820#define QCA956X_EXT_INT_WMAC_RXHP BIT(3)
821#define QCA956X_EXT_INT_PCIE_RC1 BIT(4)
822#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5)
823#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6)
824#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7)
825#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8)
826#define QCA956X_EXT_INT_PCIE_RC2 BIT(12)
827#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13)
828#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14)
829#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15)
830#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16)
831#define QCA956X_EXT_INT_USB1 BIT(24)
832#define QCA956X_EXT_INT_USB2 BIT(28)
833
834#define QCA956X_EXT_INT_WMAC_ALL \
835 (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
836 QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
837
838#define QCA956X_EXT_INT_PCIE_RC1_ALL \
839 (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
840 QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
841 QCA956X_EXT_INT_PCIE_RC1_INT3)
842
843#define QCA956X_EXT_INT_PCIE_RC2_ALL \
844 (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
845 QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
846 QCA956X_EXT_INT_PCIE_RC2_INT3)
847
848#define REV_ID_MAJOR_MASK 0xfff0
849#define REV_ID_MAJOR_AR71XX 0x00a0
850#define REV_ID_MAJOR_AR913X 0x00b0
851#define REV_ID_MAJOR_AR7240 0x00c0
852#define REV_ID_MAJOR_AR7241 0x0100
853#define REV_ID_MAJOR_AR7242 0x1100
854#define REV_ID_MAJOR_AR9330 0x0110
855#define REV_ID_MAJOR_AR9331 0x1110
856#define REV_ID_MAJOR_AR9341 0x0120
857#define REV_ID_MAJOR_AR9342 0x1120
858#define REV_ID_MAJOR_AR9344 0x2120
859#define REV_ID_MAJOR_QCA9533 0x0140
860#define REV_ID_MAJOR_QCA9533_V2 0x0160
861#define REV_ID_MAJOR_QCA9556 0x0130
862#define REV_ID_MAJOR_QCA9558 0x1130
863#define REV_ID_MAJOR_TP9343 0x0150
864#define REV_ID_MAJOR_QCA956X 0x1150
865
866#define AR71XX_REV_ID_MINOR_MASK 0x3
867#define AR71XX_REV_ID_MINOR_AR7130 0x0
868#define AR71XX_REV_ID_MINOR_AR7141 0x1
869#define AR71XX_REV_ID_MINOR_AR7161 0x2
870#define AR71XX_REV_ID_REVISION_MASK 0x3
871#define AR71XX_REV_ID_REVISION_SHIFT 2
872
873#define AR913X_REV_ID_MINOR_MASK 0x3
874#define AR913X_REV_ID_MINOR_AR9130 0x0
875#define AR913X_REV_ID_MINOR_AR9132 0x1
876#define AR913X_REV_ID_REVISION_MASK 0x3
877#define AR913X_REV_ID_REVISION_SHIFT 2
878
879#define AR933X_REV_ID_REVISION_MASK 0x3
880
881#define AR724X_REV_ID_REVISION_MASK 0x3
882
883#define AR934X_REV_ID_REVISION_MASK 0xf
884
885#define QCA953X_REV_ID_REVISION_MASK 0xf
886
887#define QCA955X_REV_ID_REVISION_MASK 0xf
888
889#define QCA956X_REV_ID_REVISION_MASK 0xf
890
891/*
892 * SPI block
893 */
894#define AR71XX_SPI_REG_FS 0x00 /* Function Select */
895#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
896#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
897#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
898
899#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
900
901#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */
902#define AR71XX_SPI_CTRL_DIV_MASK 0x3f
903
904#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
905#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
906#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
907#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0)
908#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1)
909#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2)
910#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
911 AR71XX_SPI_IOC_CS2)
912
913/*
914 * GPIO block
915 */
916#define AR71XX_GPIO_REG_OE 0x00
917#define AR71XX_GPIO_REG_IN 0x04
918#define AR71XX_GPIO_REG_OUT 0x08
919#define AR71XX_GPIO_REG_SET 0x0c
920#define AR71XX_GPIO_REG_CLEAR 0x10
921#define AR71XX_GPIO_REG_INT_MODE 0x14
922#define AR71XX_GPIO_REG_INT_TYPE 0x18
923#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
924#define AR71XX_GPIO_REG_INT_PENDING 0x20
925#define AR71XX_GPIO_REG_INT_ENABLE 0x24
926#define AR71XX_GPIO_REG_FUNC 0x28
927
928#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
929#define AR934X_GPIO_REG_OUT_FUNC1 0x30
930#define AR934X_GPIO_REG_OUT_FUNC2 0x34
931#define AR934X_GPIO_REG_OUT_FUNC3 0x38
932#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
933#define AR934X_GPIO_REG_OUT_FUNC5 0x40
934#define AR934X_GPIO_REG_FUNC 0x6c
935
936#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c
937#define QCA953X_GPIO_REG_OUT_FUNC1 0x30
938#define QCA953X_GPIO_REG_OUT_FUNC2 0x34
939#define QCA953X_GPIO_REG_OUT_FUNC3 0x38
940#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c
941#define QCA953X_GPIO_REG_IN_ENABLE0 0x44
942#define QCA953X_GPIO_REG_FUNC 0x6c
943
944#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10
945#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11
946#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9
947#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8
948#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12
949#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41
950#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42
951#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43
952#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
953#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
954
955#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
956#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
957#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
958#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
959#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
960#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
961#define QCA955X_GPIO_REG_FUNC 0x6c
962
963#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
964#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
965#define QCA956X_GPIO_REG_OUT_FUNC2 0x34
966#define QCA956X_GPIO_REG_OUT_FUNC3 0x38
967#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c
968#define QCA956X_GPIO_REG_OUT_FUNC5 0x40
969#define QCA956X_GPIO_REG_IN_ENABLE0 0x44
970#define QCA956X_GPIO_REG_IN_ENABLE3 0x50
971#define QCA956X_GPIO_REG_FUNC 0x6c
972
973#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32
974#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33
975
976#define AR71XX_GPIO_COUNT 16
977#define AR7240_GPIO_COUNT 18
978#define AR7241_GPIO_COUNT 20
979#define AR913X_GPIO_COUNT 22
980#define AR933X_GPIO_COUNT 30
981#define AR934X_GPIO_COUNT 23
982#define QCA953X_GPIO_COUNT 18
983#define QCA955X_GPIO_COUNT 24
984#define QCA956X_GPIO_COUNT 23
985
986/*
987 * SRIF block
988 */
989#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0
990#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4
991#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8
992
993#define AR934X_SRIF_DDR_DPLL1_REG 0x240
994#define AR934X_SRIF_DDR_DPLL2_REG 0x244
995#define AR934X_SRIF_DDR_DPLL3_REG 0x248
996
997#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27
998#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f
999#define AR934X_SRIF_DPLL1_NINT_SHIFT 18
1000#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff
1001#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
1002
1003#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30)
1004#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
1005#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
1006
1007#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0
1008#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4
1009#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8
1010
1011#define QCA953X_SRIF_DDR_DPLL1_REG 0x240
1012#define QCA953X_SRIF_DDR_DPLL2_REG 0x244
1013#define QCA953X_SRIF_DDR_DPLL3_REG 0x248
1014
1015#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27
1016#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
1017#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
1018#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff
1019#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
1020
1021#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
1022#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13
1023#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
1024
1025#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
1026#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
1027#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
1028#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
1029#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
1030#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
1031#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
1032
1033#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
1034#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
1035#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
1036#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
1037#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
1038#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
1039#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
1040#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
1041#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
1042#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
1043#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
1044#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
1045#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
1046#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
1047#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
1048#define AR724X_GPIO_FUNC_UART_EN BIT(1)
1049#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
1050
1051#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
1052#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
1053#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
1054#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
1055#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
1056#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
1057#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
1058#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
1059#define AR913X_GPIO_FUNC_UART_EN BIT(8)
1060#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
1061
1062#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
1063#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
1064#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
1065#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
1066#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
1067#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
1068#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
1069#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
1070#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
1071#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
1072#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
1073#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
1074#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
1075#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
1076#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
1077#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
1078#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
1079#define AR933X_GPIO_FUNC_UART_EN BIT(1)
1080#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
1081
1082#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
1083#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
1084#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
1085#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
1086#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
1087#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
1088#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
1089#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2)
1090#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1)
1091
1092#define AR934X_GPIO_OUT_GPIO 0
1093#define AR934X_GPIO_OUT_SPI_CS1 7
1094#define AR934X_GPIO_OUT_LED_LINK0 41
1095#define AR934X_GPIO_OUT_LED_LINK1 42
1096#define AR934X_GPIO_OUT_LED_LINK2 43
1097#define AR934X_GPIO_OUT_LED_LINK3 44
1098#define AR934X_GPIO_OUT_LED_LINK4 45
1099#define AR934X_GPIO_OUT_EXT_LNA0 46
1100#define AR934X_GPIO_OUT_EXT_LNA1 47
1101
1102#define QCA955X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
1103#define QCA955X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
1104#define QCA955X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
1105#define QCA955X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
1106#define QCA955X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
1107#define QCA955X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
1108#define QCA955X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
1109#define QCA955X_GPIO_FUNC_JTAG_DISABLE BIT(1)
1110
1111#define QCA955X_GPIO_OUT_GPIO 0
1112#define QCA955X_MII_EXT_MDI 1
1113#define QCA955X_SLIC_DATA_OUT 3
1114#define QCA955X_SLIC_PCM_FS 4
1115#define QCA955X_SLIC_PCM_CLK 5
1116#define QCA955X_SPI_CLK 8
1117#define QCA955X_SPI_CS_0 9
1118#define QCA955X_SPI_CS_1 10
1119#define QCA955X_SPI_CS_2 11
1120#define QCA955X_SPI_MISO 12
1121#define QCA955X_I2S_CLK 13
1122#define QCA955X_I2S_WS 14
1123#define QCA955X_I2S_SD 15
1124#define QCA955X_I2S_MCK 16
1125#define QCA955X_SPDIF_OUT 17
1126#define QCA955X_UART1_TD 18
1127#define QCA955X_UART1_RTS 19
1128#define QCA955X_UART1_RD 20
1129#define QCA955X_UART1_CTS 21
1130#define QCA955X_UART0_SOUT 22
1131#define QCA955X_SPDIF2_OUT 23
1132#define QCA955X_LED_SGMII_SPEED0 24
1133#define QCA955X_LED_SGMII_SPEED1 25
1134#define QCA955X_LED_SGMII_DUPLEX 26
1135#define QCA955X_LED_SGMII_LINK_UP 27
1136#define QCA955X_SGMII_SPEED0_INVERT 28
1137#define QCA955X_SGMII_SPEED1_INVERT 29
1138#define QCA955X_SGMII_DUPLEX_INVERT 30
1139#define QCA955X_SGMII_LINK_UP_INVERT 31
1140#define QCA955X_GE1_MII_MDO 32
1141#define QCA955X_GE1_MII_MDC 33
1142#define QCA955X_SWCOM2 38
1143#define QCA955X_SWCOM3 39
1144#define QCA955X_MAC2_GPIO 40
1145#define QCA955X_MAC3_GPIO 41
1146#define QCA955X_ATT_LED 42
1147#define QCA955X_PWR_LED 43
1148#define QCA955X_TX_FRAME 44
1149#define QCA955X_RX_CLEAR_EXTERNAL 45
1150#define QCA955X_LED_NETWORK_EN 46
1151#define QCA955X_LED_POWER_EN 47
1152#define QCA955X_WMAC_GLUE_WOW 68
1153#define QCA955X_RX_CLEAR_EXTENSION 70
1154#define QCA955X_CP_NAND_CS1 73
1155#define QCA955X_USB_SUSPEND 74
1156#define QCA955X_ETH_TX_ERR 75
1157#define QCA955X_DDR_DQ_OE 76
1158#define QCA955X_CLKREQ_N_EP 77
1159#define QCA955X_CLKREQ_N_RC 78
1160#define QCA955X_CLK_OBS0 79
1161#define QCA955X_CLK_OBS1 80
1162#define QCA955X_CLK_OBS2 81
1163#define QCA955X_CLK_OBS3 82
1164#define QCA955X_CLK_OBS4 83
1165#define QCA955X_CLK_OBS5 84
1166
1167/*
1168 * MII_CTRL block
1169 */
1170#define AR71XX_MII_REG_MII0_CTRL 0x00
1171#define AR71XX_MII_REG_MII1_CTRL 0x04
1172
1173#define AR71XX_MII_CTRL_IF_MASK 3
1174#define AR71XX_MII_CTRL_SPEED_SHIFT 4
1175#define AR71XX_MII_CTRL_SPEED_MASK 3
1176#define AR71XX_MII_CTRL_SPEED_10 0
1177#define AR71XX_MII_CTRL_SPEED_100 1
1178#define AR71XX_MII_CTRL_SPEED_1000 2
1179
1180#define AR71XX_MII0_CTRL_IF_GMII 0
1181#define AR71XX_MII0_CTRL_IF_MII 1
1182#define AR71XX_MII0_CTRL_IF_RGMII 2
1183#define AR71XX_MII0_CTRL_IF_RMII 3
1184
1185#define AR71XX_MII1_CTRL_IF_RGMII 0
1186#define AR71XX_MII1_CTRL_IF_RMII 1
1187
1188/*
1189 * AR933X GMAC interface
1190 */
1191#define AR933X_GMAC_REG_ETH_CFG 0x00
1192
1193#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
1194#define AR933X_ETH_CFG_MII_GE0 BIT(1)
1195#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
1196#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
1197#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
1198#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
1199#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
1200#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
1201#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
1202#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
1203#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
1204
1205/*
1206 * AR934X GMAC Interface
1207 */
1208#define AR934X_GMAC_REG_ETH_CFG 0x00
1209
1210#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
1211#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
1212#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
1213#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
1214#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
1215#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
1216#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
1217#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
1218#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
1219#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
1220#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
1221#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
1222#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
1223#define AR934X_ETH_CFG_RXD_DELAY BIT(14)
1224#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3
1225#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14
1226#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
1227#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
1228#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
1229
1230/*
1231 * QCA953X GMAC Interface
1232 */
1233#define QCA953X_GMAC_REG_ETH_CFG 0x00
1234
1235#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6)
1236#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7)
1237#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9)
1238#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
1239
1240/*
1241 * QCA955X GMAC Interface
1242 */
1243
1244#define QCA955X_GMAC_REG_ETH_CFG 0x00
1245#define QCA955X_GMAC_REG_SGMII_SERDES 0x18
1246
1247#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
1248#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
1249#define QCA955X_ETH_CFG_GMII_GE0 BIT(2)
1250#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3)
1251#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4)
1252#define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5)
1253#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
1254#define QCA955X_ETH_CFG_RMII_GE0 BIT(10)
1255#define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11)
1256#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12)
1257#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3
1258#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14
1259#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
1260#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3
1261#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16
1262#define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3
1263#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18
1264#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
1265#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
1266
1267#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
1268#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
1269#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
1270/*
1271 * QCA956X GMAC Interface
1272 */
1273
1274#define QCA956X_GMAC_REG_ETH_CFG 0x00
1275#define QCA956X_GMAC_REG_SGMII_RESET 0x14
1276#define QCA956X_GMAC_REG_SGMII_SERDES 0x18
1277#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c
1278#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34
1279#define QCA956X_GMAC_REG_SGMII_DEBUG 0x58
1280
1281#define QCA956X_ETH_CFG_RGMII_EN BIT(0)
1282#define QCA956X_ETH_CFG_GE0_SGMII BIT(6)
1283#define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7)
1284#define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8)
1285#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9)
1286#define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10)
1287#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
1288#define QCA956X_ETH_CFG_RXD_DELAY_MASK 0x3
1289#define QCA956X_ETH_CFG_RXD_DELAY_SHIFT 14
1290#define QCA956X_ETH_CFG_RDV_DELAY_MASK 0x3
1291#define QCA956X_ETH_CFG_RDV_DELAY_SHIFT 16
1292
1293#define QCA956X_SGMII_RESET_RX_CLK_N_RESET 0x0
1294#define QCA956X_SGMII_RESET_RX_CLK_N BIT(0)
1295#define QCA956X_SGMII_RESET_TX_CLK_N BIT(1)
1296#define QCA956X_SGMII_RESET_RX_125M_N BIT(2)
1297#define QCA956X_SGMII_RESET_TX_125M_N BIT(3)
1298#define QCA956X_SGMII_RESET_HW_RX_125M_N BIT(4)
1299
1300#define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3
1301#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT 1
1302#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7
1303#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4
1304#define QCA956X_SGMII_SERDES_PLL_BW BIT(8)
1305#define QCA956X_SGMII_SERDES_VCO_FAST BIT(9)
1306#define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10)
1307#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
1308#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16)
1309#define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17)
1310#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
1311#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
1312#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT 27
1313#define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf
1314
1315#define QCA956X_MR_AN_CONTROL_AN_ENABLE BIT(12)
1316#define QCA956X_MR_AN_CONTROL_PHY_RESET BIT(15)
1317
1318#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0
1319#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7
1320
1321#endif /* __ASM_MACH_AR71XX_REGS_H */