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1/*
2 * SMS/SDRC (SDRAM controller) common code for OMAP2/3
3 *
4 * Copyright (C) 2005, 2008 Texas Instruments Inc.
5 * Copyright (C) 2005, 2008 Nokia Corporation
6 *
7 * Tony Lindgren <tony@atomide.com>
8 * Paul Walmsley
9 * Richard Woodruff <r-woodruff2@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15#undef DEBUG
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/device.h>
20#include <linux/list.h>
21#include <linux/errno.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25
26#include "common.h"
27#include "clock.h"
28#include "sdrc.h"
29
30static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
31
32void __iomem *omap2_sdrc_base;
33void __iomem *omap2_sms_base;
34
35struct omap2_sms_regs {
36 u32 sms_sysconfig;
37};
38
39static struct omap2_sms_regs sms_context;
40
41/* SDRC_POWER register bits */
42#define SDRC_POWER_EXTCLKDIS_SHIFT 3
43#define SDRC_POWER_PWDENA_SHIFT 2
44#define SDRC_POWER_PAGEPOLICY_SHIFT 0
45
46/**
47 * omap2_sms_save_context - Save SMS registers
48 *
49 * Save SMS registers that need to be restored after off mode.
50 */
51void omap2_sms_save_context(void)
52{
53 sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
54}
55
56/**
57 * omap2_sms_restore_context - Restore SMS registers
58 *
59 * Restore SMS registers that need to be Restored after off mode.
60 */
61void omap2_sms_restore_context(void)
62{
63 sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
64}
65
66/**
67 * omap2_sdrc_get_params - return SDRC register values for a given clock rate
68 * @r: SDRC clock rate (in Hz)
69 * @sdrc_cs0: chip select 0 ram timings **
70 * @sdrc_cs1: chip select 1 ram timings **
71 *
72 * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
73 * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
74 * structs,for a given SDRC clock rate 'r'.
75 * These parameters control various timing delays in the SDRAM controller
76 * that are expressed in terms of the number of SDRC clock cycles to
77 * wait; hence the clock rate dependency.
78 *
79 * Supports 2 different timing parameters for both chip selects.
80 *
81 * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
82 * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
83 * as sdrc_init_params_cs_0.
84 *
85 * Fills in the struct omap_sdrc_params * for each chip select.
86 * Returns 0 upon success or -1 upon failure.
87 */
88int omap2_sdrc_get_params(unsigned long r,
89 struct omap_sdrc_params **sdrc_cs0,
90 struct omap_sdrc_params **sdrc_cs1)
91{
92 struct omap_sdrc_params *sp0, *sp1;
93
94 if (!sdrc_init_params_cs0)
95 return -1;
96
97 sp0 = sdrc_init_params_cs0;
98 sp1 = sdrc_init_params_cs1;
99
100 while (sp0->rate && sp0->rate != r) {
101 sp0++;
102 if (sdrc_init_params_cs1)
103 sp1++;
104 }
105
106 if (!sp0->rate)
107 return -1;
108
109 *sdrc_cs0 = sp0;
110 *sdrc_cs1 = sp1;
111 return 0;
112}
113
114
115void __init omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms)
116{
117 omap2_sdrc_base = sdrc;
118 omap2_sms_base = sms;
119}
120
121/**
122 * omap2_sdrc_init - initialize SMS, SDRC devices on boot
123 * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
124 * Support for 2 chip selects timings
125 *
126 * Turn on smart idle modes for SDRAM scheduler and controller.
127 * Program a known-good configuration for the SDRC to deal with buggy
128 * bootloaders.
129 */
130void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
131 struct omap_sdrc_params *sdrc_cs1)
132{
133 u32 l;
134
135 l = sms_read_reg(SMS_SYSCONFIG);
136 l &= ~(0x3 << 3);
137 l |= (0x2 << 3);
138 sms_write_reg(l, SMS_SYSCONFIG);
139
140 l = sdrc_read_reg(SDRC_SYSCONFIG);
141 l &= ~(0x3 << 3);
142 l |= (0x2 << 3);
143 sdrc_write_reg(l, SDRC_SYSCONFIG);
144
145 sdrc_init_params_cs0 = sdrc_cs0;
146 sdrc_init_params_cs1 = sdrc_cs1;
147
148 /* XXX Enable SRFRONIDLEREQ here also? */
149 /*
150 * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
151 * can cause random memory corruption
152 */
153 l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
154 (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
155 sdrc_write_reg(l, SDRC_POWER);
156 omap2_sms_save_context();
157}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SMS/SDRC (SDRAM controller) common code for OMAP2/3
4 *
5 * Copyright (C) 2005, 2008 Texas Instruments Inc.
6 * Copyright (C) 2005, 2008 Nokia Corporation
7 *
8 * Tony Lindgren <tony@atomide.com>
9 * Paul Walmsley
10 * Richard Woodruff <r-woodruff2@ti.com>
11 */
12#undef DEBUG
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/device.h>
17#include <linux/list.h>
18#include <linux/errno.h>
19#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22
23#include "common.h"
24#include "clock.h"
25#include "sdrc.h"
26
27static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
28
29void __iomem *omap2_sdrc_base;
30void __iomem *omap2_sms_base;
31
32struct omap2_sms_regs {
33 u32 sms_sysconfig;
34};
35
36static struct omap2_sms_regs sms_context;
37
38/* SDRC_POWER register bits */
39#define SDRC_POWER_EXTCLKDIS_SHIFT 3
40#define SDRC_POWER_PWDENA_SHIFT 2
41#define SDRC_POWER_PAGEPOLICY_SHIFT 0
42
43/**
44 * omap2_sms_save_context - Save SMS registers
45 *
46 * Save SMS registers that need to be restored after off mode.
47 */
48void omap2_sms_save_context(void)
49{
50 sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
51}
52
53/**
54 * omap2_sms_restore_context - Restore SMS registers
55 *
56 * Restore SMS registers that need to be Restored after off mode.
57 */
58void omap2_sms_restore_context(void)
59{
60 sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
61}
62
63/**
64 * omap2_sdrc_get_params - return SDRC register values for a given clock rate
65 * @r: SDRC clock rate (in Hz)
66 * @sdrc_cs0: chip select 0 ram timings **
67 * @sdrc_cs1: chip select 1 ram timings **
68 *
69 * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
70 * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
71 * structs,for a given SDRC clock rate 'r'.
72 * These parameters control various timing delays in the SDRAM controller
73 * that are expressed in terms of the number of SDRC clock cycles to
74 * wait; hence the clock rate dependency.
75 *
76 * Supports 2 different timing parameters for both chip selects.
77 *
78 * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
79 * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
80 * as sdrc_init_params_cs_0.
81 *
82 * Fills in the struct omap_sdrc_params * for each chip select.
83 * Returns 0 upon success or -1 upon failure.
84 */
85int omap2_sdrc_get_params(unsigned long r,
86 struct omap_sdrc_params **sdrc_cs0,
87 struct omap_sdrc_params **sdrc_cs1)
88{
89 struct omap_sdrc_params *sp0, *sp1;
90
91 if (!sdrc_init_params_cs0)
92 return -1;
93
94 sp0 = sdrc_init_params_cs0;
95 sp1 = sdrc_init_params_cs1;
96
97 while (sp0->rate && sp0->rate != r) {
98 sp0++;
99 if (sdrc_init_params_cs1)
100 sp1++;
101 }
102
103 if (!sp0->rate)
104 return -1;
105
106 *sdrc_cs0 = sp0;
107 *sdrc_cs1 = sp1;
108 return 0;
109}
110
111
112void __init omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms)
113{
114 omap2_sdrc_base = sdrc;
115 omap2_sms_base = sms;
116}
117
118/**
119 * omap2_sdrc_init - initialize SMS, SDRC devices on boot
120 * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
121 * Support for 2 chip selects timings
122 *
123 * Turn on smart idle modes for SDRAM scheduler and controller.
124 * Program a known-good configuration for the SDRC to deal with buggy
125 * bootloaders.
126 */
127void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
128 struct omap_sdrc_params *sdrc_cs1)
129{
130 u32 l;
131
132 l = sms_read_reg(SMS_SYSCONFIG);
133 l &= ~(0x3 << 3);
134 l |= (0x2 << 3);
135 sms_write_reg(l, SMS_SYSCONFIG);
136
137 l = sdrc_read_reg(SDRC_SYSCONFIG);
138 l &= ~(0x3 << 3);
139 l |= (0x2 << 3);
140 sdrc_write_reg(l, SDRC_SYSCONFIG);
141
142 sdrc_init_params_cs0 = sdrc_cs0;
143 sdrc_init_params_cs1 = sdrc_cs1;
144
145 /* XXX Enable SRFRONIDLEREQ here also? */
146 /*
147 * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
148 * can cause random memory corruption
149 */
150 l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
151 (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
152 sdrc_write_reg(l, SDRC_POWER);
153 omap2_sms_save_context();
154}