Loading...
1/*
2 * DRA7xx Power domains framework
3 *
4 * Copyright (C) 2009-2013 Texas Instruments, Inc.
5 * Copyright (C) 2009-2011 Nokia Corporation
6 *
7 * Generated by code originally written by:
8 * Abhijit Pagare (abhijitpagare@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 * Paul Walmsley (paul@pwsan.com)
11 *
12 * This file is automatically generated from the OMAP hardware databases.
13 * We respectfully ask that any modifications to this file be coordinated
14 * with the public linux-omap@vger.kernel.org mailing list and the
15 * authors above to ensure that the autogeneration scripts are kept
16 * up-to-date with the file contents.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25
26#include "powerdomain.h"
27
28#include "prcm-common.h"
29#include "prcm44xx.h"
30#include "prm7xx.h"
31#include "prcm_mpu7xx.h"
32
33/* iva_7xx_pwrdm: IVA-HD power domain */
34static struct powerdomain iva_7xx_pwrdm = {
35 .name = "iva_pwrdm",
36 .prcm_offs = DRA7XX_PRM_IVA_INST,
37 .prcm_partition = DRA7XX_PRM_PARTITION,
38 .pwrsts = PWRSTS_OFF_RET_ON,
39 .pwrsts_logic_ret = PWRSTS_OFF,
40 .banks = 4,
41 .pwrsts_mem_ret = {
42 [0] = PWRSTS_OFF_RET, /* hwa_mem */
43 [1] = PWRSTS_OFF_RET, /* sl2_mem */
44 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
45 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
46 },
47 .pwrsts_mem_on = {
48 [0] = PWRSTS_OFF_RET, /* hwa_mem */
49 [1] = PWRSTS_OFF_RET, /* sl2_mem */
50 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
51 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
52 },
53 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
54};
55
56/* rtc_7xx_pwrdm: */
57static struct powerdomain rtc_7xx_pwrdm = {
58 .name = "rtc_pwrdm",
59 .prcm_offs = DRA7XX_PRM_RTC_INST,
60 .prcm_partition = DRA7XX_PRM_PARTITION,
61 .pwrsts = PWRSTS_ON,
62};
63
64/* custefuse_7xx_pwrdm: Customer efuse controller power domain */
65static struct powerdomain custefuse_7xx_pwrdm = {
66 .name = "custefuse_pwrdm",
67 .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
68 .prcm_partition = DRA7XX_PRM_PARTITION,
69 .pwrsts = PWRSTS_OFF_ON,
70 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
71};
72
73/* ipu_7xx_pwrdm: Audio back end power domain */
74static struct powerdomain ipu_7xx_pwrdm = {
75 .name = "ipu_pwrdm",
76 .prcm_offs = DRA7XX_PRM_IPU_INST,
77 .prcm_partition = DRA7XX_PRM_PARTITION,
78 .pwrsts = PWRSTS_OFF_RET_ON,
79 .pwrsts_logic_ret = PWRSTS_OFF,
80 .banks = 2,
81 .pwrsts_mem_ret = {
82 [0] = PWRSTS_OFF_RET, /* aessmem */
83 [1] = PWRSTS_OFF_RET, /* periphmem */
84 },
85 .pwrsts_mem_on = {
86 [0] = PWRSTS_OFF_RET, /* aessmem */
87 [1] = PWRSTS_OFF_RET, /* periphmem */
88 },
89 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
90};
91
92/* dss_7xx_pwrdm: Display subsystem power domain */
93static struct powerdomain dss_7xx_pwrdm = {
94 .name = "dss_pwrdm",
95 .prcm_offs = DRA7XX_PRM_DSS_INST,
96 .prcm_partition = DRA7XX_PRM_PARTITION,
97 .pwrsts = PWRSTS_OFF_RET_ON,
98 .pwrsts_logic_ret = PWRSTS_OFF,
99 .banks = 1,
100 .pwrsts_mem_ret = {
101 [0] = PWRSTS_OFF_RET, /* dss_mem */
102 },
103 .pwrsts_mem_on = {
104 [0] = PWRSTS_OFF_RET, /* dss_mem */
105 },
106 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
107};
108
109/* l4per_7xx_pwrdm: Target peripherals power domain */
110static struct powerdomain l4per_7xx_pwrdm = {
111 .name = "l4per_pwrdm",
112 .prcm_offs = DRA7XX_PRM_L4PER_INST,
113 .prcm_partition = DRA7XX_PRM_PARTITION,
114 .pwrsts = PWRSTS_RET_ON,
115 .pwrsts_logic_ret = PWRSTS_OFF_RET,
116 .banks = 2,
117 .pwrsts_mem_ret = {
118 [0] = PWRSTS_OFF_RET, /* nonretained_bank */
119 [1] = PWRSTS_OFF_RET, /* retained_bank */
120 },
121 .pwrsts_mem_on = {
122 [0] = PWRSTS_OFF_RET, /* nonretained_bank */
123 [1] = PWRSTS_OFF_RET, /* retained_bank */
124 },
125 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
126};
127
128/* gpu_7xx_pwrdm: 3D accelerator power domain */
129static struct powerdomain gpu_7xx_pwrdm = {
130 .name = "gpu_pwrdm",
131 .prcm_offs = DRA7XX_PRM_GPU_INST,
132 .prcm_partition = DRA7XX_PRM_PARTITION,
133 .pwrsts = PWRSTS_OFF_ON,
134 .banks = 1,
135 .pwrsts_mem_ret = {
136 [0] = PWRSTS_OFF_RET, /* gpu_mem */
137 },
138 .pwrsts_mem_on = {
139 [0] = PWRSTS_OFF_RET, /* gpu_mem */
140 },
141 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
142};
143
144/* wkupaon_7xx_pwrdm: Wake-up power domain */
145static struct powerdomain wkupaon_7xx_pwrdm = {
146 .name = "wkupaon_pwrdm",
147 .prcm_offs = DRA7XX_PRM_WKUPAON_INST,
148 .prcm_partition = DRA7XX_PRM_PARTITION,
149 .pwrsts = PWRSTS_ON,
150 .banks = 1,
151 .pwrsts_mem_ret = {
152 },
153 .pwrsts_mem_on = {
154 [0] = PWRSTS_ON, /* wkup_bank */
155 },
156};
157
158/* core_7xx_pwrdm: CORE power domain */
159static struct powerdomain core_7xx_pwrdm = {
160 .name = "core_pwrdm",
161 .prcm_offs = DRA7XX_PRM_CORE_INST,
162 .prcm_partition = DRA7XX_PRM_PARTITION,
163 .pwrsts = PWRSTS_RET_ON,
164 .pwrsts_logic_ret = PWRSTS_OFF_RET,
165 .banks = 5,
166 .pwrsts_mem_ret = {
167 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
168 [1] = PWRSTS_OFF_RET, /* core_ocmram */
169 [2] = PWRSTS_OFF_RET, /* core_other_bank */
170 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
171 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
172 },
173 .pwrsts_mem_on = {
174 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
175 [1] = PWRSTS_OFF_RET, /* core_ocmram */
176 [2] = PWRSTS_OFF_RET, /* core_other_bank */
177 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
178 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
179 },
180 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
181};
182
183/* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
184static struct powerdomain coreaon_7xx_pwrdm = {
185 .name = "coreaon_pwrdm",
186 .prcm_offs = DRA7XX_PRM_COREAON_INST,
187 .prcm_partition = DRA7XX_PRM_PARTITION,
188 .pwrsts = PWRSTS_ON,
189};
190
191/* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
192static struct powerdomain cpu0_7xx_pwrdm = {
193 .name = "cpu0_pwrdm",
194 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST,
195 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
196 .pwrsts = PWRSTS_OFF_RET_ON,
197 .pwrsts_logic_ret = PWRSTS_OFF_RET,
198 .banks = 1,
199 .pwrsts_mem_ret = {
200 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
201 },
202 .pwrsts_mem_on = {
203 [0] = PWRSTS_ON, /* cpu0_l1 */
204 },
205};
206
207/* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
208static struct powerdomain cpu1_7xx_pwrdm = {
209 .name = "cpu1_pwrdm",
210 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST,
211 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
212 .pwrsts = PWRSTS_OFF_RET_ON,
213 .pwrsts_logic_ret = PWRSTS_OFF_RET,
214 .banks = 1,
215 .pwrsts_mem_ret = {
216 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
217 },
218 .pwrsts_mem_on = {
219 [0] = PWRSTS_ON, /* cpu1_l1 */
220 },
221};
222
223/* vpe_7xx_pwrdm: */
224static struct powerdomain vpe_7xx_pwrdm = {
225 .name = "vpe_pwrdm",
226 .prcm_offs = DRA7XX_PRM_VPE_INST,
227 .prcm_partition = DRA7XX_PRM_PARTITION,
228 .pwrsts = PWRSTS_OFF_RET_ON,
229 .pwrsts_logic_ret = PWRSTS_OFF_RET,
230 .banks = 1,
231 .pwrsts_mem_ret = {
232 [0] = PWRSTS_OFF_RET, /* vpe_bank */
233 },
234 .pwrsts_mem_on = {
235 [0] = PWRSTS_OFF_RET, /* vpe_bank */
236 },
237 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
238};
239
240/* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
241static struct powerdomain mpu_7xx_pwrdm = {
242 .name = "mpu_pwrdm",
243 .prcm_offs = DRA7XX_PRM_MPU_INST,
244 .prcm_partition = DRA7XX_PRM_PARTITION,
245 .pwrsts = PWRSTS_RET_ON,
246 .pwrsts_logic_ret = PWRSTS_OFF_RET,
247 .banks = 2,
248 .pwrsts_mem_ret = {
249 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
250 [1] = PWRSTS_RET, /* mpu_ram */
251 },
252 .pwrsts_mem_on = {
253 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
254 [1] = PWRSTS_OFF_RET, /* mpu_ram */
255 },
256};
257
258/* l3init_7xx_pwrdm: L3 initators pheripherals power domain */
259static struct powerdomain l3init_7xx_pwrdm = {
260 .name = "l3init_pwrdm",
261 .prcm_offs = DRA7XX_PRM_L3INIT_INST,
262 .prcm_partition = DRA7XX_PRM_PARTITION,
263 .pwrsts = PWRSTS_RET_ON,
264 .pwrsts_logic_ret = PWRSTS_OFF_RET,
265 .banks = 3,
266 .pwrsts_mem_ret = {
267 [0] = PWRSTS_OFF_RET, /* gmac_bank */
268 [1] = PWRSTS_OFF_RET, /* l3init_bank1 */
269 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */
270 },
271 .pwrsts_mem_on = {
272 [0] = PWRSTS_OFF_RET, /* gmac_bank */
273 [1] = PWRSTS_OFF_RET, /* l3init_bank1 */
274 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */
275 },
276 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
277};
278
279/* eve3_7xx_pwrdm: */
280static struct powerdomain eve3_7xx_pwrdm = {
281 .name = "eve3_pwrdm",
282 .prcm_offs = DRA7XX_PRM_EVE3_INST,
283 .prcm_partition = DRA7XX_PRM_PARTITION,
284 .pwrsts = PWRSTS_OFF_ON,
285 .banks = 1,
286 .pwrsts_mem_ret = {
287 [0] = PWRSTS_OFF_RET, /* eve3_bank */
288 },
289 .pwrsts_mem_on = {
290 [0] = PWRSTS_OFF_RET, /* eve3_bank */
291 },
292 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
293};
294
295/* emu_7xx_pwrdm: Emulation power domain */
296static struct powerdomain emu_7xx_pwrdm = {
297 .name = "emu_pwrdm",
298 .prcm_offs = DRA7XX_PRM_EMU_INST,
299 .prcm_partition = DRA7XX_PRM_PARTITION,
300 .pwrsts = PWRSTS_OFF_ON,
301 .banks = 1,
302 .pwrsts_mem_ret = {
303 [0] = PWRSTS_OFF_RET, /* emu_bank */
304 },
305 .pwrsts_mem_on = {
306 [0] = PWRSTS_OFF_RET, /* emu_bank */
307 },
308};
309
310/* dsp2_7xx_pwrdm: */
311static struct powerdomain dsp2_7xx_pwrdm = {
312 .name = "dsp2_pwrdm",
313 .prcm_offs = DRA7XX_PRM_DSP2_INST,
314 .prcm_partition = DRA7XX_PRM_PARTITION,
315 .pwrsts = PWRSTS_OFF_ON,
316 .banks = 3,
317 .pwrsts_mem_ret = {
318 [0] = PWRSTS_OFF_RET, /* dsp2_edma */
319 [1] = PWRSTS_OFF_RET, /* dsp2_l1 */
320 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */
321 },
322 .pwrsts_mem_on = {
323 [0] = PWRSTS_OFF_RET, /* dsp2_edma */
324 [1] = PWRSTS_OFF_RET, /* dsp2_l1 */
325 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */
326 },
327 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
328};
329
330/* dsp1_7xx_pwrdm: Tesla processor power domain */
331static struct powerdomain dsp1_7xx_pwrdm = {
332 .name = "dsp1_pwrdm",
333 .prcm_offs = DRA7XX_PRM_DSP1_INST,
334 .prcm_partition = DRA7XX_PRM_PARTITION,
335 .pwrsts = PWRSTS_OFF_ON,
336 .banks = 3,
337 .pwrsts_mem_ret = {
338 [0] = PWRSTS_OFF_RET, /* dsp1_edma */
339 [1] = PWRSTS_OFF_RET, /* dsp1_l1 */
340 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */
341 },
342 .pwrsts_mem_on = {
343 [0] = PWRSTS_OFF_RET, /* dsp1_edma */
344 [1] = PWRSTS_OFF_RET, /* dsp1_l1 */
345 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */
346 },
347 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
348};
349
350/* cam_7xx_pwrdm: Camera subsystem power domain */
351static struct powerdomain cam_7xx_pwrdm = {
352 .name = "cam_pwrdm",
353 .prcm_offs = DRA7XX_PRM_CAM_INST,
354 .prcm_partition = DRA7XX_PRM_PARTITION,
355 .pwrsts = PWRSTS_OFF_ON,
356 .banks = 1,
357 .pwrsts_mem_ret = {
358 [0] = PWRSTS_OFF_RET, /* vip_bank */
359 },
360 .pwrsts_mem_on = {
361 [0] = PWRSTS_OFF_RET, /* vip_bank */
362 },
363 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
364};
365
366/* eve4_7xx_pwrdm: */
367static struct powerdomain eve4_7xx_pwrdm = {
368 .name = "eve4_pwrdm",
369 .prcm_offs = DRA7XX_PRM_EVE4_INST,
370 .prcm_partition = DRA7XX_PRM_PARTITION,
371 .pwrsts = PWRSTS_OFF_ON,
372 .banks = 1,
373 .pwrsts_mem_ret = {
374 [0] = PWRSTS_OFF_RET, /* eve4_bank */
375 },
376 .pwrsts_mem_on = {
377 [0] = PWRSTS_OFF_RET, /* eve4_bank */
378 },
379 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
380};
381
382/* eve2_7xx_pwrdm: */
383static struct powerdomain eve2_7xx_pwrdm = {
384 .name = "eve2_pwrdm",
385 .prcm_offs = DRA7XX_PRM_EVE2_INST,
386 .prcm_partition = DRA7XX_PRM_PARTITION,
387 .pwrsts = PWRSTS_OFF_ON,
388 .banks = 1,
389 .pwrsts_mem_ret = {
390 [0] = PWRSTS_OFF_RET, /* eve2_bank */
391 },
392 .pwrsts_mem_on = {
393 [0] = PWRSTS_OFF_RET, /* eve2_bank */
394 },
395 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
396};
397
398/* eve1_7xx_pwrdm: */
399static struct powerdomain eve1_7xx_pwrdm = {
400 .name = "eve1_pwrdm",
401 .prcm_offs = DRA7XX_PRM_EVE1_INST,
402 .prcm_partition = DRA7XX_PRM_PARTITION,
403 .pwrsts = PWRSTS_OFF_ON,
404 .banks = 1,
405 .pwrsts_mem_ret = {
406 [0] = PWRSTS_OFF_RET, /* eve1_bank */
407 },
408 .pwrsts_mem_on = {
409 [0] = PWRSTS_OFF_RET, /* eve1_bank */
410 },
411 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
412};
413
414/*
415 * The following power domains are not under SW control
416 *
417 * mpuaon
418 * mmaon
419 */
420
421/* As powerdomains are added or removed above, this list must also be changed */
422static struct powerdomain *powerdomains_dra7xx[] __initdata = {
423 &iva_7xx_pwrdm,
424 &rtc_7xx_pwrdm,
425 &custefuse_7xx_pwrdm,
426 &ipu_7xx_pwrdm,
427 &dss_7xx_pwrdm,
428 &l4per_7xx_pwrdm,
429 &gpu_7xx_pwrdm,
430 &wkupaon_7xx_pwrdm,
431 &core_7xx_pwrdm,
432 &coreaon_7xx_pwrdm,
433 &cpu0_7xx_pwrdm,
434 &cpu1_7xx_pwrdm,
435 &vpe_7xx_pwrdm,
436 &mpu_7xx_pwrdm,
437 &l3init_7xx_pwrdm,
438 &eve3_7xx_pwrdm,
439 &emu_7xx_pwrdm,
440 &dsp2_7xx_pwrdm,
441 &dsp1_7xx_pwrdm,
442 &cam_7xx_pwrdm,
443 &eve4_7xx_pwrdm,
444 &eve2_7xx_pwrdm,
445 &eve1_7xx_pwrdm,
446 NULL
447};
448
449void __init dra7xx_powerdomains_init(void)
450{
451 pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
452 pwrdm_register_pwrdms(powerdomains_dra7xx);
453 pwrdm_complete_init();
454}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * DRA7xx Power domains framework
4 *
5 * Copyright (C) 2009-2013 Texas Instruments, Inc.
6 * Copyright (C) 2009-2011 Nokia Corporation
7 *
8 * Generated by code originally written by:
9 * Abhijit Pagare (abhijitpagare@ti.com)
10 * Benoit Cousson (b-cousson@ti.com)
11 * Paul Walmsley (paul@pwsan.com)
12 *
13 * This file is automatically generated from the OMAP hardware databases.
14 * We respectfully ask that any modifications to this file be coordinated
15 * with the public linux-omap@vger.kernel.org mailing list and the
16 * authors above to ensure that the autogeneration scripts are kept
17 * up-to-date with the file contents.
18 */
19
20#include <linux/kernel.h>
21#include <linux/init.h>
22
23#include "powerdomain.h"
24
25#include "prcm-common.h"
26#include "prcm44xx.h"
27#include "prm7xx.h"
28#include "prcm_mpu7xx.h"
29#include "soc.h"
30
31/* iva_7xx_pwrdm: IVA-HD power domain */
32static struct powerdomain iva_7xx_pwrdm = {
33 .name = "iva_pwrdm",
34 .prcm_offs = DRA7XX_PRM_IVA_INST,
35 .prcm_partition = DRA7XX_PRM_PARTITION,
36 .pwrsts = PWRSTS_OFF_ON,
37 .banks = 4,
38 .pwrsts_mem_on = {
39 [0] = PWRSTS_ON, /* hwa_mem */
40 [1] = PWRSTS_ON, /* sl2_mem */
41 [2] = PWRSTS_ON, /* tcm1_mem */
42 [3] = PWRSTS_ON, /* tcm2_mem */
43 },
44 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
45};
46
47/* rtc_7xx_pwrdm: */
48static struct powerdomain rtc_7xx_pwrdm = {
49 .name = "rtc_pwrdm",
50 .prcm_offs = DRA7XX_PRM_RTC_INST,
51 .prcm_partition = DRA7XX_PRM_PARTITION,
52 .pwrsts = PWRSTS_ON,
53};
54
55/* custefuse_7xx_pwrdm: Customer efuse controller power domain */
56static struct powerdomain custefuse_7xx_pwrdm = {
57 .name = "custefuse_pwrdm",
58 .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
59 .prcm_partition = DRA7XX_PRM_PARTITION,
60 .pwrsts = PWRSTS_OFF_ON,
61 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
62};
63
64/* custefuse_aon_7xx_pwrdm: Customer efuse controller power domain */
65static struct powerdomain custefuse_aon_7xx_pwrdm = {
66 .name = "custefuse_pwrdm",
67 .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
68 .prcm_partition = DRA7XX_PRM_PARTITION,
69 .pwrsts = PWRSTS_ON,
70};
71
72/* ipu_7xx_pwrdm: Audio back end power domain */
73static struct powerdomain ipu_7xx_pwrdm = {
74 .name = "ipu_pwrdm",
75 .prcm_offs = DRA7XX_PRM_IPU_INST,
76 .prcm_partition = DRA7XX_PRM_PARTITION,
77 .pwrsts = PWRSTS_OFF_ON,
78 .banks = 2,
79 .pwrsts_mem_on = {
80 [0] = PWRSTS_ON, /* aessmem */
81 [1] = PWRSTS_ON, /* periphmem */
82 },
83 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
84};
85
86/* dss_7xx_pwrdm: Display subsystem power domain */
87static struct powerdomain dss_7xx_pwrdm = {
88 .name = "dss_pwrdm",
89 .prcm_offs = DRA7XX_PRM_DSS_INST,
90 .prcm_partition = DRA7XX_PRM_PARTITION,
91 .pwrsts = PWRSTS_OFF_ON,
92 .banks = 1,
93 .pwrsts_mem_on = {
94 [0] = PWRSTS_ON, /* dss_mem */
95 },
96 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
97};
98
99/* l4per_7xx_pwrdm: Target peripherals power domain */
100static struct powerdomain l4per_7xx_pwrdm = {
101 .name = "l4per_pwrdm",
102 .prcm_offs = DRA7XX_PRM_L4PER_INST,
103 .prcm_partition = DRA7XX_PRM_PARTITION,
104 .pwrsts = PWRSTS_ON,
105 .banks = 2,
106 .pwrsts_mem_on = {
107 [0] = PWRSTS_ON, /* nonretained_bank */
108 [1] = PWRSTS_ON, /* retained_bank */
109 },
110 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
111};
112
113/* gpu_7xx_pwrdm: 3D accelerator power domain */
114static struct powerdomain gpu_7xx_pwrdm = {
115 .name = "gpu_pwrdm",
116 .prcm_offs = DRA7XX_PRM_GPU_INST,
117 .prcm_partition = DRA7XX_PRM_PARTITION,
118 .pwrsts = PWRSTS_OFF_ON,
119 .banks = 1,
120 .pwrsts_mem_on = {
121 [0] = PWRSTS_ON, /* gpu_mem */
122 },
123 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
124};
125
126/* wkupaon_7xx_pwrdm: Wake-up power domain */
127static struct powerdomain wkupaon_7xx_pwrdm = {
128 .name = "wkupaon_pwrdm",
129 .prcm_offs = DRA7XX_PRM_WKUPAON_INST,
130 .prcm_partition = DRA7XX_PRM_PARTITION,
131 .pwrsts = PWRSTS_ON,
132 .banks = 1,
133 .pwrsts_mem_on = {
134 [0] = PWRSTS_ON, /* wkup_bank */
135 },
136};
137
138/* core_7xx_pwrdm: CORE power domain */
139static struct powerdomain core_7xx_pwrdm = {
140 .name = "core_pwrdm",
141 .prcm_offs = DRA7XX_PRM_CORE_INST,
142 .prcm_partition = DRA7XX_PRM_PARTITION,
143 .pwrsts = PWRSTS_ON,
144 .banks = 5,
145 .pwrsts_mem_on = {
146 [0] = PWRSTS_ON, /* core_nret_bank */
147 [1] = PWRSTS_ON, /* core_ocmram */
148 [2] = PWRSTS_ON, /* core_other_bank */
149 [3] = PWRSTS_ON, /* ipu_l2ram */
150 [4] = PWRSTS_ON, /* ipu_unicache */
151 },
152 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
153};
154
155/* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
156static struct powerdomain coreaon_7xx_pwrdm = {
157 .name = "coreaon_pwrdm",
158 .prcm_offs = DRA7XX_PRM_COREAON_INST,
159 .prcm_partition = DRA7XX_PRM_PARTITION,
160 .pwrsts = PWRSTS_ON,
161};
162
163/* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
164static struct powerdomain cpu0_7xx_pwrdm = {
165 .name = "cpu0_pwrdm",
166 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST,
167 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
168 .pwrsts = PWRSTS_RET_ON,
169 .pwrsts_logic_ret = PWRSTS_RET,
170 .banks = 1,
171 .pwrsts_mem_ret = {
172 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
173 },
174 .pwrsts_mem_on = {
175 [0] = PWRSTS_ON, /* cpu0_l1 */
176 },
177};
178
179/* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
180static struct powerdomain cpu1_7xx_pwrdm = {
181 .name = "cpu1_pwrdm",
182 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST,
183 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
184 .pwrsts = PWRSTS_RET_ON,
185 .pwrsts_logic_ret = PWRSTS_RET,
186 .banks = 1,
187 .pwrsts_mem_ret = {
188 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
189 },
190 .pwrsts_mem_on = {
191 [0] = PWRSTS_ON, /* cpu1_l1 */
192 },
193};
194
195/* vpe_7xx_pwrdm: */
196static struct powerdomain vpe_7xx_pwrdm = {
197 .name = "vpe_pwrdm",
198 .prcm_offs = DRA7XX_PRM_VPE_INST,
199 .prcm_partition = DRA7XX_PRM_PARTITION,
200 .pwrsts = PWRSTS_OFF_ON,
201 .banks = 1,
202 .pwrsts_mem_on = {
203 [0] = PWRSTS_ON, /* vpe_bank */
204 },
205 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
206};
207
208/* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
209static struct powerdomain mpu_7xx_pwrdm = {
210 .name = "mpu_pwrdm",
211 .prcm_offs = DRA7XX_PRM_MPU_INST,
212 .prcm_partition = DRA7XX_PRM_PARTITION,
213 .pwrsts = PWRSTS_RET_ON,
214 .pwrsts_logic_ret = PWRSTS_RET,
215 .banks = 2,
216 .pwrsts_mem_ret = {
217 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
218 [1] = PWRSTS_RET, /* mpu_ram */
219 },
220 .pwrsts_mem_on = {
221 [0] = PWRSTS_ON, /* mpu_l2 */
222 [1] = PWRSTS_ON, /* mpu_ram */
223 },
224};
225
226/* l3init_7xx_pwrdm: L3 initators pheripherals power domain */
227static struct powerdomain l3init_7xx_pwrdm = {
228 .name = "l3init_pwrdm",
229 .prcm_offs = DRA7XX_PRM_L3INIT_INST,
230 .prcm_partition = DRA7XX_PRM_PARTITION,
231 .pwrsts = PWRSTS_ON,
232 .banks = 3,
233 .pwrsts_mem_on = {
234 [0] = PWRSTS_ON, /* gmac_bank */
235 [1] = PWRSTS_ON, /* l3init_bank1 */
236 [2] = PWRSTS_ON, /* l3init_bank2 */
237 },
238 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
239};
240
241/* eve3_7xx_pwrdm: */
242static struct powerdomain eve3_7xx_pwrdm = {
243 .name = "eve3_pwrdm",
244 .prcm_offs = DRA7XX_PRM_EVE3_INST,
245 .prcm_partition = DRA7XX_PRM_PARTITION,
246 .pwrsts = PWRSTS_OFF_ON,
247 .banks = 1,
248 .pwrsts_mem_on = {
249 [0] = PWRSTS_ON, /* eve3_bank */
250 },
251 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
252};
253
254/* emu_7xx_pwrdm: Emulation power domain */
255static struct powerdomain emu_7xx_pwrdm = {
256 .name = "emu_pwrdm",
257 .prcm_offs = DRA7XX_PRM_EMU_INST,
258 .prcm_partition = DRA7XX_PRM_PARTITION,
259 .pwrsts = PWRSTS_OFF_ON,
260 .banks = 1,
261 .pwrsts_mem_on = {
262 [0] = PWRSTS_ON, /* emu_bank */
263 },
264};
265
266/* dsp2_7xx_pwrdm: */
267static struct powerdomain dsp2_7xx_pwrdm = {
268 .name = "dsp2_pwrdm",
269 .prcm_offs = DRA7XX_PRM_DSP2_INST,
270 .prcm_partition = DRA7XX_PRM_PARTITION,
271 .pwrsts = PWRSTS_OFF_ON,
272 .banks = 3,
273 .pwrsts_mem_on = {
274 [0] = PWRSTS_ON, /* dsp2_edma */
275 [1] = PWRSTS_ON, /* dsp2_l1 */
276 [2] = PWRSTS_ON, /* dsp2_l2 */
277 },
278 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
279};
280
281/* dsp1_7xx_pwrdm: Tesla processor power domain */
282static struct powerdomain dsp1_7xx_pwrdm = {
283 .name = "dsp1_pwrdm",
284 .prcm_offs = DRA7XX_PRM_DSP1_INST,
285 .prcm_partition = DRA7XX_PRM_PARTITION,
286 .pwrsts = PWRSTS_OFF_ON,
287 .banks = 3,
288 .pwrsts_mem_on = {
289 [0] = PWRSTS_ON, /* dsp1_edma */
290 [1] = PWRSTS_ON, /* dsp1_l1 */
291 [2] = PWRSTS_ON, /* dsp1_l2 */
292 },
293 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
294};
295
296/* cam_7xx_pwrdm: Camera subsystem power domain */
297static struct powerdomain cam_7xx_pwrdm = {
298 .name = "cam_pwrdm",
299 .prcm_offs = DRA7XX_PRM_CAM_INST,
300 .prcm_partition = DRA7XX_PRM_PARTITION,
301 .pwrsts = PWRSTS_OFF_ON,
302 .banks = 1,
303 .pwrsts_mem_on = {
304 [0] = PWRSTS_ON, /* vip_bank */
305 },
306 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
307};
308
309/* eve4_7xx_pwrdm: */
310static struct powerdomain eve4_7xx_pwrdm = {
311 .name = "eve4_pwrdm",
312 .prcm_offs = DRA7XX_PRM_EVE4_INST,
313 .prcm_partition = DRA7XX_PRM_PARTITION,
314 .pwrsts = PWRSTS_OFF_ON,
315 .banks = 1,
316 .pwrsts_mem_on = {
317 [0] = PWRSTS_ON, /* eve4_bank */
318 },
319 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
320};
321
322/* eve2_7xx_pwrdm: */
323static struct powerdomain eve2_7xx_pwrdm = {
324 .name = "eve2_pwrdm",
325 .prcm_offs = DRA7XX_PRM_EVE2_INST,
326 .prcm_partition = DRA7XX_PRM_PARTITION,
327 .pwrsts = PWRSTS_OFF_ON,
328 .banks = 1,
329 .pwrsts_mem_on = {
330 [0] = PWRSTS_ON, /* eve2_bank */
331 },
332 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
333};
334
335/* eve1_7xx_pwrdm: */
336static struct powerdomain eve1_7xx_pwrdm = {
337 .name = "eve1_pwrdm",
338 .prcm_offs = DRA7XX_PRM_EVE1_INST,
339 .prcm_partition = DRA7XX_PRM_PARTITION,
340 .pwrsts = PWRSTS_OFF_ON,
341 .banks = 1,
342 .pwrsts_mem_on = {
343 [0] = PWRSTS_ON, /* eve1_bank */
344 },
345 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
346};
347
348/*
349 * The following power domains are not under SW control
350 *
351 * mpuaon
352 * mmaon
353 */
354
355/* As powerdomains are added or removed above, this list must also be changed */
356static struct powerdomain *powerdomains_dra7xx[] __initdata = {
357 &iva_7xx_pwrdm,
358 &rtc_7xx_pwrdm,
359 &ipu_7xx_pwrdm,
360 &dss_7xx_pwrdm,
361 &l4per_7xx_pwrdm,
362 &gpu_7xx_pwrdm,
363 &wkupaon_7xx_pwrdm,
364 &core_7xx_pwrdm,
365 &coreaon_7xx_pwrdm,
366 &cpu0_7xx_pwrdm,
367 &cpu1_7xx_pwrdm,
368 &vpe_7xx_pwrdm,
369 &mpu_7xx_pwrdm,
370 &l3init_7xx_pwrdm,
371 &eve3_7xx_pwrdm,
372 &emu_7xx_pwrdm,
373 &dsp2_7xx_pwrdm,
374 &dsp1_7xx_pwrdm,
375 &cam_7xx_pwrdm,
376 &eve4_7xx_pwrdm,
377 &eve2_7xx_pwrdm,
378 &eve1_7xx_pwrdm,
379 NULL
380};
381
382static struct powerdomain *powerdomains_dra76x[] __initdata = {
383 &custefuse_aon_7xx_pwrdm,
384 NULL
385};
386
387static struct powerdomain *powerdomains_dra74x[] __initdata = {
388 &custefuse_7xx_pwrdm,
389 NULL
390};
391
392static struct powerdomain *powerdomains_dra72x[] __initdata = {
393 &custefuse_aon_7xx_pwrdm,
394 NULL
395};
396
397void __init dra7xx_powerdomains_init(void)
398{
399 pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
400 pwrdm_register_pwrdms(powerdomains_dra7xx);
401
402 if (soc_is_dra76x())
403 pwrdm_register_pwrdms(powerdomains_dra76x);
404 else if (soc_is_dra74x())
405 pwrdm_register_pwrdms(powerdomains_dra74x);
406 else if (soc_is_dra72x())
407 pwrdm_register_pwrdms(powerdomains_dra72x);
408
409 pwrdm_complete_init();
410}