1/*
  2 *  linux/arch/arm/include/asm/pmu.h
  3 *
  4 *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
  5 *
  6 * This program is free software; you can redistribute it and/or modify
  7 * it under the terms of the GNU General Public License version 2 as
  8 * published by the Free Software Foundation.
  9 *
 10 */
 11
 12#ifndef __ARM_PMU_H__
 13#define __ARM_PMU_H__
 14
 15#include <linux/interrupt.h>
 16#include <linux/perf_event.h>
 17
 18/*
 19 * struct arm_pmu_platdata - ARM PMU platform data
 20 *
 21 * @handle_irq: an optional handler which will be called from the
 22 *	interrupt and passed the address of the low level handler,
 23 *	and can be used to implement any platform specific handling
 24 *	before or after calling it.
 25 * @runtime_resume: an optional handler which will be called by the
 26 *	runtime PM framework following a call to pm_runtime_get().
 27 *	Note that if pm_runtime_get() is called more than once in
 28 *	succession this handler will only be called once.
 29 * @runtime_suspend: an optional handler which will be called by the
 30 *	runtime PM framework following a call to pm_runtime_put().
 31 *	Note that if pm_runtime_get() is called more than once in
 32 *	succession this handler will only be called following the
 33 *	final call to pm_runtime_put() that actually disables the
 34 *	hardware.
 35 */
 36struct arm_pmu_platdata {
 37	irqreturn_t (*handle_irq)(int irq, void *dev,
 38				  irq_handler_t pmu_handler);
 39	int (*runtime_resume)(struct device *dev);
 40	int (*runtime_suspend)(struct device *dev);
 41};
 42
 43#ifdef CONFIG_HW_PERF_EVENTS
 44
 45/* The events for a given PMU register set. */
 46struct pmu_hw_events {
 47	/*
 48	 * The events that are active on the PMU for the given index.
 49	 */
 50	struct perf_event	**events;
 51
 52	/*
 53	 * A 1 bit for an index indicates that the counter is being used for
 54	 * an event. A 0 means that the counter can be used.
 55	 */
 56	unsigned long           *used_mask;
 57
 58	/*
 59	 * Hardware lock to serialize accesses to PMU registers. Needed for the
 60	 * read/modify/write sequences.
 61	 */
 62	raw_spinlock_t		pmu_lock;
 63};
 64
 65struct arm_pmu {
 66	struct pmu	pmu;
 67	cpumask_t	active_irqs;
 68	char		*name;
 69	irqreturn_t	(*handle_irq)(int irq_num, void *dev);
 70	void		(*enable)(struct perf_event *event);
 71	void		(*disable)(struct perf_event *event);
 72	int		(*get_event_idx)(struct pmu_hw_events *hw_events,
 73					 struct perf_event *event);
 74	void		(*clear_event_idx)(struct pmu_hw_events *hw_events,
 75					 struct perf_event *event);
 76	int		(*set_event_filter)(struct hw_perf_event *evt,
 77					    struct perf_event_attr *attr);
 78	u32		(*read_counter)(struct perf_event *event);
 79	void		(*write_counter)(struct perf_event *event, u32 val);
 80	void		(*start)(struct arm_pmu *);
 81	void		(*stop)(struct arm_pmu *);
 82	void		(*reset)(void *);
 83	int		(*request_irq)(struct arm_pmu *, irq_handler_t handler);
 84	void		(*free_irq)(struct arm_pmu *);
 85	int		(*map_event)(struct perf_event *event);
 86	int		num_events;
 87	atomic_t	active_events;
 88	struct mutex	reserve_mutex;
 89	u64		max_period;
 90	struct platform_device	*plat_device;
 91	struct pmu_hw_events	*(*get_hw_events)(void);
 92};
 93
 94#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
 95
 96extern const struct dev_pm_ops armpmu_dev_pm_ops;
 97
 98int armpmu_register(struct arm_pmu *armpmu, int type);
 99
100u64 armpmu_event_update(struct perf_event *event);
101
102int armpmu_event_set_period(struct perf_event *event);
103
104int armpmu_map_event(struct perf_event *event,
105		     const unsigned (*event_map)[PERF_COUNT_HW_MAX],
106		     const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
107						[PERF_COUNT_HW_CACHE_OP_MAX]
108						[PERF_COUNT_HW_CACHE_RESULT_MAX],
109		     u32 raw_event_mask);
110
111#endif /* CONFIG_HW_PERF_EVENTS */
112
113#endif /* __ARM_PMU_H__ */