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1/*
2 * CAN bus driver for the alone generic (as possible as) MSCAN controller.
3 *
4 * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
5 * Varma Electronics Oy
6 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
7 * Copyright (C) 2008-2009 Pengutronix <kernel@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the version 2 of the GNU General Public License
11 * as published by the Free Software Foundation
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/delay.h>
26#include <linux/netdevice.h>
27#include <linux/if_arp.h>
28#include <linux/if_ether.h>
29#include <linux/list.h>
30#include <linux/can/dev.h>
31#include <linux/can/error.h>
32#include <linux/io.h>
33
34#include "mscan.h"
35
36static const struct can_bittiming_const mscan_bittiming_const = {
37 .name = "mscan",
38 .tseg1_min = 4,
39 .tseg1_max = 16,
40 .tseg2_min = 2,
41 .tseg2_max = 8,
42 .sjw_max = 4,
43 .brp_min = 1,
44 .brp_max = 64,
45 .brp_inc = 1,
46};
47
48struct mscan_state {
49 u8 mode;
50 u8 canrier;
51 u8 cantier;
52};
53
54static enum can_state state_map[] = {
55 CAN_STATE_ERROR_ACTIVE,
56 CAN_STATE_ERROR_WARNING,
57 CAN_STATE_ERROR_PASSIVE,
58 CAN_STATE_BUS_OFF
59};
60
61static int mscan_set_mode(struct net_device *dev, u8 mode)
62{
63 struct mscan_priv *priv = netdev_priv(dev);
64 struct mscan_regs __iomem *regs = priv->reg_base;
65 int ret = 0;
66 int i;
67 u8 canctl1;
68
69 if (mode != MSCAN_NORMAL_MODE) {
70 if (priv->tx_active) {
71 /* Abort transfers before going to sleep */#
72 out_8(®s->cantarq, priv->tx_active);
73 /* Suppress TX done interrupts */
74 out_8(®s->cantier, 0);
75 }
76
77 canctl1 = in_8(®s->canctl1);
78 if ((mode & MSCAN_SLPRQ) && !(canctl1 & MSCAN_SLPAK)) {
79 setbits8(®s->canctl0, MSCAN_SLPRQ);
80 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
81 if (in_8(®s->canctl1) & MSCAN_SLPAK)
82 break;
83 udelay(100);
84 }
85 /*
86 * The mscan controller will fail to enter sleep mode,
87 * while there are irregular activities on bus, like
88 * somebody keeps retransmitting. This behavior is
89 * undocumented and seems to differ between mscan built
90 * in mpc5200b and mpc5200. We proceed in that case,
91 * since otherwise the slprq will be kept set and the
92 * controller will get stuck. NOTE: INITRQ or CSWAI
93 * will abort all active transmit actions, if still
94 * any, at once.
95 */
96 if (i >= MSCAN_SET_MODE_RETRIES)
97 netdev_dbg(dev,
98 "device failed to enter sleep mode. "
99 "We proceed anyhow.\n");
100 else
101 priv->can.state = CAN_STATE_SLEEPING;
102 }
103
104 if ((mode & MSCAN_INITRQ) && !(canctl1 & MSCAN_INITAK)) {
105 setbits8(®s->canctl0, MSCAN_INITRQ);
106 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
107 if (in_8(®s->canctl1) & MSCAN_INITAK)
108 break;
109 }
110 if (i >= MSCAN_SET_MODE_RETRIES)
111 ret = -ENODEV;
112 }
113 if (!ret)
114 priv->can.state = CAN_STATE_STOPPED;
115
116 if (mode & MSCAN_CSWAI)
117 setbits8(®s->canctl0, MSCAN_CSWAI);
118
119 } else {
120 canctl1 = in_8(®s->canctl1);
121 if (canctl1 & (MSCAN_SLPAK | MSCAN_INITAK)) {
122 clrbits8(®s->canctl0, MSCAN_SLPRQ | MSCAN_INITRQ);
123 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
124 canctl1 = in_8(®s->canctl1);
125 if (!(canctl1 & (MSCAN_INITAK | MSCAN_SLPAK)))
126 break;
127 }
128 if (i >= MSCAN_SET_MODE_RETRIES)
129 ret = -ENODEV;
130 else
131 priv->can.state = CAN_STATE_ERROR_ACTIVE;
132 }
133 }
134 return ret;
135}
136
137static int mscan_start(struct net_device *dev)
138{
139 struct mscan_priv *priv = netdev_priv(dev);
140 struct mscan_regs __iomem *regs = priv->reg_base;
141 u8 canrflg;
142 int err;
143
144 out_8(®s->canrier, 0);
145
146 INIT_LIST_HEAD(&priv->tx_head);
147 priv->prev_buf_id = 0;
148 priv->cur_pri = 0;
149 priv->tx_active = 0;
150 priv->shadow_canrier = 0;
151 priv->flags = 0;
152
153 if (priv->type == MSCAN_TYPE_MPC5121) {
154 /* Clear pending bus-off condition */
155 if (in_8(®s->canmisc) & MSCAN_BOHOLD)
156 out_8(®s->canmisc, MSCAN_BOHOLD);
157 }
158
159 err = mscan_set_mode(dev, MSCAN_NORMAL_MODE);
160 if (err)
161 return err;
162
163 canrflg = in_8(®s->canrflg);
164 priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
165 priv->can.state = state_map[max(MSCAN_STATE_RX(canrflg),
166 MSCAN_STATE_TX(canrflg))];
167 out_8(®s->cantier, 0);
168
169 /* Enable receive interrupts. */
170 out_8(®s->canrier, MSCAN_RX_INTS_ENABLE);
171
172 return 0;
173}
174
175static int mscan_restart(struct net_device *dev)
176{
177 struct mscan_priv *priv = netdev_priv(dev);
178
179 if (priv->type == MSCAN_TYPE_MPC5121) {
180 struct mscan_regs __iomem *regs = priv->reg_base;
181
182 priv->can.state = CAN_STATE_ERROR_ACTIVE;
183 WARN(!(in_8(®s->canmisc) & MSCAN_BOHOLD),
184 "bus-off state expected\n");
185 out_8(®s->canmisc, MSCAN_BOHOLD);
186 /* Re-enable receive interrupts. */
187 out_8(®s->canrier, MSCAN_RX_INTS_ENABLE);
188 } else {
189 if (priv->can.state <= CAN_STATE_BUS_OFF)
190 mscan_set_mode(dev, MSCAN_INIT_MODE);
191 return mscan_start(dev);
192 }
193
194 return 0;
195}
196
197static netdev_tx_t mscan_start_xmit(struct sk_buff *skb, struct net_device *dev)
198{
199 struct can_frame *frame = (struct can_frame *)skb->data;
200 struct mscan_priv *priv = netdev_priv(dev);
201 struct mscan_regs __iomem *regs = priv->reg_base;
202 int i, rtr, buf_id;
203 u32 can_id;
204
205 if (can_dropped_invalid_skb(dev, skb))
206 return NETDEV_TX_OK;
207
208 out_8(®s->cantier, 0);
209
210 i = ~priv->tx_active & MSCAN_TXE;
211 buf_id = ffs(i) - 1;
212 switch (hweight8(i)) {
213 case 0:
214 netif_stop_queue(dev);
215 netdev_err(dev, "Tx Ring full when queue awake!\n");
216 return NETDEV_TX_BUSY;
217 case 1:
218 /*
219 * if buf_id < 3, then current frame will be send out of order,
220 * since buffer with lower id have higher priority (hell..)
221 */
222 netif_stop_queue(dev);
223 case 2:
224 if (buf_id < priv->prev_buf_id) {
225 priv->cur_pri++;
226 if (priv->cur_pri == 0xff) {
227 set_bit(F_TX_WAIT_ALL, &priv->flags);
228 netif_stop_queue(dev);
229 }
230 }
231 set_bit(F_TX_PROGRESS, &priv->flags);
232 break;
233 }
234 priv->prev_buf_id = buf_id;
235 out_8(®s->cantbsel, i);
236
237 rtr = frame->can_id & CAN_RTR_FLAG;
238
239 /* RTR is always the lowest bit of interest, then IDs follow */
240 if (frame->can_id & CAN_EFF_FLAG) {
241 can_id = (frame->can_id & CAN_EFF_MASK)
242 << (MSCAN_EFF_RTR_SHIFT + 1);
243 if (rtr)
244 can_id |= 1 << MSCAN_EFF_RTR_SHIFT;
245 out_be16(®s->tx.idr3_2, can_id);
246
247 can_id >>= 16;
248 /* EFF_FLAGS are between the IDs :( */
249 can_id = (can_id & 0x7) | ((can_id << 2) & 0xffe0)
250 | MSCAN_EFF_FLAGS;
251 } else {
252 can_id = (frame->can_id & CAN_SFF_MASK)
253 << (MSCAN_SFF_RTR_SHIFT + 1);
254 if (rtr)
255 can_id |= 1 << MSCAN_SFF_RTR_SHIFT;
256 }
257 out_be16(®s->tx.idr1_0, can_id);
258
259 if (!rtr) {
260 void __iomem *data = ®s->tx.dsr1_0;
261 u16 *payload = (u16 *)frame->data;
262
263 for (i = 0; i < frame->can_dlc / 2; i++) {
264 out_be16(data, *payload++);
265 data += 2 + _MSCAN_RESERVED_DSR_SIZE;
266 }
267 /* write remaining byte if necessary */
268 if (frame->can_dlc & 1)
269 out_8(data, frame->data[frame->can_dlc - 1]);
270 }
271
272 out_8(®s->tx.dlr, frame->can_dlc);
273 out_8(®s->tx.tbpr, priv->cur_pri);
274
275 /* Start transmission. */
276 out_8(®s->cantflg, 1 << buf_id);
277
278 if (!test_bit(F_TX_PROGRESS, &priv->flags))
279 dev->trans_start = jiffies;
280
281 list_add_tail(&priv->tx_queue[buf_id].list, &priv->tx_head);
282
283 can_put_echo_skb(skb, dev, buf_id);
284
285 /* Enable interrupt. */
286 priv->tx_active |= 1 << buf_id;
287 out_8(®s->cantier, priv->tx_active);
288
289 return NETDEV_TX_OK;
290}
291
292/* This function returns the old state to see where we came from */
293static enum can_state check_set_state(struct net_device *dev, u8 canrflg)
294{
295 struct mscan_priv *priv = netdev_priv(dev);
296 enum can_state state, old_state = priv->can.state;
297
298 if (canrflg & MSCAN_CSCIF && old_state <= CAN_STATE_BUS_OFF) {
299 state = state_map[max(MSCAN_STATE_RX(canrflg),
300 MSCAN_STATE_TX(canrflg))];
301 priv->can.state = state;
302 }
303 return old_state;
304}
305
306static void mscan_get_rx_frame(struct net_device *dev, struct can_frame *frame)
307{
308 struct mscan_priv *priv = netdev_priv(dev);
309 struct mscan_regs __iomem *regs = priv->reg_base;
310 u32 can_id;
311 int i;
312
313 can_id = in_be16(®s->rx.idr1_0);
314 if (can_id & (1 << 3)) {
315 frame->can_id = CAN_EFF_FLAG;
316 can_id = ((can_id << 16) | in_be16(®s->rx.idr3_2));
317 can_id = ((can_id & 0xffe00000) |
318 ((can_id & 0x7ffff) << 2)) >> 2;
319 } else {
320 can_id >>= 4;
321 frame->can_id = 0;
322 }
323
324 frame->can_id |= can_id >> 1;
325 if (can_id & 1)
326 frame->can_id |= CAN_RTR_FLAG;
327
328 frame->can_dlc = get_can_dlc(in_8(®s->rx.dlr) & 0xf);
329
330 if (!(frame->can_id & CAN_RTR_FLAG)) {
331 void __iomem *data = ®s->rx.dsr1_0;
332 u16 *payload = (u16 *)frame->data;
333
334 for (i = 0; i < frame->can_dlc / 2; i++) {
335 *payload++ = in_be16(data);
336 data += 2 + _MSCAN_RESERVED_DSR_SIZE;
337 }
338 /* read remaining byte if necessary */
339 if (frame->can_dlc & 1)
340 frame->data[frame->can_dlc - 1] = in_8(data);
341 }
342
343 out_8(®s->canrflg, MSCAN_RXF);
344}
345
346static void mscan_get_err_frame(struct net_device *dev, struct can_frame *frame,
347 u8 canrflg)
348{
349 struct mscan_priv *priv = netdev_priv(dev);
350 struct mscan_regs __iomem *regs = priv->reg_base;
351 struct net_device_stats *stats = &dev->stats;
352 enum can_state old_state;
353
354 netdev_dbg(dev, "error interrupt (canrflg=%#x)\n", canrflg);
355 frame->can_id = CAN_ERR_FLAG;
356
357 if (canrflg & MSCAN_OVRIF) {
358 frame->can_id |= CAN_ERR_CRTL;
359 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
360 stats->rx_over_errors++;
361 stats->rx_errors++;
362 } else {
363 frame->data[1] = 0;
364 }
365
366 old_state = check_set_state(dev, canrflg);
367 /* State changed */
368 if (old_state != priv->can.state) {
369 switch (priv->can.state) {
370 case CAN_STATE_ERROR_WARNING:
371 frame->can_id |= CAN_ERR_CRTL;
372 priv->can.can_stats.error_warning++;
373 if ((priv->shadow_statflg & MSCAN_RSTAT_MSK) <
374 (canrflg & MSCAN_RSTAT_MSK))
375 frame->data[1] |= CAN_ERR_CRTL_RX_WARNING;
376 if ((priv->shadow_statflg & MSCAN_TSTAT_MSK) <
377 (canrflg & MSCAN_TSTAT_MSK))
378 frame->data[1] |= CAN_ERR_CRTL_TX_WARNING;
379 break;
380 case CAN_STATE_ERROR_PASSIVE:
381 frame->can_id |= CAN_ERR_CRTL;
382 priv->can.can_stats.error_passive++;
383 frame->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
384 break;
385 case CAN_STATE_BUS_OFF:
386 frame->can_id |= CAN_ERR_BUSOFF;
387 /*
388 * The MSCAN on the MPC5200 does recover from bus-off
389 * automatically. To avoid that we stop the chip doing
390 * a light-weight stop (we are in irq-context).
391 */
392 if (priv->type != MSCAN_TYPE_MPC5121) {
393 out_8(®s->cantier, 0);
394 out_8(®s->canrier, 0);
395 setbits8(®s->canctl0,
396 MSCAN_SLPRQ | MSCAN_INITRQ);
397 }
398 can_bus_off(dev);
399 break;
400 default:
401 break;
402 }
403 }
404 priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
405 frame->can_dlc = CAN_ERR_DLC;
406 out_8(®s->canrflg, MSCAN_ERR_IF);
407}
408
409static int mscan_rx_poll(struct napi_struct *napi, int quota)
410{
411 struct mscan_priv *priv = container_of(napi, struct mscan_priv, napi);
412 struct net_device *dev = napi->dev;
413 struct mscan_regs __iomem *regs = priv->reg_base;
414 struct net_device_stats *stats = &dev->stats;
415 int npackets = 0;
416 int ret = 1;
417 struct sk_buff *skb;
418 struct can_frame *frame;
419 u8 canrflg;
420
421 while (npackets < quota) {
422 canrflg = in_8(®s->canrflg);
423 if (!(canrflg & (MSCAN_RXF | MSCAN_ERR_IF)))
424 break;
425
426 skb = alloc_can_skb(dev, &frame);
427 if (!skb) {
428 if (printk_ratelimit())
429 netdev_notice(dev, "packet dropped\n");
430 stats->rx_dropped++;
431 out_8(®s->canrflg, canrflg);
432 continue;
433 }
434
435 if (canrflg & MSCAN_RXF)
436 mscan_get_rx_frame(dev, frame);
437 else if (canrflg & MSCAN_ERR_IF)
438 mscan_get_err_frame(dev, frame, canrflg);
439
440 stats->rx_packets++;
441 stats->rx_bytes += frame->can_dlc;
442 npackets++;
443 netif_receive_skb(skb);
444 }
445
446 if (!(in_8(®s->canrflg) & (MSCAN_RXF | MSCAN_ERR_IF))) {
447 napi_complete(&priv->napi);
448 clear_bit(F_RX_PROGRESS, &priv->flags);
449 if (priv->can.state < CAN_STATE_BUS_OFF)
450 out_8(®s->canrier, priv->shadow_canrier);
451 ret = 0;
452 }
453 return ret;
454}
455
456static irqreturn_t mscan_isr(int irq, void *dev_id)
457{
458 struct net_device *dev = (struct net_device *)dev_id;
459 struct mscan_priv *priv = netdev_priv(dev);
460 struct mscan_regs __iomem *regs = priv->reg_base;
461 struct net_device_stats *stats = &dev->stats;
462 u8 cantier, cantflg, canrflg;
463 irqreturn_t ret = IRQ_NONE;
464
465 cantier = in_8(®s->cantier) & MSCAN_TXE;
466 cantflg = in_8(®s->cantflg) & cantier;
467
468 if (cantier && cantflg) {
469 struct list_head *tmp, *pos;
470
471 list_for_each_safe(pos, tmp, &priv->tx_head) {
472 struct tx_queue_entry *entry =
473 list_entry(pos, struct tx_queue_entry, list);
474 u8 mask = entry->mask;
475
476 if (!(cantflg & mask))
477 continue;
478
479 out_8(®s->cantbsel, mask);
480 stats->tx_bytes += in_8(®s->tx.dlr);
481 stats->tx_packets++;
482 can_get_echo_skb(dev, entry->id);
483 priv->tx_active &= ~mask;
484 list_del(pos);
485 }
486
487 if (list_empty(&priv->tx_head)) {
488 clear_bit(F_TX_WAIT_ALL, &priv->flags);
489 clear_bit(F_TX_PROGRESS, &priv->flags);
490 priv->cur_pri = 0;
491 } else {
492 dev->trans_start = jiffies;
493 }
494
495 if (!test_bit(F_TX_WAIT_ALL, &priv->flags))
496 netif_wake_queue(dev);
497
498 out_8(®s->cantier, priv->tx_active);
499 ret = IRQ_HANDLED;
500 }
501
502 canrflg = in_8(®s->canrflg);
503 if ((canrflg & ~MSCAN_STAT_MSK) &&
504 !test_and_set_bit(F_RX_PROGRESS, &priv->flags)) {
505 if (canrflg & ~MSCAN_STAT_MSK) {
506 priv->shadow_canrier = in_8(®s->canrier);
507 out_8(®s->canrier, 0);
508 napi_schedule(&priv->napi);
509 ret = IRQ_HANDLED;
510 } else {
511 clear_bit(F_RX_PROGRESS, &priv->flags);
512 }
513 }
514 return ret;
515}
516
517static int mscan_do_set_mode(struct net_device *dev, enum can_mode mode)
518{
519 int ret = 0;
520
521 switch (mode) {
522 case CAN_MODE_START:
523 ret = mscan_restart(dev);
524 if (ret)
525 break;
526 if (netif_queue_stopped(dev))
527 netif_wake_queue(dev);
528 break;
529
530 default:
531 ret = -EOPNOTSUPP;
532 break;
533 }
534 return ret;
535}
536
537static int mscan_do_set_bittiming(struct net_device *dev)
538{
539 struct mscan_priv *priv = netdev_priv(dev);
540 struct mscan_regs __iomem *regs = priv->reg_base;
541 struct can_bittiming *bt = &priv->can.bittiming;
542 u8 btr0, btr1;
543
544 btr0 = BTR0_SET_BRP(bt->brp) | BTR0_SET_SJW(bt->sjw);
545 btr1 = (BTR1_SET_TSEG1(bt->prop_seg + bt->phase_seg1) |
546 BTR1_SET_TSEG2(bt->phase_seg2) |
547 BTR1_SET_SAM(priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES));
548
549 netdev_info(dev, "setting BTR0=0x%02x BTR1=0x%02x\n", btr0, btr1);
550
551 out_8(®s->canbtr0, btr0);
552 out_8(®s->canbtr1, btr1);
553
554 return 0;
555}
556
557static int mscan_get_berr_counter(const struct net_device *dev,
558 struct can_berr_counter *bec)
559{
560 struct mscan_priv *priv = netdev_priv(dev);
561 struct mscan_regs __iomem *regs = priv->reg_base;
562
563 bec->txerr = in_8(®s->cantxerr);
564 bec->rxerr = in_8(®s->canrxerr);
565
566 return 0;
567}
568
569static int mscan_open(struct net_device *dev)
570{
571 int ret;
572 struct mscan_priv *priv = netdev_priv(dev);
573 struct mscan_regs __iomem *regs = priv->reg_base;
574
575 if (priv->clk_ipg) {
576 ret = clk_prepare_enable(priv->clk_ipg);
577 if (ret)
578 goto exit_retcode;
579 }
580 if (priv->clk_can) {
581 ret = clk_prepare_enable(priv->clk_can);
582 if (ret)
583 goto exit_dis_ipg_clock;
584 }
585
586 /* common open */
587 ret = open_candev(dev);
588 if (ret)
589 goto exit_dis_can_clock;
590
591 napi_enable(&priv->napi);
592
593 ret = request_irq(dev->irq, mscan_isr, 0, dev->name, dev);
594 if (ret < 0) {
595 netdev_err(dev, "failed to attach interrupt\n");
596 goto exit_napi_disable;
597 }
598
599 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
600 setbits8(®s->canctl1, MSCAN_LISTEN);
601 else
602 clrbits8(®s->canctl1, MSCAN_LISTEN);
603
604 ret = mscan_start(dev);
605 if (ret)
606 goto exit_free_irq;
607
608 netif_start_queue(dev);
609
610 return 0;
611
612exit_free_irq:
613 free_irq(dev->irq, dev);
614exit_napi_disable:
615 napi_disable(&priv->napi);
616 close_candev(dev);
617exit_dis_can_clock:
618 if (priv->clk_can)
619 clk_disable_unprepare(priv->clk_can);
620exit_dis_ipg_clock:
621 if (priv->clk_ipg)
622 clk_disable_unprepare(priv->clk_ipg);
623exit_retcode:
624 return ret;
625}
626
627static int mscan_close(struct net_device *dev)
628{
629 struct mscan_priv *priv = netdev_priv(dev);
630 struct mscan_regs __iomem *regs = priv->reg_base;
631
632 netif_stop_queue(dev);
633 napi_disable(&priv->napi);
634
635 out_8(®s->cantier, 0);
636 out_8(®s->canrier, 0);
637 mscan_set_mode(dev, MSCAN_INIT_MODE);
638 close_candev(dev);
639 free_irq(dev->irq, dev);
640
641 if (priv->clk_can)
642 clk_disable_unprepare(priv->clk_can);
643 if (priv->clk_ipg)
644 clk_disable_unprepare(priv->clk_ipg);
645
646 return 0;
647}
648
649static const struct net_device_ops mscan_netdev_ops = {
650 .ndo_open = mscan_open,
651 .ndo_stop = mscan_close,
652 .ndo_start_xmit = mscan_start_xmit,
653 .ndo_change_mtu = can_change_mtu,
654};
655
656int register_mscandev(struct net_device *dev, int mscan_clksrc)
657{
658 struct mscan_priv *priv = netdev_priv(dev);
659 struct mscan_regs __iomem *regs = priv->reg_base;
660 u8 ctl1;
661
662 ctl1 = in_8(®s->canctl1);
663 if (mscan_clksrc)
664 ctl1 |= MSCAN_CLKSRC;
665 else
666 ctl1 &= ~MSCAN_CLKSRC;
667
668 if (priv->type == MSCAN_TYPE_MPC5121) {
669 priv->can.do_get_berr_counter = mscan_get_berr_counter;
670 ctl1 |= MSCAN_BORM; /* bus-off recovery upon request */
671 }
672
673 ctl1 |= MSCAN_CANE;
674 out_8(®s->canctl1, ctl1);
675 udelay(100);
676
677 /* acceptance mask/acceptance code (accept everything) */
678 out_be16(®s->canidar1_0, 0);
679 out_be16(®s->canidar3_2, 0);
680 out_be16(®s->canidar5_4, 0);
681 out_be16(®s->canidar7_6, 0);
682
683 out_be16(®s->canidmr1_0, 0xffff);
684 out_be16(®s->canidmr3_2, 0xffff);
685 out_be16(®s->canidmr5_4, 0xffff);
686 out_be16(®s->canidmr7_6, 0xffff);
687 /* Two 32 bit Acceptance Filters */
688 out_8(®s->canidac, MSCAN_AF_32BIT);
689
690 mscan_set_mode(dev, MSCAN_INIT_MODE);
691
692 return register_candev(dev);
693}
694
695void unregister_mscandev(struct net_device *dev)
696{
697 struct mscan_priv *priv = netdev_priv(dev);
698 struct mscan_regs __iomem *regs = priv->reg_base;
699 mscan_set_mode(dev, MSCAN_INIT_MODE);
700 clrbits8(®s->canctl1, MSCAN_CANE);
701 unregister_candev(dev);
702}
703
704struct net_device *alloc_mscandev(void)
705{
706 struct net_device *dev;
707 struct mscan_priv *priv;
708 int i;
709
710 dev = alloc_candev(sizeof(struct mscan_priv), MSCAN_ECHO_SKB_MAX);
711 if (!dev)
712 return NULL;
713 priv = netdev_priv(dev);
714
715 dev->netdev_ops = &mscan_netdev_ops;
716
717 dev->flags |= IFF_ECHO; /* we support local echo */
718
719 netif_napi_add(dev, &priv->napi, mscan_rx_poll, 8);
720
721 priv->can.bittiming_const = &mscan_bittiming_const;
722 priv->can.do_set_bittiming = mscan_do_set_bittiming;
723 priv->can.do_set_mode = mscan_do_set_mode;
724 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
725 CAN_CTRLMODE_LISTENONLY;
726
727 for (i = 0; i < TX_QUEUE_SIZE; i++) {
728 priv->tx_queue[i].id = i;
729 priv->tx_queue[i].mask = 1 << i;
730 }
731
732 return dev;
733}
734
735MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>");
736MODULE_LICENSE("GPL v2");
737MODULE_DESCRIPTION("CAN port driver for a MSCAN based chips");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * CAN bus driver for the alone generic (as possible as) MSCAN controller.
4 *
5 * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
6 * Varma Electronics Oy
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
8 * Copyright (C) 2008-2009 Pengutronix <kernel@pengutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/interrupt.h>
14#include <linux/delay.h>
15#include <linux/netdevice.h>
16#include <linux/if_arp.h>
17#include <linux/if_ether.h>
18#include <linux/list.h>
19#include <linux/can/dev.h>
20#include <linux/can/error.h>
21#include <linux/io.h>
22
23#include "mscan.h"
24
25static const struct can_bittiming_const mscan_bittiming_const = {
26 .name = "mscan",
27 .tseg1_min = 4,
28 .tseg1_max = 16,
29 .tseg2_min = 2,
30 .tseg2_max = 8,
31 .sjw_max = 4,
32 .brp_min = 1,
33 .brp_max = 64,
34 .brp_inc = 1,
35};
36
37struct mscan_state {
38 u8 mode;
39 u8 canrier;
40 u8 cantier;
41};
42
43static enum can_state state_map[] = {
44 CAN_STATE_ERROR_ACTIVE,
45 CAN_STATE_ERROR_WARNING,
46 CAN_STATE_ERROR_PASSIVE,
47 CAN_STATE_BUS_OFF
48};
49
50static int mscan_set_mode(struct net_device *dev, u8 mode)
51{
52 struct mscan_priv *priv = netdev_priv(dev);
53 struct mscan_regs __iomem *regs = priv->reg_base;
54 int ret = 0;
55 int i;
56 u8 canctl1;
57
58 if (mode != MSCAN_NORMAL_MODE) {
59 if (priv->tx_active) {
60 /* Abort transfers before going to sleep */#
61 out_8(®s->cantarq, priv->tx_active);
62 /* Suppress TX done interrupts */
63 out_8(®s->cantier, 0);
64 }
65
66 canctl1 = in_8(®s->canctl1);
67 if ((mode & MSCAN_SLPRQ) && !(canctl1 & MSCAN_SLPAK)) {
68 setbits8(®s->canctl0, MSCAN_SLPRQ);
69 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
70 if (in_8(®s->canctl1) & MSCAN_SLPAK)
71 break;
72 udelay(100);
73 }
74 /*
75 * The mscan controller will fail to enter sleep mode,
76 * while there are irregular activities on bus, like
77 * somebody keeps retransmitting. This behavior is
78 * undocumented and seems to differ between mscan built
79 * in mpc5200b and mpc5200. We proceed in that case,
80 * since otherwise the slprq will be kept set and the
81 * controller will get stuck. NOTE: INITRQ or CSWAI
82 * will abort all active transmit actions, if still
83 * any, at once.
84 */
85 if (i >= MSCAN_SET_MODE_RETRIES)
86 netdev_dbg(dev,
87 "device failed to enter sleep mode. "
88 "We proceed anyhow.\n");
89 else
90 priv->can.state = CAN_STATE_SLEEPING;
91 }
92
93 if ((mode & MSCAN_INITRQ) && !(canctl1 & MSCAN_INITAK)) {
94 setbits8(®s->canctl0, MSCAN_INITRQ);
95 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
96 if (in_8(®s->canctl1) & MSCAN_INITAK)
97 break;
98 }
99 if (i >= MSCAN_SET_MODE_RETRIES)
100 ret = -ENODEV;
101 }
102 if (!ret)
103 priv->can.state = CAN_STATE_STOPPED;
104
105 if (mode & MSCAN_CSWAI)
106 setbits8(®s->canctl0, MSCAN_CSWAI);
107
108 } else {
109 canctl1 = in_8(®s->canctl1);
110 if (canctl1 & (MSCAN_SLPAK | MSCAN_INITAK)) {
111 clrbits8(®s->canctl0, MSCAN_SLPRQ | MSCAN_INITRQ);
112 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
113 canctl1 = in_8(®s->canctl1);
114 if (!(canctl1 & (MSCAN_INITAK | MSCAN_SLPAK)))
115 break;
116 }
117 if (i >= MSCAN_SET_MODE_RETRIES)
118 ret = -ENODEV;
119 else
120 priv->can.state = CAN_STATE_ERROR_ACTIVE;
121 }
122 }
123 return ret;
124}
125
126static int mscan_start(struct net_device *dev)
127{
128 struct mscan_priv *priv = netdev_priv(dev);
129 struct mscan_regs __iomem *regs = priv->reg_base;
130 u8 canrflg;
131 int err;
132
133 out_8(®s->canrier, 0);
134
135 INIT_LIST_HEAD(&priv->tx_head);
136 priv->prev_buf_id = 0;
137 priv->cur_pri = 0;
138 priv->tx_active = 0;
139 priv->shadow_canrier = 0;
140 priv->flags = 0;
141
142 if (priv->type == MSCAN_TYPE_MPC5121) {
143 /* Clear pending bus-off condition */
144 if (in_8(®s->canmisc) & MSCAN_BOHOLD)
145 out_8(®s->canmisc, MSCAN_BOHOLD);
146 }
147
148 err = mscan_set_mode(dev, MSCAN_NORMAL_MODE);
149 if (err)
150 return err;
151
152 canrflg = in_8(®s->canrflg);
153 priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
154 priv->can.state = state_map[max(MSCAN_STATE_RX(canrflg),
155 MSCAN_STATE_TX(canrflg))];
156 out_8(®s->cantier, 0);
157
158 /* Enable receive interrupts. */
159 out_8(®s->canrier, MSCAN_RX_INTS_ENABLE);
160
161 return 0;
162}
163
164static int mscan_restart(struct net_device *dev)
165{
166 struct mscan_priv *priv = netdev_priv(dev);
167
168 if (priv->type == MSCAN_TYPE_MPC5121) {
169 struct mscan_regs __iomem *regs = priv->reg_base;
170
171 priv->can.state = CAN_STATE_ERROR_ACTIVE;
172 WARN(!(in_8(®s->canmisc) & MSCAN_BOHOLD),
173 "bus-off state expected\n");
174 out_8(®s->canmisc, MSCAN_BOHOLD);
175 /* Re-enable receive interrupts. */
176 out_8(®s->canrier, MSCAN_RX_INTS_ENABLE);
177 } else {
178 if (priv->can.state <= CAN_STATE_BUS_OFF)
179 mscan_set_mode(dev, MSCAN_INIT_MODE);
180 return mscan_start(dev);
181 }
182
183 return 0;
184}
185
186static netdev_tx_t mscan_start_xmit(struct sk_buff *skb, struct net_device *dev)
187{
188 struct can_frame *frame = (struct can_frame *)skb->data;
189 struct mscan_priv *priv = netdev_priv(dev);
190 struct mscan_regs __iomem *regs = priv->reg_base;
191 int i, rtr, buf_id;
192 u32 can_id;
193
194 if (can_dropped_invalid_skb(dev, skb))
195 return NETDEV_TX_OK;
196
197 out_8(®s->cantier, 0);
198
199 i = ~priv->tx_active & MSCAN_TXE;
200 buf_id = ffs(i) - 1;
201 switch (hweight8(i)) {
202 case 0:
203 netif_stop_queue(dev);
204 netdev_err(dev, "Tx Ring full when queue awake!\n");
205 return NETDEV_TX_BUSY;
206 case 1:
207 /*
208 * if buf_id < 3, then current frame will be send out of order,
209 * since buffer with lower id have higher priority (hell..)
210 */
211 netif_stop_queue(dev);
212 case 2:
213 if (buf_id < priv->prev_buf_id) {
214 priv->cur_pri++;
215 if (priv->cur_pri == 0xff) {
216 set_bit(F_TX_WAIT_ALL, &priv->flags);
217 netif_stop_queue(dev);
218 }
219 }
220 set_bit(F_TX_PROGRESS, &priv->flags);
221 break;
222 }
223 priv->prev_buf_id = buf_id;
224 out_8(®s->cantbsel, i);
225
226 rtr = frame->can_id & CAN_RTR_FLAG;
227
228 /* RTR is always the lowest bit of interest, then IDs follow */
229 if (frame->can_id & CAN_EFF_FLAG) {
230 can_id = (frame->can_id & CAN_EFF_MASK)
231 << (MSCAN_EFF_RTR_SHIFT + 1);
232 if (rtr)
233 can_id |= 1 << MSCAN_EFF_RTR_SHIFT;
234 out_be16(®s->tx.idr3_2, can_id);
235
236 can_id >>= 16;
237 /* EFF_FLAGS are between the IDs :( */
238 can_id = (can_id & 0x7) | ((can_id << 2) & 0xffe0)
239 | MSCAN_EFF_FLAGS;
240 } else {
241 can_id = (frame->can_id & CAN_SFF_MASK)
242 << (MSCAN_SFF_RTR_SHIFT + 1);
243 if (rtr)
244 can_id |= 1 << MSCAN_SFF_RTR_SHIFT;
245 }
246 out_be16(®s->tx.idr1_0, can_id);
247
248 if (!rtr) {
249 void __iomem *data = ®s->tx.dsr1_0;
250 u16 *payload = (u16 *)frame->data;
251
252 for (i = 0; i < frame->can_dlc / 2; i++) {
253 out_be16(data, *payload++);
254 data += 2 + _MSCAN_RESERVED_DSR_SIZE;
255 }
256 /* write remaining byte if necessary */
257 if (frame->can_dlc & 1)
258 out_8(data, frame->data[frame->can_dlc - 1]);
259 }
260
261 out_8(®s->tx.dlr, frame->can_dlc);
262 out_8(®s->tx.tbpr, priv->cur_pri);
263
264 /* Start transmission. */
265 out_8(®s->cantflg, 1 << buf_id);
266
267 if (!test_bit(F_TX_PROGRESS, &priv->flags))
268 netif_trans_update(dev);
269
270 list_add_tail(&priv->tx_queue[buf_id].list, &priv->tx_head);
271
272 can_put_echo_skb(skb, dev, buf_id);
273
274 /* Enable interrupt. */
275 priv->tx_active |= 1 << buf_id;
276 out_8(®s->cantier, priv->tx_active);
277
278 return NETDEV_TX_OK;
279}
280
281static enum can_state get_new_state(struct net_device *dev, u8 canrflg)
282{
283 struct mscan_priv *priv = netdev_priv(dev);
284
285 if (unlikely(canrflg & MSCAN_CSCIF))
286 return state_map[max(MSCAN_STATE_RX(canrflg),
287 MSCAN_STATE_TX(canrflg))];
288
289 return priv->can.state;
290}
291
292static void mscan_get_rx_frame(struct net_device *dev, struct can_frame *frame)
293{
294 struct mscan_priv *priv = netdev_priv(dev);
295 struct mscan_regs __iomem *regs = priv->reg_base;
296 u32 can_id;
297 int i;
298
299 can_id = in_be16(®s->rx.idr1_0);
300 if (can_id & (1 << 3)) {
301 frame->can_id = CAN_EFF_FLAG;
302 can_id = ((can_id << 16) | in_be16(®s->rx.idr3_2));
303 can_id = ((can_id & 0xffe00000) |
304 ((can_id & 0x7ffff) << 2)) >> 2;
305 } else {
306 can_id >>= 4;
307 frame->can_id = 0;
308 }
309
310 frame->can_id |= can_id >> 1;
311 if (can_id & 1)
312 frame->can_id |= CAN_RTR_FLAG;
313
314 frame->can_dlc = get_can_dlc(in_8(®s->rx.dlr) & 0xf);
315
316 if (!(frame->can_id & CAN_RTR_FLAG)) {
317 void __iomem *data = ®s->rx.dsr1_0;
318 u16 *payload = (u16 *)frame->data;
319
320 for (i = 0; i < frame->can_dlc / 2; i++) {
321 *payload++ = in_be16(data);
322 data += 2 + _MSCAN_RESERVED_DSR_SIZE;
323 }
324 /* read remaining byte if necessary */
325 if (frame->can_dlc & 1)
326 frame->data[frame->can_dlc - 1] = in_8(data);
327 }
328
329 out_8(®s->canrflg, MSCAN_RXF);
330}
331
332static void mscan_get_err_frame(struct net_device *dev, struct can_frame *frame,
333 u8 canrflg)
334{
335 struct mscan_priv *priv = netdev_priv(dev);
336 struct mscan_regs __iomem *regs = priv->reg_base;
337 struct net_device_stats *stats = &dev->stats;
338 enum can_state new_state;
339
340 netdev_dbg(dev, "error interrupt (canrflg=%#x)\n", canrflg);
341 frame->can_id = CAN_ERR_FLAG;
342
343 if (canrflg & MSCAN_OVRIF) {
344 frame->can_id |= CAN_ERR_CRTL;
345 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
346 stats->rx_over_errors++;
347 stats->rx_errors++;
348 } else {
349 frame->data[1] = 0;
350 }
351
352 new_state = get_new_state(dev, canrflg);
353 if (new_state != priv->can.state) {
354 can_change_state(dev, frame,
355 state_map[MSCAN_STATE_TX(canrflg)],
356 state_map[MSCAN_STATE_RX(canrflg)]);
357
358 if (priv->can.state == CAN_STATE_BUS_OFF) {
359 /*
360 * The MSCAN on the MPC5200 does recover from bus-off
361 * automatically. To avoid that we stop the chip doing
362 * a light-weight stop (we are in irq-context).
363 */
364 if (priv->type != MSCAN_TYPE_MPC5121) {
365 out_8(®s->cantier, 0);
366 out_8(®s->canrier, 0);
367 setbits8(®s->canctl0,
368 MSCAN_SLPRQ | MSCAN_INITRQ);
369 }
370 can_bus_off(dev);
371 }
372 }
373 priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
374 frame->can_dlc = CAN_ERR_DLC;
375 out_8(®s->canrflg, MSCAN_ERR_IF);
376}
377
378static int mscan_rx_poll(struct napi_struct *napi, int quota)
379{
380 struct mscan_priv *priv = container_of(napi, struct mscan_priv, napi);
381 struct net_device *dev = napi->dev;
382 struct mscan_regs __iomem *regs = priv->reg_base;
383 struct net_device_stats *stats = &dev->stats;
384 int npackets = 0;
385 int ret = 1;
386 struct sk_buff *skb;
387 struct can_frame *frame;
388 u8 canrflg;
389
390 while (npackets < quota) {
391 canrflg = in_8(®s->canrflg);
392 if (!(canrflg & (MSCAN_RXF | MSCAN_ERR_IF)))
393 break;
394
395 skb = alloc_can_skb(dev, &frame);
396 if (!skb) {
397 if (printk_ratelimit())
398 netdev_notice(dev, "packet dropped\n");
399 stats->rx_dropped++;
400 out_8(®s->canrflg, canrflg);
401 continue;
402 }
403
404 if (canrflg & MSCAN_RXF)
405 mscan_get_rx_frame(dev, frame);
406 else if (canrflg & MSCAN_ERR_IF)
407 mscan_get_err_frame(dev, frame, canrflg);
408
409 stats->rx_packets++;
410 stats->rx_bytes += frame->can_dlc;
411 npackets++;
412 netif_receive_skb(skb);
413 }
414
415 if (!(in_8(®s->canrflg) & (MSCAN_RXF | MSCAN_ERR_IF))) {
416 napi_complete(&priv->napi);
417 clear_bit(F_RX_PROGRESS, &priv->flags);
418 if (priv->can.state < CAN_STATE_BUS_OFF)
419 out_8(®s->canrier, priv->shadow_canrier);
420 ret = 0;
421 }
422 return ret;
423}
424
425static irqreturn_t mscan_isr(int irq, void *dev_id)
426{
427 struct net_device *dev = (struct net_device *)dev_id;
428 struct mscan_priv *priv = netdev_priv(dev);
429 struct mscan_regs __iomem *regs = priv->reg_base;
430 struct net_device_stats *stats = &dev->stats;
431 u8 cantier, cantflg, canrflg;
432 irqreturn_t ret = IRQ_NONE;
433
434 cantier = in_8(®s->cantier) & MSCAN_TXE;
435 cantflg = in_8(®s->cantflg) & cantier;
436
437 if (cantier && cantflg) {
438 struct list_head *tmp, *pos;
439
440 list_for_each_safe(pos, tmp, &priv->tx_head) {
441 struct tx_queue_entry *entry =
442 list_entry(pos, struct tx_queue_entry, list);
443 u8 mask = entry->mask;
444
445 if (!(cantflg & mask))
446 continue;
447
448 out_8(®s->cantbsel, mask);
449 stats->tx_bytes += in_8(®s->tx.dlr);
450 stats->tx_packets++;
451 can_get_echo_skb(dev, entry->id);
452 priv->tx_active &= ~mask;
453 list_del(pos);
454 }
455
456 if (list_empty(&priv->tx_head)) {
457 clear_bit(F_TX_WAIT_ALL, &priv->flags);
458 clear_bit(F_TX_PROGRESS, &priv->flags);
459 priv->cur_pri = 0;
460 } else {
461 netif_trans_update(dev);
462 }
463
464 if (!test_bit(F_TX_WAIT_ALL, &priv->flags))
465 netif_wake_queue(dev);
466
467 out_8(®s->cantier, priv->tx_active);
468 ret = IRQ_HANDLED;
469 }
470
471 canrflg = in_8(®s->canrflg);
472 if ((canrflg & ~MSCAN_STAT_MSK) &&
473 !test_and_set_bit(F_RX_PROGRESS, &priv->flags)) {
474 if (canrflg & ~MSCAN_STAT_MSK) {
475 priv->shadow_canrier = in_8(®s->canrier);
476 out_8(®s->canrier, 0);
477 napi_schedule(&priv->napi);
478 ret = IRQ_HANDLED;
479 } else {
480 clear_bit(F_RX_PROGRESS, &priv->flags);
481 }
482 }
483 return ret;
484}
485
486static int mscan_do_set_mode(struct net_device *dev, enum can_mode mode)
487{
488 int ret = 0;
489
490 switch (mode) {
491 case CAN_MODE_START:
492 ret = mscan_restart(dev);
493 if (ret)
494 break;
495 if (netif_queue_stopped(dev))
496 netif_wake_queue(dev);
497 break;
498
499 default:
500 ret = -EOPNOTSUPP;
501 break;
502 }
503 return ret;
504}
505
506static int mscan_do_set_bittiming(struct net_device *dev)
507{
508 struct mscan_priv *priv = netdev_priv(dev);
509 struct mscan_regs __iomem *regs = priv->reg_base;
510 struct can_bittiming *bt = &priv->can.bittiming;
511 u8 btr0, btr1;
512
513 btr0 = BTR0_SET_BRP(bt->brp) | BTR0_SET_SJW(bt->sjw);
514 btr1 = (BTR1_SET_TSEG1(bt->prop_seg + bt->phase_seg1) |
515 BTR1_SET_TSEG2(bt->phase_seg2) |
516 BTR1_SET_SAM(priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES));
517
518 netdev_info(dev, "setting BTR0=0x%02x BTR1=0x%02x\n", btr0, btr1);
519
520 out_8(®s->canbtr0, btr0);
521 out_8(®s->canbtr1, btr1);
522
523 return 0;
524}
525
526static int mscan_get_berr_counter(const struct net_device *dev,
527 struct can_berr_counter *bec)
528{
529 struct mscan_priv *priv = netdev_priv(dev);
530 struct mscan_regs __iomem *regs = priv->reg_base;
531
532 bec->txerr = in_8(®s->cantxerr);
533 bec->rxerr = in_8(®s->canrxerr);
534
535 return 0;
536}
537
538static int mscan_open(struct net_device *dev)
539{
540 int ret;
541 struct mscan_priv *priv = netdev_priv(dev);
542 struct mscan_regs __iomem *regs = priv->reg_base;
543
544 if (priv->clk_ipg) {
545 ret = clk_prepare_enable(priv->clk_ipg);
546 if (ret)
547 goto exit_retcode;
548 }
549 if (priv->clk_can) {
550 ret = clk_prepare_enable(priv->clk_can);
551 if (ret)
552 goto exit_dis_ipg_clock;
553 }
554
555 /* common open */
556 ret = open_candev(dev);
557 if (ret)
558 goto exit_dis_can_clock;
559
560 napi_enable(&priv->napi);
561
562 ret = request_irq(dev->irq, mscan_isr, 0, dev->name, dev);
563 if (ret < 0) {
564 netdev_err(dev, "failed to attach interrupt\n");
565 goto exit_napi_disable;
566 }
567
568 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
569 setbits8(®s->canctl1, MSCAN_LISTEN);
570 else
571 clrbits8(®s->canctl1, MSCAN_LISTEN);
572
573 ret = mscan_start(dev);
574 if (ret)
575 goto exit_free_irq;
576
577 netif_start_queue(dev);
578
579 return 0;
580
581exit_free_irq:
582 free_irq(dev->irq, dev);
583exit_napi_disable:
584 napi_disable(&priv->napi);
585 close_candev(dev);
586exit_dis_can_clock:
587 if (priv->clk_can)
588 clk_disable_unprepare(priv->clk_can);
589exit_dis_ipg_clock:
590 if (priv->clk_ipg)
591 clk_disable_unprepare(priv->clk_ipg);
592exit_retcode:
593 return ret;
594}
595
596static int mscan_close(struct net_device *dev)
597{
598 struct mscan_priv *priv = netdev_priv(dev);
599 struct mscan_regs __iomem *regs = priv->reg_base;
600
601 netif_stop_queue(dev);
602 napi_disable(&priv->napi);
603
604 out_8(®s->cantier, 0);
605 out_8(®s->canrier, 0);
606 mscan_set_mode(dev, MSCAN_INIT_MODE);
607 close_candev(dev);
608 free_irq(dev->irq, dev);
609
610 if (priv->clk_can)
611 clk_disable_unprepare(priv->clk_can);
612 if (priv->clk_ipg)
613 clk_disable_unprepare(priv->clk_ipg);
614
615 return 0;
616}
617
618static const struct net_device_ops mscan_netdev_ops = {
619 .ndo_open = mscan_open,
620 .ndo_stop = mscan_close,
621 .ndo_start_xmit = mscan_start_xmit,
622 .ndo_change_mtu = can_change_mtu,
623};
624
625int register_mscandev(struct net_device *dev, int mscan_clksrc)
626{
627 struct mscan_priv *priv = netdev_priv(dev);
628 struct mscan_regs __iomem *regs = priv->reg_base;
629 u8 ctl1;
630
631 ctl1 = in_8(®s->canctl1);
632 if (mscan_clksrc)
633 ctl1 |= MSCAN_CLKSRC;
634 else
635 ctl1 &= ~MSCAN_CLKSRC;
636
637 if (priv->type == MSCAN_TYPE_MPC5121) {
638 priv->can.do_get_berr_counter = mscan_get_berr_counter;
639 ctl1 |= MSCAN_BORM; /* bus-off recovery upon request */
640 }
641
642 ctl1 |= MSCAN_CANE;
643 out_8(®s->canctl1, ctl1);
644 udelay(100);
645
646 /* acceptance mask/acceptance code (accept everything) */
647 out_be16(®s->canidar1_0, 0);
648 out_be16(®s->canidar3_2, 0);
649 out_be16(®s->canidar5_4, 0);
650 out_be16(®s->canidar7_6, 0);
651
652 out_be16(®s->canidmr1_0, 0xffff);
653 out_be16(®s->canidmr3_2, 0xffff);
654 out_be16(®s->canidmr5_4, 0xffff);
655 out_be16(®s->canidmr7_6, 0xffff);
656 /* Two 32 bit Acceptance Filters */
657 out_8(®s->canidac, MSCAN_AF_32BIT);
658
659 mscan_set_mode(dev, MSCAN_INIT_MODE);
660
661 return register_candev(dev);
662}
663
664void unregister_mscandev(struct net_device *dev)
665{
666 struct mscan_priv *priv = netdev_priv(dev);
667 struct mscan_regs __iomem *regs = priv->reg_base;
668 mscan_set_mode(dev, MSCAN_INIT_MODE);
669 clrbits8(®s->canctl1, MSCAN_CANE);
670 unregister_candev(dev);
671}
672
673struct net_device *alloc_mscandev(void)
674{
675 struct net_device *dev;
676 struct mscan_priv *priv;
677 int i;
678
679 dev = alloc_candev(sizeof(struct mscan_priv), MSCAN_ECHO_SKB_MAX);
680 if (!dev)
681 return NULL;
682 priv = netdev_priv(dev);
683
684 dev->netdev_ops = &mscan_netdev_ops;
685
686 dev->flags |= IFF_ECHO; /* we support local echo */
687
688 netif_napi_add(dev, &priv->napi, mscan_rx_poll, 8);
689
690 priv->can.bittiming_const = &mscan_bittiming_const;
691 priv->can.do_set_bittiming = mscan_do_set_bittiming;
692 priv->can.do_set_mode = mscan_do_set_mode;
693 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
694 CAN_CTRLMODE_LISTENONLY;
695
696 for (i = 0; i < TX_QUEUE_SIZE; i++) {
697 priv->tx_queue[i].id = i;
698 priv->tx_queue[i].mask = 1 << i;
699 }
700
701 return dev;
702}
703
704MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>");
705MODULE_LICENSE("GPL v2");
706MODULE_DESCRIPTION("CAN port driver for a MSCAN based chips");