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1// SPDX-License-Identifier: GPL-2.0-or-later
2// Copyright IBM Corp
3// Copyright ASPEED Technology
4
5#define pr_fmt(fmt) "clk-ast2600: " fmt
6
7#include <linux/mfd/syscon.h>
8#include <linux/of_address.h>
9#include <linux/of_device.h>
10#include <linux/platform_device.h>
11#include <linux/regmap.h>
12#include <linux/slab.h>
13
14#include <dt-bindings/clock/ast2600-clock.h>
15
16#include "clk-aspeed.h"
17
18#define ASPEED_G6_NUM_CLKS 67
19
20#define ASPEED_G6_SILICON_REV 0x004
21
22#define ASPEED_G6_RESET_CTRL 0x040
23#define ASPEED_G6_RESET_CTRL2 0x050
24
25#define ASPEED_G6_CLK_STOP_CTRL 0x080
26#define ASPEED_G6_CLK_STOP_CTRL2 0x090
27
28#define ASPEED_G6_MISC_CTRL 0x0C0
29#define UART_DIV13_EN BIT(12)
30
31#define ASPEED_G6_CLK_SELECTION1 0x300
32#define ASPEED_G6_CLK_SELECTION2 0x304
33#define ASPEED_G6_CLK_SELECTION4 0x310
34
35#define ASPEED_HPLL_PARAM 0x200
36#define ASPEED_APLL_PARAM 0x210
37#define ASPEED_MPLL_PARAM 0x220
38#define ASPEED_EPLL_PARAM 0x240
39#define ASPEED_DPLL_PARAM 0x260
40
41#define ASPEED_G6_STRAP1 0x500
42
43/* Globally visible clocks */
44static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
45
46/* Keeps track of all clocks */
47static struct clk_hw_onecell_data *aspeed_g6_clk_data;
48
49static void __iomem *scu_g6_base;
50
51/*
52 * Clocks marked with CLK_IS_CRITICAL:
53 *
54 * ref0 and ref1 are essential for the SoC to operate
55 * mpll is required if SDRAM is used
56 */
57static const struct aspeed_gate_data aspeed_g6_gates[] = {
58 /* clk rst name parent flags */
59 [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
60 [ASPEED_CLK_GATE_ECLK] = { 1, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
61 [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
62 /* vclk parent - dclk/d1clk/hclk/mclk */
63 [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
64 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
65 /* From dpll */
66 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
67 [ASPEED_CLK_GATE_REF0CLK] = { 6, -1, "ref0clk-gate", "clkin", CLK_IS_CRITICAL },
68 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
69 /* Reserved 8 */
70 [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
71 /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
72 [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", "d1clk", 0 }, /* GFX CRT */
73 /* Reserved 11/12 */
74 [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
75 [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
76 [ASPEED_CLK_GATE_UART5CLK] = { 15, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
77 /* Reserved 16/19 */
78 [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac12", 0 }, /* MAC1 */
79 [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac12", 0 }, /* MAC2 */
80 /* Reserved 22/23 */
81 [ASPEED_CLK_GATE_RSACLK] = { 24, 4, "rsaclk-gate", NULL, 0 }, /* HAC */
82 [ASPEED_CLK_GATE_RVASCLK] = { 25, 9, "rvasclk-gate", NULL, 0 }, /* RVAS */
83 /* Reserved 26 */
84 [ASPEED_CLK_GATE_EMMCCLK] = { 27, 16, "emmcclk-gate", NULL, 0 }, /* For card clk */
85 /* Reserved 28/29/30 */
86 [ASPEED_CLK_GATE_LCLK] = { 32, 32, "lclk-gate", NULL, 0 }, /* LPC */
87 [ASPEED_CLK_GATE_ESPICLK] = { 33, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
88 [ASPEED_CLK_GATE_REF1CLK] = { 34, -1, "ref1clk-gate", "clkin", CLK_IS_CRITICAL },
89 /* Reserved 35 */
90 [ASPEED_CLK_GATE_SDCLK] = { 36, 56, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
91 [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
92 /* Reserved 38 RSA: no longer used */
93 /* Reserved 39 */
94 [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */
95 [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */
96 [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */
97 [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */
98 [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */
99 [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */
100 [ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */
101 [ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */
102 [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
103 [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
104 [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
105 [ASPEED_CLK_GATE_UART4CLK] = { 51, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
106 [ASPEED_CLK_GATE_MAC3CLK] = { 52, 52, "mac3clk-gate", "mac34", 0 }, /* MAC3 */
107 [ASPEED_CLK_GATE_MAC4CLK] = { 53, 53, "mac4clk-gate", "mac34", 0 }, /* MAC4 */
108 [ASPEED_CLK_GATE_UART6CLK] = { 54, -1, "uart6clk-gate", "uartx", 0 }, /* UART6 */
109 [ASPEED_CLK_GATE_UART7CLK] = { 55, -1, "uart7clk-gate", "uartx", 0 }, /* UART7 */
110 [ASPEED_CLK_GATE_UART8CLK] = { 56, -1, "uart8clk-gate", "uartx", 0 }, /* UART8 */
111 [ASPEED_CLK_GATE_UART9CLK] = { 57, -1, "uart9clk-gate", "uartx", 0 }, /* UART9 */
112 [ASPEED_CLK_GATE_UART10CLK] = { 58, -1, "uart10clk-gate", "uartx", 0 }, /* UART10 */
113 [ASPEED_CLK_GATE_UART11CLK] = { 59, -1, "uart11clk-gate", "uartx", 0 }, /* UART11 */
114 [ASPEED_CLK_GATE_UART12CLK] = { 60, -1, "uart12clk-gate", "uartx", 0 }, /* UART12 */
115 [ASPEED_CLK_GATE_UART13CLK] = { 61, -1, "uart13clk-gate", "uartx", 0 }, /* UART13 */
116 [ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", NULL, 0 }, /* FSI */
117};
118
119static const char * const eclk_parent_names[] = { "mpll", "hpll", "dpll" };
120
121static const struct clk_div_table ast2600_eclk_div_table[] = {
122 { 0x0, 2 },
123 { 0x1, 2 },
124 { 0x2, 3 },
125 { 0x3, 4 },
126 { 0x4, 5 },
127 { 0x5, 6 },
128 { 0x6, 7 },
129 { 0x7, 8 },
130 { 0 }
131};
132
133static const struct clk_div_table ast2600_mac_div_table[] = {
134 { 0x0, 4 },
135 { 0x1, 4 },
136 { 0x2, 6 },
137 { 0x3, 8 },
138 { 0x4, 10 },
139 { 0x5, 12 },
140 { 0x6, 14 },
141 { 0x7, 16 },
142 { 0 }
143};
144
145static const struct clk_div_table ast2600_div_table[] = {
146 { 0x0, 4 },
147 { 0x1, 8 },
148 { 0x2, 12 },
149 { 0x3, 16 },
150 { 0x4, 20 },
151 { 0x5, 24 },
152 { 0x6, 28 },
153 { 0x7, 32 },
154 { 0 }
155};
156
157/* For hpll/dpll/epll/mpll */
158static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
159{
160 unsigned int mult, div;
161
162 if (val & BIT(24)) {
163 /* Pass through mode */
164 mult = div = 1;
165 } else {
166 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
167 u32 m = val & 0x1fff;
168 u32 n = (val >> 13) & 0x3f;
169 u32 p = (val >> 19) & 0xf;
170 mult = (m + 1) / (n + 1);
171 div = (p + 1);
172 }
173 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
174 mult, div);
175};
176
177static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
178{
179 unsigned int mult, div;
180
181 if (val & BIT(20)) {
182 /* Pass through mode */
183 mult = div = 1;
184 } else {
185 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
186 u32 m = (val >> 5) & 0x3f;
187 u32 od = (val >> 4) & 0x1;
188 u32 n = val & 0xf;
189
190 mult = (2 - od) * (m + 2);
191 div = n + 1;
192 }
193 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
194 mult, div);
195};
196
197static u32 get_bit(u8 idx)
198{
199 return BIT(idx % 32);
200}
201
202static u32 get_reset_reg(struct aspeed_clk_gate *gate)
203{
204 if (gate->reset_idx < 32)
205 return ASPEED_G6_RESET_CTRL;
206
207 return ASPEED_G6_RESET_CTRL2;
208}
209
210static u32 get_clock_reg(struct aspeed_clk_gate *gate)
211{
212 if (gate->clock_idx < 32)
213 return ASPEED_G6_CLK_STOP_CTRL;
214
215 return ASPEED_G6_CLK_STOP_CTRL2;
216}
217
218static int aspeed_g6_clk_is_enabled(struct clk_hw *hw)
219{
220 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
221 u32 clk = get_bit(gate->clock_idx);
222 u32 rst = get_bit(gate->reset_idx);
223 u32 reg;
224 u32 enval;
225
226 /*
227 * If the IP is in reset, treat the clock as not enabled,
228 * this happens with some clocks such as the USB one when
229 * coming from cold reset. Without this, aspeed_clk_enable()
230 * will fail to lift the reset.
231 */
232 if (gate->reset_idx >= 0) {
233 regmap_read(gate->map, get_reset_reg(gate), ®);
234
235 if (reg & rst)
236 return 0;
237 }
238
239 regmap_read(gate->map, get_clock_reg(gate), ®);
240
241 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
242
243 return ((reg & clk) == enval) ? 1 : 0;
244}
245
246static int aspeed_g6_clk_enable(struct clk_hw *hw)
247{
248 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
249 unsigned long flags;
250 u32 clk = get_bit(gate->clock_idx);
251 u32 rst = get_bit(gate->reset_idx);
252
253 spin_lock_irqsave(gate->lock, flags);
254
255 if (aspeed_g6_clk_is_enabled(hw)) {
256 spin_unlock_irqrestore(gate->lock, flags);
257 return 0;
258 }
259
260 if (gate->reset_idx >= 0) {
261 /* Put IP in reset */
262 regmap_write(gate->map, get_reset_reg(gate), rst);
263 /* Delay 100us */
264 udelay(100);
265 }
266
267 /* Enable clock */
268 if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
269 /* Clock is clear to enable, so use set to clear register */
270 regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk);
271 } else {
272 /* Clock is set to enable, so use write to set register */
273 regmap_write(gate->map, get_clock_reg(gate), clk);
274 }
275
276 if (gate->reset_idx >= 0) {
277 /* A delay of 10ms is specified by the ASPEED docs */
278 mdelay(10);
279 /* Take IP out of reset */
280 regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst);
281 }
282
283 spin_unlock_irqrestore(gate->lock, flags);
284
285 return 0;
286}
287
288static void aspeed_g6_clk_disable(struct clk_hw *hw)
289{
290 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
291 unsigned long flags;
292 u32 clk = get_bit(gate->clock_idx);
293
294 spin_lock_irqsave(gate->lock, flags);
295
296 if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
297 regmap_write(gate->map, get_clock_reg(gate), clk);
298 } else {
299 /* Use set to clear register */
300 regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk);
301 }
302
303 spin_unlock_irqrestore(gate->lock, flags);
304}
305
306static const struct clk_ops aspeed_g6_clk_gate_ops = {
307 .enable = aspeed_g6_clk_enable,
308 .disable = aspeed_g6_clk_disable,
309 .is_enabled = aspeed_g6_clk_is_enabled,
310};
311
312static int aspeed_g6_reset_deassert(struct reset_controller_dev *rcdev,
313 unsigned long id)
314{
315 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
316 u32 rst = get_bit(id);
317 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
318
319 /* Use set to clear register */
320 return regmap_write(ar->map, reg + 0x04, rst);
321}
322
323static int aspeed_g6_reset_assert(struct reset_controller_dev *rcdev,
324 unsigned long id)
325{
326 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
327 u32 rst = get_bit(id);
328 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
329
330 return regmap_write(ar->map, reg, rst);
331}
332
333static int aspeed_g6_reset_status(struct reset_controller_dev *rcdev,
334 unsigned long id)
335{
336 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
337 int ret;
338 u32 val;
339 u32 rst = get_bit(id);
340 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
341
342 ret = regmap_read(ar->map, reg, &val);
343 if (ret)
344 return ret;
345
346 return !!(val & rst);
347}
348
349static const struct reset_control_ops aspeed_g6_reset_ops = {
350 .assert = aspeed_g6_reset_assert,
351 .deassert = aspeed_g6_reset_deassert,
352 .status = aspeed_g6_reset_status,
353};
354
355static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev,
356 const char *name, const char *parent_name, unsigned long flags,
357 struct regmap *map, u8 clock_idx, u8 reset_idx,
358 u8 clk_gate_flags, spinlock_t *lock)
359{
360 struct aspeed_clk_gate *gate;
361 struct clk_init_data init;
362 struct clk_hw *hw;
363 int ret;
364
365 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
366 if (!gate)
367 return ERR_PTR(-ENOMEM);
368
369 init.name = name;
370 init.ops = &aspeed_g6_clk_gate_ops;
371 init.flags = flags;
372 init.parent_names = parent_name ? &parent_name : NULL;
373 init.num_parents = parent_name ? 1 : 0;
374
375 gate->map = map;
376 gate->clock_idx = clock_idx;
377 gate->reset_idx = reset_idx;
378 gate->flags = clk_gate_flags;
379 gate->lock = lock;
380 gate->hw.init = &init;
381
382 hw = &gate->hw;
383 ret = clk_hw_register(dev, hw);
384 if (ret) {
385 kfree(gate);
386 hw = ERR_PTR(ret);
387 }
388
389 return hw;
390}
391
392static const char * const vclk_parent_names[] = {
393 "dpll",
394 "d1pll",
395 "hclk",
396 "mclk",
397};
398
399static const char * const d1clk_parent_names[] = {
400 "dpll",
401 "epll",
402 "usb-phy-40m",
403 "gpioc6_clkin",
404 "dp_phy_pll",
405};
406
407static int aspeed_g6_clk_probe(struct platform_device *pdev)
408{
409 struct device *dev = &pdev->dev;
410 struct aspeed_reset *ar;
411 struct regmap *map;
412 struct clk_hw *hw;
413 u32 val, rate;
414 int i, ret;
415
416 map = syscon_node_to_regmap(dev->of_node);
417 if (IS_ERR(map)) {
418 dev_err(dev, "no syscon regmap\n");
419 return PTR_ERR(map);
420 }
421
422 ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
423 if (!ar)
424 return -ENOMEM;
425
426 ar->map = map;
427
428 ar->rcdev.owner = THIS_MODULE;
429 ar->rcdev.nr_resets = 64;
430 ar->rcdev.ops = &aspeed_g6_reset_ops;
431 ar->rcdev.of_node = dev->of_node;
432
433 ret = devm_reset_controller_register(dev, &ar->rcdev);
434 if (ret) {
435 dev_err(dev, "could not register reset controller\n");
436 return ret;
437 }
438
439 /* UART clock div13 setting */
440 regmap_read(map, ASPEED_G6_MISC_CTRL, &val);
441 if (val & UART_DIV13_EN)
442 rate = 24000000 / 13;
443 else
444 rate = 24000000;
445 hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
446 if (IS_ERR(hw))
447 return PTR_ERR(hw);
448 aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw;
449
450 /* UART6~13 clock div13 setting */
451 regmap_read(map, 0x80, &val);
452 if (val & BIT(31))
453 rate = 24000000 / 13;
454 else
455 rate = 24000000;
456 hw = clk_hw_register_fixed_rate(dev, "uartx", NULL, 0, rate);
457 if (IS_ERR(hw))
458 return PTR_ERR(hw);
459 aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
460
461 /* EMMC ext clock divider */
462 hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "hpll", 0,
463 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 15, 0,
464 &aspeed_g6_clk_lock);
465 if (IS_ERR(hw))
466 return PTR_ERR(hw);
467 hw = clk_hw_register_divider_table(dev, "emmc_extclk", "emmc_extclk_gate", 0,
468 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 12, 3, 0,
469 ast2600_div_table,
470 &aspeed_g6_clk_lock);
471 if (IS_ERR(hw))
472 return PTR_ERR(hw);
473 aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;
474
475 /* SD/SDIO clock divider and gate */
476 hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
477 scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0,
478 &aspeed_g6_clk_lock);
479 if (IS_ERR(hw))
480 return PTR_ERR(hw);
481 hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
482 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0,
483 ast2600_div_table,
484 &aspeed_g6_clk_lock);
485 if (IS_ERR(hw))
486 return PTR_ERR(hw);
487 aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
488
489 /* MAC1/2 AHB bus clock divider */
490 hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,
491 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
492 ast2600_mac_div_table,
493 &aspeed_g6_clk_lock);
494 if (IS_ERR(hw))
495 return PTR_ERR(hw);
496 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
497
498 /* MAC3/4 AHB bus clock divider */
499 hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,
500 scu_g6_base + 0x310, 24, 3, 0,
501 ast2600_mac_div_table,
502 &aspeed_g6_clk_lock);
503 if (IS_ERR(hw))
504 return PTR_ERR(hw);
505 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
506
507 /* LPC Host (LHCLK) clock divider */
508 hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
509 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
510 ast2600_div_table,
511 &aspeed_g6_clk_lock);
512 if (IS_ERR(hw))
513 return PTR_ERR(hw);
514 aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
515
516 /* gfx d1clk : use dp clk */
517 regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10));
518 /* SoC Display clock selection */
519 hw = clk_hw_register_mux(dev, "d1clk", d1clk_parent_names,
520 ARRAY_SIZE(d1clk_parent_names), 0,
521 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 8, 3, 0,
522 &aspeed_g6_clk_lock);
523 if (IS_ERR(hw))
524 return PTR_ERR(hw);
525 aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw;
526
527 /* d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1 */
528 regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */
529
530 /* P-Bus (BCLK) clock divider */
531 hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
532 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
533 ast2600_div_table,
534 &aspeed_g6_clk_lock);
535 if (IS_ERR(hw))
536 return PTR_ERR(hw);
537 aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw;
538
539 /* Video Capture clock selection */
540 hw = clk_hw_register_mux(dev, "vclk", vclk_parent_names,
541 ARRAY_SIZE(vclk_parent_names), 0,
542 scu_g6_base + ASPEED_G6_CLK_SELECTION2, 12, 3, 0,
543 &aspeed_g6_clk_lock);
544 if (IS_ERR(hw))
545 return PTR_ERR(hw);
546 aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw;
547
548 /* Video Engine clock divider */
549 hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0,
550 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 28, 3, 0,
551 ast2600_eclk_div_table,
552 &aspeed_g6_clk_lock);
553 if (IS_ERR(hw))
554 return PTR_ERR(hw);
555 aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw;
556
557 for (i = 0; i < ARRAY_SIZE(aspeed_g6_gates); i++) {
558 const struct aspeed_gate_data *gd = &aspeed_g6_gates[i];
559 u32 gate_flags;
560
561 /*
562 * Special case: the USB port 1 clock (bit 14) is always
563 * working the opposite way from the other ones.
564 */
565 gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
566 hw = aspeed_g6_clk_hw_register_gate(dev,
567 gd->name,
568 gd->parent_name,
569 gd->flags,
570 map,
571 gd->clock_idx,
572 gd->reset_idx,
573 gate_flags,
574 &aspeed_g6_clk_lock);
575 if (IS_ERR(hw))
576 return PTR_ERR(hw);
577 aspeed_g6_clk_data->hws[i] = hw;
578 }
579
580 return 0;
581};
582
583static const struct of_device_id aspeed_g6_clk_dt_ids[] = {
584 { .compatible = "aspeed,ast2600-scu" },
585 { }
586};
587
588static struct platform_driver aspeed_g6_clk_driver = {
589 .probe = aspeed_g6_clk_probe,
590 .driver = {
591 .name = "ast2600-clk",
592 .of_match_table = aspeed_g6_clk_dt_ids,
593 .suppress_bind_attrs = true,
594 },
595};
596builtin_platform_driver(aspeed_g6_clk_driver);
597
598static const u32 ast2600_a0_axi_ahb_div_table[] = {
599 2, 2, 3, 5,
600};
601
602static const u32 ast2600_a1_axi_ahb_div_table[] = {
603 4, 6, 2, 4,
604};
605
606static void __init aspeed_g6_cc(struct regmap *map)
607{
608 struct clk_hw *hw;
609 u32 val, div, chip_id, axi_div, ahb_div;
610
611 clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
612
613 /*
614 * High-speed PLL clock derived from the crystal. This the CPU clock,
615 * and we assume that it is enabled
616 */
617 regmap_read(map, ASPEED_HPLL_PARAM, &val);
618 aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val);
619
620 regmap_read(map, ASPEED_MPLL_PARAM, &val);
621 aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val);
622
623 regmap_read(map, ASPEED_DPLL_PARAM, &val);
624 aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val);
625
626 regmap_read(map, ASPEED_EPLL_PARAM, &val);
627 aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val);
628
629 regmap_read(map, ASPEED_APLL_PARAM, &val);
630 aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val);
631
632 /* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/
633 regmap_read(map, ASPEED_G6_STRAP1, &val);
634 if (val & BIT(16))
635 axi_div = 1;
636 else
637 axi_div = 2;
638
639 regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
640 if (chip_id & BIT(16))
641 ahb_div = ast2600_a1_axi_ahb_div_table[(val >> 11) & 0x3];
642 else
643 ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
644
645 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
646 aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;
647
648 regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val);
649 val = (val >> 23) & 0x7;
650 div = 4 * (val + 1);
651 hw = clk_hw_register_fixed_factor(NULL, "apb1", "hpll", 0, 1, div);
652 aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw;
653
654 regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val);
655 val = (val >> 9) & 0x7;
656 div = 2 * (val + 1);
657 hw = clk_hw_register_fixed_factor(NULL, "apb2", "ahb", 0, 1, div);
658 aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw;
659
660 /* USB 2.0 port1 phy 40MHz clock */
661 hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000);
662 aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw;
663};
664
665static void __init aspeed_g6_cc_init(struct device_node *np)
666{
667 struct regmap *map;
668 int ret;
669 int i;
670
671 scu_g6_base = of_iomap(np, 0);
672 if (!scu_g6_base)
673 return;
674
675 aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws,
676 ASPEED_G6_NUM_CLKS), GFP_KERNEL);
677 if (!aspeed_g6_clk_data)
678 return;
679
680 /*
681 * This way all clocks fetched before the platform device probes,
682 * except those we assign here for early use, will be deferred.
683 */
684 for (i = 0; i < ASPEED_G6_NUM_CLKS; i++)
685 aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
686
687 /*
688 * We check that the regmap works on this very first access,
689 * but as this is an MMIO-backed regmap, subsequent regmap
690 * access is not going to fail and we skip error checks from
691 * this point.
692 */
693 map = syscon_node_to_regmap(np);
694 if (IS_ERR(map)) {
695 pr_err("no syscon regmap\n");
696 return;
697 }
698
699 aspeed_g6_cc(map);
700 aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
701 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
702 if (ret)
703 pr_err("failed to add DT provider: %d\n", ret);
704};
705CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init);