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1/*
2 * linux/arch/arm/mach-omap2/id.c
3 *
4 * OMAP2 CPU identification code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
8 *
9 * Copyright (C) 2009-11 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/random.h>
22#include <linux/slab.h>
23
24#ifdef CONFIG_SOC_BUS
25#include <linux/sys_soc.h>
26#endif
27
28#include <asm/cputype.h>
29
30#include "common.h"
31
32#include "id.h"
33
34#include "soc.h"
35#include "control.h"
36
37#define OMAP4_SILICON_TYPE_STANDARD 0x01
38#define OMAP4_SILICON_TYPE_PERFORMANCE 0x02
39
40#define OMAP_SOC_MAX_NAME_LENGTH 16
41
42static unsigned int omap_revision;
43static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
44static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
45u32 omap_features;
46
47unsigned int omap_rev(void)
48{
49 return omap_revision;
50}
51EXPORT_SYMBOL(omap_rev);
52
53int omap_type(void)
54{
55 u32 val = 0;
56
57 if (cpu_is_omap24xx()) {
58 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
59 } else if (soc_is_am33xx() || soc_is_am43xx()) {
60 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
61 } else if (cpu_is_omap34xx()) {
62 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
63 } else if (cpu_is_omap44xx()) {
64 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
65 } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
66 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
67 val &= OMAP5_DEVICETYPE_MASK;
68 val >>= 6;
69 goto out;
70 } else {
71 pr_err("Cannot detect omap type!\n");
72 goto out;
73 }
74
75 val &= OMAP2_DEVICETYPE_MASK;
76 val >>= 8;
77
78out:
79 return val;
80}
81EXPORT_SYMBOL(omap_type);
82
83
84/*----------------------------------------------------------------------------*/
85
86#define OMAP_TAP_IDCODE 0x0204
87#define OMAP_TAP_DIE_ID_0 0x0218
88#define OMAP_TAP_DIE_ID_1 0x021C
89#define OMAP_TAP_DIE_ID_2 0x0220
90#define OMAP_TAP_DIE_ID_3 0x0224
91
92#define OMAP_TAP_DIE_ID_44XX_0 0x0200
93#define OMAP_TAP_DIE_ID_44XX_1 0x0208
94#define OMAP_TAP_DIE_ID_44XX_2 0x020c
95#define OMAP_TAP_DIE_ID_44XX_3 0x0210
96
97#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
98
99struct omap_id {
100 u16 hawkeye; /* Silicon type (Hawkeye id) */
101 u8 dev; /* Device type from production_id reg */
102 u32 type; /* Combined type id copied to omap_revision */
103};
104
105/* Register values to detect the OMAP version */
106static struct omap_id omap_ids[] __initdata = {
107 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
108 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
109 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
110 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
111 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
112 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
113};
114
115static void __iomem *tap_base;
116static u16 tap_prod_id;
117
118void omap_get_die_id(struct omap_die_id *odi)
119{
120 if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
121 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
122 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
123 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
124 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
125
126 return;
127 }
128 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
129 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
130 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
131 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
132}
133
134static int __init omap_feed_randpool(void)
135{
136 struct omap_die_id odi;
137
138 /* Throw the die ID into the entropy pool at boot */
139 omap_get_die_id(&odi);
140 add_device_randomness(&odi, sizeof(odi));
141 return 0;
142}
143omap_device_initcall(omap_feed_randpool);
144
145void __init omap2xxx_check_revision(void)
146{
147 int i, j;
148 u32 idcode, prod_id;
149 u16 hawkeye;
150 u8 dev_type, rev;
151 struct omap_die_id odi;
152
153 idcode = read_tap_reg(OMAP_TAP_IDCODE);
154 prod_id = read_tap_reg(tap_prod_id);
155 hawkeye = (idcode >> 12) & 0xffff;
156 rev = (idcode >> 28) & 0x0f;
157 dev_type = (prod_id >> 16) & 0x0f;
158 omap_get_die_id(&odi);
159
160 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
161 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
162 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
163 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
164 odi.id_1, (odi.id_1 >> 28) & 0xf);
165 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
166 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
167 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
168 prod_id, dev_type);
169
170 /* Check hawkeye ids */
171 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
172 if (hawkeye == omap_ids[i].hawkeye)
173 break;
174 }
175
176 if (i == ARRAY_SIZE(omap_ids)) {
177 printk(KERN_ERR "Unknown OMAP CPU id\n");
178 return;
179 }
180
181 for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
182 if (dev_type == omap_ids[j].dev)
183 break;
184 }
185
186 if (j == ARRAY_SIZE(omap_ids)) {
187 pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
188 omap_ids[i].type >> 16);
189 j = i;
190 }
191
192 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
193 sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
194
195 pr_info("%s", soc_name);
196 if ((omap_rev() >> 8) & 0x0f)
197 pr_info("%s", soc_rev);
198 pr_info("\n");
199}
200
201#define OMAP3_SHOW_FEATURE(feat) \
202 if (omap3_has_ ##feat()) \
203 printk(#feat" ");
204
205static void __init omap3_cpuinfo(void)
206{
207 const char *cpu_name;
208
209 /*
210 * OMAP3430 and OMAP3530 are assumed to be same.
211 *
212 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
213 * on available features. Upon detection, update the CPU id
214 * and CPU class bits.
215 */
216 if (cpu_is_omap3630()) {
217 cpu_name = "OMAP3630";
218 } else if (soc_is_am35xx()) {
219 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
220 } else if (cpu_is_ti816x()) {
221 cpu_name = "TI816X";
222 } else if (soc_is_am335x()) {
223 cpu_name = "AM335X";
224 } else if (soc_is_am437x()) {
225 cpu_name = "AM437x";
226 } else if (cpu_is_ti814x()) {
227 cpu_name = "TI814X";
228 } else if (omap3_has_iva() && omap3_has_sgx()) {
229 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
230 cpu_name = "OMAP3430/3530";
231 } else if (omap3_has_iva()) {
232 cpu_name = "OMAP3525";
233 } else if (omap3_has_sgx()) {
234 cpu_name = "OMAP3515";
235 } else {
236 cpu_name = "OMAP3503";
237 }
238
239 sprintf(soc_name, "%s", cpu_name);
240
241 /* Print verbose information */
242 pr_info("%s %s (", soc_name, soc_rev);
243
244 OMAP3_SHOW_FEATURE(l2cache);
245 OMAP3_SHOW_FEATURE(iva);
246 OMAP3_SHOW_FEATURE(sgx);
247 OMAP3_SHOW_FEATURE(neon);
248 OMAP3_SHOW_FEATURE(isp);
249 OMAP3_SHOW_FEATURE(192mhz_clk);
250
251 printk(")\n");
252}
253
254#define OMAP3_CHECK_FEATURE(status,feat) \
255 if (((status & OMAP3_ ##feat## _MASK) \
256 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
257 omap_features |= OMAP3_HAS_ ##feat; \
258 }
259
260void __init omap3xxx_check_features(void)
261{
262 u32 status;
263
264 omap_features = 0;
265
266 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
267
268 OMAP3_CHECK_FEATURE(status, L2CACHE);
269 OMAP3_CHECK_FEATURE(status, IVA);
270 OMAP3_CHECK_FEATURE(status, SGX);
271 OMAP3_CHECK_FEATURE(status, NEON);
272 OMAP3_CHECK_FEATURE(status, ISP);
273 if (cpu_is_omap3630())
274 omap_features |= OMAP3_HAS_192MHZ_CLK;
275 if (cpu_is_omap3430() || cpu_is_omap3630())
276 omap_features |= OMAP3_HAS_IO_WAKEUP;
277 if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
278 omap_rev() == OMAP3430_REV_ES3_1_2)
279 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
280
281 omap_features |= OMAP3_HAS_SDRC;
282
283 /*
284 * am35x fixups:
285 * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
286 * reserved and therefore return 0 when read. Unfortunately,
287 * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
288 * mean that a feature is present even though it isn't so clear
289 * the incorrectly set feature bits.
290 */
291 if (soc_is_am35xx())
292 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
293
294 /*
295 * TODO: Get additional info (where applicable)
296 * e.g. Size of L2 cache.
297 */
298
299 omap3_cpuinfo();
300}
301
302void __init omap4xxx_check_features(void)
303{
304 u32 si_type;
305
306 si_type =
307 (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03;
308
309 if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
310 omap_features = OMAP4_HAS_PERF_SILICON;
311}
312
313void __init ti81xx_check_features(void)
314{
315 omap_features = OMAP3_HAS_NEON;
316 omap3_cpuinfo();
317}
318
319void __init am33xx_check_features(void)
320{
321 u32 status;
322
323 omap_features = OMAP3_HAS_NEON;
324
325 status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
326 if (status & AM33XX_SGX_MASK)
327 omap_features |= OMAP3_HAS_SGX;
328
329 omap3_cpuinfo();
330}
331
332void __init omap3xxx_check_revision(void)
333{
334 const char *cpu_rev;
335 u32 cpuid, idcode;
336 u16 hawkeye;
337 u8 rev;
338
339 /*
340 * We cannot access revision registers on ES1.0.
341 * If the processor type is Cortex-A8 and the revision is 0x0
342 * it means its Cortex r0p0 which is 3430 ES1.0.
343 */
344 cpuid = read_cpuid_id();
345 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
346 omap_revision = OMAP3430_REV_ES1_0;
347 cpu_rev = "1.0";
348 return;
349 }
350
351 /*
352 * Detection for 34xx ES2.0 and above can be done with just
353 * hawkeye and rev. See TRM 1.5.2 Device Identification.
354 * Note that rev does not map directly to our defined processor
355 * revision numbers as ES1.0 uses value 0.
356 */
357 idcode = read_tap_reg(OMAP_TAP_IDCODE);
358 hawkeye = (idcode >> 12) & 0xffff;
359 rev = (idcode >> 28) & 0xff;
360
361 switch (hawkeye) {
362 case 0xb7ae:
363 /* Handle 34xx/35xx devices */
364 switch (rev) {
365 case 0: /* Take care of early samples */
366 case 1:
367 omap_revision = OMAP3430_REV_ES2_0;
368 cpu_rev = "2.0";
369 break;
370 case 2:
371 omap_revision = OMAP3430_REV_ES2_1;
372 cpu_rev = "2.1";
373 break;
374 case 3:
375 omap_revision = OMAP3430_REV_ES3_0;
376 cpu_rev = "3.0";
377 break;
378 case 4:
379 omap_revision = OMAP3430_REV_ES3_1;
380 cpu_rev = "3.1";
381 break;
382 case 7:
383 /* FALLTHROUGH */
384 default:
385 /* Use the latest known revision as default */
386 omap_revision = OMAP3430_REV_ES3_1_2;
387 cpu_rev = "3.1.2";
388 }
389 break;
390 case 0xb868:
391 /*
392 * Handle OMAP/AM 3505/3517 devices
393 *
394 * Set the device to be OMAP3517 here. Actual device
395 * is identified later based on the features.
396 */
397 switch (rev) {
398 case 0:
399 omap_revision = AM35XX_REV_ES1_0;
400 cpu_rev = "1.0";
401 break;
402 case 1:
403 /* FALLTHROUGH */
404 default:
405 omap_revision = AM35XX_REV_ES1_1;
406 cpu_rev = "1.1";
407 }
408 break;
409 case 0xb891:
410 /* Handle 36xx devices */
411
412 switch(rev) {
413 case 0: /* Take care of early samples */
414 omap_revision = OMAP3630_REV_ES1_0;
415 cpu_rev = "1.0";
416 break;
417 case 1:
418 omap_revision = OMAP3630_REV_ES1_1;
419 cpu_rev = "1.1";
420 break;
421 case 2:
422 /* FALLTHROUGH */
423 default:
424 omap_revision = OMAP3630_REV_ES1_2;
425 cpu_rev = "1.2";
426 }
427 break;
428 case 0xb81e:
429 switch (rev) {
430 case 0:
431 omap_revision = TI8168_REV_ES1_0;
432 cpu_rev = "1.0";
433 break;
434 case 1:
435 omap_revision = TI8168_REV_ES1_1;
436 cpu_rev = "1.1";
437 break;
438 case 2:
439 omap_revision = TI8168_REV_ES2_0;
440 cpu_rev = "2.0";
441 break;
442 case 3:
443 /* FALLTHROUGH */
444 default:
445 omap_revision = TI8168_REV_ES2_1;
446 cpu_rev = "2.1";
447 }
448 break;
449 case 0xb944:
450 switch (rev) {
451 case 0:
452 omap_revision = AM335X_REV_ES1_0;
453 cpu_rev = "1.0";
454 break;
455 case 1:
456 omap_revision = AM335X_REV_ES2_0;
457 cpu_rev = "2.0";
458 break;
459 case 2:
460 /* FALLTHROUGH */
461 default:
462 omap_revision = AM335X_REV_ES2_1;
463 cpu_rev = "2.1";
464 break;
465 }
466 break;
467 case 0xb98c:
468 switch (rev) {
469 case 0:
470 omap_revision = AM437X_REV_ES1_0;
471 cpu_rev = "1.0";
472 break;
473 case 1:
474 /* FALLTHROUGH */
475 default:
476 omap_revision = AM437X_REV_ES1_1;
477 cpu_rev = "1.1";
478 break;
479 }
480 break;
481 case 0xb8f2:
482 switch (rev) {
483 case 0:
484 /* FALLTHROUGH */
485 case 1:
486 omap_revision = TI8148_REV_ES1_0;
487 cpu_rev = "1.0";
488 break;
489 case 2:
490 omap_revision = TI8148_REV_ES2_0;
491 cpu_rev = "2.0";
492 break;
493 case 3:
494 /* FALLTHROUGH */
495 default:
496 omap_revision = TI8148_REV_ES2_1;
497 cpu_rev = "2.1";
498 break;
499 }
500 break;
501 default:
502 /* Unknown default to latest silicon rev as default */
503 omap_revision = OMAP3630_REV_ES1_2;
504 cpu_rev = "1.2";
505 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
506 }
507 sprintf(soc_rev, "ES%s", cpu_rev);
508}
509
510void __init omap4xxx_check_revision(void)
511{
512 u32 idcode;
513 u16 hawkeye;
514 u8 rev;
515
516 /*
517 * The IC rev detection is done with hawkeye and rev.
518 * Note that rev does not map directly to defined processor
519 * revision numbers as ES1.0 uses value 0.
520 */
521 idcode = read_tap_reg(OMAP_TAP_IDCODE);
522 hawkeye = (idcode >> 12) & 0xffff;
523 rev = (idcode >> 28) & 0xf;
524
525 /*
526 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
527 * Use ARM register to detect the correct ES version
528 */
529 if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
530 idcode = read_cpuid_id();
531 rev = (idcode & 0xf) - 1;
532 }
533
534 switch (hawkeye) {
535 case 0xb852:
536 switch (rev) {
537 case 0:
538 omap_revision = OMAP4430_REV_ES1_0;
539 break;
540 case 1:
541 default:
542 omap_revision = OMAP4430_REV_ES2_0;
543 }
544 break;
545 case 0xb95c:
546 switch (rev) {
547 case 3:
548 omap_revision = OMAP4430_REV_ES2_1;
549 break;
550 case 4:
551 omap_revision = OMAP4430_REV_ES2_2;
552 break;
553 case 6:
554 default:
555 omap_revision = OMAP4430_REV_ES2_3;
556 }
557 break;
558 case 0xb94e:
559 switch (rev) {
560 case 0:
561 omap_revision = OMAP4460_REV_ES1_0;
562 break;
563 case 2:
564 default:
565 omap_revision = OMAP4460_REV_ES1_1;
566 break;
567 }
568 break;
569 case 0xb975:
570 switch (rev) {
571 case 0:
572 default:
573 omap_revision = OMAP4470_REV_ES1_0;
574 break;
575 }
576 break;
577 default:
578 /* Unknown default to latest silicon rev as default */
579 omap_revision = OMAP4430_REV_ES2_3;
580 }
581
582 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
583 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
584 (omap_rev() >> 8) & 0xf);
585 pr_info("%s %s\n", soc_name, soc_rev);
586}
587
588void __init omap5xxx_check_revision(void)
589{
590 u32 idcode;
591 u16 hawkeye;
592 u8 rev;
593
594 idcode = read_tap_reg(OMAP_TAP_IDCODE);
595 hawkeye = (idcode >> 12) & 0xffff;
596 rev = (idcode >> 28) & 0xff;
597 switch (hawkeye) {
598 case 0xb942:
599 switch (rev) {
600 case 0:
601 /* No support for ES1.0 Test chip */
602 BUG();
603 case 1:
604 default:
605 omap_revision = OMAP5430_REV_ES2_0;
606 }
607 break;
608
609 case 0xb998:
610 switch (rev) {
611 case 0:
612 /* No support for ES1.0 Test chip */
613 BUG();
614 case 1:
615 default:
616 omap_revision = OMAP5432_REV_ES2_0;
617 }
618 break;
619
620 default:
621 /* Unknown default to latest silicon rev as default*/
622 omap_revision = OMAP5430_REV_ES2_0;
623 }
624
625 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
626 sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
627
628 pr_info("%s %s\n", soc_name, soc_rev);
629}
630
631/*
632 * Set up things for map_io and processor detection later on. Gets called
633 * pretty much first thing from board init. For multi-omap, this gets
634 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
635 * detect the exact revision later on in omap2_detect_revision() once map_io
636 * is done.
637 */
638void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
639{
640 omap_revision = class;
641 tap_base = tap;
642
643 /* XXX What is this intended to do? */
644 if (cpu_is_omap34xx())
645 tap_prod_id = 0x0210;
646 else
647 tap_prod_id = 0x0208;
648}
649
650#ifdef CONFIG_SOC_BUS
651
652static const char * const omap_types[] = {
653 [OMAP2_DEVICE_TYPE_TEST] = "TST",
654 [OMAP2_DEVICE_TYPE_EMU] = "EMU",
655 [OMAP2_DEVICE_TYPE_SEC] = "HS",
656 [OMAP2_DEVICE_TYPE_GP] = "GP",
657 [OMAP2_DEVICE_TYPE_BAD] = "BAD",
658};
659
660static const char * __init omap_get_family(void)
661{
662 if (cpu_is_omap24xx())
663 return kasprintf(GFP_KERNEL, "OMAP2");
664 else if (cpu_is_omap34xx())
665 return kasprintf(GFP_KERNEL, "OMAP3");
666 else if (cpu_is_omap44xx())
667 return kasprintf(GFP_KERNEL, "OMAP4");
668 else if (soc_is_omap54xx())
669 return kasprintf(GFP_KERNEL, "OMAP5");
670 else if (soc_is_am43xx())
671 return kasprintf(GFP_KERNEL, "AM43xx");
672 else
673 return kasprintf(GFP_KERNEL, "Unknown");
674}
675
676static ssize_t omap_get_type(struct device *dev,
677 struct device_attribute *attr,
678 char *buf)
679{
680 return sprintf(buf, "%s\n", omap_types[omap_type()]);
681}
682
683static struct device_attribute omap_soc_attr =
684 __ATTR(type, S_IRUGO, omap_get_type, NULL);
685
686void __init omap_soc_device_init(void)
687{
688 struct device *parent;
689 struct soc_device *soc_dev;
690 struct soc_device_attribute *soc_dev_attr;
691
692 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
693 if (!soc_dev_attr)
694 return;
695
696 soc_dev_attr->machine = soc_name;
697 soc_dev_attr->family = omap_get_family();
698 soc_dev_attr->revision = soc_rev;
699
700 soc_dev = soc_device_register(soc_dev_attr);
701 if (IS_ERR(soc_dev)) {
702 kfree(soc_dev_attr);
703 return;
704 }
705
706 parent = soc_device_to_device(soc_dev);
707 device_create_file(parent, &omap_soc_attr);
708}
709#endif /* CONFIG_SOC_BUS */
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mach-omap2/id.c
4 *
5 * OMAP2 CPU identification code
6 *
7 * Copyright (C) 2005 Nokia Corporation
8 * Written by Tony Lindgren <tony@atomide.com>
9 *
10 * Copyright (C) 2009-11 Texas Instruments
11 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/random.h>
19#include <linux/slab.h>
20
21#ifdef CONFIG_SOC_BUS
22#include <linux/sys_soc.h>
23#endif
24
25#include <asm/cputype.h>
26
27#include "common.h"
28
29#include "id.h"
30
31#include "soc.h"
32#include "control.h"
33
34#define OMAP4_SILICON_TYPE_STANDARD 0x01
35#define OMAP4_SILICON_TYPE_PERFORMANCE 0x02
36
37#define OMAP_SOC_MAX_NAME_LENGTH 16
38
39static unsigned int omap_revision;
40static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
41static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
42u32 omap_features;
43
44unsigned int omap_rev(void)
45{
46 return omap_revision;
47}
48EXPORT_SYMBOL(omap_rev);
49
50int omap_type(void)
51{
52 static u32 val = OMAP2_DEVICETYPE_MASK;
53
54 if (val < OMAP2_DEVICETYPE_MASK)
55 return val;
56
57 if (soc_is_omap24xx()) {
58 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
59 } else if (soc_is_ti81xx()) {
60 val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
61 } else if (soc_is_am33xx() || soc_is_am43xx()) {
62 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
63 } else if (soc_is_omap34xx()) {
64 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
65 } else if (soc_is_omap44xx()) {
66 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
67 } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
68 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
69 val &= OMAP5_DEVICETYPE_MASK;
70 val >>= 6;
71 goto out;
72 } else {
73 pr_err("Cannot detect omap type!\n");
74 goto out;
75 }
76
77 val &= OMAP2_DEVICETYPE_MASK;
78 val >>= 8;
79
80out:
81 return val;
82}
83EXPORT_SYMBOL(omap_type);
84
85
86/*----------------------------------------------------------------------------*/
87
88#define OMAP_TAP_IDCODE 0x0204
89#define OMAP_TAP_DIE_ID_0 0x0218
90#define OMAP_TAP_DIE_ID_1 0x021C
91#define OMAP_TAP_DIE_ID_2 0x0220
92#define OMAP_TAP_DIE_ID_3 0x0224
93
94#define OMAP_TAP_DIE_ID_44XX_0 0x0200
95#define OMAP_TAP_DIE_ID_44XX_1 0x0208
96#define OMAP_TAP_DIE_ID_44XX_2 0x020c
97#define OMAP_TAP_DIE_ID_44XX_3 0x0210
98
99#define read_tap_reg(reg) readl_relaxed(tap_base + (reg))
100
101struct omap_id {
102 u16 hawkeye; /* Silicon type (Hawkeye id) */
103 u8 dev; /* Device type from production_id reg */
104 u32 type; /* Combined type id copied to omap_revision */
105};
106
107/* Register values to detect the OMAP version */
108static struct omap_id omap_ids[] __initdata = {
109 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
110 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
111 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
112 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
113 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
114 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
115};
116
117static void __iomem *tap_base;
118static u16 tap_prod_id;
119
120void omap_get_die_id(struct omap_die_id *odi)
121{
122 if (soc_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
123 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
124 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
125 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
126 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
127
128 return;
129 }
130 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
131 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
132 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
133 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
134}
135
136static int __init omap_feed_randpool(void)
137{
138 struct omap_die_id odi;
139
140 /* Throw the die ID into the entropy pool at boot */
141 omap_get_die_id(&odi);
142 add_device_randomness(&odi, sizeof(odi));
143 return 0;
144}
145omap_device_initcall(omap_feed_randpool);
146
147void __init omap2xxx_check_revision(void)
148{
149 int i, j;
150 u32 idcode, prod_id;
151 u16 hawkeye;
152 u8 dev_type, rev;
153 struct omap_die_id odi;
154
155 idcode = read_tap_reg(OMAP_TAP_IDCODE);
156 prod_id = read_tap_reg(tap_prod_id);
157 hawkeye = (idcode >> 12) & 0xffff;
158 rev = (idcode >> 28) & 0x0f;
159 dev_type = (prod_id >> 16) & 0x0f;
160 omap_get_die_id(&odi);
161
162 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
163 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
164 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
165 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
166 odi.id_1, (odi.id_1 >> 28) & 0xf);
167 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
168 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
169 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
170 prod_id, dev_type);
171
172 /* Check hawkeye ids */
173 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
174 if (hawkeye == omap_ids[i].hawkeye)
175 break;
176 }
177
178 if (i == ARRAY_SIZE(omap_ids)) {
179 printk(KERN_ERR "Unknown OMAP CPU id\n");
180 return;
181 }
182
183 for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
184 if (dev_type == omap_ids[j].dev)
185 break;
186 }
187
188 if (j == ARRAY_SIZE(omap_ids)) {
189 pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
190 omap_ids[i].type >> 16);
191 j = i;
192 }
193
194 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
195 sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
196
197 pr_info("%s", soc_name);
198 if ((omap_rev() >> 8) & 0x0f)
199 pr_cont("%s", soc_rev);
200 pr_cont("\n");
201}
202
203#define OMAP3_SHOW_FEATURE(feat) \
204 if (omap3_has_ ##feat()) \
205 n += scnprintf(buf + n, sizeof(buf) - n, #feat " ");
206
207static void __init omap3_cpuinfo(void)
208{
209 const char *cpu_name;
210 char buf[64];
211 int n = 0;
212
213 memset(buf, 0, sizeof(buf));
214
215 /*
216 * OMAP3430 and OMAP3530 are assumed to be same.
217 *
218 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
219 * on available features. Upon detection, update the CPU id
220 * and CPU class bits.
221 */
222 if (soc_is_omap3630()) {
223 if (omap3_has_iva() && omap3_has_sgx()) {
224 cpu_name = (omap3_has_isp()) ? "OMAP3630/DM3730" : "OMAP3621";
225 } else if (omap3_has_iva()) {
226 cpu_name = "DM3725";
227 } else if (omap3_has_sgx()) {
228 cpu_name = "OMAP3615/AM3715";
229 } else {
230 cpu_name = (omap3_has_isp()) ? "AM3703" : "OMAP3611";
231 }
232 } else if (soc_is_am35xx()) {
233 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
234 } else if (soc_is_ti816x()) {
235 cpu_name = "TI816X";
236 } else if (soc_is_am335x()) {
237 cpu_name = "AM335X";
238 } else if (soc_is_am437x()) {
239 cpu_name = "AM437x";
240 } else if (soc_is_ti814x()) {
241 cpu_name = "TI814X";
242 } else if (omap3_has_iva() && omap3_has_sgx()) {
243 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
244 cpu_name = "OMAP3430/3530";
245 } else if (omap3_has_iva()) {
246 cpu_name = "OMAP3525";
247 } else if (omap3_has_sgx()) {
248 cpu_name = "OMAP3515";
249 } else {
250 cpu_name = "OMAP3503";
251 }
252
253 scnprintf(soc_name, sizeof(soc_name), "%s", cpu_name);
254
255 /* Print verbose information */
256 n += scnprintf(buf, sizeof(buf) - n, "%s %s (", soc_name, soc_rev);
257
258 OMAP3_SHOW_FEATURE(l2cache);
259 OMAP3_SHOW_FEATURE(iva);
260 OMAP3_SHOW_FEATURE(sgx);
261 OMAP3_SHOW_FEATURE(neon);
262 OMAP3_SHOW_FEATURE(isp);
263 OMAP3_SHOW_FEATURE(192mhz_clk);
264 if (*(buf + n - 1) == ' ')
265 n--;
266 n += scnprintf(buf + n, sizeof(buf) - n, ")\n");
267 pr_info("%s", buf);
268}
269
270#define OMAP3_CHECK_FEATURE(status,feat) \
271 if (((status & OMAP3_ ##feat## _MASK) \
272 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
273 omap_features |= OMAP3_HAS_ ##feat; \
274 }
275
276void __init omap3xxx_check_features(void)
277{
278 u32 status;
279
280 omap_features = 0;
281
282 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
283
284 OMAP3_CHECK_FEATURE(status, L2CACHE);
285 OMAP3_CHECK_FEATURE(status, IVA);
286 OMAP3_CHECK_FEATURE(status, SGX);
287 OMAP3_CHECK_FEATURE(status, NEON);
288 OMAP3_CHECK_FEATURE(status, ISP);
289 if (soc_is_omap3630())
290 omap_features |= OMAP3_HAS_192MHZ_CLK;
291 if (soc_is_omap3430() || soc_is_omap3630())
292 omap_features |= OMAP3_HAS_IO_WAKEUP;
293 if (soc_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
294 omap_rev() == OMAP3430_REV_ES3_1_2)
295 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
296
297 omap_features |= OMAP3_HAS_SDRC;
298
299 /*
300 * am35x fixups:
301 * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
302 * reserved and therefore return 0 when read. Unfortunately,
303 * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
304 * mean that a feature is present even though it isn't so clear
305 * the incorrectly set feature bits.
306 */
307 if (soc_is_am35xx())
308 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
309
310 /*
311 * TODO: Get additional info (where applicable)
312 * e.g. Size of L2 cache.
313 */
314
315 omap3_cpuinfo();
316}
317
318void __init omap4xxx_check_features(void)
319{
320 u32 si_type;
321
322 si_type =
323 (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03;
324
325 if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
326 omap_features = OMAP4_HAS_PERF_SILICON;
327}
328
329void __init ti81xx_check_features(void)
330{
331 omap_features = OMAP3_HAS_NEON;
332 omap3_cpuinfo();
333}
334
335void __init am33xx_check_features(void)
336{
337 u32 status;
338
339 omap_features = OMAP3_HAS_NEON;
340
341 status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
342 if (status & AM33XX_SGX_MASK)
343 omap_features |= OMAP3_HAS_SGX;
344
345 omap3_cpuinfo();
346}
347
348void __init omap3xxx_check_revision(void)
349{
350 const char *cpu_rev;
351 u32 cpuid, idcode;
352 u16 hawkeye;
353 u8 rev;
354
355 /*
356 * We cannot access revision registers on ES1.0.
357 * If the processor type is Cortex-A8 and the revision is 0x0
358 * it means its Cortex r0p0 which is 3430 ES1.0.
359 */
360 cpuid = read_cpuid_id();
361 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
362 omap_revision = OMAP3430_REV_ES1_0;
363 cpu_rev = "1.0";
364 return;
365 }
366
367 /*
368 * Detection for 34xx ES2.0 and above can be done with just
369 * hawkeye and rev. See TRM 1.5.2 Device Identification.
370 * Note that rev does not map directly to our defined processor
371 * revision numbers as ES1.0 uses value 0.
372 */
373 idcode = read_tap_reg(OMAP_TAP_IDCODE);
374 hawkeye = (idcode >> 12) & 0xffff;
375 rev = (idcode >> 28) & 0xff;
376
377 switch (hawkeye) {
378 case 0xb7ae:
379 /* Handle 34xx/35xx devices */
380 switch (rev) {
381 case 0: /* Take care of early samples */
382 case 1:
383 omap_revision = OMAP3430_REV_ES2_0;
384 cpu_rev = "2.0";
385 break;
386 case 2:
387 omap_revision = OMAP3430_REV_ES2_1;
388 cpu_rev = "2.1";
389 break;
390 case 3:
391 omap_revision = OMAP3430_REV_ES3_0;
392 cpu_rev = "3.0";
393 break;
394 case 4:
395 omap_revision = OMAP3430_REV_ES3_1;
396 cpu_rev = "3.1";
397 break;
398 case 7:
399 /* FALLTHROUGH */
400 default:
401 /* Use the latest known revision as default */
402 omap_revision = OMAP3430_REV_ES3_1_2;
403 cpu_rev = "3.1.2";
404 }
405 break;
406 case 0xb868:
407 /*
408 * Handle OMAP/AM 3505/3517 devices
409 *
410 * Set the device to be OMAP3517 here. Actual device
411 * is identified later based on the features.
412 */
413 switch (rev) {
414 case 0:
415 omap_revision = AM35XX_REV_ES1_0;
416 cpu_rev = "1.0";
417 break;
418 case 1:
419 /* FALLTHROUGH */
420 default:
421 omap_revision = AM35XX_REV_ES1_1;
422 cpu_rev = "1.1";
423 }
424 break;
425 case 0xb891:
426 /* Handle 36xx devices */
427
428 switch(rev) {
429 case 0: /* Take care of early samples */
430 omap_revision = OMAP3630_REV_ES1_0;
431 cpu_rev = "1.0";
432 break;
433 case 1:
434 omap_revision = OMAP3630_REV_ES1_1;
435 cpu_rev = "1.1";
436 break;
437 case 2:
438 /* FALLTHROUGH */
439 default:
440 omap_revision = OMAP3630_REV_ES1_2;
441 cpu_rev = "1.2";
442 }
443 break;
444 case 0xb81e:
445 switch (rev) {
446 case 0:
447 omap_revision = TI8168_REV_ES1_0;
448 cpu_rev = "1.0";
449 break;
450 case 1:
451 omap_revision = TI8168_REV_ES1_1;
452 cpu_rev = "1.1";
453 break;
454 case 2:
455 omap_revision = TI8168_REV_ES2_0;
456 cpu_rev = "2.0";
457 break;
458 case 3:
459 /* FALLTHROUGH */
460 default:
461 omap_revision = TI8168_REV_ES2_1;
462 cpu_rev = "2.1";
463 }
464 break;
465 case 0xb944:
466 switch (rev) {
467 case 0:
468 omap_revision = AM335X_REV_ES1_0;
469 cpu_rev = "1.0";
470 break;
471 case 1:
472 omap_revision = AM335X_REV_ES2_0;
473 cpu_rev = "2.0";
474 break;
475 case 2:
476 /* FALLTHROUGH */
477 default:
478 omap_revision = AM335X_REV_ES2_1;
479 cpu_rev = "2.1";
480 break;
481 }
482 break;
483 case 0xb98c:
484 switch (rev) {
485 case 0:
486 omap_revision = AM437X_REV_ES1_0;
487 cpu_rev = "1.0";
488 break;
489 case 1:
490 omap_revision = AM437X_REV_ES1_1;
491 cpu_rev = "1.1";
492 break;
493 case 2:
494 /* FALLTHROUGH */
495 default:
496 omap_revision = AM437X_REV_ES1_2;
497 cpu_rev = "1.2";
498 break;
499 }
500 break;
501 case 0xb8f2:
502 case 0xb968:
503 switch (rev) {
504 case 0:
505 /* FALLTHROUGH */
506 case 1:
507 omap_revision = TI8148_REV_ES1_0;
508 cpu_rev = "1.0";
509 break;
510 case 2:
511 omap_revision = TI8148_REV_ES2_0;
512 cpu_rev = "2.0";
513 break;
514 case 3:
515 /* FALLTHROUGH */
516 default:
517 omap_revision = TI8148_REV_ES2_1;
518 cpu_rev = "2.1";
519 break;
520 }
521 break;
522 default:
523 /* Unknown default to latest silicon rev as default */
524 omap_revision = OMAP3630_REV_ES1_2;
525 cpu_rev = "1.2";
526 pr_warn("Warning: unknown chip type: hawkeye %04x, assuming OMAP3630ES1.2\n",
527 hawkeye);
528 }
529 sprintf(soc_rev, "ES%s", cpu_rev);
530}
531
532void __init omap4xxx_check_revision(void)
533{
534 u32 idcode;
535 u16 hawkeye;
536 u8 rev;
537
538 /*
539 * The IC rev detection is done with hawkeye and rev.
540 * Note that rev does not map directly to defined processor
541 * revision numbers as ES1.0 uses value 0.
542 */
543 idcode = read_tap_reg(OMAP_TAP_IDCODE);
544 hawkeye = (idcode >> 12) & 0xffff;
545 rev = (idcode >> 28) & 0xf;
546
547 /*
548 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
549 * Use ARM register to detect the correct ES version
550 */
551 if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
552 idcode = read_cpuid_id();
553 rev = (idcode & 0xf) - 1;
554 }
555
556 switch (hawkeye) {
557 case 0xb852:
558 switch (rev) {
559 case 0:
560 omap_revision = OMAP4430_REV_ES1_0;
561 break;
562 case 1:
563 default:
564 omap_revision = OMAP4430_REV_ES2_0;
565 }
566 break;
567 case 0xb95c:
568 switch (rev) {
569 case 3:
570 omap_revision = OMAP4430_REV_ES2_1;
571 break;
572 case 4:
573 omap_revision = OMAP4430_REV_ES2_2;
574 break;
575 case 6:
576 default:
577 omap_revision = OMAP4430_REV_ES2_3;
578 }
579 break;
580 case 0xb94e:
581 switch (rev) {
582 case 0:
583 omap_revision = OMAP4460_REV_ES1_0;
584 break;
585 case 2:
586 default:
587 omap_revision = OMAP4460_REV_ES1_1;
588 break;
589 }
590 break;
591 case 0xb975:
592 switch (rev) {
593 case 0:
594 default:
595 omap_revision = OMAP4470_REV_ES1_0;
596 break;
597 }
598 break;
599 default:
600 /* Unknown default to latest silicon rev as default */
601 omap_revision = OMAP4430_REV_ES2_3;
602 }
603
604 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
605 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
606 (omap_rev() >> 8) & 0xf);
607 pr_info("%s %s\n", soc_name, soc_rev);
608}
609
610void __init omap5xxx_check_revision(void)
611{
612 u32 idcode;
613 u16 hawkeye;
614 u8 rev;
615
616 idcode = read_tap_reg(OMAP_TAP_IDCODE);
617 hawkeye = (idcode >> 12) & 0xffff;
618 rev = (idcode >> 28) & 0xff;
619 switch (hawkeye) {
620 case 0xb942:
621 switch (rev) {
622 case 0:
623 /* No support for ES1.0 Test chip */
624 BUG();
625 case 1:
626 default:
627 omap_revision = OMAP5430_REV_ES2_0;
628 }
629 break;
630
631 case 0xb998:
632 switch (rev) {
633 case 0:
634 /* No support for ES1.0 Test chip */
635 BUG();
636 case 1:
637 default:
638 omap_revision = OMAP5432_REV_ES2_0;
639 }
640 break;
641
642 default:
643 /* Unknown default to latest silicon rev as default*/
644 omap_revision = OMAP5430_REV_ES2_0;
645 }
646
647 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
648 sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
649
650 pr_info("%s %s\n", soc_name, soc_rev);
651}
652
653void __init dra7xxx_check_revision(void)
654{
655 u32 idcode;
656 u16 hawkeye;
657 u8 rev, package;
658 struct omap_die_id odi;
659
660 omap_get_die_id(&odi);
661 package = (odi.id_2 >> 16) & 0x3;
662 idcode = read_tap_reg(OMAP_TAP_IDCODE);
663 hawkeye = (idcode >> 12) & 0xffff;
664 rev = (idcode >> 28) & 0xff;
665 switch (hawkeye) {
666 case 0xbb50:
667 switch (rev) {
668 case 0:
669 default:
670 switch (package) {
671 case 0x2:
672 omap_revision = DRA762_ABZ_REV_ES1_0;
673 break;
674 case 0x3:
675 omap_revision = DRA762_ACD_REV_ES1_0;
676 break;
677 default:
678 omap_revision = DRA762_REV_ES1_0;
679 break;
680 }
681 break;
682 }
683 break;
684
685 case 0xb990:
686 switch (rev) {
687 case 0:
688 omap_revision = DRA752_REV_ES1_0;
689 break;
690 case 1:
691 omap_revision = DRA752_REV_ES1_1;
692 break;
693 case 2:
694 default:
695 omap_revision = DRA752_REV_ES2_0;
696 break;
697 }
698 break;
699
700 case 0xb9bc:
701 switch (rev) {
702 case 0:
703 omap_revision = DRA722_REV_ES1_0;
704 break;
705 case 1:
706 omap_revision = DRA722_REV_ES2_0;
707 break;
708 case 2:
709 default:
710 omap_revision = DRA722_REV_ES2_1;
711 break;
712 }
713 break;
714
715 default:
716 /* Unknown default to latest silicon rev as default*/
717 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
718 __func__, idcode, hawkeye, rev);
719 omap_revision = DRA752_REV_ES2_0;
720 }
721
722 sprintf(soc_name, "DRA%03x", omap_rev() >> 16);
723 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
724 (omap_rev() >> 8) & 0xf);
725
726 pr_info("%s %s\n", soc_name, soc_rev);
727}
728
729/*
730 * Set up things for map_io and processor detection later on. Gets called
731 * pretty much first thing from board init. For multi-omap, this gets
732 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
733 * detect the exact revision later on in omap2_detect_revision() once map_io
734 * is done.
735 */
736void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
737{
738 omap_revision = class;
739 tap_base = tap;
740
741 /* XXX What is this intended to do? */
742 if (soc_is_omap34xx())
743 tap_prod_id = 0x0210;
744 else
745 tap_prod_id = 0x0208;
746}
747
748#ifdef CONFIG_SOC_BUS
749
750static const char * const omap_types[] = {
751 [OMAP2_DEVICE_TYPE_TEST] = "TST",
752 [OMAP2_DEVICE_TYPE_EMU] = "EMU",
753 [OMAP2_DEVICE_TYPE_SEC] = "HS",
754 [OMAP2_DEVICE_TYPE_GP] = "GP",
755 [OMAP2_DEVICE_TYPE_BAD] = "BAD",
756};
757
758static const char * __init omap_get_family(void)
759{
760 if (soc_is_omap24xx())
761 return kasprintf(GFP_KERNEL, "OMAP2");
762 else if (soc_is_omap34xx())
763 return kasprintf(GFP_KERNEL, "OMAP3");
764 else if (soc_is_omap44xx())
765 return kasprintf(GFP_KERNEL, "OMAP4");
766 else if (soc_is_omap54xx())
767 return kasprintf(GFP_KERNEL, "OMAP5");
768 else if (soc_is_am33xx() || soc_is_am335x())
769 return kasprintf(GFP_KERNEL, "AM33xx");
770 else if (soc_is_am43xx())
771 return kasprintf(GFP_KERNEL, "AM43xx");
772 else if (soc_is_dra7xx())
773 return kasprintf(GFP_KERNEL, "DRA7");
774 else
775 return kasprintf(GFP_KERNEL, "Unknown");
776}
777
778static ssize_t omap_get_type(struct device *dev,
779 struct device_attribute *attr,
780 char *buf)
781{
782 return sprintf(buf, "%s\n", omap_types[omap_type()]);
783}
784
785static struct device_attribute omap_soc_attr =
786 __ATTR(type, S_IRUGO, omap_get_type, NULL);
787
788void __init omap_soc_device_init(void)
789{
790 struct device *parent;
791 struct soc_device *soc_dev;
792 struct soc_device_attribute *soc_dev_attr;
793
794 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
795 if (!soc_dev_attr)
796 return;
797
798 soc_dev_attr->machine = soc_name;
799 soc_dev_attr->family = omap_get_family();
800 soc_dev_attr->revision = soc_rev;
801
802 soc_dev = soc_device_register(soc_dev_attr);
803 if (IS_ERR(soc_dev)) {
804 kfree(soc_dev_attr);
805 return;
806 }
807
808 parent = soc_device_to_device(soc_dev);
809 device_create_file(parent, &omap_soc_attr);
810}
811#endif /* CONFIG_SOC_BUS */