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1/*
2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
10#include <linux/signal.h>
11#include <linux/slab.h>
12#include <linux/module.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
16#include <linux/ethtool.h>
17#include <linux/usb.h>
18#include <linux/crc32.h>
19#include <linux/if_vlan.h>
20#include <linux/uaccess.h>
21#include <linux/list.h>
22#include <linux/ip.h>
23#include <linux/ipv6.h>
24#include <net/ip6_checksum.h>
25
26/* Version Information */
27#define DRIVER_VERSION "v1.06.0 (2014/03/03)"
28#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
29#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
30#define MODULENAME "r8152"
31
32#define R8152_PHY_ID 32
33
34#define PLA_IDR 0xc000
35#define PLA_RCR 0xc010
36#define PLA_RMS 0xc016
37#define PLA_RXFIFO_CTRL0 0xc0a0
38#define PLA_RXFIFO_CTRL1 0xc0a4
39#define PLA_RXFIFO_CTRL2 0xc0a8
40#define PLA_FMC 0xc0b4
41#define PLA_CFG_WOL 0xc0b6
42#define PLA_TEREDO_CFG 0xc0bc
43#define PLA_MAR 0xcd00
44#define PLA_BACKUP 0xd000
45#define PAL_BDC_CR 0xd1a0
46#define PLA_TEREDO_TIMER 0xd2cc
47#define PLA_REALWOW_TIMER 0xd2e8
48#define PLA_LEDSEL 0xdd90
49#define PLA_LED_FEATURE 0xdd92
50#define PLA_PHYAR 0xde00
51#define PLA_BOOT_CTRL 0xe004
52#define PLA_GPHY_INTR_IMR 0xe022
53#define PLA_EEE_CR 0xe040
54#define PLA_EEEP_CR 0xe080
55#define PLA_MAC_PWR_CTRL 0xe0c0
56#define PLA_MAC_PWR_CTRL2 0xe0ca
57#define PLA_MAC_PWR_CTRL3 0xe0cc
58#define PLA_MAC_PWR_CTRL4 0xe0ce
59#define PLA_WDT6_CTRL 0xe428
60#define PLA_TCR0 0xe610
61#define PLA_TCR1 0xe612
62#define PLA_TXFIFO_CTRL 0xe618
63#define PLA_RSTTALLY 0xe800
64#define PLA_CR 0xe813
65#define PLA_CRWECR 0xe81c
66#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
67#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
68#define PLA_CONFIG5 0xe822
69#define PLA_PHY_PWR 0xe84c
70#define PLA_OOB_CTRL 0xe84f
71#define PLA_CPCR 0xe854
72#define PLA_MISC_0 0xe858
73#define PLA_MISC_1 0xe85a
74#define PLA_OCP_GPHY_BASE 0xe86c
75#define PLA_TALLYCNT 0xe890
76#define PLA_SFF_STS_7 0xe8de
77#define PLA_PHYSTATUS 0xe908
78#define PLA_BP_BA 0xfc26
79#define PLA_BP_0 0xfc28
80#define PLA_BP_1 0xfc2a
81#define PLA_BP_2 0xfc2c
82#define PLA_BP_3 0xfc2e
83#define PLA_BP_4 0xfc30
84#define PLA_BP_5 0xfc32
85#define PLA_BP_6 0xfc34
86#define PLA_BP_7 0xfc36
87#define PLA_BP_EN 0xfc38
88
89#define USB_U2P3_CTRL 0xb460
90#define USB_DEV_STAT 0xb808
91#define USB_USB_CTRL 0xd406
92#define USB_PHY_CTRL 0xd408
93#define USB_TX_AGG 0xd40a
94#define USB_RX_BUF_TH 0xd40c
95#define USB_USB_TIMER 0xd428
96#define USB_RX_EARLY_AGG 0xd42c
97#define USB_PM_CTRL_STATUS 0xd432
98#define USB_TX_DMA 0xd434
99#define USB_TOLERANCE 0xd490
100#define USB_LPM_CTRL 0xd41a
101#define USB_UPS_CTRL 0xd800
102#define USB_MISC_0 0xd81a
103#define USB_POWER_CUT 0xd80a
104#define USB_AFE_CTRL2 0xd824
105#define USB_WDT11_CTRL 0xe43c
106#define USB_BP_BA 0xfc26
107#define USB_BP_0 0xfc28
108#define USB_BP_1 0xfc2a
109#define USB_BP_2 0xfc2c
110#define USB_BP_3 0xfc2e
111#define USB_BP_4 0xfc30
112#define USB_BP_5 0xfc32
113#define USB_BP_6 0xfc34
114#define USB_BP_7 0xfc36
115#define USB_BP_EN 0xfc38
116
117/* OCP Registers */
118#define OCP_ALDPS_CONFIG 0x2010
119#define OCP_EEE_CONFIG1 0x2080
120#define OCP_EEE_CONFIG2 0x2092
121#define OCP_EEE_CONFIG3 0x2094
122#define OCP_BASE_MII 0xa400
123#define OCP_EEE_AR 0xa41a
124#define OCP_EEE_DATA 0xa41c
125#define OCP_PHY_STATUS 0xa420
126#define OCP_POWER_CFG 0xa430
127#define OCP_EEE_CFG 0xa432
128#define OCP_SRAM_ADDR 0xa436
129#define OCP_SRAM_DATA 0xa438
130#define OCP_DOWN_SPEED 0xa442
131#define OCP_EEE_CFG2 0xa5d0
132#define OCP_ADC_CFG 0xbc06
133
134/* SRAM Register */
135#define SRAM_LPF_CFG 0x8012
136#define SRAM_10M_AMP1 0x8080
137#define SRAM_10M_AMP2 0x8082
138#define SRAM_IMPEDANCE 0x8084
139
140/* PLA_RCR */
141#define RCR_AAP 0x00000001
142#define RCR_APM 0x00000002
143#define RCR_AM 0x00000004
144#define RCR_AB 0x00000008
145#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
146
147/* PLA_RXFIFO_CTRL0 */
148#define RXFIFO_THR1_NORMAL 0x00080002
149#define RXFIFO_THR1_OOB 0x01800003
150
151/* PLA_RXFIFO_CTRL1 */
152#define RXFIFO_THR2_FULL 0x00000060
153#define RXFIFO_THR2_HIGH 0x00000038
154#define RXFIFO_THR2_OOB 0x0000004a
155#define RXFIFO_THR2_NORMAL 0x00a0
156
157/* PLA_RXFIFO_CTRL2 */
158#define RXFIFO_THR3_FULL 0x00000078
159#define RXFIFO_THR3_HIGH 0x00000048
160#define RXFIFO_THR3_OOB 0x0000005a
161#define RXFIFO_THR3_NORMAL 0x0110
162
163/* PLA_TXFIFO_CTRL */
164#define TXFIFO_THR_NORMAL 0x00400008
165#define TXFIFO_THR_NORMAL2 0x01000008
166
167/* PLA_FMC */
168#define FMC_FCR_MCU_EN 0x0001
169
170/* PLA_EEEP_CR */
171#define EEEP_CR_EEEP_TX 0x0002
172
173/* PLA_WDT6_CTRL */
174#define WDT6_SET_MODE 0x0010
175
176/* PLA_TCR0 */
177#define TCR0_TX_EMPTY 0x0800
178#define TCR0_AUTO_FIFO 0x0080
179
180/* PLA_TCR1 */
181#define VERSION_MASK 0x7cf0
182
183/* PLA_RSTTALLY */
184#define TALLY_RESET 0x0001
185
186/* PLA_CR */
187#define CR_RST 0x10
188#define CR_RE 0x08
189#define CR_TE 0x04
190
191/* PLA_CRWECR */
192#define CRWECR_NORAML 0x00
193#define CRWECR_CONFIG 0xc0
194
195/* PLA_OOB_CTRL */
196#define NOW_IS_OOB 0x80
197#define TXFIFO_EMPTY 0x20
198#define RXFIFO_EMPTY 0x10
199#define LINK_LIST_READY 0x02
200#define DIS_MCU_CLROOB 0x01
201#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
202
203/* PLA_MISC_1 */
204#define RXDY_GATED_EN 0x0008
205
206/* PLA_SFF_STS_7 */
207#define RE_INIT_LL 0x8000
208#define MCU_BORW_EN 0x4000
209
210/* PLA_CPCR */
211#define CPCR_RX_VLAN 0x0040
212
213/* PLA_CFG_WOL */
214#define MAGIC_EN 0x0001
215
216/* PLA_TEREDO_CFG */
217#define TEREDO_SEL 0x8000
218#define TEREDO_WAKE_MASK 0x7f00
219#define TEREDO_RS_EVENT_MASK 0x00fe
220#define OOB_TEREDO_EN 0x0001
221
222/* PAL_BDC_CR */
223#define ALDPS_PROXY_MODE 0x0001
224
225/* PLA_CONFIG34 */
226#define LINK_ON_WAKE_EN 0x0010
227#define LINK_OFF_WAKE_EN 0x0008
228
229/* PLA_CONFIG5 */
230#define BWF_EN 0x0040
231#define MWF_EN 0x0020
232#define UWF_EN 0x0010
233#define LAN_WAKE_EN 0x0002
234
235/* PLA_LED_FEATURE */
236#define LED_MODE_MASK 0x0700
237
238/* PLA_PHY_PWR */
239#define TX_10M_IDLE_EN 0x0080
240#define PFM_PWM_SWITCH 0x0040
241
242/* PLA_MAC_PWR_CTRL */
243#define D3_CLK_GATED_EN 0x00004000
244#define MCU_CLK_RATIO 0x07010f07
245#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
246#define ALDPS_SPDWN_RATIO 0x0f87
247
248/* PLA_MAC_PWR_CTRL2 */
249#define EEE_SPDWN_RATIO 0x8007
250
251/* PLA_MAC_PWR_CTRL3 */
252#define PKT_AVAIL_SPDWN_EN 0x0100
253#define SUSPEND_SPDWN_EN 0x0004
254#define U1U2_SPDWN_EN 0x0002
255#define L1_SPDWN_EN 0x0001
256
257/* PLA_MAC_PWR_CTRL4 */
258#define PWRSAVE_SPDWN_EN 0x1000
259#define RXDV_SPDWN_EN 0x0800
260#define TX10MIDLE_EN 0x0100
261#define TP100_SPDWN_EN 0x0020
262#define TP500_SPDWN_EN 0x0010
263#define TP1000_SPDWN_EN 0x0008
264#define EEE_SPDWN_EN 0x0001
265
266/* PLA_GPHY_INTR_IMR */
267#define GPHY_STS_MSK 0x0001
268#define SPEED_DOWN_MSK 0x0002
269#define SPDWN_RXDV_MSK 0x0004
270#define SPDWN_LINKCHG_MSK 0x0008
271
272/* PLA_PHYAR */
273#define PHYAR_FLAG 0x80000000
274
275/* PLA_EEE_CR */
276#define EEE_RX_EN 0x0001
277#define EEE_TX_EN 0x0002
278
279/* PLA_BOOT_CTRL */
280#define AUTOLOAD_DONE 0x0002
281
282/* USB_DEV_STAT */
283#define STAT_SPEED_MASK 0x0006
284#define STAT_SPEED_HIGH 0x0000
285#define STAT_SPEED_FULL 0x0001
286
287/* USB_TX_AGG */
288#define TX_AGG_MAX_THRESHOLD 0x03
289
290/* USB_RX_BUF_TH */
291#define RX_THR_SUPPER 0x0c350180
292#define RX_THR_HIGH 0x7a120180
293#define RX_THR_SLOW 0xffff0180
294
295/* USB_TX_DMA */
296#define TEST_MODE_DISABLE 0x00000001
297#define TX_SIZE_ADJUST1 0x00000100
298
299/* USB_UPS_CTRL */
300#define POWER_CUT 0x0100
301
302/* USB_PM_CTRL_STATUS */
303#define RESUME_INDICATE 0x0001
304
305/* USB_USB_CTRL */
306#define RX_AGG_DISABLE 0x0010
307
308/* USB_U2P3_CTRL */
309#define U2P3_ENABLE 0x0001
310
311/* USB_POWER_CUT */
312#define PWR_EN 0x0001
313#define PHASE2_EN 0x0008
314
315/* USB_MISC_0 */
316#define PCUT_STATUS 0x0001
317
318/* USB_RX_EARLY_AGG */
319#define EARLY_AGG_SUPPER 0x0e832981
320#define EARLY_AGG_HIGH 0x0e837a12
321#define EARLY_AGG_SLOW 0x0e83ffff
322
323/* USB_WDT11_CTRL */
324#define TIMER11_EN 0x0001
325
326/* USB_LPM_CTRL */
327#define LPM_TIMER_MASK 0x0c
328#define LPM_TIMER_500MS 0x04 /* 500 ms */
329#define LPM_TIMER_500US 0x0c /* 500 us */
330
331/* USB_AFE_CTRL2 */
332#define SEN_VAL_MASK 0xf800
333#define SEN_VAL_NORMAL 0xa000
334#define SEL_RXIDLE 0x0100
335
336/* OCP_ALDPS_CONFIG */
337#define ENPWRSAVE 0x8000
338#define ENPDNPS 0x0200
339#define LINKENA 0x0100
340#define DIS_SDSAVE 0x0010
341
342/* OCP_PHY_STATUS */
343#define PHY_STAT_MASK 0x0007
344#define PHY_STAT_LAN_ON 3
345#define PHY_STAT_PWRDN 5
346
347/* OCP_POWER_CFG */
348#define EEE_CLKDIV_EN 0x8000
349#define EN_ALDPS 0x0004
350#define EN_10M_PLLOFF 0x0001
351
352/* OCP_EEE_CONFIG1 */
353#define RG_TXLPI_MSK_HFDUP 0x8000
354#define RG_MATCLR_EN 0x4000
355#define EEE_10_CAP 0x2000
356#define EEE_NWAY_EN 0x1000
357#define TX_QUIET_EN 0x0200
358#define RX_QUIET_EN 0x0100
359#define SDRISETIME 0x0010 /* bit 4 ~ 6 */
360#define RG_RXLPI_MSK_HFDUP 0x0008
361#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
362
363/* OCP_EEE_CONFIG2 */
364#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
365#define RG_DACQUIET_EN 0x0400
366#define RG_LDVQUIET_EN 0x0200
367#define RG_CKRSEL 0x0020
368#define RG_EEEPRG_EN 0x0010
369
370/* OCP_EEE_CONFIG3 */
371#define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */
372#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
373#define MSK_PH 0x0006 /* bit 0 ~ 3 */
374
375/* OCP_EEE_AR */
376/* bit[15:14] function */
377#define FUN_ADDR 0x0000
378#define FUN_DATA 0x4000
379/* bit[4:0] device addr */
380#define DEVICE_ADDR 0x0007
381
382/* OCP_EEE_DATA */
383#define EEE_ADDR 0x003C
384#define EEE_DATA 0x0002
385
386/* OCP_EEE_CFG */
387#define CTAP_SHORT_EN 0x0040
388#define EEE10_EN 0x0010
389
390/* OCP_DOWN_SPEED */
391#define EN_10M_BGOFF 0x0080
392
393/* OCP_EEE_CFG2 */
394#define MY1000_EEE 0x0004
395#define MY100_EEE 0x0002
396
397/* OCP_ADC_CFG */
398#define CKADSEL_L 0x0100
399#define ADC_EN 0x0080
400#define EN_EMI_L 0x0040
401
402/* SRAM_LPF_CFG */
403#define LPF_AUTO_TUNE 0x8000
404
405/* SRAM_10M_AMP1 */
406#define GDAC_IB_UPALL 0x0008
407
408/* SRAM_10M_AMP2 */
409#define AMP_DN 0x0200
410
411/* SRAM_IMPEDANCE */
412#define RX_DRIVING_MASK 0x6000
413
414enum rtl_register_content {
415 _1000bps = 0x10,
416 _100bps = 0x08,
417 _10bps = 0x04,
418 LINK_STATUS = 0x02,
419 FULL_DUP = 0x01,
420};
421
422#define RTL8152_MAX_TX 10
423#define RTL8152_MAX_RX 10
424#define INTBUFSIZE 2
425#define CRC_SIZE 4
426#define TX_ALIGN 4
427#define RX_ALIGN 8
428
429#define INTR_LINK 0x0004
430
431#define RTL8152_REQT_READ 0xc0
432#define RTL8152_REQT_WRITE 0x40
433#define RTL8152_REQ_GET_REGS 0x05
434#define RTL8152_REQ_SET_REGS 0x05
435
436#define BYTE_EN_DWORD 0xff
437#define BYTE_EN_WORD 0x33
438#define BYTE_EN_BYTE 0x11
439#define BYTE_EN_SIX_BYTES 0x3f
440#define BYTE_EN_START_MASK 0x0f
441#define BYTE_EN_END_MASK 0xf0
442
443#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
444#define RTL8152_TX_TIMEOUT (HZ)
445
446/* rtl8152 flags */
447enum rtl8152_flags {
448 RTL8152_UNPLUG = 0,
449 RTL8152_SET_RX_MODE,
450 WORK_ENABLE,
451 RTL8152_LINK_CHG,
452 SELECTIVE_SUSPEND,
453 PHY_RESET,
454 SCHEDULE_TASKLET,
455};
456
457/* Define these values to match your device */
458#define VENDOR_ID_REALTEK 0x0bda
459#define PRODUCT_ID_RTL8152 0x8152
460#define PRODUCT_ID_RTL8153 0x8153
461
462#define VENDOR_ID_SAMSUNG 0x04e8
463#define PRODUCT_ID_SAMSUNG 0xa101
464
465#define MCU_TYPE_PLA 0x0100
466#define MCU_TYPE_USB 0x0000
467
468#define REALTEK_USB_DEVICE(vend, prod) \
469 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC)
470
471struct tally_counter {
472 __le64 tx_packets;
473 __le64 rx_packets;
474 __le64 tx_errors;
475 __le32 rx_errors;
476 __le16 rx_missed;
477 __le16 align_errors;
478 __le32 tx_one_collision;
479 __le32 tx_multi_collision;
480 __le64 rx_unicast;
481 __le64 rx_broadcast;
482 __le32 rx_multicast;
483 __le16 tx_aborted;
484 __le16 tx_underun;
485};
486
487struct rx_desc {
488 __le32 opts1;
489#define RX_LEN_MASK 0x7fff
490
491 __le32 opts2;
492#define RD_UDP_CS (1 << 23)
493#define RD_TCP_CS (1 << 22)
494#define RD_IPV6_CS (1 << 20)
495#define RD_IPV4_CS (1 << 19)
496
497 __le32 opts3;
498#define IPF (1 << 23) /* IP checksum fail */
499#define UDPF (1 << 22) /* UDP checksum fail */
500#define TCPF (1 << 21) /* TCP checksum fail */
501
502 __le32 opts4;
503 __le32 opts5;
504 __le32 opts6;
505};
506
507struct tx_desc {
508 __le32 opts1;
509#define TX_FS (1 << 31) /* First segment of a packet */
510#define TX_LS (1 << 30) /* Final segment of a packet */
511#define GTSENDV4 (1 << 28)
512#define GTSENDV6 (1 << 27)
513#define GTTCPHO_SHIFT 18
514#define GTTCPHO_MAX 0x7fU
515#define TX_LEN_MAX 0x3ffffU
516
517 __le32 opts2;
518#define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
519#define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
520#define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
521#define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
522#define MSS_SHIFT 17
523#define MSS_MAX 0x7ffU
524#define TCPHO_SHIFT 17
525#define TCPHO_MAX 0x7ffU
526};
527
528struct r8152;
529
530struct rx_agg {
531 struct list_head list;
532 struct urb *urb;
533 struct r8152 *context;
534 void *buffer;
535 void *head;
536};
537
538struct tx_agg {
539 struct list_head list;
540 struct urb *urb;
541 struct r8152 *context;
542 void *buffer;
543 void *head;
544 u32 skb_num;
545 u32 skb_len;
546};
547
548struct r8152 {
549 unsigned long flags;
550 struct usb_device *udev;
551 struct tasklet_struct tl;
552 struct usb_interface *intf;
553 struct net_device *netdev;
554 struct urb *intr_urb;
555 struct tx_agg tx_info[RTL8152_MAX_TX];
556 struct rx_agg rx_info[RTL8152_MAX_RX];
557 struct list_head rx_done, tx_free;
558 struct sk_buff_head tx_queue;
559 spinlock_t rx_lock, tx_lock;
560 struct delayed_work schedule;
561 struct mii_if_info mii;
562
563 struct rtl_ops {
564 void (*init)(struct r8152 *);
565 int (*enable)(struct r8152 *);
566 void (*disable)(struct r8152 *);
567 void (*up)(struct r8152 *);
568 void (*down)(struct r8152 *);
569 void (*unload)(struct r8152 *);
570 } rtl_ops;
571
572 int intr_interval;
573 u32 saved_wolopts;
574 u32 msg_enable;
575 u32 tx_qlen;
576 u16 ocp_base;
577 u8 *intr_buff;
578 u8 version;
579 u8 speed;
580};
581
582enum rtl_version {
583 RTL_VER_UNKNOWN = 0,
584 RTL_VER_01,
585 RTL_VER_02,
586 RTL_VER_03,
587 RTL_VER_04,
588 RTL_VER_05,
589 RTL_VER_MAX
590};
591
592enum tx_csum_stat {
593 TX_CSUM_SUCCESS = 0,
594 TX_CSUM_TSO,
595 TX_CSUM_NONE
596};
597
598/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
599 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
600 */
601static const int multicast_filter_limit = 32;
602static unsigned int rx_buf_sz = 16384;
603
604#define RTL_LIMITED_TSO_SIZE (rx_buf_sz - sizeof(struct tx_desc) - \
605 VLAN_ETH_HLEN - VLAN_HLEN)
606
607static
608int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
609{
610 int ret;
611 void *tmp;
612
613 tmp = kmalloc(size, GFP_KERNEL);
614 if (!tmp)
615 return -ENOMEM;
616
617 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
618 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
619 value, index, tmp, size, 500);
620
621 memcpy(data, tmp, size);
622 kfree(tmp);
623
624 return ret;
625}
626
627static
628int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
629{
630 int ret;
631 void *tmp;
632
633 tmp = kmalloc(size, GFP_KERNEL);
634 if (!tmp)
635 return -ENOMEM;
636
637 memcpy(tmp, data, size);
638
639 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
640 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
641 value, index, tmp, size, 500);
642
643 kfree(tmp);
644
645 return ret;
646}
647
648static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
649 void *data, u16 type)
650{
651 u16 limit = 64;
652 int ret = 0;
653
654 if (test_bit(RTL8152_UNPLUG, &tp->flags))
655 return -ENODEV;
656
657 /* both size and indix must be 4 bytes align */
658 if ((size & 3) || !size || (index & 3) || !data)
659 return -EPERM;
660
661 if ((u32)index + (u32)size > 0xffff)
662 return -EPERM;
663
664 while (size) {
665 if (size > limit) {
666 ret = get_registers(tp, index, type, limit, data);
667 if (ret < 0)
668 break;
669
670 index += limit;
671 data += limit;
672 size -= limit;
673 } else {
674 ret = get_registers(tp, index, type, size, data);
675 if (ret < 0)
676 break;
677
678 index += size;
679 data += size;
680 size = 0;
681 break;
682 }
683 }
684
685 return ret;
686}
687
688static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
689 u16 size, void *data, u16 type)
690{
691 int ret;
692 u16 byteen_start, byteen_end, byen;
693 u16 limit = 512;
694
695 if (test_bit(RTL8152_UNPLUG, &tp->flags))
696 return -ENODEV;
697
698 /* both size and indix must be 4 bytes align */
699 if ((size & 3) || !size || (index & 3) || !data)
700 return -EPERM;
701
702 if ((u32)index + (u32)size > 0xffff)
703 return -EPERM;
704
705 byteen_start = byteen & BYTE_EN_START_MASK;
706 byteen_end = byteen & BYTE_EN_END_MASK;
707
708 byen = byteen_start | (byteen_start << 4);
709 ret = set_registers(tp, index, type | byen, 4, data);
710 if (ret < 0)
711 goto error1;
712
713 index += 4;
714 data += 4;
715 size -= 4;
716
717 if (size) {
718 size -= 4;
719
720 while (size) {
721 if (size > limit) {
722 ret = set_registers(tp, index,
723 type | BYTE_EN_DWORD,
724 limit, data);
725 if (ret < 0)
726 goto error1;
727
728 index += limit;
729 data += limit;
730 size -= limit;
731 } else {
732 ret = set_registers(tp, index,
733 type | BYTE_EN_DWORD,
734 size, data);
735 if (ret < 0)
736 goto error1;
737
738 index += size;
739 data += size;
740 size = 0;
741 break;
742 }
743 }
744
745 byen = byteen_end | (byteen_end >> 4);
746 ret = set_registers(tp, index, type | byen, 4, data);
747 if (ret < 0)
748 goto error1;
749 }
750
751error1:
752 return ret;
753}
754
755static inline
756int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
757{
758 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
759}
760
761static inline
762int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
763{
764 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
765}
766
767static inline
768int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
769{
770 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
771}
772
773static inline
774int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
775{
776 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
777}
778
779static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
780{
781 __le32 data;
782
783 generic_ocp_read(tp, index, sizeof(data), &data, type);
784
785 return __le32_to_cpu(data);
786}
787
788static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
789{
790 __le32 tmp = __cpu_to_le32(data);
791
792 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
793}
794
795static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
796{
797 u32 data;
798 __le32 tmp;
799 u8 shift = index & 2;
800
801 index &= ~3;
802
803 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
804
805 data = __le32_to_cpu(tmp);
806 data >>= (shift * 8);
807 data &= 0xffff;
808
809 return (u16)data;
810}
811
812static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
813{
814 u32 mask = 0xffff;
815 __le32 tmp;
816 u16 byen = BYTE_EN_WORD;
817 u8 shift = index & 2;
818
819 data &= mask;
820
821 if (index & 2) {
822 byen <<= shift;
823 mask <<= (shift * 8);
824 data <<= (shift * 8);
825 index &= ~3;
826 }
827
828 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
829
830 data |= __le32_to_cpu(tmp) & ~mask;
831 tmp = __cpu_to_le32(data);
832
833 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
834}
835
836static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
837{
838 u32 data;
839 __le32 tmp;
840 u8 shift = index & 3;
841
842 index &= ~3;
843
844 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
845
846 data = __le32_to_cpu(tmp);
847 data >>= (shift * 8);
848 data &= 0xff;
849
850 return (u8)data;
851}
852
853static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
854{
855 u32 mask = 0xff;
856 __le32 tmp;
857 u16 byen = BYTE_EN_BYTE;
858 u8 shift = index & 3;
859
860 data &= mask;
861
862 if (index & 3) {
863 byen <<= shift;
864 mask <<= (shift * 8);
865 data <<= (shift * 8);
866 index &= ~3;
867 }
868
869 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
870
871 data |= __le32_to_cpu(tmp) & ~mask;
872 tmp = __cpu_to_le32(data);
873
874 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
875}
876
877static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
878{
879 u16 ocp_base, ocp_index;
880
881 ocp_base = addr & 0xf000;
882 if (ocp_base != tp->ocp_base) {
883 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
884 tp->ocp_base = ocp_base;
885 }
886
887 ocp_index = (addr & 0x0fff) | 0xb000;
888 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
889}
890
891static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
892{
893 u16 ocp_base, ocp_index;
894
895 ocp_base = addr & 0xf000;
896 if (ocp_base != tp->ocp_base) {
897 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
898 tp->ocp_base = ocp_base;
899 }
900
901 ocp_index = (addr & 0x0fff) | 0xb000;
902 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
903}
904
905static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
906{
907 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
908}
909
910static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
911{
912 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
913}
914
915static void sram_write(struct r8152 *tp, u16 addr, u16 data)
916{
917 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
918 ocp_reg_write(tp, OCP_SRAM_DATA, data);
919}
920
921static u16 sram_read(struct r8152 *tp, u16 addr)
922{
923 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
924 return ocp_reg_read(tp, OCP_SRAM_DATA);
925}
926
927static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
928{
929 struct r8152 *tp = netdev_priv(netdev);
930 int ret;
931
932 if (test_bit(RTL8152_UNPLUG, &tp->flags))
933 return -ENODEV;
934
935 if (phy_id != R8152_PHY_ID)
936 return -EINVAL;
937
938 ret = usb_autopm_get_interface(tp->intf);
939 if (ret < 0)
940 goto out;
941
942 ret = r8152_mdio_read(tp, reg);
943
944 usb_autopm_put_interface(tp->intf);
945
946out:
947 return ret;
948}
949
950static
951void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
952{
953 struct r8152 *tp = netdev_priv(netdev);
954
955 if (test_bit(RTL8152_UNPLUG, &tp->flags))
956 return;
957
958 if (phy_id != R8152_PHY_ID)
959 return;
960
961 if (usb_autopm_get_interface(tp->intf) < 0)
962 return;
963
964 r8152_mdio_write(tp, reg, val);
965
966 usb_autopm_put_interface(tp->intf);
967}
968
969static
970int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
971
972static inline void set_ethernet_addr(struct r8152 *tp)
973{
974 struct net_device *dev = tp->netdev;
975 int ret;
976 u8 node_id[8] = {0};
977
978 if (tp->version == RTL_VER_01)
979 ret = pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id);
980 else
981 ret = pla_ocp_read(tp, PLA_BACKUP, sizeof(node_id), node_id);
982
983 if (ret < 0) {
984 netif_notice(tp, probe, dev, "inet addr fail\n");
985 } else {
986 if (tp->version != RTL_VER_01) {
987 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR,
988 CRWECR_CONFIG);
989 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES,
990 sizeof(node_id), node_id);
991 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR,
992 CRWECR_NORAML);
993 }
994
995 memcpy(dev->dev_addr, node_id, dev->addr_len);
996 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
997 }
998}
999
1000static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1001{
1002 struct r8152 *tp = netdev_priv(netdev);
1003 struct sockaddr *addr = p;
1004
1005 if (!is_valid_ether_addr(addr->sa_data))
1006 return -EADDRNOTAVAIL;
1007
1008 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1009
1010 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1011 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1012 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1013
1014 return 0;
1015}
1016
1017static void read_bulk_callback(struct urb *urb)
1018{
1019 struct net_device *netdev;
1020 int status = urb->status;
1021 struct rx_agg *agg;
1022 struct r8152 *tp;
1023 int result;
1024
1025 agg = urb->context;
1026 if (!agg)
1027 return;
1028
1029 tp = agg->context;
1030 if (!tp)
1031 return;
1032
1033 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1034 return;
1035
1036 if (!test_bit(WORK_ENABLE, &tp->flags))
1037 return;
1038
1039 netdev = tp->netdev;
1040
1041 /* When link down, the driver would cancel all bulks. */
1042 /* This avoid the re-submitting bulk */
1043 if (!netif_carrier_ok(netdev))
1044 return;
1045
1046 usb_mark_last_busy(tp->udev);
1047
1048 switch (status) {
1049 case 0:
1050 if (urb->actual_length < ETH_ZLEN)
1051 break;
1052
1053 spin_lock(&tp->rx_lock);
1054 list_add_tail(&agg->list, &tp->rx_done);
1055 spin_unlock(&tp->rx_lock);
1056 tasklet_schedule(&tp->tl);
1057 return;
1058 case -ESHUTDOWN:
1059 set_bit(RTL8152_UNPLUG, &tp->flags);
1060 netif_device_detach(tp->netdev);
1061 return;
1062 case -ENOENT:
1063 return; /* the urb is in unlink state */
1064 case -ETIME:
1065 if (net_ratelimit())
1066 netdev_warn(netdev, "maybe reset is needed?\n");
1067 break;
1068 default:
1069 if (net_ratelimit())
1070 netdev_warn(netdev, "Rx status %d\n", status);
1071 break;
1072 }
1073
1074 result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1075 if (result == -ENODEV) {
1076 netif_device_detach(tp->netdev);
1077 } else if (result) {
1078 spin_lock(&tp->rx_lock);
1079 list_add_tail(&agg->list, &tp->rx_done);
1080 spin_unlock(&tp->rx_lock);
1081 tasklet_schedule(&tp->tl);
1082 }
1083}
1084
1085static void write_bulk_callback(struct urb *urb)
1086{
1087 struct net_device_stats *stats;
1088 struct net_device *netdev;
1089 struct tx_agg *agg;
1090 struct r8152 *tp;
1091 int status = urb->status;
1092
1093 agg = urb->context;
1094 if (!agg)
1095 return;
1096
1097 tp = agg->context;
1098 if (!tp)
1099 return;
1100
1101 netdev = tp->netdev;
1102 stats = &netdev->stats;
1103 if (status) {
1104 if (net_ratelimit())
1105 netdev_warn(netdev, "Tx status %d\n", status);
1106 stats->tx_errors += agg->skb_num;
1107 } else {
1108 stats->tx_packets += agg->skb_num;
1109 stats->tx_bytes += agg->skb_len;
1110 }
1111
1112 spin_lock(&tp->tx_lock);
1113 list_add_tail(&agg->list, &tp->tx_free);
1114 spin_unlock(&tp->tx_lock);
1115
1116 usb_autopm_put_interface_async(tp->intf);
1117
1118 if (!netif_carrier_ok(netdev))
1119 return;
1120
1121 if (!test_bit(WORK_ENABLE, &tp->flags))
1122 return;
1123
1124 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1125 return;
1126
1127 if (!skb_queue_empty(&tp->tx_queue))
1128 tasklet_schedule(&tp->tl);
1129}
1130
1131static void intr_callback(struct urb *urb)
1132{
1133 struct r8152 *tp;
1134 __le16 *d;
1135 int status = urb->status;
1136 int res;
1137
1138 tp = urb->context;
1139 if (!tp)
1140 return;
1141
1142 if (!test_bit(WORK_ENABLE, &tp->flags))
1143 return;
1144
1145 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1146 return;
1147
1148 switch (status) {
1149 case 0: /* success */
1150 break;
1151 case -ECONNRESET: /* unlink */
1152 case -ESHUTDOWN:
1153 netif_device_detach(tp->netdev);
1154 case -ENOENT:
1155 return;
1156 case -EOVERFLOW:
1157 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1158 goto resubmit;
1159 /* -EPIPE: should clear the halt */
1160 default:
1161 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1162 goto resubmit;
1163 }
1164
1165 d = urb->transfer_buffer;
1166 if (INTR_LINK & __le16_to_cpu(d[0])) {
1167 if (!(tp->speed & LINK_STATUS)) {
1168 set_bit(RTL8152_LINK_CHG, &tp->flags);
1169 schedule_delayed_work(&tp->schedule, 0);
1170 }
1171 } else {
1172 if (tp->speed & LINK_STATUS) {
1173 set_bit(RTL8152_LINK_CHG, &tp->flags);
1174 schedule_delayed_work(&tp->schedule, 0);
1175 }
1176 }
1177
1178resubmit:
1179 res = usb_submit_urb(urb, GFP_ATOMIC);
1180 if (res == -ENODEV)
1181 netif_device_detach(tp->netdev);
1182 else if (res)
1183 netif_err(tp, intr, tp->netdev,
1184 "can't resubmit intr, status %d\n", res);
1185}
1186
1187static inline void *rx_agg_align(void *data)
1188{
1189 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1190}
1191
1192static inline void *tx_agg_align(void *data)
1193{
1194 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1195}
1196
1197static void free_all_mem(struct r8152 *tp)
1198{
1199 int i;
1200
1201 for (i = 0; i < RTL8152_MAX_RX; i++) {
1202 usb_free_urb(tp->rx_info[i].urb);
1203 tp->rx_info[i].urb = NULL;
1204
1205 kfree(tp->rx_info[i].buffer);
1206 tp->rx_info[i].buffer = NULL;
1207 tp->rx_info[i].head = NULL;
1208 }
1209
1210 for (i = 0; i < RTL8152_MAX_TX; i++) {
1211 usb_free_urb(tp->tx_info[i].urb);
1212 tp->tx_info[i].urb = NULL;
1213
1214 kfree(tp->tx_info[i].buffer);
1215 tp->tx_info[i].buffer = NULL;
1216 tp->tx_info[i].head = NULL;
1217 }
1218
1219 usb_free_urb(tp->intr_urb);
1220 tp->intr_urb = NULL;
1221
1222 kfree(tp->intr_buff);
1223 tp->intr_buff = NULL;
1224}
1225
1226static int alloc_all_mem(struct r8152 *tp)
1227{
1228 struct net_device *netdev = tp->netdev;
1229 struct usb_interface *intf = tp->intf;
1230 struct usb_host_interface *alt = intf->cur_altsetting;
1231 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1232 struct urb *urb;
1233 int node, i;
1234 u8 *buf;
1235
1236 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1237
1238 spin_lock_init(&tp->rx_lock);
1239 spin_lock_init(&tp->tx_lock);
1240 INIT_LIST_HEAD(&tp->rx_done);
1241 INIT_LIST_HEAD(&tp->tx_free);
1242 skb_queue_head_init(&tp->tx_queue);
1243
1244 for (i = 0; i < RTL8152_MAX_RX; i++) {
1245 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1246 if (!buf)
1247 goto err1;
1248
1249 if (buf != rx_agg_align(buf)) {
1250 kfree(buf);
1251 buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL,
1252 node);
1253 if (!buf)
1254 goto err1;
1255 }
1256
1257 urb = usb_alloc_urb(0, GFP_KERNEL);
1258 if (!urb) {
1259 kfree(buf);
1260 goto err1;
1261 }
1262
1263 INIT_LIST_HEAD(&tp->rx_info[i].list);
1264 tp->rx_info[i].context = tp;
1265 tp->rx_info[i].urb = urb;
1266 tp->rx_info[i].buffer = buf;
1267 tp->rx_info[i].head = rx_agg_align(buf);
1268 }
1269
1270 for (i = 0; i < RTL8152_MAX_TX; i++) {
1271 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1272 if (!buf)
1273 goto err1;
1274
1275 if (buf != tx_agg_align(buf)) {
1276 kfree(buf);
1277 buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL,
1278 node);
1279 if (!buf)
1280 goto err1;
1281 }
1282
1283 urb = usb_alloc_urb(0, GFP_KERNEL);
1284 if (!urb) {
1285 kfree(buf);
1286 goto err1;
1287 }
1288
1289 INIT_LIST_HEAD(&tp->tx_info[i].list);
1290 tp->tx_info[i].context = tp;
1291 tp->tx_info[i].urb = urb;
1292 tp->tx_info[i].buffer = buf;
1293 tp->tx_info[i].head = tx_agg_align(buf);
1294
1295 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1296 }
1297
1298 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1299 if (!tp->intr_urb)
1300 goto err1;
1301
1302 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1303 if (!tp->intr_buff)
1304 goto err1;
1305
1306 tp->intr_interval = (int)ep_intr->desc.bInterval;
1307 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1308 tp->intr_buff, INTBUFSIZE, intr_callback,
1309 tp, tp->intr_interval);
1310
1311 return 0;
1312
1313err1:
1314 free_all_mem(tp);
1315 return -ENOMEM;
1316}
1317
1318static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1319{
1320 struct tx_agg *agg = NULL;
1321 unsigned long flags;
1322
1323 if (list_empty(&tp->tx_free))
1324 return NULL;
1325
1326 spin_lock_irqsave(&tp->tx_lock, flags);
1327 if (!list_empty(&tp->tx_free)) {
1328 struct list_head *cursor;
1329
1330 cursor = tp->tx_free.next;
1331 list_del_init(cursor);
1332 agg = list_entry(cursor, struct tx_agg, list);
1333 }
1334 spin_unlock_irqrestore(&tp->tx_lock, flags);
1335
1336 return agg;
1337}
1338
1339static inline __be16 get_protocol(struct sk_buff *skb)
1340{
1341 __be16 protocol;
1342
1343 if (skb->protocol == htons(ETH_P_8021Q))
1344 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1345 else
1346 protocol = skb->protocol;
1347
1348 return protocol;
1349}
1350
1351/*
1352 * r8152_csum_workaround()
1353 * The hw limites the value the transport offset. When the offset is out of the
1354 * range, calculate the checksum by sw.
1355 */
1356static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1357 struct sk_buff_head *list)
1358{
1359 if (skb_shinfo(skb)->gso_size) {
1360 netdev_features_t features = tp->netdev->features;
1361 struct sk_buff_head seg_list;
1362 struct sk_buff *segs, *nskb;
1363
1364 features &= ~(NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO);
1365 segs = skb_gso_segment(skb, features);
1366 if (IS_ERR(segs) || !segs)
1367 goto drop;
1368
1369 __skb_queue_head_init(&seg_list);
1370
1371 do {
1372 nskb = segs;
1373 segs = segs->next;
1374 nskb->next = NULL;
1375 __skb_queue_tail(&seg_list, nskb);
1376 } while (segs);
1377
1378 skb_queue_splice(&seg_list, list);
1379 dev_kfree_skb(skb);
1380 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1381 if (skb_checksum_help(skb) < 0)
1382 goto drop;
1383
1384 __skb_queue_head(list, skb);
1385 } else {
1386 struct net_device_stats *stats;
1387
1388drop:
1389 stats = &tp->netdev->stats;
1390 stats->tx_dropped++;
1391 dev_kfree_skb(skb);
1392 }
1393}
1394
1395/*
1396 * msdn_giant_send_check()
1397 * According to the document of microsoft, the TCP Pseudo Header excludes the
1398 * packet length for IPv6 TCP large packets.
1399 */
1400static int msdn_giant_send_check(struct sk_buff *skb)
1401{
1402 const struct ipv6hdr *ipv6h;
1403 struct tcphdr *th;
1404 int ret;
1405
1406 ret = skb_cow_head(skb, 0);
1407 if (ret)
1408 return ret;
1409
1410 ipv6h = ipv6_hdr(skb);
1411 th = tcp_hdr(skb);
1412
1413 th->check = 0;
1414 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1415
1416 return ret;
1417}
1418
1419static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1420 struct sk_buff *skb, u32 len, u32 transport_offset)
1421{
1422 u32 mss = skb_shinfo(skb)->gso_size;
1423 u32 opts1, opts2 = 0;
1424 int ret = TX_CSUM_SUCCESS;
1425
1426 WARN_ON_ONCE(len > TX_LEN_MAX);
1427
1428 opts1 = len | TX_FS | TX_LS;
1429
1430 if (mss) {
1431 if (transport_offset > GTTCPHO_MAX) {
1432 netif_warn(tp, tx_err, tp->netdev,
1433 "Invalid transport offset 0x%x for TSO\n",
1434 transport_offset);
1435 ret = TX_CSUM_TSO;
1436 goto unavailable;
1437 }
1438
1439 switch (get_protocol(skb)) {
1440 case htons(ETH_P_IP):
1441 opts1 |= GTSENDV4;
1442 break;
1443
1444 case htons(ETH_P_IPV6):
1445 if (msdn_giant_send_check(skb)) {
1446 ret = TX_CSUM_TSO;
1447 goto unavailable;
1448 }
1449 opts1 |= GTSENDV6;
1450 break;
1451
1452 default:
1453 WARN_ON_ONCE(1);
1454 break;
1455 }
1456
1457 opts1 |= transport_offset << GTTCPHO_SHIFT;
1458 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1459 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1460 u8 ip_protocol;
1461
1462 if (transport_offset > TCPHO_MAX) {
1463 netif_warn(tp, tx_err, tp->netdev,
1464 "Invalid transport offset 0x%x\n",
1465 transport_offset);
1466 ret = TX_CSUM_NONE;
1467 goto unavailable;
1468 }
1469
1470 switch (get_protocol(skb)) {
1471 case htons(ETH_P_IP):
1472 opts2 |= IPV4_CS;
1473 ip_protocol = ip_hdr(skb)->protocol;
1474 break;
1475
1476 case htons(ETH_P_IPV6):
1477 opts2 |= IPV6_CS;
1478 ip_protocol = ipv6_hdr(skb)->nexthdr;
1479 break;
1480
1481 default:
1482 ip_protocol = IPPROTO_RAW;
1483 break;
1484 }
1485
1486 if (ip_protocol == IPPROTO_TCP)
1487 opts2 |= TCP_CS;
1488 else if (ip_protocol == IPPROTO_UDP)
1489 opts2 |= UDP_CS;
1490 else
1491 WARN_ON_ONCE(1);
1492
1493 opts2 |= transport_offset << TCPHO_SHIFT;
1494 }
1495
1496 desc->opts2 = cpu_to_le32(opts2);
1497 desc->opts1 = cpu_to_le32(opts1);
1498
1499unavailable:
1500 return ret;
1501}
1502
1503static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1504{
1505 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1506 int remain, ret;
1507 u8 *tx_data;
1508
1509 __skb_queue_head_init(&skb_head);
1510 spin_lock(&tx_queue->lock);
1511 skb_queue_splice_init(tx_queue, &skb_head);
1512 spin_unlock(&tx_queue->lock);
1513
1514 tx_data = agg->head;
1515 agg->skb_num = agg->skb_len = 0;
1516 remain = rx_buf_sz;
1517
1518 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1519 struct tx_desc *tx_desc;
1520 struct sk_buff *skb;
1521 unsigned int len;
1522 u32 offset;
1523
1524 skb = __skb_dequeue(&skb_head);
1525 if (!skb)
1526 break;
1527
1528 len = skb->len + sizeof(*tx_desc);
1529
1530 if (len > remain) {
1531 __skb_queue_head(&skb_head, skb);
1532 break;
1533 }
1534
1535 tx_data = tx_agg_align(tx_data);
1536 tx_desc = (struct tx_desc *)tx_data;
1537
1538 offset = (u32)skb_transport_offset(skb);
1539
1540 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1541 r8152_csum_workaround(tp, skb, &skb_head);
1542 continue;
1543 }
1544
1545 tx_data += sizeof(*tx_desc);
1546
1547 len = skb->len;
1548 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1549 struct net_device_stats *stats = &tp->netdev->stats;
1550
1551 stats->tx_dropped++;
1552 dev_kfree_skb_any(skb);
1553 tx_data -= sizeof(*tx_desc);
1554 continue;
1555 }
1556
1557 tx_data += len;
1558 agg->skb_len += len;
1559 agg->skb_num++;
1560
1561 dev_kfree_skb_any(skb);
1562
1563 remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1564 }
1565
1566 if (!skb_queue_empty(&skb_head)) {
1567 spin_lock(&tx_queue->lock);
1568 skb_queue_splice(&skb_head, tx_queue);
1569 spin_unlock(&tx_queue->lock);
1570 }
1571
1572 netif_tx_lock(tp->netdev);
1573
1574 if (netif_queue_stopped(tp->netdev) &&
1575 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1576 netif_wake_queue(tp->netdev);
1577
1578 netif_tx_unlock(tp->netdev);
1579
1580 ret = usb_autopm_get_interface_async(tp->intf);
1581 if (ret < 0)
1582 goto out_tx_fill;
1583
1584 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1585 agg->head, (int)(tx_data - (u8 *)agg->head),
1586 (usb_complete_t)write_bulk_callback, agg);
1587
1588 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1589 if (ret < 0)
1590 usb_autopm_put_interface_async(tp->intf);
1591
1592out_tx_fill:
1593 return ret;
1594}
1595
1596static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1597{
1598 u8 checksum = CHECKSUM_NONE;
1599 u32 opts2, opts3;
1600
1601 if (tp->version == RTL_VER_01)
1602 goto return_result;
1603
1604 opts2 = le32_to_cpu(rx_desc->opts2);
1605 opts3 = le32_to_cpu(rx_desc->opts3);
1606
1607 if (opts2 & RD_IPV4_CS) {
1608 if (opts3 & IPF)
1609 checksum = CHECKSUM_NONE;
1610 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1611 checksum = CHECKSUM_NONE;
1612 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1613 checksum = CHECKSUM_NONE;
1614 else
1615 checksum = CHECKSUM_UNNECESSARY;
1616 } else if (RD_IPV6_CS) {
1617 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1618 checksum = CHECKSUM_UNNECESSARY;
1619 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1620 checksum = CHECKSUM_UNNECESSARY;
1621 }
1622
1623return_result:
1624 return checksum;
1625}
1626
1627static void rx_bottom(struct r8152 *tp)
1628{
1629 unsigned long flags;
1630 struct list_head *cursor, *next, rx_queue;
1631
1632 if (list_empty(&tp->rx_done))
1633 return;
1634
1635 INIT_LIST_HEAD(&rx_queue);
1636 spin_lock_irqsave(&tp->rx_lock, flags);
1637 list_splice_init(&tp->rx_done, &rx_queue);
1638 spin_unlock_irqrestore(&tp->rx_lock, flags);
1639
1640 list_for_each_safe(cursor, next, &rx_queue) {
1641 struct rx_desc *rx_desc;
1642 struct rx_agg *agg;
1643 int len_used = 0;
1644 struct urb *urb;
1645 u8 *rx_data;
1646 int ret;
1647
1648 list_del_init(cursor);
1649
1650 agg = list_entry(cursor, struct rx_agg, list);
1651 urb = agg->urb;
1652 if (urb->actual_length < ETH_ZLEN)
1653 goto submit;
1654
1655 rx_desc = agg->head;
1656 rx_data = agg->head;
1657 len_used += sizeof(struct rx_desc);
1658
1659 while (urb->actual_length > len_used) {
1660 struct net_device *netdev = tp->netdev;
1661 struct net_device_stats *stats = &netdev->stats;
1662 unsigned int pkt_len;
1663 struct sk_buff *skb;
1664
1665 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1666 if (pkt_len < ETH_ZLEN)
1667 break;
1668
1669 len_used += pkt_len;
1670 if (urb->actual_length < len_used)
1671 break;
1672
1673 pkt_len -= CRC_SIZE;
1674 rx_data += sizeof(struct rx_desc);
1675
1676 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1677 if (!skb) {
1678 stats->rx_dropped++;
1679 goto find_next_rx;
1680 }
1681
1682 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1683 memcpy(skb->data, rx_data, pkt_len);
1684 skb_put(skb, pkt_len);
1685 skb->protocol = eth_type_trans(skb, netdev);
1686 netif_receive_skb(skb);
1687 stats->rx_packets++;
1688 stats->rx_bytes += pkt_len;
1689
1690find_next_rx:
1691 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1692 rx_desc = (struct rx_desc *)rx_data;
1693 len_used = (int)(rx_data - (u8 *)agg->head);
1694 len_used += sizeof(struct rx_desc);
1695 }
1696
1697submit:
1698 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1699 if (ret && ret != -ENODEV) {
1700 spin_lock_irqsave(&tp->rx_lock, flags);
1701 list_add_tail(&agg->list, &tp->rx_done);
1702 spin_unlock_irqrestore(&tp->rx_lock, flags);
1703 tasklet_schedule(&tp->tl);
1704 }
1705 }
1706}
1707
1708static void tx_bottom(struct r8152 *tp)
1709{
1710 int res;
1711
1712 do {
1713 struct tx_agg *agg;
1714
1715 if (skb_queue_empty(&tp->tx_queue))
1716 break;
1717
1718 agg = r8152_get_tx_agg(tp);
1719 if (!agg)
1720 break;
1721
1722 res = r8152_tx_agg_fill(tp, agg);
1723 if (res) {
1724 struct net_device *netdev = tp->netdev;
1725
1726 if (res == -ENODEV) {
1727 netif_device_detach(netdev);
1728 } else {
1729 struct net_device_stats *stats = &netdev->stats;
1730 unsigned long flags;
1731
1732 netif_warn(tp, tx_err, netdev,
1733 "failed tx_urb %d\n", res);
1734 stats->tx_dropped += agg->skb_num;
1735
1736 spin_lock_irqsave(&tp->tx_lock, flags);
1737 list_add_tail(&agg->list, &tp->tx_free);
1738 spin_unlock_irqrestore(&tp->tx_lock, flags);
1739 }
1740 }
1741 } while (res == 0);
1742}
1743
1744static void bottom_half(unsigned long data)
1745{
1746 struct r8152 *tp;
1747
1748 tp = (struct r8152 *)data;
1749
1750 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1751 return;
1752
1753 if (!test_bit(WORK_ENABLE, &tp->flags))
1754 return;
1755
1756 /* When link down, the driver would cancel all bulks. */
1757 /* This avoid the re-submitting bulk */
1758 if (!netif_carrier_ok(tp->netdev))
1759 return;
1760
1761 rx_bottom(tp);
1762 tx_bottom(tp);
1763}
1764
1765static
1766int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1767{
1768 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1769 agg->head, rx_buf_sz,
1770 (usb_complete_t)read_bulk_callback, agg);
1771
1772 return usb_submit_urb(agg->urb, mem_flags);
1773}
1774
1775static void rtl_drop_queued_tx(struct r8152 *tp)
1776{
1777 struct net_device_stats *stats = &tp->netdev->stats;
1778 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1779 struct sk_buff *skb;
1780
1781 if (skb_queue_empty(tx_queue))
1782 return;
1783
1784 __skb_queue_head_init(&skb_head);
1785 spin_lock_bh(&tx_queue->lock);
1786 skb_queue_splice_init(tx_queue, &skb_head);
1787 spin_unlock_bh(&tx_queue->lock);
1788
1789 while ((skb = __skb_dequeue(&skb_head))) {
1790 dev_kfree_skb(skb);
1791 stats->tx_dropped++;
1792 }
1793}
1794
1795static void rtl8152_tx_timeout(struct net_device *netdev)
1796{
1797 struct r8152 *tp = netdev_priv(netdev);
1798 int i;
1799
1800 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1801 for (i = 0; i < RTL8152_MAX_TX; i++)
1802 usb_unlink_urb(tp->tx_info[i].urb);
1803}
1804
1805static void rtl8152_set_rx_mode(struct net_device *netdev)
1806{
1807 struct r8152 *tp = netdev_priv(netdev);
1808
1809 if (tp->speed & LINK_STATUS) {
1810 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1811 schedule_delayed_work(&tp->schedule, 0);
1812 }
1813}
1814
1815static void _rtl8152_set_rx_mode(struct net_device *netdev)
1816{
1817 struct r8152 *tp = netdev_priv(netdev);
1818 u32 mc_filter[2]; /* Multicast hash filter */
1819 __le32 tmp[2];
1820 u32 ocp_data;
1821
1822 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1823 netif_stop_queue(netdev);
1824 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1825 ocp_data &= ~RCR_ACPT_ALL;
1826 ocp_data |= RCR_AB | RCR_APM;
1827
1828 if (netdev->flags & IFF_PROMISC) {
1829 /* Unconditionally log net taps. */
1830 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1831 ocp_data |= RCR_AM | RCR_AAP;
1832 mc_filter[1] = mc_filter[0] = 0xffffffff;
1833 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1834 (netdev->flags & IFF_ALLMULTI)) {
1835 /* Too many to filter perfectly -- accept all multicasts. */
1836 ocp_data |= RCR_AM;
1837 mc_filter[1] = mc_filter[0] = 0xffffffff;
1838 } else {
1839 struct netdev_hw_addr *ha;
1840
1841 mc_filter[1] = mc_filter[0] = 0;
1842 netdev_for_each_mc_addr(ha, netdev) {
1843 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1844 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1845 ocp_data |= RCR_AM;
1846 }
1847 }
1848
1849 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1850 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1851
1852 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1853 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1854 netif_wake_queue(netdev);
1855}
1856
1857static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1858 struct net_device *netdev)
1859{
1860 struct r8152 *tp = netdev_priv(netdev);
1861
1862 skb_tx_timestamp(skb);
1863
1864 skb_queue_tail(&tp->tx_queue, skb);
1865
1866 if (!list_empty(&tp->tx_free)) {
1867 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1868 set_bit(SCHEDULE_TASKLET, &tp->flags);
1869 schedule_delayed_work(&tp->schedule, 0);
1870 } else {
1871 usb_mark_last_busy(tp->udev);
1872 tasklet_schedule(&tp->tl);
1873 }
1874 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen)
1875 netif_stop_queue(netdev);
1876
1877 return NETDEV_TX_OK;
1878}
1879
1880static void r8152b_reset_packet_filter(struct r8152 *tp)
1881{
1882 u32 ocp_data;
1883
1884 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1885 ocp_data &= ~FMC_FCR_MCU_EN;
1886 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1887 ocp_data |= FMC_FCR_MCU_EN;
1888 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1889}
1890
1891static void rtl8152_nic_reset(struct r8152 *tp)
1892{
1893 int i;
1894
1895 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1896
1897 for (i = 0; i < 1000; i++) {
1898 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1899 break;
1900 udelay(100);
1901 }
1902}
1903
1904static void set_tx_qlen(struct r8152 *tp)
1905{
1906 struct net_device *netdev = tp->netdev;
1907
1908 tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1909 sizeof(struct tx_desc));
1910}
1911
1912static inline u8 rtl8152_get_speed(struct r8152 *tp)
1913{
1914 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1915}
1916
1917static void rtl_set_eee_plus(struct r8152 *tp)
1918{
1919 u32 ocp_data;
1920 u8 speed;
1921
1922 speed = rtl8152_get_speed(tp);
1923 if (speed & _10bps) {
1924 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1925 ocp_data |= EEEP_CR_EEEP_TX;
1926 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1927 } else {
1928 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1929 ocp_data &= ~EEEP_CR_EEEP_TX;
1930 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1931 }
1932}
1933
1934static void rxdy_gated_en(struct r8152 *tp, bool enable)
1935{
1936 u32 ocp_data;
1937
1938 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1939 if (enable)
1940 ocp_data |= RXDY_GATED_EN;
1941 else
1942 ocp_data &= ~RXDY_GATED_EN;
1943 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1944}
1945
1946static int rtl_enable(struct r8152 *tp)
1947{
1948 u32 ocp_data;
1949 int i, ret;
1950
1951 r8152b_reset_packet_filter(tp);
1952
1953 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
1954 ocp_data |= CR_RE | CR_TE;
1955 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
1956
1957 rxdy_gated_en(tp, false);
1958
1959 INIT_LIST_HEAD(&tp->rx_done);
1960 ret = 0;
1961 for (i = 0; i < RTL8152_MAX_RX; i++) {
1962 INIT_LIST_HEAD(&tp->rx_info[i].list);
1963 ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1964 }
1965
1966 return ret;
1967}
1968
1969static int rtl8152_enable(struct r8152 *tp)
1970{
1971 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1972 return -ENODEV;
1973
1974 set_tx_qlen(tp);
1975 rtl_set_eee_plus(tp);
1976
1977 return rtl_enable(tp);
1978}
1979
1980static void r8153_set_rx_agg(struct r8152 *tp)
1981{
1982 u8 speed;
1983
1984 speed = rtl8152_get_speed(tp);
1985 if (speed & _1000bps) {
1986 if (tp->udev->speed == USB_SPEED_SUPER) {
1987 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
1988 RX_THR_SUPPER);
1989 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1990 EARLY_AGG_SUPPER);
1991 } else {
1992 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
1993 RX_THR_HIGH);
1994 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1995 EARLY_AGG_HIGH);
1996 }
1997 } else {
1998 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
1999 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2000 EARLY_AGG_SLOW);
2001 }
2002}
2003
2004static int rtl8153_enable(struct r8152 *tp)
2005{
2006 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2007 return -ENODEV;
2008
2009 set_tx_qlen(tp);
2010 rtl_set_eee_plus(tp);
2011 r8153_set_rx_agg(tp);
2012
2013 return rtl_enable(tp);
2014}
2015
2016static void rtl8152_disable(struct r8152 *tp)
2017{
2018 u32 ocp_data;
2019 int i;
2020
2021 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2022 rtl_drop_queued_tx(tp);
2023 return;
2024 }
2025
2026 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2027 ocp_data &= ~RCR_ACPT_ALL;
2028 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2029
2030 rtl_drop_queued_tx(tp);
2031
2032 for (i = 0; i < RTL8152_MAX_TX; i++)
2033 usb_kill_urb(tp->tx_info[i].urb);
2034
2035 rxdy_gated_en(tp, true);
2036
2037 for (i = 0; i < 1000; i++) {
2038 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2039 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2040 break;
2041 mdelay(1);
2042 }
2043
2044 for (i = 0; i < 1000; i++) {
2045 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2046 break;
2047 mdelay(1);
2048 }
2049
2050 for (i = 0; i < RTL8152_MAX_RX; i++)
2051 usb_kill_urb(tp->rx_info[i].urb);
2052
2053 rtl8152_nic_reset(tp);
2054}
2055
2056static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2057{
2058 u32 ocp_data;
2059
2060 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2061 if (enable)
2062 ocp_data |= POWER_CUT;
2063 else
2064 ocp_data &= ~POWER_CUT;
2065 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2066
2067 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2068 ocp_data &= ~RESUME_INDICATE;
2069 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2070}
2071
2072#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2073
2074static u32 __rtl_get_wol(struct r8152 *tp)
2075{
2076 u32 ocp_data;
2077 u32 wolopts = 0;
2078
2079 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2080 if (!(ocp_data & LAN_WAKE_EN))
2081 return 0;
2082
2083 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2084 if (ocp_data & LINK_ON_WAKE_EN)
2085 wolopts |= WAKE_PHY;
2086
2087 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2088 if (ocp_data & UWF_EN)
2089 wolopts |= WAKE_UCAST;
2090 if (ocp_data & BWF_EN)
2091 wolopts |= WAKE_BCAST;
2092 if (ocp_data & MWF_EN)
2093 wolopts |= WAKE_MCAST;
2094
2095 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2096 if (ocp_data & MAGIC_EN)
2097 wolopts |= WAKE_MAGIC;
2098
2099 return wolopts;
2100}
2101
2102static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2103{
2104 u32 ocp_data;
2105
2106 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2107
2108 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2109 ocp_data &= ~LINK_ON_WAKE_EN;
2110 if (wolopts & WAKE_PHY)
2111 ocp_data |= LINK_ON_WAKE_EN;
2112 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2113
2114 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2115 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2116 if (wolopts & WAKE_UCAST)
2117 ocp_data |= UWF_EN;
2118 if (wolopts & WAKE_BCAST)
2119 ocp_data |= BWF_EN;
2120 if (wolopts & WAKE_MCAST)
2121 ocp_data |= MWF_EN;
2122 if (wolopts & WAKE_ANY)
2123 ocp_data |= LAN_WAKE_EN;
2124 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2125
2126 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2127
2128 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2129 ocp_data &= ~MAGIC_EN;
2130 if (wolopts & WAKE_MAGIC)
2131 ocp_data |= MAGIC_EN;
2132 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2133
2134 if (wolopts & WAKE_ANY)
2135 device_set_wakeup_enable(&tp->udev->dev, true);
2136 else
2137 device_set_wakeup_enable(&tp->udev->dev, false);
2138}
2139
2140static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2141{
2142 if (enable) {
2143 u32 ocp_data;
2144
2145 __rtl_set_wol(tp, WAKE_ANY);
2146
2147 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2148
2149 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2150 ocp_data |= LINK_OFF_WAKE_EN;
2151 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2152
2153 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2154 } else {
2155 __rtl_set_wol(tp, tp->saved_wolopts);
2156 }
2157}
2158
2159static void rtl_phy_reset(struct r8152 *tp)
2160{
2161 u16 data;
2162 int i;
2163
2164 clear_bit(PHY_RESET, &tp->flags);
2165
2166 data = r8152_mdio_read(tp, MII_BMCR);
2167
2168 /* don't reset again before the previous one complete */
2169 if (data & BMCR_RESET)
2170 return;
2171
2172 data |= BMCR_RESET;
2173 r8152_mdio_write(tp, MII_BMCR, data);
2174
2175 for (i = 0; i < 50; i++) {
2176 msleep(20);
2177 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2178 break;
2179 }
2180}
2181
2182static void rtl_clear_bp(struct r8152 *tp)
2183{
2184 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
2185 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
2186 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
2187 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
2188 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
2189 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
2190 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
2191 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
2192 mdelay(3);
2193 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
2194 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
2195}
2196
2197static void r8153_clear_bp(struct r8152 *tp)
2198{
2199 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
2200 ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0);
2201 rtl_clear_bp(tp);
2202}
2203
2204static void r8153_teredo_off(struct r8152 *tp)
2205{
2206 u32 ocp_data;
2207
2208 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2209 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2210 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2211
2212 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2213 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2214 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2215}
2216
2217static void r8152b_disable_aldps(struct r8152 *tp)
2218{
2219 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2220 msleep(20);
2221}
2222
2223static inline void r8152b_enable_aldps(struct r8152 *tp)
2224{
2225 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2226 LINKENA | DIS_SDSAVE);
2227}
2228
2229static void r8152b_hw_phy_cfg(struct r8152 *tp)
2230{
2231 u16 data;
2232
2233 data = r8152_mdio_read(tp, MII_BMCR);
2234 if (data & BMCR_PDOWN) {
2235 data &= ~BMCR_PDOWN;
2236 r8152_mdio_write(tp, MII_BMCR, data);
2237 }
2238
2239 r8152b_disable_aldps(tp);
2240
2241 rtl_clear_bp(tp);
2242
2243 r8152b_enable_aldps(tp);
2244 set_bit(PHY_RESET, &tp->flags);
2245}
2246
2247static void r8152b_exit_oob(struct r8152 *tp)
2248{
2249 u32 ocp_data;
2250 int i;
2251
2252 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2253 return;
2254
2255 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2256 ocp_data &= ~RCR_ACPT_ALL;
2257 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2258
2259 rxdy_gated_en(tp, true);
2260 r8153_teredo_off(tp);
2261 r8152b_hw_phy_cfg(tp);
2262
2263 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2264 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2265
2266 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2267 ocp_data &= ~NOW_IS_OOB;
2268 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2269
2270 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2271 ocp_data &= ~MCU_BORW_EN;
2272 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2273
2274 for (i = 0; i < 1000; i++) {
2275 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2276 if (ocp_data & LINK_LIST_READY)
2277 break;
2278 mdelay(1);
2279 }
2280
2281 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2282 ocp_data |= RE_INIT_LL;
2283 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2284
2285 for (i = 0; i < 1000; i++) {
2286 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2287 if (ocp_data & LINK_LIST_READY)
2288 break;
2289 mdelay(1);
2290 }
2291
2292 rtl8152_nic_reset(tp);
2293
2294 /* rx share fifo credit full threshold */
2295 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2296
2297 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
2298 ocp_data &= STAT_SPEED_MASK;
2299 if (ocp_data == STAT_SPEED_FULL) {
2300 /* rx share fifo credit near full threshold */
2301 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2302 RXFIFO_THR2_FULL);
2303 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2304 RXFIFO_THR3_FULL);
2305 } else {
2306 /* rx share fifo credit near full threshold */
2307 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2308 RXFIFO_THR2_HIGH);
2309 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2310 RXFIFO_THR3_HIGH);
2311 }
2312
2313 /* TX share fifo free credit full threshold */
2314 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2315
2316 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2317 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2318 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2319 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2320
2321 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2322 ocp_data &= ~CPCR_RX_VLAN;
2323 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2324
2325 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2326
2327 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2328 ocp_data |= TCR0_AUTO_FIFO;
2329 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2330}
2331
2332static void r8152b_enter_oob(struct r8152 *tp)
2333{
2334 u32 ocp_data;
2335 int i;
2336
2337 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2338 ocp_data &= ~NOW_IS_OOB;
2339 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2340
2341 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2342 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2343 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2344
2345 rtl8152_disable(tp);
2346
2347 for (i = 0; i < 1000; i++) {
2348 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2349 if (ocp_data & LINK_LIST_READY)
2350 break;
2351 mdelay(1);
2352 }
2353
2354 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2355 ocp_data |= RE_INIT_LL;
2356 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2357
2358 for (i = 0; i < 1000; i++) {
2359 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2360 if (ocp_data & LINK_LIST_READY)
2361 break;
2362 mdelay(1);
2363 }
2364
2365 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2366
2367 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2368 ocp_data |= CPCR_RX_VLAN;
2369 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2370
2371 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2372 ocp_data |= ALDPS_PROXY_MODE;
2373 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2374
2375 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2376 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2377 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2378
2379 rxdy_gated_en(tp, false);
2380
2381 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2382 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2383 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2384}
2385
2386static void r8153_hw_phy_cfg(struct r8152 *tp)
2387{
2388 u32 ocp_data;
2389 u16 data;
2390
2391 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2392 data = r8152_mdio_read(tp, MII_BMCR);
2393 if (data & BMCR_PDOWN) {
2394 data &= ~BMCR_PDOWN;
2395 r8152_mdio_write(tp, MII_BMCR, data);
2396 }
2397
2398 r8153_clear_bp(tp);
2399
2400 if (tp->version == RTL_VER_03) {
2401 data = ocp_reg_read(tp, OCP_EEE_CFG);
2402 data &= ~CTAP_SHORT_EN;
2403 ocp_reg_write(tp, OCP_EEE_CFG, data);
2404 }
2405
2406 data = ocp_reg_read(tp, OCP_POWER_CFG);
2407 data |= EEE_CLKDIV_EN;
2408 ocp_reg_write(tp, OCP_POWER_CFG, data);
2409
2410 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2411 data |= EN_10M_BGOFF;
2412 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2413 data = ocp_reg_read(tp, OCP_POWER_CFG);
2414 data |= EN_10M_PLLOFF;
2415 ocp_reg_write(tp, OCP_POWER_CFG, data);
2416 data = sram_read(tp, SRAM_IMPEDANCE);
2417 data &= ~RX_DRIVING_MASK;
2418 sram_write(tp, SRAM_IMPEDANCE, data);
2419
2420 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2421 ocp_data |= PFM_PWM_SWITCH;
2422 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2423
2424 data = sram_read(tp, SRAM_LPF_CFG);
2425 data |= LPF_AUTO_TUNE;
2426 sram_write(tp, SRAM_LPF_CFG, data);
2427
2428 data = sram_read(tp, SRAM_10M_AMP1);
2429 data |= GDAC_IB_UPALL;
2430 sram_write(tp, SRAM_10M_AMP1, data);
2431 data = sram_read(tp, SRAM_10M_AMP2);
2432 data |= AMP_DN;
2433 sram_write(tp, SRAM_10M_AMP2, data);
2434
2435 set_bit(PHY_RESET, &tp->flags);
2436}
2437
2438static void r8153_u1u2en(struct r8152 *tp, bool enable)
2439{
2440 u8 u1u2[8];
2441
2442 if (enable)
2443 memset(u1u2, 0xff, sizeof(u1u2));
2444 else
2445 memset(u1u2, 0x00, sizeof(u1u2));
2446
2447 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2448}
2449
2450static void r8153_u2p3en(struct r8152 *tp, bool enable)
2451{
2452 u32 ocp_data;
2453
2454 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2455 if (enable)
2456 ocp_data |= U2P3_ENABLE;
2457 else
2458 ocp_data &= ~U2P3_ENABLE;
2459 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2460}
2461
2462static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2463{
2464 u32 ocp_data;
2465
2466 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2467 if (enable)
2468 ocp_data |= PWR_EN | PHASE2_EN;
2469 else
2470 ocp_data &= ~(PWR_EN | PHASE2_EN);
2471 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2472
2473 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2474 ocp_data &= ~PCUT_STATUS;
2475 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2476}
2477
2478static void r8153_first_init(struct r8152 *tp)
2479{
2480 u32 ocp_data;
2481 int i;
2482
2483 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2484 return;
2485
2486 rxdy_gated_en(tp, true);
2487 r8153_teredo_off(tp);
2488
2489 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2490 ocp_data &= ~RCR_ACPT_ALL;
2491 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2492
2493 r8153_hw_phy_cfg(tp);
2494
2495 rtl8152_nic_reset(tp);
2496
2497 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2498 ocp_data &= ~NOW_IS_OOB;
2499 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2500
2501 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2502 ocp_data &= ~MCU_BORW_EN;
2503 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2504
2505 for (i = 0; i < 1000; i++) {
2506 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2507 if (ocp_data & LINK_LIST_READY)
2508 break;
2509 mdelay(1);
2510 }
2511
2512 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2513 ocp_data |= RE_INIT_LL;
2514 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2515
2516 for (i = 0; i < 1000; i++) {
2517 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2518 if (ocp_data & LINK_LIST_READY)
2519 break;
2520 mdelay(1);
2521 }
2522
2523 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2524 ocp_data &= ~CPCR_RX_VLAN;
2525 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2526
2527 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2528
2529 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2530 ocp_data |= TCR0_AUTO_FIFO;
2531 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2532
2533 rtl8152_nic_reset(tp);
2534
2535 /* rx share fifo credit full threshold */
2536 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2537 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2538 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2539 /* TX share fifo free credit full threshold */
2540 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2541
2542 /* rx aggregation */
2543 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2544 ocp_data &= ~RX_AGG_DISABLE;
2545 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2546}
2547
2548static void r8153_enter_oob(struct r8152 *tp)
2549{
2550 u32 ocp_data;
2551 int i;
2552
2553 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2554 ocp_data &= ~NOW_IS_OOB;
2555 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2556
2557 rtl8152_disable(tp);
2558
2559 for (i = 0; i < 1000; i++) {
2560 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2561 if (ocp_data & LINK_LIST_READY)
2562 break;
2563 mdelay(1);
2564 }
2565
2566 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2567 ocp_data |= RE_INIT_LL;
2568 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2569
2570 for (i = 0; i < 1000; i++) {
2571 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2572 if (ocp_data & LINK_LIST_READY)
2573 break;
2574 mdelay(1);
2575 }
2576
2577 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2578
2579 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2580 ocp_data &= ~TEREDO_WAKE_MASK;
2581 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2582
2583 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2584 ocp_data |= CPCR_RX_VLAN;
2585 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2586
2587 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2588 ocp_data |= ALDPS_PROXY_MODE;
2589 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2590
2591 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2592 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2593 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2594
2595 rxdy_gated_en(tp, false);
2596
2597 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2598 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2599 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2600}
2601
2602static void r8153_disable_aldps(struct r8152 *tp)
2603{
2604 u16 data;
2605
2606 data = ocp_reg_read(tp, OCP_POWER_CFG);
2607 data &= ~EN_ALDPS;
2608 ocp_reg_write(tp, OCP_POWER_CFG, data);
2609 msleep(20);
2610}
2611
2612static void r8153_enable_aldps(struct r8152 *tp)
2613{
2614 u16 data;
2615
2616 data = ocp_reg_read(tp, OCP_POWER_CFG);
2617 data |= EN_ALDPS;
2618 ocp_reg_write(tp, OCP_POWER_CFG, data);
2619}
2620
2621static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2622{
2623 u16 bmcr, anar, gbcr;
2624 int ret = 0;
2625
2626 cancel_delayed_work_sync(&tp->schedule);
2627 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2628 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2629 ADVERTISE_100HALF | ADVERTISE_100FULL);
2630 if (tp->mii.supports_gmii) {
2631 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2632 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2633 } else {
2634 gbcr = 0;
2635 }
2636
2637 if (autoneg == AUTONEG_DISABLE) {
2638 if (speed == SPEED_10) {
2639 bmcr = 0;
2640 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2641 } else if (speed == SPEED_100) {
2642 bmcr = BMCR_SPEED100;
2643 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2644 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2645 bmcr = BMCR_SPEED1000;
2646 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2647 } else {
2648 ret = -EINVAL;
2649 goto out;
2650 }
2651
2652 if (duplex == DUPLEX_FULL)
2653 bmcr |= BMCR_FULLDPLX;
2654 } else {
2655 if (speed == SPEED_10) {
2656 if (duplex == DUPLEX_FULL)
2657 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2658 else
2659 anar |= ADVERTISE_10HALF;
2660 } else if (speed == SPEED_100) {
2661 if (duplex == DUPLEX_FULL) {
2662 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2663 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2664 } else {
2665 anar |= ADVERTISE_10HALF;
2666 anar |= ADVERTISE_100HALF;
2667 }
2668 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2669 if (duplex == DUPLEX_FULL) {
2670 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2671 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2672 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2673 } else {
2674 anar |= ADVERTISE_10HALF;
2675 anar |= ADVERTISE_100HALF;
2676 gbcr |= ADVERTISE_1000HALF;
2677 }
2678 } else {
2679 ret = -EINVAL;
2680 goto out;
2681 }
2682
2683 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2684 }
2685
2686 if (test_bit(PHY_RESET, &tp->flags))
2687 bmcr |= BMCR_RESET;
2688
2689 if (tp->mii.supports_gmii)
2690 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2691
2692 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2693 r8152_mdio_write(tp, MII_BMCR, bmcr);
2694
2695 if (test_bit(PHY_RESET, &tp->flags)) {
2696 int i;
2697
2698 clear_bit(PHY_RESET, &tp->flags);
2699 for (i = 0; i < 50; i++) {
2700 msleep(20);
2701 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2702 break;
2703 }
2704 }
2705
2706out:
2707
2708 return ret;
2709}
2710
2711static void rtl8152_down(struct r8152 *tp)
2712{
2713 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2714 rtl_drop_queued_tx(tp);
2715 return;
2716 }
2717
2718 r8152_power_cut_en(tp, false);
2719 r8152b_disable_aldps(tp);
2720 r8152b_enter_oob(tp);
2721 r8152b_enable_aldps(tp);
2722}
2723
2724static void rtl8153_down(struct r8152 *tp)
2725{
2726 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2727 rtl_drop_queued_tx(tp);
2728 return;
2729 }
2730
2731 r8153_u1u2en(tp, false);
2732 r8153_power_cut_en(tp, false);
2733 r8153_disable_aldps(tp);
2734 r8153_enter_oob(tp);
2735 r8153_enable_aldps(tp);
2736}
2737
2738static void set_carrier(struct r8152 *tp)
2739{
2740 struct net_device *netdev = tp->netdev;
2741 u8 speed;
2742
2743 clear_bit(RTL8152_LINK_CHG, &tp->flags);
2744 speed = rtl8152_get_speed(tp);
2745
2746 if (speed & LINK_STATUS) {
2747 if (!(tp->speed & LINK_STATUS)) {
2748 tp->rtl_ops.enable(tp);
2749 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2750 netif_carrier_on(netdev);
2751 }
2752 } else {
2753 if (tp->speed & LINK_STATUS) {
2754 netif_carrier_off(netdev);
2755 tasklet_disable(&tp->tl);
2756 tp->rtl_ops.disable(tp);
2757 tasklet_enable(&tp->tl);
2758 }
2759 }
2760 tp->speed = speed;
2761}
2762
2763static void rtl_work_func_t(struct work_struct *work)
2764{
2765 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2766
2767 if (usb_autopm_get_interface(tp->intf) < 0)
2768 return;
2769
2770 if (!test_bit(WORK_ENABLE, &tp->flags))
2771 goto out1;
2772
2773 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2774 goto out1;
2775
2776 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2777 set_carrier(tp);
2778
2779 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2780 _rtl8152_set_rx_mode(tp->netdev);
2781
2782 if (test_bit(SCHEDULE_TASKLET, &tp->flags) &&
2783 (tp->speed & LINK_STATUS)) {
2784 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2785 tasklet_schedule(&tp->tl);
2786 }
2787
2788 if (test_bit(PHY_RESET, &tp->flags))
2789 rtl_phy_reset(tp);
2790
2791out1:
2792 usb_autopm_put_interface(tp->intf);
2793}
2794
2795static int rtl8152_open(struct net_device *netdev)
2796{
2797 struct r8152 *tp = netdev_priv(netdev);
2798 int res = 0;
2799
2800 res = alloc_all_mem(tp);
2801 if (res)
2802 goto out;
2803
2804 res = usb_autopm_get_interface(tp->intf);
2805 if (res < 0) {
2806 free_all_mem(tp);
2807 goto out;
2808 }
2809
2810 /* The WORK_ENABLE may be set when autoresume occurs */
2811 if (test_bit(WORK_ENABLE, &tp->flags)) {
2812 clear_bit(WORK_ENABLE, &tp->flags);
2813 usb_kill_urb(tp->intr_urb);
2814 cancel_delayed_work_sync(&tp->schedule);
2815 if (tp->speed & LINK_STATUS)
2816 tp->rtl_ops.disable(tp);
2817 }
2818
2819 tp->rtl_ops.up(tp);
2820
2821 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2822 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2823 DUPLEX_FULL);
2824 tp->speed = 0;
2825 netif_carrier_off(netdev);
2826 netif_start_queue(netdev);
2827 set_bit(WORK_ENABLE, &tp->flags);
2828
2829 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2830 if (res) {
2831 if (res == -ENODEV)
2832 netif_device_detach(tp->netdev);
2833 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2834 res);
2835 free_all_mem(tp);
2836 }
2837
2838 usb_autopm_put_interface(tp->intf);
2839
2840out:
2841 return res;
2842}
2843
2844static int rtl8152_close(struct net_device *netdev)
2845{
2846 struct r8152 *tp = netdev_priv(netdev);
2847 int res = 0;
2848
2849 clear_bit(WORK_ENABLE, &tp->flags);
2850 usb_kill_urb(tp->intr_urb);
2851 cancel_delayed_work_sync(&tp->schedule);
2852 netif_stop_queue(netdev);
2853
2854 res = usb_autopm_get_interface(tp->intf);
2855 if (res < 0) {
2856 rtl_drop_queued_tx(tp);
2857 } else {
2858 /*
2859 * The autosuspend may have been enabled and wouldn't
2860 * be disable when autoresume occurs, because the
2861 * netif_running() would be false.
2862 */
2863 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2864 rtl_runtime_suspend_enable(tp, false);
2865 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
2866 }
2867
2868 tasklet_disable(&tp->tl);
2869 tp->rtl_ops.down(tp);
2870 tasklet_enable(&tp->tl);
2871 usb_autopm_put_interface(tp->intf);
2872 }
2873
2874 free_all_mem(tp);
2875
2876 return res;
2877}
2878
2879static void r8152b_enable_eee(struct r8152 *tp)
2880{
2881 u32 ocp_data;
2882
2883 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2884 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2885 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2886 ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
2887 EEE_10_CAP | EEE_NWAY_EN |
2888 TX_QUIET_EN | RX_QUIET_EN |
2889 SDRISETIME | RG_RXLPI_MSK_HFDUP |
2890 SDFALLTIME);
2891 ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
2892 RG_LDVQUIET_EN | RG_CKRSEL |
2893 RG_EEEPRG_EN);
2894 ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
2895 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
2896 ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
2897 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
2898 ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
2899 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2900}
2901
2902static void r8153_enable_eee(struct r8152 *tp)
2903{
2904 u32 ocp_data;
2905 u16 data;
2906
2907 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2908 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2909 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2910 data = ocp_reg_read(tp, OCP_EEE_CFG);
2911 data |= EEE10_EN;
2912 ocp_reg_write(tp, OCP_EEE_CFG, data);
2913 data = ocp_reg_read(tp, OCP_EEE_CFG2);
2914 data |= MY1000_EEE | MY100_EEE;
2915 ocp_reg_write(tp, OCP_EEE_CFG2, data);
2916}
2917
2918static void r8152b_enable_fc(struct r8152 *tp)
2919{
2920 u16 anar;
2921
2922 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2923 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2924 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2925}
2926
2927static void rtl_tally_reset(struct r8152 *tp)
2928{
2929 u32 ocp_data;
2930
2931 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
2932 ocp_data |= TALLY_RESET;
2933 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
2934}
2935
2936static void r8152b_init(struct r8152 *tp)
2937{
2938 u32 ocp_data;
2939
2940 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2941 return;
2942
2943 if (tp->version == RTL_VER_01) {
2944 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
2945 ocp_data &= ~LED_MODE_MASK;
2946 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
2947 }
2948
2949 r8152_power_cut_en(tp, false);
2950
2951 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2952 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
2953 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2954 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
2955 ocp_data &= ~MCU_CLK_RATIO_MASK;
2956 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
2957 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
2958 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
2959 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
2960 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
2961
2962 r8152b_enable_eee(tp);
2963 r8152b_enable_aldps(tp);
2964 r8152b_enable_fc(tp);
2965 rtl_tally_reset(tp);
2966
2967 /* enable rx aggregation */
2968 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2969 ocp_data &= ~RX_AGG_DISABLE;
2970 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2971}
2972
2973static void r8153_init(struct r8152 *tp)
2974{
2975 u32 ocp_data;
2976 int i;
2977
2978 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2979 return;
2980
2981 r8153_u1u2en(tp, false);
2982
2983 for (i = 0; i < 500; i++) {
2984 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
2985 AUTOLOAD_DONE)
2986 break;
2987 msleep(20);
2988 }
2989
2990 for (i = 0; i < 500; i++) {
2991 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
2992 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
2993 break;
2994 msleep(20);
2995 }
2996
2997 r8153_u2p3en(tp, false);
2998
2999 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3000 ocp_data &= ~TIMER11_EN;
3001 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3002
3003 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3004 ocp_data &= ~LED_MODE_MASK;
3005 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3006
3007 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
3008 ocp_data &= ~LPM_TIMER_MASK;
3009 if (tp->udev->speed == USB_SPEED_SUPER)
3010 ocp_data |= LPM_TIMER_500US;
3011 else
3012 ocp_data |= LPM_TIMER_500MS;
3013 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3014
3015 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3016 ocp_data &= ~SEN_VAL_MASK;
3017 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3018 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3019
3020 r8153_power_cut_en(tp, false);
3021 r8153_u1u2en(tp, true);
3022
3023 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3024 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3025 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3026 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3027 U1U2_SPDWN_EN | L1_SPDWN_EN);
3028 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3029 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3030 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3031 EEE_SPDWN_EN);
3032
3033 r8153_enable_eee(tp);
3034 r8153_enable_aldps(tp);
3035 r8152b_enable_fc(tp);
3036 rtl_tally_reset(tp);
3037}
3038
3039static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3040{
3041 struct r8152 *tp = usb_get_intfdata(intf);
3042
3043 if (PMSG_IS_AUTO(message))
3044 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3045 else
3046 netif_device_detach(tp->netdev);
3047
3048 if (netif_running(tp->netdev)) {
3049 clear_bit(WORK_ENABLE, &tp->flags);
3050 usb_kill_urb(tp->intr_urb);
3051 cancel_delayed_work_sync(&tp->schedule);
3052 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3053 rtl_runtime_suspend_enable(tp, true);
3054 } else {
3055 tasklet_disable(&tp->tl);
3056 tp->rtl_ops.down(tp);
3057 tasklet_enable(&tp->tl);
3058 }
3059 }
3060
3061 return 0;
3062}
3063
3064static int rtl8152_resume(struct usb_interface *intf)
3065{
3066 struct r8152 *tp = usb_get_intfdata(intf);
3067
3068 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3069 tp->rtl_ops.init(tp);
3070 netif_device_attach(tp->netdev);
3071 }
3072
3073 if (netif_running(tp->netdev)) {
3074 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3075 rtl_runtime_suspend_enable(tp, false);
3076 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3077 if (tp->speed & LINK_STATUS)
3078 tp->rtl_ops.disable(tp);
3079 } else {
3080 tp->rtl_ops.up(tp);
3081 rtl8152_set_speed(tp, AUTONEG_ENABLE,
3082 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
3083 DUPLEX_FULL);
3084 }
3085 tp->speed = 0;
3086 netif_carrier_off(tp->netdev);
3087 set_bit(WORK_ENABLE, &tp->flags);
3088 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3089 }
3090
3091 return 0;
3092}
3093
3094static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3095{
3096 struct r8152 *tp = netdev_priv(dev);
3097
3098 if (usb_autopm_get_interface(tp->intf) < 0)
3099 return;
3100
3101 wol->supported = WAKE_ANY;
3102 wol->wolopts = __rtl_get_wol(tp);
3103
3104 usb_autopm_put_interface(tp->intf);
3105}
3106
3107static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3108{
3109 struct r8152 *tp = netdev_priv(dev);
3110 int ret;
3111
3112 ret = usb_autopm_get_interface(tp->intf);
3113 if (ret < 0)
3114 goto out_set_wol;
3115
3116 __rtl_set_wol(tp, wol->wolopts);
3117 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3118
3119 usb_autopm_put_interface(tp->intf);
3120
3121out_set_wol:
3122 return ret;
3123}
3124
3125static u32 rtl8152_get_msglevel(struct net_device *dev)
3126{
3127 struct r8152 *tp = netdev_priv(dev);
3128
3129 return tp->msg_enable;
3130}
3131
3132static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3133{
3134 struct r8152 *tp = netdev_priv(dev);
3135
3136 tp->msg_enable = value;
3137}
3138
3139static void rtl8152_get_drvinfo(struct net_device *netdev,
3140 struct ethtool_drvinfo *info)
3141{
3142 struct r8152 *tp = netdev_priv(netdev);
3143
3144 strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
3145 strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
3146 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3147}
3148
3149static
3150int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3151{
3152 struct r8152 *tp = netdev_priv(netdev);
3153
3154 if (!tp->mii.mdio_read)
3155 return -EOPNOTSUPP;
3156
3157 return mii_ethtool_gset(&tp->mii, cmd);
3158}
3159
3160static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3161{
3162 struct r8152 *tp = netdev_priv(dev);
3163 int ret;
3164
3165 ret = usb_autopm_get_interface(tp->intf);
3166 if (ret < 0)
3167 goto out;
3168
3169 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3170
3171 usb_autopm_put_interface(tp->intf);
3172
3173out:
3174 return ret;
3175}
3176
3177static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3178 "tx_packets",
3179 "rx_packets",
3180 "tx_errors",
3181 "rx_errors",
3182 "rx_missed",
3183 "align_errors",
3184 "tx_single_collisions",
3185 "tx_multi_collisions",
3186 "rx_unicast",
3187 "rx_broadcast",
3188 "rx_multicast",
3189 "tx_aborted",
3190 "tx_underrun",
3191};
3192
3193static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3194{
3195 switch (sset) {
3196 case ETH_SS_STATS:
3197 return ARRAY_SIZE(rtl8152_gstrings);
3198 default:
3199 return -EOPNOTSUPP;
3200 }
3201}
3202
3203static void rtl8152_get_ethtool_stats(struct net_device *dev,
3204 struct ethtool_stats *stats, u64 *data)
3205{
3206 struct r8152 *tp = netdev_priv(dev);
3207 struct tally_counter tally;
3208
3209 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3210
3211 data[0] = le64_to_cpu(tally.tx_packets);
3212 data[1] = le64_to_cpu(tally.rx_packets);
3213 data[2] = le64_to_cpu(tally.tx_errors);
3214 data[3] = le32_to_cpu(tally.rx_errors);
3215 data[4] = le16_to_cpu(tally.rx_missed);
3216 data[5] = le16_to_cpu(tally.align_errors);
3217 data[6] = le32_to_cpu(tally.tx_one_collision);
3218 data[7] = le32_to_cpu(tally.tx_multi_collision);
3219 data[8] = le64_to_cpu(tally.rx_unicast);
3220 data[9] = le64_to_cpu(tally.rx_broadcast);
3221 data[10] = le32_to_cpu(tally.rx_multicast);
3222 data[11] = le16_to_cpu(tally.tx_aborted);
3223 data[12] = le16_to_cpu(tally.tx_underun);
3224}
3225
3226static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3227{
3228 switch (stringset) {
3229 case ETH_SS_STATS:
3230 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3231 break;
3232 }
3233}
3234
3235static struct ethtool_ops ops = {
3236 .get_drvinfo = rtl8152_get_drvinfo,
3237 .get_settings = rtl8152_get_settings,
3238 .set_settings = rtl8152_set_settings,
3239 .get_link = ethtool_op_get_link,
3240 .get_msglevel = rtl8152_get_msglevel,
3241 .set_msglevel = rtl8152_set_msglevel,
3242 .get_wol = rtl8152_get_wol,
3243 .set_wol = rtl8152_set_wol,
3244 .get_strings = rtl8152_get_strings,
3245 .get_sset_count = rtl8152_get_sset_count,
3246 .get_ethtool_stats = rtl8152_get_ethtool_stats,
3247};
3248
3249static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3250{
3251 struct r8152 *tp = netdev_priv(netdev);
3252 struct mii_ioctl_data *data = if_mii(rq);
3253 int res;
3254
3255 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3256 return -ENODEV;
3257
3258 res = usb_autopm_get_interface(tp->intf);
3259 if (res < 0)
3260 goto out;
3261
3262 switch (cmd) {
3263 case SIOCGMIIPHY:
3264 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3265 break;
3266
3267 case SIOCGMIIREG:
3268 data->val_out = r8152_mdio_read(tp, data->reg_num);
3269 break;
3270
3271 case SIOCSMIIREG:
3272 if (!capable(CAP_NET_ADMIN)) {
3273 res = -EPERM;
3274 break;
3275 }
3276 r8152_mdio_write(tp, data->reg_num, data->val_in);
3277 break;
3278
3279 default:
3280 res = -EOPNOTSUPP;
3281 }
3282
3283 usb_autopm_put_interface(tp->intf);
3284
3285out:
3286 return res;
3287}
3288
3289static const struct net_device_ops rtl8152_netdev_ops = {
3290 .ndo_open = rtl8152_open,
3291 .ndo_stop = rtl8152_close,
3292 .ndo_do_ioctl = rtl8152_ioctl,
3293 .ndo_start_xmit = rtl8152_start_xmit,
3294 .ndo_tx_timeout = rtl8152_tx_timeout,
3295 .ndo_set_rx_mode = rtl8152_set_rx_mode,
3296 .ndo_set_mac_address = rtl8152_set_mac_address,
3297
3298 .ndo_change_mtu = eth_change_mtu,
3299 .ndo_validate_addr = eth_validate_addr,
3300};
3301
3302static void r8152b_get_version(struct r8152 *tp)
3303{
3304 u32 ocp_data;
3305 u16 version;
3306
3307 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3308 version = (u16)(ocp_data & VERSION_MASK);
3309
3310 switch (version) {
3311 case 0x4c00:
3312 tp->version = RTL_VER_01;
3313 break;
3314 case 0x4c10:
3315 tp->version = RTL_VER_02;
3316 break;
3317 case 0x5c00:
3318 tp->version = RTL_VER_03;
3319 tp->mii.supports_gmii = 1;
3320 break;
3321 case 0x5c10:
3322 tp->version = RTL_VER_04;
3323 tp->mii.supports_gmii = 1;
3324 break;
3325 case 0x5c20:
3326 tp->version = RTL_VER_05;
3327 tp->mii.supports_gmii = 1;
3328 break;
3329 default:
3330 netif_info(tp, probe, tp->netdev,
3331 "Unknown version 0x%04x\n", version);
3332 break;
3333 }
3334}
3335
3336static void rtl8152_unload(struct r8152 *tp)
3337{
3338 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3339 return;
3340
3341 if (tp->version != RTL_VER_01)
3342 r8152_power_cut_en(tp, true);
3343}
3344
3345static void rtl8153_unload(struct r8152 *tp)
3346{
3347 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3348 return;
3349
3350 r8153_power_cut_en(tp, true);
3351}
3352
3353static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id)
3354{
3355 struct rtl_ops *ops = &tp->rtl_ops;
3356 int ret = -ENODEV;
3357
3358 switch (id->idVendor) {
3359 case VENDOR_ID_REALTEK:
3360 switch (id->idProduct) {
3361 case PRODUCT_ID_RTL8152:
3362 ops->init = r8152b_init;
3363 ops->enable = rtl8152_enable;
3364 ops->disable = rtl8152_disable;
3365 ops->up = r8152b_exit_oob;
3366 ops->down = rtl8152_down;
3367 ops->unload = rtl8152_unload;
3368 ret = 0;
3369 break;
3370 case PRODUCT_ID_RTL8153:
3371 ops->init = r8153_init;
3372 ops->enable = rtl8153_enable;
3373 ops->disable = rtl8152_disable;
3374 ops->up = r8153_first_init;
3375 ops->down = rtl8153_down;
3376 ops->unload = rtl8153_unload;
3377 ret = 0;
3378 break;
3379 default:
3380 break;
3381 }
3382 break;
3383
3384 case VENDOR_ID_SAMSUNG:
3385 switch (id->idProduct) {
3386 case PRODUCT_ID_SAMSUNG:
3387 ops->init = r8153_init;
3388 ops->enable = rtl8153_enable;
3389 ops->disable = rtl8152_disable;
3390 ops->up = r8153_first_init;
3391 ops->down = rtl8153_down;
3392 ops->unload = rtl8153_unload;
3393 ret = 0;
3394 break;
3395 default:
3396 break;
3397 }
3398 break;
3399
3400 default:
3401 break;
3402 }
3403
3404 if (ret)
3405 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3406
3407 return ret;
3408}
3409
3410static int rtl8152_probe(struct usb_interface *intf,
3411 const struct usb_device_id *id)
3412{
3413 struct usb_device *udev = interface_to_usbdev(intf);
3414 struct r8152 *tp;
3415 struct net_device *netdev;
3416 int ret;
3417
3418 if (udev->actconfig->desc.bConfigurationValue != 1) {
3419 usb_driver_set_configuration(udev, 1);
3420 return -ENODEV;
3421 }
3422
3423 usb_reset_device(udev);
3424 netdev = alloc_etherdev(sizeof(struct r8152));
3425 if (!netdev) {
3426 dev_err(&intf->dev, "Out of memory\n");
3427 return -ENOMEM;
3428 }
3429
3430 SET_NETDEV_DEV(netdev, &intf->dev);
3431 tp = netdev_priv(netdev);
3432 tp->msg_enable = 0x7FFF;
3433
3434 tp->udev = udev;
3435 tp->netdev = netdev;
3436 tp->intf = intf;
3437
3438 ret = rtl_ops_init(tp, id);
3439 if (ret)
3440 goto out;
3441
3442 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
3443 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3444
3445 netdev->netdev_ops = &rtl8152_netdev_ops;
3446 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
3447
3448 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3449 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
3450 NETIF_F_TSO6;
3451 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3452 NETIF_F_TSO | NETIF_F_FRAGLIST |
3453 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
3454
3455 SET_ETHTOOL_OPS(netdev, &ops);
3456 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
3457
3458 tp->mii.dev = netdev;
3459 tp->mii.mdio_read = read_mii_word;
3460 tp->mii.mdio_write = write_mii_word;
3461 tp->mii.phy_id_mask = 0x3f;
3462 tp->mii.reg_num_mask = 0x1f;
3463 tp->mii.phy_id = R8152_PHY_ID;
3464 tp->mii.supports_gmii = 0;
3465
3466 intf->needs_remote_wakeup = 1;
3467
3468 r8152b_get_version(tp);
3469 tp->rtl_ops.init(tp);
3470 set_ethernet_addr(tp);
3471
3472 usb_set_intfdata(intf, tp);
3473
3474 ret = register_netdev(netdev);
3475 if (ret != 0) {
3476 netif_err(tp, probe, netdev, "couldn't register the device\n");
3477 goto out1;
3478 }
3479
3480 tp->saved_wolopts = __rtl_get_wol(tp);
3481 if (tp->saved_wolopts)
3482 device_set_wakeup_enable(&udev->dev, true);
3483 else
3484 device_set_wakeup_enable(&udev->dev, false);
3485
3486 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
3487
3488 return 0;
3489
3490out1:
3491 usb_set_intfdata(intf, NULL);
3492out:
3493 free_netdev(netdev);
3494 return ret;
3495}
3496
3497static void rtl8152_disconnect(struct usb_interface *intf)
3498{
3499 struct r8152 *tp = usb_get_intfdata(intf);
3500
3501 usb_set_intfdata(intf, NULL);
3502 if (tp) {
3503 set_bit(RTL8152_UNPLUG, &tp->flags);
3504 tasklet_kill(&tp->tl);
3505 unregister_netdev(tp->netdev);
3506 tp->rtl_ops.unload(tp);
3507 free_netdev(tp->netdev);
3508 }
3509}
3510
3511/* table of devices that work with this driver */
3512static struct usb_device_id rtl8152_table[] = {
3513 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
3514 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)},
3515 {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)},
3516 {}
3517};
3518
3519MODULE_DEVICE_TABLE(usb, rtl8152_table);
3520
3521static struct usb_driver rtl8152_driver = {
3522 .name = MODULENAME,
3523 .id_table = rtl8152_table,
3524 .probe = rtl8152_probe,
3525 .disconnect = rtl8152_disconnect,
3526 .suspend = rtl8152_suspend,
3527 .resume = rtl8152_resume,
3528 .reset_resume = rtl8152_resume,
3529 .supports_autosuspend = 1,
3530 .disable_hub_initiated_lpm = 1,
3531};
3532
3533module_usb_driver(rtl8152_driver);
3534
3535MODULE_AUTHOR(DRIVER_AUTHOR);
3536MODULE_DESCRIPTION(DRIVER_DESC);
3537MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4 */
5
6#include <linux/signal.h>
7#include <linux/slab.h>
8#include <linux/module.h>
9#include <linux/netdevice.h>
10#include <linux/etherdevice.h>
11#include <linux/mii.h>
12#include <linux/ethtool.h>
13#include <linux/usb.h>
14#include <linux/crc32.h>
15#include <linux/if_vlan.h>
16#include <linux/uaccess.h>
17#include <linux/list.h>
18#include <linux/ip.h>
19#include <linux/ipv6.h>
20#include <net/ip6_checksum.h>
21#include <uapi/linux/mdio.h>
22#include <linux/mdio.h>
23#include <linux/usb/cdc.h>
24#include <linux/suspend.h>
25#include <linux/atomic.h>
26#include <linux/acpi.h>
27#include <linux/firmware.h>
28#include <crypto/hash.h>
29#include <linux/usb/r8152.h>
30
31/* Information for net-next */
32#define NETNEXT_VERSION "12"
33
34/* Information for net */
35#define NET_VERSION "11"
36
37#define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
38#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40#define MODULENAME "r8152"
41
42#define R8152_PHY_ID 32
43
44#define PLA_IDR 0xc000
45#define PLA_RCR 0xc010
46#define PLA_RCR1 0xc012
47#define PLA_RMS 0xc016
48#define PLA_RXFIFO_CTRL0 0xc0a0
49#define PLA_RXFIFO_FULL 0xc0a2
50#define PLA_RXFIFO_CTRL1 0xc0a4
51#define PLA_RX_FIFO_FULL 0xc0a6
52#define PLA_RXFIFO_CTRL2 0xc0a8
53#define PLA_RX_FIFO_EMPTY 0xc0aa
54#define PLA_DMY_REG0 0xc0b0
55#define PLA_FMC 0xc0b4
56#define PLA_CFG_WOL 0xc0b6
57#define PLA_TEREDO_CFG 0xc0bc
58#define PLA_TEREDO_WAKE_BASE 0xc0c4
59#define PLA_MAR 0xcd00
60#define PLA_BACKUP 0xd000
61#define PLA_BDC_CR 0xd1a0
62#define PLA_TEREDO_TIMER 0xd2cc
63#define PLA_REALWOW_TIMER 0xd2e8
64#define PLA_UPHY_TIMER 0xd388
65#define PLA_SUSPEND_FLAG 0xd38a
66#define PLA_INDICATE_FALG 0xd38c
67#define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
68#define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
69#define PLA_EXTRA_STATUS 0xd398
70#define PLA_GPHY_CTRL 0xd3ae
71#define PLA_POL_GPIO_CTRL 0xdc6a
72#define PLA_EFUSE_DATA 0xdd00
73#define PLA_EFUSE_CMD 0xdd02
74#define PLA_LEDSEL 0xdd90
75#define PLA_LED_FEATURE 0xdd92
76#define PLA_PHYAR 0xde00
77#define PLA_BOOT_CTRL 0xe004
78#define PLA_LWAKE_CTRL_REG 0xe007
79#define PLA_GPHY_INTR_IMR 0xe022
80#define PLA_EEE_CR 0xe040
81#define PLA_EEE_TXTWSYS 0xe04c
82#define PLA_EEE_TXTWSYS_2P5G 0xe058
83#define PLA_EEEP_CR 0xe080
84#define PLA_MAC_PWR_CTRL 0xe0c0
85#define PLA_MAC_PWR_CTRL2 0xe0ca
86#define PLA_MAC_PWR_CTRL3 0xe0cc
87#define PLA_MAC_PWR_CTRL4 0xe0ce
88#define PLA_WDT6_CTRL 0xe428
89#define PLA_TCR0 0xe610
90#define PLA_TCR1 0xe612
91#define PLA_MTPS 0xe615
92#define PLA_TXFIFO_CTRL 0xe618
93#define PLA_TXFIFO_FULL 0xe61a
94#define PLA_RSTTALLY 0xe800
95#define PLA_CR 0xe813
96#define PLA_CRWECR 0xe81c
97#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
98#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
99#define PLA_CONFIG5 0xe822
100#define PLA_PHY_PWR 0xe84c
101#define PLA_OOB_CTRL 0xe84f
102#define PLA_CPCR 0xe854
103#define PLA_MISC_0 0xe858
104#define PLA_MISC_1 0xe85a
105#define PLA_OCP_GPHY_BASE 0xe86c
106#define PLA_TALLYCNT 0xe890
107#define PLA_SFF_STS_7 0xe8de
108#define PLA_PHYSTATUS 0xe908
109#define PLA_CONFIG6 0xe90a /* CONFIG6 */
110#define PLA_USB_CFG 0xe952
111#define PLA_BP_BA 0xfc26
112#define PLA_BP_0 0xfc28
113#define PLA_BP_1 0xfc2a
114#define PLA_BP_2 0xfc2c
115#define PLA_BP_3 0xfc2e
116#define PLA_BP_4 0xfc30
117#define PLA_BP_5 0xfc32
118#define PLA_BP_6 0xfc34
119#define PLA_BP_7 0xfc36
120#define PLA_BP_EN 0xfc38
121
122#define USB_USB2PHY 0xb41e
123#define USB_SSPHYLINK1 0xb426
124#define USB_SSPHYLINK2 0xb428
125#define USB_L1_CTRL 0xb45e
126#define USB_U2P3_CTRL 0xb460
127#define USB_CSR_DUMMY1 0xb464
128#define USB_CSR_DUMMY2 0xb466
129#define USB_DEV_STAT 0xb808
130#define USB_CONNECT_TIMER 0xcbf8
131#define USB_MSC_TIMER 0xcbfc
132#define USB_BURST_SIZE 0xcfc0
133#define USB_FW_FIX_EN0 0xcfca
134#define USB_FW_FIX_EN1 0xcfcc
135#define USB_LPM_CONFIG 0xcfd8
136#define USB_ECM_OPTION 0xcfee
137#define USB_CSTMR 0xcfef /* RTL8153A */
138#define USB_MISC_2 0xcfff
139#define USB_ECM_OP 0xd26b
140#define USB_GPHY_CTRL 0xd284
141#define USB_SPEED_OPTION 0xd32a
142#define USB_FW_CTRL 0xd334 /* RTL8153B */
143#define USB_FC_TIMER 0xd340
144#define USB_USB_CTRL 0xd406
145#define USB_PHY_CTRL 0xd408
146#define USB_TX_AGG 0xd40a
147#define USB_RX_BUF_TH 0xd40c
148#define USB_USB_TIMER 0xd428
149#define USB_RX_EARLY_TIMEOUT 0xd42c
150#define USB_RX_EARLY_SIZE 0xd42e
151#define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
152#define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
153#define USB_TX_DMA 0xd434
154#define USB_UPT_RXDMA_OWN 0xd437
155#define USB_UPHY3_MDCMDIO 0xd480
156#define USB_TOLERANCE 0xd490
157#define USB_LPM_CTRL 0xd41a
158#define USB_BMU_RESET 0xd4b0
159#define USB_BMU_CONFIG 0xd4b4
160#define USB_U1U2_TIMER 0xd4da
161#define USB_FW_TASK 0xd4e8 /* RTL8153B */
162#define USB_RX_AGGR_NUM 0xd4ee
163#define USB_UPS_CTRL 0xd800
164#define USB_POWER_CUT 0xd80a
165#define USB_MISC_0 0xd81a
166#define USB_MISC_1 0xd81f
167#define USB_AFE_CTRL2 0xd824
168#define USB_UPHY_XTAL 0xd826
169#define USB_UPS_CFG 0xd842
170#define USB_UPS_FLAGS 0xd848
171#define USB_WDT1_CTRL 0xe404
172#define USB_WDT11_CTRL 0xe43c
173#define USB_BP_BA PLA_BP_BA
174#define USB_BP_0 PLA_BP_0
175#define USB_BP_1 PLA_BP_1
176#define USB_BP_2 PLA_BP_2
177#define USB_BP_3 PLA_BP_3
178#define USB_BP_4 PLA_BP_4
179#define USB_BP_5 PLA_BP_5
180#define USB_BP_6 PLA_BP_6
181#define USB_BP_7 PLA_BP_7
182#define USB_BP_EN PLA_BP_EN /* RTL8153A */
183#define USB_BP_8 0xfc38 /* RTL8153B */
184#define USB_BP_9 0xfc3a
185#define USB_BP_10 0xfc3c
186#define USB_BP_11 0xfc3e
187#define USB_BP_12 0xfc40
188#define USB_BP_13 0xfc42
189#define USB_BP_14 0xfc44
190#define USB_BP_15 0xfc46
191#define USB_BP2_EN 0xfc48
192
193/* OCP Registers */
194#define OCP_ALDPS_CONFIG 0x2010
195#define OCP_EEE_CONFIG1 0x2080
196#define OCP_EEE_CONFIG2 0x2092
197#define OCP_EEE_CONFIG3 0x2094
198#define OCP_BASE_MII 0xa400
199#define OCP_EEE_AR 0xa41a
200#define OCP_EEE_DATA 0xa41c
201#define OCP_PHY_STATUS 0xa420
202#define OCP_NCTL_CFG 0xa42c
203#define OCP_POWER_CFG 0xa430
204#define OCP_EEE_CFG 0xa432
205#define OCP_SRAM_ADDR 0xa436
206#define OCP_SRAM_DATA 0xa438
207#define OCP_DOWN_SPEED 0xa442
208#define OCP_EEE_ABLE 0xa5c4
209#define OCP_EEE_ADV 0xa5d0
210#define OCP_EEE_LPABLE 0xa5d2
211#define OCP_10GBT_CTRL 0xa5d4
212#define OCP_10GBT_STAT 0xa5d6
213#define OCP_EEE_ADV2 0xa6d4
214#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
215#define OCP_PHY_PATCH_STAT 0xb800
216#define OCP_PHY_PATCH_CMD 0xb820
217#define OCP_PHY_LOCK 0xb82e
218#define OCP_ADC_IOFFSET 0xbcfc
219#define OCP_ADC_CFG 0xbc06
220#define OCP_SYSCLK_CFG 0xc416
221
222/* SRAM Register */
223#define SRAM_GREEN_CFG 0x8011
224#define SRAM_LPF_CFG 0x8012
225#define SRAM_GPHY_FW_VER 0x801e
226#define SRAM_10M_AMP1 0x8080
227#define SRAM_10M_AMP2 0x8082
228#define SRAM_IMPEDANCE 0x8084
229#define SRAM_PHY_LOCK 0xb82e
230
231/* PLA_RCR */
232#define RCR_AAP 0x00000001
233#define RCR_APM 0x00000002
234#define RCR_AM 0x00000004
235#define RCR_AB 0x00000008
236#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
237#define SLOT_EN BIT(11)
238
239/* PLA_RCR1 */
240#define OUTER_VLAN BIT(7)
241#define INNER_VLAN BIT(6)
242
243/* PLA_RXFIFO_CTRL0 */
244#define RXFIFO_THR1_NORMAL 0x00080002
245#define RXFIFO_THR1_OOB 0x01800003
246
247/* PLA_RXFIFO_FULL */
248#define RXFIFO_FULL_MASK 0xfff
249
250/* PLA_RXFIFO_CTRL1 */
251#define RXFIFO_THR2_FULL 0x00000060
252#define RXFIFO_THR2_HIGH 0x00000038
253#define RXFIFO_THR2_OOB 0x0000004a
254#define RXFIFO_THR2_NORMAL 0x00a0
255
256/* PLA_RXFIFO_CTRL2 */
257#define RXFIFO_THR3_FULL 0x00000078
258#define RXFIFO_THR3_HIGH 0x00000048
259#define RXFIFO_THR3_OOB 0x0000005a
260#define RXFIFO_THR3_NORMAL 0x0110
261
262/* PLA_TXFIFO_CTRL */
263#define TXFIFO_THR_NORMAL 0x00400008
264#define TXFIFO_THR_NORMAL2 0x01000008
265
266/* PLA_DMY_REG0 */
267#define ECM_ALDPS 0x0002
268
269/* PLA_FMC */
270#define FMC_FCR_MCU_EN 0x0001
271
272/* PLA_EEEP_CR */
273#define EEEP_CR_EEEP_TX 0x0002
274
275/* PLA_WDT6_CTRL */
276#define WDT6_SET_MODE 0x0010
277
278/* PLA_TCR0 */
279#define TCR0_TX_EMPTY 0x0800
280#define TCR0_AUTO_FIFO 0x0080
281
282/* PLA_TCR1 */
283#define VERSION_MASK 0x7cf0
284#define IFG_MASK (BIT(3) | BIT(9) | BIT(8))
285#define IFG_144NS BIT(9)
286#define IFG_96NS (BIT(9) | BIT(8))
287
288/* PLA_MTPS */
289#define MTPS_JUMBO (12 * 1024 / 64)
290#define MTPS_DEFAULT (6 * 1024 / 64)
291
292/* PLA_RSTTALLY */
293#define TALLY_RESET 0x0001
294
295/* PLA_CR */
296#define CR_RST 0x10
297#define CR_RE 0x08
298#define CR_TE 0x04
299
300/* PLA_CRWECR */
301#define CRWECR_NORAML 0x00
302#define CRWECR_CONFIG 0xc0
303
304/* PLA_OOB_CTRL */
305#define NOW_IS_OOB 0x80
306#define TXFIFO_EMPTY 0x20
307#define RXFIFO_EMPTY 0x10
308#define LINK_LIST_READY 0x02
309#define DIS_MCU_CLROOB 0x01
310#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
311
312/* PLA_MISC_1 */
313#define RXDY_GATED_EN 0x0008
314
315/* PLA_SFF_STS_7 */
316#define RE_INIT_LL 0x8000
317#define MCU_BORW_EN 0x4000
318
319/* PLA_CPCR */
320#define FLOW_CTRL_EN BIT(0)
321#define CPCR_RX_VLAN 0x0040
322
323/* PLA_CFG_WOL */
324#define MAGIC_EN 0x0001
325
326/* PLA_TEREDO_CFG */
327#define TEREDO_SEL 0x8000
328#define TEREDO_WAKE_MASK 0x7f00
329#define TEREDO_RS_EVENT_MASK 0x00fe
330#define OOB_TEREDO_EN 0x0001
331
332/* PLA_BDC_CR */
333#define ALDPS_PROXY_MODE 0x0001
334
335/* PLA_EFUSE_CMD */
336#define EFUSE_READ_CMD BIT(15)
337#define EFUSE_DATA_BIT16 BIT(7)
338
339/* PLA_CONFIG34 */
340#define LINK_ON_WAKE_EN 0x0010
341#define LINK_OFF_WAKE_EN 0x0008
342
343/* PLA_CONFIG6 */
344#define LANWAKE_CLR_EN BIT(0)
345
346/* PLA_USB_CFG */
347#define EN_XG_LIP BIT(1)
348#define EN_G_LIP BIT(2)
349
350/* PLA_CONFIG5 */
351#define BWF_EN 0x0040
352#define MWF_EN 0x0020
353#define UWF_EN 0x0010
354#define LAN_WAKE_EN 0x0002
355
356/* PLA_LED_FEATURE */
357#define LED_MODE_MASK 0x0700
358
359/* PLA_PHY_PWR */
360#define TX_10M_IDLE_EN 0x0080
361#define PFM_PWM_SWITCH 0x0040
362#define TEST_IO_OFF BIT(4)
363
364/* PLA_MAC_PWR_CTRL */
365#define D3_CLK_GATED_EN 0x00004000
366#define MCU_CLK_RATIO 0x07010f07
367#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
368#define ALDPS_SPDWN_RATIO 0x0f87
369
370/* PLA_MAC_PWR_CTRL2 */
371#define EEE_SPDWN_RATIO 0x8007
372#define MAC_CLK_SPDWN_EN BIT(15)
373#define EEE_SPDWN_RATIO_MASK 0xff
374
375/* PLA_MAC_PWR_CTRL3 */
376#define PLA_MCU_SPDWN_EN BIT(14)
377#define PKT_AVAIL_SPDWN_EN 0x0100
378#define SUSPEND_SPDWN_EN 0x0004
379#define U1U2_SPDWN_EN 0x0002
380#define L1_SPDWN_EN 0x0001
381
382/* PLA_MAC_PWR_CTRL4 */
383#define PWRSAVE_SPDWN_EN 0x1000
384#define RXDV_SPDWN_EN 0x0800
385#define TX10MIDLE_EN 0x0100
386#define IDLE_SPDWN_EN BIT(6)
387#define TP100_SPDWN_EN 0x0020
388#define TP500_SPDWN_EN 0x0010
389#define TP1000_SPDWN_EN 0x0008
390#define EEE_SPDWN_EN 0x0001
391
392/* PLA_GPHY_INTR_IMR */
393#define GPHY_STS_MSK 0x0001
394#define SPEED_DOWN_MSK 0x0002
395#define SPDWN_RXDV_MSK 0x0004
396#define SPDWN_LINKCHG_MSK 0x0008
397
398/* PLA_PHYAR */
399#define PHYAR_FLAG 0x80000000
400
401/* PLA_EEE_CR */
402#define EEE_RX_EN 0x0001
403#define EEE_TX_EN 0x0002
404
405/* PLA_BOOT_CTRL */
406#define AUTOLOAD_DONE 0x0002
407
408/* PLA_LWAKE_CTRL_REG */
409#define LANWAKE_PIN BIT(7)
410
411/* PLA_SUSPEND_FLAG */
412#define LINK_CHG_EVENT BIT(0)
413
414/* PLA_INDICATE_FALG */
415#define UPCOMING_RUNTIME_D3 BIT(0)
416
417/* PLA_MACDBG_PRE and PLA_MACDBG_POST */
418#define DEBUG_OE BIT(0)
419#define DEBUG_LTSSM 0x0082
420
421/* PLA_EXTRA_STATUS */
422#define CUR_LINK_OK BIT(15)
423#define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
424#define LINK_CHANGE_FLAG BIT(8)
425#define POLL_LINK_CHG BIT(0)
426
427/* PLA_GPHY_CTRL */
428#define GPHY_FLASH BIT(1)
429
430/* PLA_POL_GPIO_CTRL */
431#define DACK_DET_EN BIT(15)
432#define POL_GPHY_PATCH BIT(4)
433
434/* USB_USB2PHY */
435#define USB2PHY_SUSPEND 0x0001
436#define USB2PHY_L1 0x0002
437
438/* USB_SSPHYLINK1 */
439#define DELAY_PHY_PWR_CHG BIT(1)
440
441/* USB_SSPHYLINK2 */
442#define pwd_dn_scale_mask 0x3ffe
443#define pwd_dn_scale(x) ((x) << 1)
444
445/* USB_CSR_DUMMY1 */
446#define DYNAMIC_BURST 0x0001
447
448/* USB_CSR_DUMMY2 */
449#define EP4_FULL_FC 0x0001
450
451/* USB_DEV_STAT */
452#define STAT_SPEED_MASK 0x0006
453#define STAT_SPEED_HIGH 0x0000
454#define STAT_SPEED_FULL 0x0002
455
456/* USB_FW_FIX_EN0 */
457#define FW_FIX_SUSPEND BIT(14)
458
459/* USB_FW_FIX_EN1 */
460#define FW_IP_RESET_EN BIT(9)
461
462/* USB_LPM_CONFIG */
463#define LPM_U1U2_EN BIT(0)
464
465/* USB_TX_AGG */
466#define TX_AGG_MAX_THRESHOLD 0x03
467
468/* USB_RX_BUF_TH */
469#define RX_THR_SUPPER 0x0c350180
470#define RX_THR_HIGH 0x7a120180
471#define RX_THR_SLOW 0xffff0180
472#define RX_THR_B 0x00010001
473
474/* USB_TX_DMA */
475#define TEST_MODE_DISABLE 0x00000001
476#define TX_SIZE_ADJUST1 0x00000100
477
478/* USB_BMU_RESET */
479#define BMU_RESET_EP_IN 0x01
480#define BMU_RESET_EP_OUT 0x02
481
482/* USB_BMU_CONFIG */
483#define ACT_ODMA BIT(1)
484
485/* USB_UPT_RXDMA_OWN */
486#define OWN_UPDATE BIT(0)
487#define OWN_CLEAR BIT(1)
488
489/* USB_FW_TASK */
490#define FC_PATCH_TASK BIT(1)
491
492/* USB_RX_AGGR_NUM */
493#define RX_AGGR_NUM_MASK 0x1ff
494
495/* USB_UPS_CTRL */
496#define POWER_CUT 0x0100
497
498/* USB_PM_CTRL_STATUS */
499#define RESUME_INDICATE 0x0001
500
501/* USB_ECM_OPTION */
502#define BYPASS_MAC_RESET BIT(5)
503
504/* USB_CSTMR */
505#define FORCE_SUPER BIT(0)
506
507/* USB_MISC_2 */
508#define UPS_FORCE_PWR_DOWN BIT(0)
509
510/* USB_ECM_OP */
511#define EN_ALL_SPEED BIT(0)
512
513/* USB_GPHY_CTRL */
514#define GPHY_PATCH_DONE BIT(2)
515#define BYPASS_FLASH BIT(5)
516#define BACKUP_RESTRORE BIT(6)
517
518/* USB_SPEED_OPTION */
519#define RG_PWRDN_EN BIT(8)
520#define ALL_SPEED_OFF BIT(9)
521
522/* USB_FW_CTRL */
523#define FLOW_CTRL_PATCH_OPT BIT(1)
524#define AUTO_SPEEDUP BIT(3)
525#define FLOW_CTRL_PATCH_2 BIT(8)
526
527/* USB_FC_TIMER */
528#define CTRL_TIMER_EN BIT(15)
529
530/* USB_USB_CTRL */
531#define CDC_ECM_EN BIT(3)
532#define RX_AGG_DISABLE 0x0010
533#define RX_ZERO_EN 0x0080
534
535/* USB_U2P3_CTRL */
536#define U2P3_ENABLE 0x0001
537#define RX_DETECT8 BIT(3)
538
539/* USB_POWER_CUT */
540#define PWR_EN 0x0001
541#define PHASE2_EN 0x0008
542#define UPS_EN BIT(4)
543#define USP_PREWAKE BIT(5)
544
545/* USB_MISC_0 */
546#define PCUT_STATUS 0x0001
547
548/* USB_RX_EARLY_TIMEOUT */
549#define COALESCE_SUPER 85000U
550#define COALESCE_HIGH 250000U
551#define COALESCE_SLOW 524280U
552
553/* USB_WDT1_CTRL */
554#define WTD1_EN BIT(0)
555
556/* USB_WDT11_CTRL */
557#define TIMER11_EN 0x0001
558
559/* USB_LPM_CTRL */
560/* bit 4 ~ 5: fifo empty boundary */
561#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
562/* bit 2 ~ 3: LMP timer */
563#define LPM_TIMER_MASK 0x0c
564#define LPM_TIMER_500MS 0x04 /* 500 ms */
565#define LPM_TIMER_500US 0x0c /* 500 us */
566#define ROK_EXIT_LPM 0x02
567
568/* USB_AFE_CTRL2 */
569#define SEN_VAL_MASK 0xf800
570#define SEN_VAL_NORMAL 0xa000
571#define SEL_RXIDLE 0x0100
572
573/* USB_UPHY_XTAL */
574#define OOBS_POLLING BIT(8)
575
576/* USB_UPS_CFG */
577#define SAW_CNT_1MS_MASK 0x0fff
578#define MID_REVERSE BIT(5) /* RTL8156A */
579
580/* USB_UPS_FLAGS */
581#define UPS_FLAGS_R_TUNE BIT(0)
582#define UPS_FLAGS_EN_10M_CKDIV BIT(1)
583#define UPS_FLAGS_250M_CKDIV BIT(2)
584#define UPS_FLAGS_EN_ALDPS BIT(3)
585#define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
586#define UPS_FLAGS_SPEED_MASK (0xf << 16)
587#define ups_flags_speed(x) ((x) << 16)
588#define UPS_FLAGS_EN_EEE BIT(20)
589#define UPS_FLAGS_EN_500M_EEE BIT(21)
590#define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
591#define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
592#define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
593#define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
594#define UPS_FLAGS_EN_GREEN BIT(26)
595#define UPS_FLAGS_EN_FLOW_CTR BIT(27)
596
597enum spd_duplex {
598 NWAY_10M_HALF,
599 NWAY_10M_FULL,
600 NWAY_100M_HALF,
601 NWAY_100M_FULL,
602 NWAY_1000M_FULL,
603 FORCE_10M_HALF,
604 FORCE_10M_FULL,
605 FORCE_100M_HALF,
606 FORCE_100M_FULL,
607 FORCE_1000M_FULL,
608 NWAY_2500M_FULL,
609};
610
611/* OCP_ALDPS_CONFIG */
612#define ENPWRSAVE 0x8000
613#define ENPDNPS 0x0200
614#define LINKENA 0x0100
615#define DIS_SDSAVE 0x0010
616
617/* OCP_PHY_STATUS */
618#define PHY_STAT_MASK 0x0007
619#define PHY_STAT_EXT_INIT 2
620#define PHY_STAT_LAN_ON 3
621#define PHY_STAT_PWRDN 5
622
623/* OCP_NCTL_CFG */
624#define PGA_RETURN_EN BIT(1)
625
626/* OCP_POWER_CFG */
627#define EEE_CLKDIV_EN 0x8000
628#define EN_ALDPS 0x0004
629#define EN_10M_PLLOFF 0x0001
630
631/* OCP_EEE_CONFIG1 */
632#define RG_TXLPI_MSK_HFDUP 0x8000
633#define RG_MATCLR_EN 0x4000
634#define EEE_10_CAP 0x2000
635#define EEE_NWAY_EN 0x1000
636#define TX_QUIET_EN 0x0200
637#define RX_QUIET_EN 0x0100
638#define sd_rise_time_mask 0x0070
639#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
640#define RG_RXLPI_MSK_HFDUP 0x0008
641#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
642
643/* OCP_EEE_CONFIG2 */
644#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
645#define RG_DACQUIET_EN 0x0400
646#define RG_LDVQUIET_EN 0x0200
647#define RG_CKRSEL 0x0020
648#define RG_EEEPRG_EN 0x0010
649
650/* OCP_EEE_CONFIG3 */
651#define fast_snr_mask 0xff80
652#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
653#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
654#define MSK_PH 0x0006 /* bit 0 ~ 3 */
655
656/* OCP_EEE_AR */
657/* bit[15:14] function */
658#define FUN_ADDR 0x0000
659#define FUN_DATA 0x4000
660/* bit[4:0] device addr */
661
662/* OCP_EEE_CFG */
663#define CTAP_SHORT_EN 0x0040
664#define EEE10_EN 0x0010
665
666/* OCP_DOWN_SPEED */
667#define EN_EEE_CMODE BIT(14)
668#define EN_EEE_1000 BIT(13)
669#define EN_EEE_100 BIT(12)
670#define EN_10M_CLKDIV BIT(11)
671#define EN_10M_BGOFF 0x0080
672
673/* OCP_10GBT_CTRL */
674#define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */
675
676/* OCP_PHY_STATE */
677#define TXDIS_STATE 0x01
678#define ABD_STATE 0x02
679
680/* OCP_PHY_PATCH_STAT */
681#define PATCH_READY BIT(6)
682
683/* OCP_PHY_PATCH_CMD */
684#define PATCH_REQUEST BIT(4)
685
686/* OCP_PHY_LOCK */
687#define PATCH_LOCK BIT(0)
688
689/* OCP_ADC_CFG */
690#define CKADSEL_L 0x0100
691#define ADC_EN 0x0080
692#define EN_EMI_L 0x0040
693
694/* OCP_SYSCLK_CFG */
695#define sysclk_div_expo(x) (min(x, 5) << 8)
696#define clk_div_expo(x) (min(x, 5) << 4)
697
698/* SRAM_GREEN_CFG */
699#define GREEN_ETH_EN BIT(15)
700#define R_TUNE_EN BIT(11)
701
702/* SRAM_LPF_CFG */
703#define LPF_AUTO_TUNE 0x8000
704
705/* SRAM_10M_AMP1 */
706#define GDAC_IB_UPALL 0x0008
707
708/* SRAM_10M_AMP2 */
709#define AMP_DN 0x0200
710
711/* SRAM_IMPEDANCE */
712#define RX_DRIVING_MASK 0x6000
713
714/* SRAM_PHY_LOCK */
715#define PHY_PATCH_LOCK 0x0001
716
717/* MAC PASSTHRU */
718#define AD_MASK 0xfee0
719#define BND_MASK 0x0004
720#define BD_MASK 0x0001
721#define EFUSE 0xcfdb
722#define PASS_THRU_MASK 0x1
723
724#define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
725
726enum rtl_register_content {
727 _2500bps = BIT(10),
728 _1250bps = BIT(9),
729 _500bps = BIT(8),
730 _tx_flow = BIT(6),
731 _rx_flow = BIT(5),
732 _1000bps = 0x10,
733 _100bps = 0x08,
734 _10bps = 0x04,
735 LINK_STATUS = 0x02,
736 FULL_DUP = 0x01,
737};
738
739#define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
740#define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
741
742#define RTL8152_MAX_TX 4
743#define RTL8152_MAX_RX 10
744#define INTBUFSIZE 2
745#define TX_ALIGN 4
746#define RX_ALIGN 8
747
748#define RTL8152_RX_MAX_PENDING 4096
749#define RTL8152_RXFG_HEADSZ 256
750
751#define INTR_LINK 0x0004
752
753#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
754#define RTL8153_RMS RTL8153_MAX_PACKET
755#define RTL8152_TX_TIMEOUT (5 * HZ)
756#define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
757#define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
758#define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
759
760/* rtl8152 flags */
761enum rtl8152_flags {
762 RTL8152_UNPLUG = 0,
763 RTL8152_SET_RX_MODE,
764 WORK_ENABLE,
765 RTL8152_LINK_CHG,
766 SELECTIVE_SUSPEND,
767 PHY_RESET,
768 SCHEDULE_TASKLET,
769 GREEN_ETHERNET,
770 RX_EPROTO,
771};
772
773#define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
774#define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
775
776struct tally_counter {
777 __le64 tx_packets;
778 __le64 rx_packets;
779 __le64 tx_errors;
780 __le32 rx_errors;
781 __le16 rx_missed;
782 __le16 align_errors;
783 __le32 tx_one_collision;
784 __le32 tx_multi_collision;
785 __le64 rx_unicast;
786 __le64 rx_broadcast;
787 __le32 rx_multicast;
788 __le16 tx_aborted;
789 __le16 tx_underrun;
790};
791
792struct rx_desc {
793 __le32 opts1;
794#define RX_LEN_MASK 0x7fff
795
796 __le32 opts2;
797#define RD_UDP_CS BIT(23)
798#define RD_TCP_CS BIT(22)
799#define RD_IPV6_CS BIT(20)
800#define RD_IPV4_CS BIT(19)
801
802 __le32 opts3;
803#define IPF BIT(23) /* IP checksum fail */
804#define UDPF BIT(22) /* UDP checksum fail */
805#define TCPF BIT(21) /* TCP checksum fail */
806#define RX_VLAN_TAG BIT(16)
807
808 __le32 opts4;
809 __le32 opts5;
810 __le32 opts6;
811};
812
813struct tx_desc {
814 __le32 opts1;
815#define TX_FS BIT(31) /* First segment of a packet */
816#define TX_LS BIT(30) /* Final segment of a packet */
817#define GTSENDV4 BIT(28)
818#define GTSENDV6 BIT(27)
819#define GTTCPHO_SHIFT 18
820#define GTTCPHO_MAX 0x7fU
821#define TX_LEN_MAX 0x3ffffU
822
823 __le32 opts2;
824#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
825#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
826#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
827#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
828#define MSS_SHIFT 17
829#define MSS_MAX 0x7ffU
830#define TCPHO_SHIFT 17
831#define TCPHO_MAX 0x7ffU
832#define TX_VLAN_TAG BIT(16)
833};
834
835struct r8152;
836
837struct rx_agg {
838 struct list_head list, info_list;
839 struct urb *urb;
840 struct r8152 *context;
841 struct page *page;
842 void *buffer;
843};
844
845struct tx_agg {
846 struct list_head list;
847 struct urb *urb;
848 struct r8152 *context;
849 void *buffer;
850 void *head;
851 u32 skb_num;
852 u32 skb_len;
853};
854
855struct r8152 {
856 unsigned long flags;
857 struct usb_device *udev;
858 struct napi_struct napi;
859 struct usb_interface *intf;
860 struct net_device *netdev;
861 struct urb *intr_urb;
862 struct tx_agg tx_info[RTL8152_MAX_TX];
863 struct list_head rx_info, rx_used;
864 struct list_head rx_done, tx_free;
865 struct sk_buff_head tx_queue, rx_queue;
866 spinlock_t rx_lock, tx_lock;
867 struct delayed_work schedule, hw_phy_work;
868 struct mii_if_info mii;
869 struct mutex control; /* use for hw setting */
870#ifdef CONFIG_PM_SLEEP
871 struct notifier_block pm_notifier;
872#endif
873 struct tasklet_struct tx_tl;
874
875 struct rtl_ops {
876 void (*init)(struct r8152 *tp);
877 int (*enable)(struct r8152 *tp);
878 void (*disable)(struct r8152 *tp);
879 void (*up)(struct r8152 *tp);
880 void (*down)(struct r8152 *tp);
881 void (*unload)(struct r8152 *tp);
882 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
883 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
884 bool (*in_nway)(struct r8152 *tp);
885 void (*hw_phy_cfg)(struct r8152 *tp);
886 void (*autosuspend_en)(struct r8152 *tp, bool enable);
887 void (*change_mtu)(struct r8152 *tp);
888 } rtl_ops;
889
890 struct ups_info {
891 u32 r_tune:1;
892 u32 _10m_ckdiv:1;
893 u32 _250m_ckdiv:1;
894 u32 aldps:1;
895 u32 lite_mode:2;
896 u32 speed_duplex:4;
897 u32 eee:1;
898 u32 eee_lite:1;
899 u32 eee_ckdiv:1;
900 u32 eee_plloff_100:1;
901 u32 eee_plloff_giga:1;
902 u32 eee_cmod_lv:1;
903 u32 green:1;
904 u32 flow_control:1;
905 u32 ctap_short_off:1;
906 } ups_info;
907
908#define RTL_VER_SIZE 32
909
910 struct rtl_fw {
911 const char *fw_name;
912 const struct firmware *fw;
913
914 char version[RTL_VER_SIZE];
915 int (*pre_fw)(struct r8152 *tp);
916 int (*post_fw)(struct r8152 *tp);
917
918 bool retry;
919 } rtl_fw;
920
921 atomic_t rx_count;
922
923 bool eee_en;
924 int intr_interval;
925 u32 saved_wolopts;
926 u32 msg_enable;
927 u32 tx_qlen;
928 u32 coalesce;
929 u32 advertising;
930 u32 rx_buf_sz;
931 u32 rx_copybreak;
932 u32 rx_pending;
933 u32 fc_pause_on, fc_pause_off;
934
935 unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out;
936
937 u32 support_2500full:1;
938 u32 lenovo_macpassthru:1;
939 u32 dell_tb_rx_agg_bug:1;
940 u16 ocp_base;
941 u16 speed;
942 u16 eee_adv;
943 u8 *intr_buff;
944 u8 version;
945 u8 duplex;
946 u8 autoneg;
947};
948
949/**
950 * struct fw_block - block type and total length
951 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
952 * RTL_FW_USB and so on.
953 * @length: total length of the current block.
954 */
955struct fw_block {
956 __le32 type;
957 __le32 length;
958} __packed;
959
960/**
961 * struct fw_header - header of the firmware file
962 * @checksum: checksum of sha256 which is calculated from the whole file
963 * except the checksum field of the file. That is, calculate sha256
964 * from the version field to the end of the file.
965 * @version: version of this firmware.
966 * @blocks: the first firmware block of the file
967 */
968struct fw_header {
969 u8 checksum[32];
970 char version[RTL_VER_SIZE];
971 struct fw_block blocks[];
972} __packed;
973
974enum rtl8152_fw_flags {
975 FW_FLAGS_USB = 0,
976 FW_FLAGS_PLA,
977 FW_FLAGS_START,
978 FW_FLAGS_STOP,
979 FW_FLAGS_NC,
980 FW_FLAGS_NC1,
981 FW_FLAGS_NC2,
982 FW_FLAGS_UC2,
983 FW_FLAGS_UC,
984 FW_FLAGS_SPEED_UP,
985 FW_FLAGS_VER,
986};
987
988enum rtl8152_fw_fixup_cmd {
989 FW_FIXUP_AND = 0,
990 FW_FIXUP_OR,
991 FW_FIXUP_NOT,
992 FW_FIXUP_XOR,
993};
994
995struct fw_phy_set {
996 __le16 addr;
997 __le16 data;
998} __packed;
999
1000struct fw_phy_speed_up {
1001 struct fw_block blk_hdr;
1002 __le16 fw_offset;
1003 __le16 version;
1004 __le16 fw_reg;
1005 __le16 reserved;
1006 char info[];
1007} __packed;
1008
1009struct fw_phy_ver {
1010 struct fw_block blk_hdr;
1011 struct fw_phy_set ver;
1012 __le32 reserved;
1013} __packed;
1014
1015struct fw_phy_fixup {
1016 struct fw_block blk_hdr;
1017 struct fw_phy_set setting;
1018 __le16 bit_cmd;
1019 __le16 reserved;
1020} __packed;
1021
1022struct fw_phy_union {
1023 struct fw_block blk_hdr;
1024 __le16 fw_offset;
1025 __le16 fw_reg;
1026 struct fw_phy_set pre_set[2];
1027 struct fw_phy_set bp[8];
1028 struct fw_phy_set bp_en;
1029 u8 pre_num;
1030 u8 bp_num;
1031 char info[];
1032} __packed;
1033
1034/**
1035 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
1036 * The layout of the firmware block is:
1037 * <struct fw_mac> + <info> + <firmware data>.
1038 * @blk_hdr: firmware descriptor (type, length)
1039 * @fw_offset: offset of the firmware binary data. The start address of
1040 * the data would be the address of struct fw_mac + @fw_offset.
1041 * @fw_reg: the register to load the firmware. Depends on chip.
1042 * @bp_ba_addr: the register to write break point base address. Depends on
1043 * chip.
1044 * @bp_ba_value: break point base address. Depends on chip.
1045 * @bp_en_addr: the register to write break point enabled mask. Depends
1046 * on chip.
1047 * @bp_en_value: break point enabled mask. Depends on the firmware.
1048 * @bp_start: the start register of break points. Depends on chip.
1049 * @bp_num: the break point number which needs to be set for this firmware.
1050 * Depends on the firmware.
1051 * @bp: break points. Depends on firmware.
1052 * @reserved: reserved space (unused)
1053 * @fw_ver_reg: the register to store the fw version.
1054 * @fw_ver_data: the firmware version of the current type.
1055 * @info: additional information for debugging, and is followed by the
1056 * binary data of firmware.
1057 */
1058struct fw_mac {
1059 struct fw_block blk_hdr;
1060 __le16 fw_offset;
1061 __le16 fw_reg;
1062 __le16 bp_ba_addr;
1063 __le16 bp_ba_value;
1064 __le16 bp_en_addr;
1065 __le16 bp_en_value;
1066 __le16 bp_start;
1067 __le16 bp_num;
1068 __le16 bp[16]; /* any value determined by firmware */
1069 __le32 reserved;
1070 __le16 fw_ver_reg;
1071 u8 fw_ver_data;
1072 char info[];
1073} __packed;
1074
1075/**
1076 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
1077 * This is used to set patch key when loading the firmware of PHY.
1078 * @blk_hdr: firmware descriptor (type, length)
1079 * @key_reg: the register to write the patch key.
1080 * @key_data: patch key.
1081 * @reserved: reserved space (unused)
1082 */
1083struct fw_phy_patch_key {
1084 struct fw_block blk_hdr;
1085 __le16 key_reg;
1086 __le16 key_data;
1087 __le32 reserved;
1088} __packed;
1089
1090/**
1091 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
1092 * The layout of the firmware block is:
1093 * <struct fw_phy_nc> + <info> + <firmware data>.
1094 * @blk_hdr: firmware descriptor (type, length)
1095 * @fw_offset: offset of the firmware binary data. The start address of
1096 * the data would be the address of struct fw_phy_nc + @fw_offset.
1097 * @fw_reg: the register to load the firmware. Depends on chip.
1098 * @ba_reg: the register to write the base address. Depends on chip.
1099 * @ba_data: base address. Depends on chip.
1100 * @patch_en_addr: the register of enabling patch mode. Depends on chip.
1101 * @patch_en_value: patch mode enabled mask. Depends on the firmware.
1102 * @mode_reg: the regitster of switching the mode.
1103 * @mode_pre: the mode needing to be set before loading the firmware.
1104 * @mode_post: the mode to be set when finishing to load the firmware.
1105 * @reserved: reserved space (unused)
1106 * @bp_start: the start register of break points. Depends on chip.
1107 * @bp_num: the break point number which needs to be set for this firmware.
1108 * Depends on the firmware.
1109 * @bp: break points. Depends on firmware.
1110 * @info: additional information for debugging, and is followed by the
1111 * binary data of firmware.
1112 */
1113struct fw_phy_nc {
1114 struct fw_block blk_hdr;
1115 __le16 fw_offset;
1116 __le16 fw_reg;
1117 __le16 ba_reg;
1118 __le16 ba_data;
1119 __le16 patch_en_addr;
1120 __le16 patch_en_value;
1121 __le16 mode_reg;
1122 __le16 mode_pre;
1123 __le16 mode_post;
1124 __le16 reserved;
1125 __le16 bp_start;
1126 __le16 bp_num;
1127 __le16 bp[4];
1128 char info[];
1129} __packed;
1130
1131enum rtl_fw_type {
1132 RTL_FW_END = 0,
1133 RTL_FW_PLA,
1134 RTL_FW_USB,
1135 RTL_FW_PHY_START,
1136 RTL_FW_PHY_STOP,
1137 RTL_FW_PHY_NC,
1138 RTL_FW_PHY_FIXUP,
1139 RTL_FW_PHY_UNION_NC,
1140 RTL_FW_PHY_UNION_NC1,
1141 RTL_FW_PHY_UNION_NC2,
1142 RTL_FW_PHY_UNION_UC2,
1143 RTL_FW_PHY_UNION_UC,
1144 RTL_FW_PHY_UNION_MISC,
1145 RTL_FW_PHY_SPEED_UP,
1146 RTL_FW_PHY_VER,
1147};
1148
1149enum rtl_version {
1150 RTL_VER_UNKNOWN = 0,
1151 RTL_VER_01,
1152 RTL_VER_02,
1153 RTL_VER_03,
1154 RTL_VER_04,
1155 RTL_VER_05,
1156 RTL_VER_06,
1157 RTL_VER_07,
1158 RTL_VER_08,
1159 RTL_VER_09,
1160
1161 RTL_TEST_01,
1162 RTL_VER_10,
1163 RTL_VER_11,
1164 RTL_VER_12,
1165 RTL_VER_13,
1166 RTL_VER_14,
1167 RTL_VER_15,
1168
1169 RTL_VER_MAX
1170};
1171
1172enum tx_csum_stat {
1173 TX_CSUM_SUCCESS = 0,
1174 TX_CSUM_TSO,
1175 TX_CSUM_NONE
1176};
1177
1178#define RTL_ADVERTISED_10_HALF BIT(0)
1179#define RTL_ADVERTISED_10_FULL BIT(1)
1180#define RTL_ADVERTISED_100_HALF BIT(2)
1181#define RTL_ADVERTISED_100_FULL BIT(3)
1182#define RTL_ADVERTISED_1000_HALF BIT(4)
1183#define RTL_ADVERTISED_1000_FULL BIT(5)
1184#define RTL_ADVERTISED_2500_FULL BIT(6)
1185
1186/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1187 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1188 */
1189static const int multicast_filter_limit = 32;
1190static unsigned int agg_buf_sz = 16384;
1191
1192#define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc))
1193
1194static
1195int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1196{
1197 int ret;
1198 void *tmp;
1199
1200 tmp = kmalloc(size, GFP_KERNEL);
1201 if (!tmp)
1202 return -ENOMEM;
1203
1204 ret = usb_control_msg(tp->udev, tp->pipe_ctrl_in,
1205 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1206 value, index, tmp, size, 500);
1207 if (ret < 0)
1208 memset(data, 0xff, size);
1209 else
1210 memcpy(data, tmp, size);
1211
1212 kfree(tmp);
1213
1214 return ret;
1215}
1216
1217static
1218int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1219{
1220 int ret;
1221 void *tmp;
1222
1223 tmp = kmemdup(data, size, GFP_KERNEL);
1224 if (!tmp)
1225 return -ENOMEM;
1226
1227 ret = usb_control_msg(tp->udev, tp->pipe_ctrl_out,
1228 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1229 value, index, tmp, size, 500);
1230
1231 kfree(tmp);
1232
1233 return ret;
1234}
1235
1236static void rtl_set_unplug(struct r8152 *tp)
1237{
1238 if (tp->udev->state == USB_STATE_NOTATTACHED) {
1239 set_bit(RTL8152_UNPLUG, &tp->flags);
1240 smp_mb__after_atomic();
1241 }
1242}
1243
1244static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1245 void *data, u16 type)
1246{
1247 u16 limit = 64;
1248 int ret = 0;
1249
1250 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1251 return -ENODEV;
1252
1253 /* both size and indix must be 4 bytes align */
1254 if ((size & 3) || !size || (index & 3) || !data)
1255 return -EPERM;
1256
1257 if ((u32)index + (u32)size > 0xffff)
1258 return -EPERM;
1259
1260 while (size) {
1261 if (size > limit) {
1262 ret = get_registers(tp, index, type, limit, data);
1263 if (ret < 0)
1264 break;
1265
1266 index += limit;
1267 data += limit;
1268 size -= limit;
1269 } else {
1270 ret = get_registers(tp, index, type, size, data);
1271 if (ret < 0)
1272 break;
1273
1274 index += size;
1275 data += size;
1276 size = 0;
1277 break;
1278 }
1279 }
1280
1281 if (ret == -ENODEV)
1282 rtl_set_unplug(tp);
1283
1284 return ret;
1285}
1286
1287static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1288 u16 size, void *data, u16 type)
1289{
1290 int ret;
1291 u16 byteen_start, byteen_end, byen;
1292 u16 limit = 512;
1293
1294 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1295 return -ENODEV;
1296
1297 /* both size and indix must be 4 bytes align */
1298 if ((size & 3) || !size || (index & 3) || !data)
1299 return -EPERM;
1300
1301 if ((u32)index + (u32)size > 0xffff)
1302 return -EPERM;
1303
1304 byteen_start = byteen & BYTE_EN_START_MASK;
1305 byteen_end = byteen & BYTE_EN_END_MASK;
1306
1307 byen = byteen_start | (byteen_start << 4);
1308 ret = set_registers(tp, index, type | byen, 4, data);
1309 if (ret < 0)
1310 goto error1;
1311
1312 index += 4;
1313 data += 4;
1314 size -= 4;
1315
1316 if (size) {
1317 size -= 4;
1318
1319 while (size) {
1320 if (size > limit) {
1321 ret = set_registers(tp, index,
1322 type | BYTE_EN_DWORD,
1323 limit, data);
1324 if (ret < 0)
1325 goto error1;
1326
1327 index += limit;
1328 data += limit;
1329 size -= limit;
1330 } else {
1331 ret = set_registers(tp, index,
1332 type | BYTE_EN_DWORD,
1333 size, data);
1334 if (ret < 0)
1335 goto error1;
1336
1337 index += size;
1338 data += size;
1339 size = 0;
1340 break;
1341 }
1342 }
1343
1344 byen = byteen_end | (byteen_end >> 4);
1345 ret = set_registers(tp, index, type | byen, 4, data);
1346 if (ret < 0)
1347 goto error1;
1348 }
1349
1350error1:
1351 if (ret == -ENODEV)
1352 rtl_set_unplug(tp);
1353
1354 return ret;
1355}
1356
1357static inline
1358int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1359{
1360 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1361}
1362
1363static inline
1364int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1365{
1366 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1367}
1368
1369static inline
1370int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1371{
1372 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1373}
1374
1375static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1376{
1377 __le32 data;
1378
1379 generic_ocp_read(tp, index, sizeof(data), &data, type);
1380
1381 return __le32_to_cpu(data);
1382}
1383
1384static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1385{
1386 __le32 tmp = __cpu_to_le32(data);
1387
1388 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1389}
1390
1391static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1392{
1393 u32 data;
1394 __le32 tmp;
1395 u16 byen = BYTE_EN_WORD;
1396 u8 shift = index & 2;
1397
1398 index &= ~3;
1399 byen <<= shift;
1400
1401 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1402
1403 data = __le32_to_cpu(tmp);
1404 data >>= (shift * 8);
1405 data &= 0xffff;
1406
1407 return (u16)data;
1408}
1409
1410static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1411{
1412 u32 mask = 0xffff;
1413 __le32 tmp;
1414 u16 byen = BYTE_EN_WORD;
1415 u8 shift = index & 2;
1416
1417 data &= mask;
1418
1419 if (index & 2) {
1420 byen <<= shift;
1421 mask <<= (shift * 8);
1422 data <<= (shift * 8);
1423 index &= ~3;
1424 }
1425
1426 tmp = __cpu_to_le32(data);
1427
1428 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1429}
1430
1431static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1432{
1433 u32 data;
1434 __le32 tmp;
1435 u8 shift = index & 3;
1436
1437 index &= ~3;
1438
1439 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1440
1441 data = __le32_to_cpu(tmp);
1442 data >>= (shift * 8);
1443 data &= 0xff;
1444
1445 return (u8)data;
1446}
1447
1448static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1449{
1450 u32 mask = 0xff;
1451 __le32 tmp;
1452 u16 byen = BYTE_EN_BYTE;
1453 u8 shift = index & 3;
1454
1455 data &= mask;
1456
1457 if (index & 3) {
1458 byen <<= shift;
1459 mask <<= (shift * 8);
1460 data <<= (shift * 8);
1461 index &= ~3;
1462 }
1463
1464 tmp = __cpu_to_le32(data);
1465
1466 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1467}
1468
1469static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1470{
1471 u16 ocp_base, ocp_index;
1472
1473 ocp_base = addr & 0xf000;
1474 if (ocp_base != tp->ocp_base) {
1475 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1476 tp->ocp_base = ocp_base;
1477 }
1478
1479 ocp_index = (addr & 0x0fff) | 0xb000;
1480 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1481}
1482
1483static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1484{
1485 u16 ocp_base, ocp_index;
1486
1487 ocp_base = addr & 0xf000;
1488 if (ocp_base != tp->ocp_base) {
1489 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1490 tp->ocp_base = ocp_base;
1491 }
1492
1493 ocp_index = (addr & 0x0fff) | 0xb000;
1494 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1495}
1496
1497static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1498{
1499 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1500}
1501
1502static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1503{
1504 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1505}
1506
1507static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1508{
1509 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1510 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1511}
1512
1513static u16 sram_read(struct r8152 *tp, u16 addr)
1514{
1515 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1516 return ocp_reg_read(tp, OCP_SRAM_DATA);
1517}
1518
1519static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1520{
1521 struct r8152 *tp = netdev_priv(netdev);
1522 int ret;
1523
1524 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1525 return -ENODEV;
1526
1527 if (phy_id != R8152_PHY_ID)
1528 return -EINVAL;
1529
1530 ret = r8152_mdio_read(tp, reg);
1531
1532 return ret;
1533}
1534
1535static
1536void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1537{
1538 struct r8152 *tp = netdev_priv(netdev);
1539
1540 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1541 return;
1542
1543 if (phy_id != R8152_PHY_ID)
1544 return;
1545
1546 r8152_mdio_write(tp, reg, val);
1547}
1548
1549static int
1550r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1551
1552static int
1553rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
1554 u32 advertising);
1555
1556static int __rtl8152_set_mac_address(struct net_device *netdev, void *p,
1557 bool in_resume)
1558{
1559 struct r8152 *tp = netdev_priv(netdev);
1560 struct sockaddr *addr = p;
1561 int ret = -EADDRNOTAVAIL;
1562
1563 if (!is_valid_ether_addr(addr->sa_data))
1564 goto out1;
1565
1566 if (!in_resume) {
1567 ret = usb_autopm_get_interface(tp->intf);
1568 if (ret < 0)
1569 goto out1;
1570 }
1571
1572 mutex_lock(&tp->control);
1573
1574 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1575
1576 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1577 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1578 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1579
1580 mutex_unlock(&tp->control);
1581
1582 if (!in_resume)
1583 usb_autopm_put_interface(tp->intf);
1584out1:
1585 return ret;
1586}
1587
1588static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1589{
1590 return __rtl8152_set_mac_address(netdev, p, false);
1591}
1592
1593/* Devices containing proper chips can support a persistent
1594 * host system provided MAC address.
1595 * Examples of this are Dell TB15 and Dell WD15 docks
1596 */
1597static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1598{
1599 acpi_status status;
1600 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1601 union acpi_object *obj;
1602 int ret = -EINVAL;
1603 u32 ocp_data;
1604 unsigned char buf[6];
1605 char *mac_obj_name;
1606 acpi_object_type mac_obj_type;
1607 int mac_strlen;
1608
1609 if (tp->lenovo_macpassthru) {
1610 mac_obj_name = "\\MACA";
1611 mac_obj_type = ACPI_TYPE_STRING;
1612 mac_strlen = 0x16;
1613 } else {
1614 /* test for -AD variant of RTL8153 */
1615 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1616 if ((ocp_data & AD_MASK) == 0x1000) {
1617 /* test for MAC address pass-through bit */
1618 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1619 if ((ocp_data & PASS_THRU_MASK) != 1) {
1620 netif_dbg(tp, probe, tp->netdev,
1621 "No efuse for RTL8153-AD MAC pass through\n");
1622 return -ENODEV;
1623 }
1624 } else {
1625 /* test for RTL8153-BND and RTL8153-BD */
1626 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1627 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1628 netif_dbg(tp, probe, tp->netdev,
1629 "Invalid variant for MAC pass through\n");
1630 return -ENODEV;
1631 }
1632 }
1633
1634 mac_obj_name = "\\_SB.AMAC";
1635 mac_obj_type = ACPI_TYPE_BUFFER;
1636 mac_strlen = 0x17;
1637 }
1638
1639 /* returns _AUXMAC_#AABBCCDDEEFF# */
1640 status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1641 obj = (union acpi_object *)buffer.pointer;
1642 if (!ACPI_SUCCESS(status))
1643 return -ENODEV;
1644 if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1645 netif_warn(tp, probe, tp->netdev,
1646 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1647 obj->type, obj->string.length);
1648 goto amacout;
1649 }
1650
1651 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1652 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1653 netif_warn(tp, probe, tp->netdev,
1654 "Invalid header when reading pass-thru MAC addr\n");
1655 goto amacout;
1656 }
1657 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1658 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1659 netif_warn(tp, probe, tp->netdev,
1660 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1661 ret, buf);
1662 ret = -EINVAL;
1663 goto amacout;
1664 }
1665 memcpy(sa->sa_data, buf, 6);
1666 netif_info(tp, probe, tp->netdev,
1667 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1668
1669amacout:
1670 kfree(obj);
1671 return ret;
1672}
1673
1674static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1675{
1676 struct net_device *dev = tp->netdev;
1677 int ret;
1678
1679 sa->sa_family = dev->type;
1680
1681 ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1682 if (ret < 0) {
1683 if (tp->version == RTL_VER_01) {
1684 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1685 } else {
1686 /* if device doesn't support MAC pass through this will
1687 * be expected to be non-zero
1688 */
1689 ret = vendor_mac_passthru_addr_read(tp, sa);
1690 if (ret < 0)
1691 ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1692 sa->sa_data);
1693 }
1694 }
1695
1696 if (ret < 0) {
1697 netif_err(tp, probe, dev, "Get ether addr fail\n");
1698 } else if (!is_valid_ether_addr(sa->sa_data)) {
1699 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1700 sa->sa_data);
1701 eth_hw_addr_random(dev);
1702 ether_addr_copy(sa->sa_data, dev->dev_addr);
1703 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1704 sa->sa_data);
1705 return 0;
1706 }
1707
1708 return ret;
1709}
1710
1711static int set_ethernet_addr(struct r8152 *tp, bool in_resume)
1712{
1713 struct net_device *dev = tp->netdev;
1714 struct sockaddr sa;
1715 int ret;
1716
1717 ret = determine_ethernet_addr(tp, &sa);
1718 if (ret < 0)
1719 return ret;
1720
1721 if (tp->version == RTL_VER_01)
1722 ether_addr_copy(dev->dev_addr, sa.sa_data);
1723 else
1724 ret = __rtl8152_set_mac_address(dev, &sa, in_resume);
1725
1726 return ret;
1727}
1728
1729static void read_bulk_callback(struct urb *urb)
1730{
1731 struct net_device *netdev;
1732 int status = urb->status;
1733 struct rx_agg *agg;
1734 struct r8152 *tp;
1735 unsigned long flags;
1736
1737 agg = urb->context;
1738 if (!agg)
1739 return;
1740
1741 tp = agg->context;
1742 if (!tp)
1743 return;
1744
1745 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1746 return;
1747
1748 if (!test_bit(WORK_ENABLE, &tp->flags))
1749 return;
1750
1751 netdev = tp->netdev;
1752
1753 /* When link down, the driver would cancel all bulks. */
1754 /* This avoid the re-submitting bulk */
1755 if (!netif_carrier_ok(netdev))
1756 return;
1757
1758 usb_mark_last_busy(tp->udev);
1759
1760 switch (status) {
1761 case 0:
1762 if (urb->actual_length < ETH_ZLEN)
1763 break;
1764
1765 spin_lock_irqsave(&tp->rx_lock, flags);
1766 list_add_tail(&agg->list, &tp->rx_done);
1767 spin_unlock_irqrestore(&tp->rx_lock, flags);
1768 napi_schedule(&tp->napi);
1769 return;
1770 case -ESHUTDOWN:
1771 rtl_set_unplug(tp);
1772 netif_device_detach(tp->netdev);
1773 return;
1774 case -EPROTO:
1775 urb->actual_length = 0;
1776 spin_lock_irqsave(&tp->rx_lock, flags);
1777 list_add_tail(&agg->list, &tp->rx_done);
1778 spin_unlock_irqrestore(&tp->rx_lock, flags);
1779 set_bit(RX_EPROTO, &tp->flags);
1780 schedule_delayed_work(&tp->schedule, 1);
1781 return;
1782 case -ENOENT:
1783 return; /* the urb is in unlink state */
1784 case -ETIME:
1785 if (net_ratelimit())
1786 netdev_warn(netdev, "maybe reset is needed?\n");
1787 break;
1788 default:
1789 if (net_ratelimit())
1790 netdev_warn(netdev, "Rx status %d\n", status);
1791 break;
1792 }
1793
1794 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1795}
1796
1797static void write_bulk_callback(struct urb *urb)
1798{
1799 struct net_device_stats *stats;
1800 struct net_device *netdev;
1801 struct tx_agg *agg;
1802 struct r8152 *tp;
1803 unsigned long flags;
1804 int status = urb->status;
1805
1806 agg = urb->context;
1807 if (!agg)
1808 return;
1809
1810 tp = agg->context;
1811 if (!tp)
1812 return;
1813
1814 netdev = tp->netdev;
1815 stats = &netdev->stats;
1816 if (status) {
1817 if (net_ratelimit())
1818 netdev_warn(netdev, "Tx status %d\n", status);
1819 stats->tx_errors += agg->skb_num;
1820 } else {
1821 stats->tx_packets += agg->skb_num;
1822 stats->tx_bytes += agg->skb_len;
1823 }
1824
1825 spin_lock_irqsave(&tp->tx_lock, flags);
1826 list_add_tail(&agg->list, &tp->tx_free);
1827 spin_unlock_irqrestore(&tp->tx_lock, flags);
1828
1829 usb_autopm_put_interface_async(tp->intf);
1830
1831 if (!netif_carrier_ok(netdev))
1832 return;
1833
1834 if (!test_bit(WORK_ENABLE, &tp->flags))
1835 return;
1836
1837 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1838 return;
1839
1840 if (!skb_queue_empty(&tp->tx_queue))
1841 tasklet_schedule(&tp->tx_tl);
1842}
1843
1844static void intr_callback(struct urb *urb)
1845{
1846 struct r8152 *tp;
1847 __le16 *d;
1848 int status = urb->status;
1849 int res;
1850
1851 tp = urb->context;
1852 if (!tp)
1853 return;
1854
1855 if (!test_bit(WORK_ENABLE, &tp->flags))
1856 return;
1857
1858 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1859 return;
1860
1861 switch (status) {
1862 case 0: /* success */
1863 break;
1864 case -ECONNRESET: /* unlink */
1865 case -ESHUTDOWN:
1866 netif_device_detach(tp->netdev);
1867 fallthrough;
1868 case -ENOENT:
1869 case -EPROTO:
1870 netif_info(tp, intr, tp->netdev,
1871 "Stop submitting intr, status %d\n", status);
1872 return;
1873 case -EOVERFLOW:
1874 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1875 goto resubmit;
1876 /* -EPIPE: should clear the halt */
1877 default:
1878 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1879 goto resubmit;
1880 }
1881
1882 d = urb->transfer_buffer;
1883 if (INTR_LINK & __le16_to_cpu(d[0])) {
1884 if (!netif_carrier_ok(tp->netdev)) {
1885 set_bit(RTL8152_LINK_CHG, &tp->flags);
1886 schedule_delayed_work(&tp->schedule, 0);
1887 }
1888 } else {
1889 if (netif_carrier_ok(tp->netdev)) {
1890 netif_stop_queue(tp->netdev);
1891 set_bit(RTL8152_LINK_CHG, &tp->flags);
1892 schedule_delayed_work(&tp->schedule, 0);
1893 }
1894 }
1895
1896resubmit:
1897 res = usb_submit_urb(urb, GFP_ATOMIC);
1898 if (res == -ENODEV) {
1899 rtl_set_unplug(tp);
1900 netif_device_detach(tp->netdev);
1901 } else if (res) {
1902 netif_err(tp, intr, tp->netdev,
1903 "can't resubmit intr, status %d\n", res);
1904 }
1905}
1906
1907static inline void *rx_agg_align(void *data)
1908{
1909 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1910}
1911
1912static inline void *tx_agg_align(void *data)
1913{
1914 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1915}
1916
1917static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1918{
1919 list_del(&agg->info_list);
1920
1921 usb_free_urb(agg->urb);
1922 put_page(agg->page);
1923 kfree(agg);
1924
1925 atomic_dec(&tp->rx_count);
1926}
1927
1928static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1929{
1930 struct net_device *netdev = tp->netdev;
1931 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1932 unsigned int order = get_order(tp->rx_buf_sz);
1933 struct rx_agg *rx_agg;
1934 unsigned long flags;
1935
1936 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1937 if (!rx_agg)
1938 return NULL;
1939
1940 rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1941 if (!rx_agg->page)
1942 goto free_rx;
1943
1944 rx_agg->buffer = page_address(rx_agg->page);
1945
1946 rx_agg->urb = usb_alloc_urb(0, mflags);
1947 if (!rx_agg->urb)
1948 goto free_buf;
1949
1950 rx_agg->context = tp;
1951
1952 INIT_LIST_HEAD(&rx_agg->list);
1953 INIT_LIST_HEAD(&rx_agg->info_list);
1954 spin_lock_irqsave(&tp->rx_lock, flags);
1955 list_add_tail(&rx_agg->info_list, &tp->rx_info);
1956 spin_unlock_irqrestore(&tp->rx_lock, flags);
1957
1958 atomic_inc(&tp->rx_count);
1959
1960 return rx_agg;
1961
1962free_buf:
1963 __free_pages(rx_agg->page, order);
1964free_rx:
1965 kfree(rx_agg);
1966 return NULL;
1967}
1968
1969static void free_all_mem(struct r8152 *tp)
1970{
1971 struct rx_agg *agg, *agg_next;
1972 unsigned long flags;
1973 int i;
1974
1975 spin_lock_irqsave(&tp->rx_lock, flags);
1976
1977 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1978 free_rx_agg(tp, agg);
1979
1980 spin_unlock_irqrestore(&tp->rx_lock, flags);
1981
1982 WARN_ON(atomic_read(&tp->rx_count));
1983
1984 for (i = 0; i < RTL8152_MAX_TX; i++) {
1985 usb_free_urb(tp->tx_info[i].urb);
1986 tp->tx_info[i].urb = NULL;
1987
1988 kfree(tp->tx_info[i].buffer);
1989 tp->tx_info[i].buffer = NULL;
1990 tp->tx_info[i].head = NULL;
1991 }
1992
1993 usb_free_urb(tp->intr_urb);
1994 tp->intr_urb = NULL;
1995
1996 kfree(tp->intr_buff);
1997 tp->intr_buff = NULL;
1998}
1999
2000static int alloc_all_mem(struct r8152 *tp)
2001{
2002 struct net_device *netdev = tp->netdev;
2003 struct usb_interface *intf = tp->intf;
2004 struct usb_host_interface *alt = intf->cur_altsetting;
2005 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
2006 int node, i;
2007
2008 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
2009
2010 spin_lock_init(&tp->rx_lock);
2011 spin_lock_init(&tp->tx_lock);
2012 INIT_LIST_HEAD(&tp->rx_info);
2013 INIT_LIST_HEAD(&tp->tx_free);
2014 INIT_LIST_HEAD(&tp->rx_done);
2015 skb_queue_head_init(&tp->tx_queue);
2016 skb_queue_head_init(&tp->rx_queue);
2017 atomic_set(&tp->rx_count, 0);
2018
2019 for (i = 0; i < RTL8152_MAX_RX; i++) {
2020 if (!alloc_rx_agg(tp, GFP_KERNEL))
2021 goto err1;
2022 }
2023
2024 for (i = 0; i < RTL8152_MAX_TX; i++) {
2025 struct urb *urb;
2026 u8 *buf;
2027
2028 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
2029 if (!buf)
2030 goto err1;
2031
2032 if (buf != tx_agg_align(buf)) {
2033 kfree(buf);
2034 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
2035 node);
2036 if (!buf)
2037 goto err1;
2038 }
2039
2040 urb = usb_alloc_urb(0, GFP_KERNEL);
2041 if (!urb) {
2042 kfree(buf);
2043 goto err1;
2044 }
2045
2046 INIT_LIST_HEAD(&tp->tx_info[i].list);
2047 tp->tx_info[i].context = tp;
2048 tp->tx_info[i].urb = urb;
2049 tp->tx_info[i].buffer = buf;
2050 tp->tx_info[i].head = tx_agg_align(buf);
2051
2052 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
2053 }
2054
2055 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
2056 if (!tp->intr_urb)
2057 goto err1;
2058
2059 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
2060 if (!tp->intr_buff)
2061 goto err1;
2062
2063 tp->intr_interval = (int)ep_intr->desc.bInterval;
2064 usb_fill_int_urb(tp->intr_urb, tp->udev, tp->pipe_intr,
2065 tp->intr_buff, INTBUFSIZE, intr_callback,
2066 tp, tp->intr_interval);
2067
2068 return 0;
2069
2070err1:
2071 free_all_mem(tp);
2072 return -ENOMEM;
2073}
2074
2075static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
2076{
2077 struct tx_agg *agg = NULL;
2078 unsigned long flags;
2079
2080 if (list_empty(&tp->tx_free))
2081 return NULL;
2082
2083 spin_lock_irqsave(&tp->tx_lock, flags);
2084 if (!list_empty(&tp->tx_free)) {
2085 struct list_head *cursor;
2086
2087 cursor = tp->tx_free.next;
2088 list_del_init(cursor);
2089 agg = list_entry(cursor, struct tx_agg, list);
2090 }
2091 spin_unlock_irqrestore(&tp->tx_lock, flags);
2092
2093 return agg;
2094}
2095
2096/* r8152_csum_workaround()
2097 * The hw limits the value of the transport offset. When the offset is out of
2098 * range, calculate the checksum by sw.
2099 */
2100static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
2101 struct sk_buff_head *list)
2102{
2103 if (skb_shinfo(skb)->gso_size) {
2104 netdev_features_t features = tp->netdev->features;
2105 struct sk_buff *segs, *seg, *next;
2106 struct sk_buff_head seg_list;
2107
2108 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
2109 segs = skb_gso_segment(skb, features);
2110 if (IS_ERR(segs) || !segs)
2111 goto drop;
2112
2113 __skb_queue_head_init(&seg_list);
2114
2115 skb_list_walk_safe(segs, seg, next) {
2116 skb_mark_not_on_list(seg);
2117 __skb_queue_tail(&seg_list, seg);
2118 }
2119
2120 skb_queue_splice(&seg_list, list);
2121 dev_kfree_skb(skb);
2122 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2123 if (skb_checksum_help(skb) < 0)
2124 goto drop;
2125
2126 __skb_queue_head(list, skb);
2127 } else {
2128 struct net_device_stats *stats;
2129
2130drop:
2131 stats = &tp->netdev->stats;
2132 stats->tx_dropped++;
2133 dev_kfree_skb(skb);
2134 }
2135}
2136
2137static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
2138{
2139 if (skb_vlan_tag_present(skb)) {
2140 u32 opts2;
2141
2142 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
2143 desc->opts2 |= cpu_to_le32(opts2);
2144 }
2145}
2146
2147static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
2148{
2149 u32 opts2 = le32_to_cpu(desc->opts2);
2150
2151 if (opts2 & RX_VLAN_TAG)
2152 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2153 swab16(opts2 & 0xffff));
2154}
2155
2156static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
2157 struct sk_buff *skb, u32 len, u32 transport_offset)
2158{
2159 u32 mss = skb_shinfo(skb)->gso_size;
2160 u32 opts1, opts2 = 0;
2161 int ret = TX_CSUM_SUCCESS;
2162
2163 WARN_ON_ONCE(len > TX_LEN_MAX);
2164
2165 opts1 = len | TX_FS | TX_LS;
2166
2167 if (mss) {
2168 if (transport_offset > GTTCPHO_MAX) {
2169 netif_warn(tp, tx_err, tp->netdev,
2170 "Invalid transport offset 0x%x for TSO\n",
2171 transport_offset);
2172 ret = TX_CSUM_TSO;
2173 goto unavailable;
2174 }
2175
2176 switch (vlan_get_protocol(skb)) {
2177 case htons(ETH_P_IP):
2178 opts1 |= GTSENDV4;
2179 break;
2180
2181 case htons(ETH_P_IPV6):
2182 if (skb_cow_head(skb, 0)) {
2183 ret = TX_CSUM_TSO;
2184 goto unavailable;
2185 }
2186 tcp_v6_gso_csum_prep(skb);
2187 opts1 |= GTSENDV6;
2188 break;
2189
2190 default:
2191 WARN_ON_ONCE(1);
2192 break;
2193 }
2194
2195 opts1 |= transport_offset << GTTCPHO_SHIFT;
2196 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2197 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2198 u8 ip_protocol;
2199
2200 if (transport_offset > TCPHO_MAX) {
2201 netif_warn(tp, tx_err, tp->netdev,
2202 "Invalid transport offset 0x%x\n",
2203 transport_offset);
2204 ret = TX_CSUM_NONE;
2205 goto unavailable;
2206 }
2207
2208 switch (vlan_get_protocol(skb)) {
2209 case htons(ETH_P_IP):
2210 opts2 |= IPV4_CS;
2211 ip_protocol = ip_hdr(skb)->protocol;
2212 break;
2213
2214 case htons(ETH_P_IPV6):
2215 opts2 |= IPV6_CS;
2216 ip_protocol = ipv6_hdr(skb)->nexthdr;
2217 break;
2218
2219 default:
2220 ip_protocol = IPPROTO_RAW;
2221 break;
2222 }
2223
2224 if (ip_protocol == IPPROTO_TCP)
2225 opts2 |= TCP_CS;
2226 else if (ip_protocol == IPPROTO_UDP)
2227 opts2 |= UDP_CS;
2228 else
2229 WARN_ON_ONCE(1);
2230
2231 opts2 |= transport_offset << TCPHO_SHIFT;
2232 }
2233
2234 desc->opts2 = cpu_to_le32(opts2);
2235 desc->opts1 = cpu_to_le32(opts1);
2236
2237unavailable:
2238 return ret;
2239}
2240
2241static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2242{
2243 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2244 int remain, ret;
2245 u8 *tx_data;
2246
2247 __skb_queue_head_init(&skb_head);
2248 spin_lock(&tx_queue->lock);
2249 skb_queue_splice_init(tx_queue, &skb_head);
2250 spin_unlock(&tx_queue->lock);
2251
2252 tx_data = agg->head;
2253 agg->skb_num = 0;
2254 agg->skb_len = 0;
2255 remain = agg_buf_sz;
2256
2257 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2258 struct tx_desc *tx_desc;
2259 struct sk_buff *skb;
2260 unsigned int len;
2261 u32 offset;
2262
2263 skb = __skb_dequeue(&skb_head);
2264 if (!skb)
2265 break;
2266
2267 len = skb->len + sizeof(*tx_desc);
2268
2269 if (len > remain) {
2270 __skb_queue_head(&skb_head, skb);
2271 break;
2272 }
2273
2274 tx_data = tx_agg_align(tx_data);
2275 tx_desc = (struct tx_desc *)tx_data;
2276
2277 offset = (u32)skb_transport_offset(skb);
2278
2279 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
2280 r8152_csum_workaround(tp, skb, &skb_head);
2281 continue;
2282 }
2283
2284 rtl_tx_vlan_tag(tx_desc, skb);
2285
2286 tx_data += sizeof(*tx_desc);
2287
2288 len = skb->len;
2289 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2290 struct net_device_stats *stats = &tp->netdev->stats;
2291
2292 stats->tx_dropped++;
2293 dev_kfree_skb_any(skb);
2294 tx_data -= sizeof(*tx_desc);
2295 continue;
2296 }
2297
2298 tx_data += len;
2299 agg->skb_len += len;
2300 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2301
2302 dev_kfree_skb_any(skb);
2303
2304 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2305
2306 if (tp->dell_tb_rx_agg_bug)
2307 break;
2308 }
2309
2310 if (!skb_queue_empty(&skb_head)) {
2311 spin_lock(&tx_queue->lock);
2312 skb_queue_splice(&skb_head, tx_queue);
2313 spin_unlock(&tx_queue->lock);
2314 }
2315
2316 netif_tx_lock(tp->netdev);
2317
2318 if (netif_queue_stopped(tp->netdev) &&
2319 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2320 netif_wake_queue(tp->netdev);
2321
2322 netif_tx_unlock(tp->netdev);
2323
2324 ret = usb_autopm_get_interface_async(tp->intf);
2325 if (ret < 0)
2326 goto out_tx_fill;
2327
2328 usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_out,
2329 agg->head, (int)(tx_data - (u8 *)agg->head),
2330 (usb_complete_t)write_bulk_callback, agg);
2331
2332 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2333 if (ret < 0)
2334 usb_autopm_put_interface_async(tp->intf);
2335
2336out_tx_fill:
2337 return ret;
2338}
2339
2340static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2341{
2342 u8 checksum = CHECKSUM_NONE;
2343 u32 opts2, opts3;
2344
2345 if (!(tp->netdev->features & NETIF_F_RXCSUM))
2346 goto return_result;
2347
2348 opts2 = le32_to_cpu(rx_desc->opts2);
2349 opts3 = le32_to_cpu(rx_desc->opts3);
2350
2351 if (opts2 & RD_IPV4_CS) {
2352 if (opts3 & IPF)
2353 checksum = CHECKSUM_NONE;
2354 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2355 checksum = CHECKSUM_UNNECESSARY;
2356 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2357 checksum = CHECKSUM_UNNECESSARY;
2358 } else if (opts2 & RD_IPV6_CS) {
2359 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2360 checksum = CHECKSUM_UNNECESSARY;
2361 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2362 checksum = CHECKSUM_UNNECESSARY;
2363 }
2364
2365return_result:
2366 return checksum;
2367}
2368
2369static inline bool rx_count_exceed(struct r8152 *tp)
2370{
2371 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2372}
2373
2374static inline int agg_offset(struct rx_agg *agg, void *addr)
2375{
2376 return (int)(addr - agg->buffer);
2377}
2378
2379static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2380{
2381 struct rx_agg *agg, *agg_next, *agg_free = NULL;
2382 unsigned long flags;
2383
2384 spin_lock_irqsave(&tp->rx_lock, flags);
2385
2386 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2387 if (page_count(agg->page) == 1) {
2388 if (!agg_free) {
2389 list_del_init(&agg->list);
2390 agg_free = agg;
2391 continue;
2392 }
2393 if (rx_count_exceed(tp)) {
2394 list_del_init(&agg->list);
2395 free_rx_agg(tp, agg);
2396 }
2397 break;
2398 }
2399 }
2400
2401 spin_unlock_irqrestore(&tp->rx_lock, flags);
2402
2403 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2404 agg_free = alloc_rx_agg(tp, mflags);
2405
2406 return agg_free;
2407}
2408
2409static int rx_bottom(struct r8152 *tp, int budget)
2410{
2411 unsigned long flags;
2412 struct list_head *cursor, *next, rx_queue;
2413 int ret = 0, work_done = 0;
2414 struct napi_struct *napi = &tp->napi;
2415
2416 if (!skb_queue_empty(&tp->rx_queue)) {
2417 while (work_done < budget) {
2418 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2419 struct net_device *netdev = tp->netdev;
2420 struct net_device_stats *stats = &netdev->stats;
2421 unsigned int pkt_len;
2422
2423 if (!skb)
2424 break;
2425
2426 pkt_len = skb->len;
2427 napi_gro_receive(napi, skb);
2428 work_done++;
2429 stats->rx_packets++;
2430 stats->rx_bytes += pkt_len;
2431 }
2432 }
2433
2434 if (list_empty(&tp->rx_done))
2435 goto out1;
2436
2437 clear_bit(RX_EPROTO, &tp->flags);
2438 INIT_LIST_HEAD(&rx_queue);
2439 spin_lock_irqsave(&tp->rx_lock, flags);
2440 list_splice_init(&tp->rx_done, &rx_queue);
2441 spin_unlock_irqrestore(&tp->rx_lock, flags);
2442
2443 list_for_each_safe(cursor, next, &rx_queue) {
2444 struct rx_desc *rx_desc;
2445 struct rx_agg *agg, *agg_free;
2446 int len_used = 0;
2447 struct urb *urb;
2448 u8 *rx_data;
2449
2450 list_del_init(cursor);
2451
2452 agg = list_entry(cursor, struct rx_agg, list);
2453 urb = agg->urb;
2454 if (urb->status != 0 || urb->actual_length < ETH_ZLEN)
2455 goto submit;
2456
2457 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2458
2459 rx_desc = agg->buffer;
2460 rx_data = agg->buffer;
2461 len_used += sizeof(struct rx_desc);
2462
2463 while (urb->actual_length > len_used) {
2464 struct net_device *netdev = tp->netdev;
2465 struct net_device_stats *stats = &netdev->stats;
2466 unsigned int pkt_len, rx_frag_head_sz;
2467 struct sk_buff *skb;
2468
2469 /* limit the skb numbers for rx_queue */
2470 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2471 break;
2472
2473 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2474 if (pkt_len < ETH_ZLEN)
2475 break;
2476
2477 len_used += pkt_len;
2478 if (urb->actual_length < len_used)
2479 break;
2480
2481 pkt_len -= ETH_FCS_LEN;
2482 rx_data += sizeof(struct rx_desc);
2483
2484 if (!agg_free || tp->rx_copybreak > pkt_len)
2485 rx_frag_head_sz = pkt_len;
2486 else
2487 rx_frag_head_sz = tp->rx_copybreak;
2488
2489 skb = napi_alloc_skb(napi, rx_frag_head_sz);
2490 if (!skb) {
2491 stats->rx_dropped++;
2492 goto find_next_rx;
2493 }
2494
2495 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2496 memcpy(skb->data, rx_data, rx_frag_head_sz);
2497 skb_put(skb, rx_frag_head_sz);
2498 pkt_len -= rx_frag_head_sz;
2499 rx_data += rx_frag_head_sz;
2500 if (pkt_len) {
2501 skb_add_rx_frag(skb, 0, agg->page,
2502 agg_offset(agg, rx_data),
2503 pkt_len,
2504 SKB_DATA_ALIGN(pkt_len));
2505 get_page(agg->page);
2506 }
2507
2508 skb->protocol = eth_type_trans(skb, netdev);
2509 rtl_rx_vlan_tag(rx_desc, skb);
2510 if (work_done < budget) {
2511 work_done++;
2512 stats->rx_packets++;
2513 stats->rx_bytes += skb->len;
2514 napi_gro_receive(napi, skb);
2515 } else {
2516 __skb_queue_tail(&tp->rx_queue, skb);
2517 }
2518
2519find_next_rx:
2520 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2521 rx_desc = (struct rx_desc *)rx_data;
2522 len_used = agg_offset(agg, rx_data);
2523 len_used += sizeof(struct rx_desc);
2524 }
2525
2526 WARN_ON(!agg_free && page_count(agg->page) > 1);
2527
2528 if (agg_free) {
2529 spin_lock_irqsave(&tp->rx_lock, flags);
2530 if (page_count(agg->page) == 1) {
2531 list_add(&agg_free->list, &tp->rx_used);
2532 } else {
2533 list_add_tail(&agg->list, &tp->rx_used);
2534 agg = agg_free;
2535 urb = agg->urb;
2536 }
2537 spin_unlock_irqrestore(&tp->rx_lock, flags);
2538 }
2539
2540submit:
2541 if (!ret) {
2542 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2543 } else {
2544 urb->actual_length = 0;
2545 list_add_tail(&agg->list, next);
2546 }
2547 }
2548
2549 if (!list_empty(&rx_queue)) {
2550 spin_lock_irqsave(&tp->rx_lock, flags);
2551 list_splice_tail(&rx_queue, &tp->rx_done);
2552 spin_unlock_irqrestore(&tp->rx_lock, flags);
2553 }
2554
2555out1:
2556 return work_done;
2557}
2558
2559static void tx_bottom(struct r8152 *tp)
2560{
2561 int res;
2562
2563 do {
2564 struct net_device *netdev = tp->netdev;
2565 struct tx_agg *agg;
2566
2567 if (skb_queue_empty(&tp->tx_queue))
2568 break;
2569
2570 agg = r8152_get_tx_agg(tp);
2571 if (!agg)
2572 break;
2573
2574 res = r8152_tx_agg_fill(tp, agg);
2575 if (!res)
2576 continue;
2577
2578 if (res == -ENODEV) {
2579 rtl_set_unplug(tp);
2580 netif_device_detach(netdev);
2581 } else {
2582 struct net_device_stats *stats = &netdev->stats;
2583 unsigned long flags;
2584
2585 netif_warn(tp, tx_err, netdev,
2586 "failed tx_urb %d\n", res);
2587 stats->tx_dropped += agg->skb_num;
2588
2589 spin_lock_irqsave(&tp->tx_lock, flags);
2590 list_add_tail(&agg->list, &tp->tx_free);
2591 spin_unlock_irqrestore(&tp->tx_lock, flags);
2592 }
2593 } while (res == 0);
2594}
2595
2596static void bottom_half(struct tasklet_struct *t)
2597{
2598 struct r8152 *tp = from_tasklet(tp, t, tx_tl);
2599
2600 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2601 return;
2602
2603 if (!test_bit(WORK_ENABLE, &tp->flags))
2604 return;
2605
2606 /* When link down, the driver would cancel all bulks. */
2607 /* This avoid the re-submitting bulk */
2608 if (!netif_carrier_ok(tp->netdev))
2609 return;
2610
2611 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2612
2613 tx_bottom(tp);
2614}
2615
2616static int r8152_poll(struct napi_struct *napi, int budget)
2617{
2618 struct r8152 *tp = container_of(napi, struct r8152, napi);
2619 int work_done;
2620
2621 work_done = rx_bottom(tp, budget);
2622
2623 if (work_done < budget) {
2624 if (!napi_complete_done(napi, work_done))
2625 goto out;
2626 if (!list_empty(&tp->rx_done))
2627 napi_schedule(napi);
2628 }
2629
2630out:
2631 return work_done;
2632}
2633
2634static
2635int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2636{
2637 int ret;
2638
2639 /* The rx would be stopped, so skip submitting */
2640 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2641 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2642 return 0;
2643
2644 usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_in,
2645 agg->buffer, tp->rx_buf_sz,
2646 (usb_complete_t)read_bulk_callback, agg);
2647
2648 ret = usb_submit_urb(agg->urb, mem_flags);
2649 if (ret == -ENODEV) {
2650 rtl_set_unplug(tp);
2651 netif_device_detach(tp->netdev);
2652 } else if (ret) {
2653 struct urb *urb = agg->urb;
2654 unsigned long flags;
2655
2656 urb->actual_length = 0;
2657 spin_lock_irqsave(&tp->rx_lock, flags);
2658 list_add_tail(&agg->list, &tp->rx_done);
2659 spin_unlock_irqrestore(&tp->rx_lock, flags);
2660
2661 netif_err(tp, rx_err, tp->netdev,
2662 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2663
2664 napi_schedule(&tp->napi);
2665 }
2666
2667 return ret;
2668}
2669
2670static void rtl_drop_queued_tx(struct r8152 *tp)
2671{
2672 struct net_device_stats *stats = &tp->netdev->stats;
2673 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2674 struct sk_buff *skb;
2675
2676 if (skb_queue_empty(tx_queue))
2677 return;
2678
2679 __skb_queue_head_init(&skb_head);
2680 spin_lock_bh(&tx_queue->lock);
2681 skb_queue_splice_init(tx_queue, &skb_head);
2682 spin_unlock_bh(&tx_queue->lock);
2683
2684 while ((skb = __skb_dequeue(&skb_head))) {
2685 dev_kfree_skb(skb);
2686 stats->tx_dropped++;
2687 }
2688}
2689
2690static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2691{
2692 struct r8152 *tp = netdev_priv(netdev);
2693
2694 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2695
2696 usb_queue_reset_device(tp->intf);
2697}
2698
2699static void rtl8152_set_rx_mode(struct net_device *netdev)
2700{
2701 struct r8152 *tp = netdev_priv(netdev);
2702
2703 if (netif_carrier_ok(netdev)) {
2704 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2705 schedule_delayed_work(&tp->schedule, 0);
2706 }
2707}
2708
2709static void _rtl8152_set_rx_mode(struct net_device *netdev)
2710{
2711 struct r8152 *tp = netdev_priv(netdev);
2712 u32 mc_filter[2]; /* Multicast hash filter */
2713 __le32 tmp[2];
2714 u32 ocp_data;
2715
2716 netif_stop_queue(netdev);
2717 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2718 ocp_data &= ~RCR_ACPT_ALL;
2719 ocp_data |= RCR_AB | RCR_APM;
2720
2721 if (netdev->flags & IFF_PROMISC) {
2722 /* Unconditionally log net taps. */
2723 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2724 ocp_data |= RCR_AM | RCR_AAP;
2725 mc_filter[1] = 0xffffffff;
2726 mc_filter[0] = 0xffffffff;
2727 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2728 (netdev->flags & IFF_ALLMULTI)) {
2729 /* Too many to filter perfectly -- accept all multicasts. */
2730 ocp_data |= RCR_AM;
2731 mc_filter[1] = 0xffffffff;
2732 mc_filter[0] = 0xffffffff;
2733 } else {
2734 struct netdev_hw_addr *ha;
2735
2736 mc_filter[1] = 0;
2737 mc_filter[0] = 0;
2738 netdev_for_each_mc_addr(ha, netdev) {
2739 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2740
2741 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2742 ocp_data |= RCR_AM;
2743 }
2744 }
2745
2746 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2747 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2748
2749 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2750 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2751 netif_wake_queue(netdev);
2752}
2753
2754static netdev_features_t
2755rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2756 netdev_features_t features)
2757{
2758 u32 mss = skb_shinfo(skb)->gso_size;
2759 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2760 int offset = skb_transport_offset(skb);
2761
2762 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2763 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2764 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2765 features &= ~NETIF_F_GSO_MASK;
2766
2767 return features;
2768}
2769
2770static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2771 struct net_device *netdev)
2772{
2773 struct r8152 *tp = netdev_priv(netdev);
2774
2775 skb_tx_timestamp(skb);
2776
2777 skb_queue_tail(&tp->tx_queue, skb);
2778
2779 if (!list_empty(&tp->tx_free)) {
2780 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2781 set_bit(SCHEDULE_TASKLET, &tp->flags);
2782 schedule_delayed_work(&tp->schedule, 0);
2783 } else {
2784 usb_mark_last_busy(tp->udev);
2785 tasklet_schedule(&tp->tx_tl);
2786 }
2787 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2788 netif_stop_queue(netdev);
2789 }
2790
2791 return NETDEV_TX_OK;
2792}
2793
2794static void r8152b_reset_packet_filter(struct r8152 *tp)
2795{
2796 u32 ocp_data;
2797
2798 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2799 ocp_data &= ~FMC_FCR_MCU_EN;
2800 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2801 ocp_data |= FMC_FCR_MCU_EN;
2802 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2803}
2804
2805static void rtl8152_nic_reset(struct r8152 *tp)
2806{
2807 u32 ocp_data;
2808 int i;
2809
2810 switch (tp->version) {
2811 case RTL_TEST_01:
2812 case RTL_VER_10:
2813 case RTL_VER_11:
2814 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2815 ocp_data &= ~CR_TE;
2816 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2817
2818 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2819 ocp_data &= ~BMU_RESET_EP_IN;
2820 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2821
2822 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2823 ocp_data |= CDC_ECM_EN;
2824 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2825
2826 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2827 ocp_data &= ~CR_RE;
2828 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2829
2830 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2831 ocp_data |= BMU_RESET_EP_IN;
2832 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2833
2834 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2835 ocp_data &= ~CDC_ECM_EN;
2836 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2837 break;
2838
2839 default:
2840 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2841
2842 for (i = 0; i < 1000; i++) {
2843 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2844 break;
2845 usleep_range(100, 400);
2846 }
2847 break;
2848 }
2849}
2850
2851static void set_tx_qlen(struct r8152 *tp)
2852{
2853 tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));
2854}
2855
2856static inline u16 rtl8152_get_speed(struct r8152 *tp)
2857{
2858 return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2859}
2860
2861static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
2862{
2863 u32 ocp_data;
2864
2865 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2866 if (enable)
2867 ocp_data |= EEEP_CR_EEEP_TX;
2868 else
2869 ocp_data &= ~EEEP_CR_EEEP_TX;
2870 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2871}
2872
2873static void rtl_set_eee_plus(struct r8152 *tp)
2874{
2875 if (rtl8152_get_speed(tp) & _10bps)
2876 rtl_eee_plus_en(tp, true);
2877 else
2878 rtl_eee_plus_en(tp, false);
2879}
2880
2881static void rxdy_gated_en(struct r8152 *tp, bool enable)
2882{
2883 u32 ocp_data;
2884
2885 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2886 if (enable)
2887 ocp_data |= RXDY_GATED_EN;
2888 else
2889 ocp_data &= ~RXDY_GATED_EN;
2890 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2891}
2892
2893static int rtl_start_rx(struct r8152 *tp)
2894{
2895 struct rx_agg *agg, *agg_next;
2896 struct list_head tmp_list;
2897 unsigned long flags;
2898 int ret = 0, i = 0;
2899
2900 INIT_LIST_HEAD(&tmp_list);
2901
2902 spin_lock_irqsave(&tp->rx_lock, flags);
2903
2904 INIT_LIST_HEAD(&tp->rx_done);
2905 INIT_LIST_HEAD(&tp->rx_used);
2906
2907 list_splice_init(&tp->rx_info, &tmp_list);
2908
2909 spin_unlock_irqrestore(&tp->rx_lock, flags);
2910
2911 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2912 INIT_LIST_HEAD(&agg->list);
2913
2914 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2915 if (++i > RTL8152_MAX_RX) {
2916 spin_lock_irqsave(&tp->rx_lock, flags);
2917 list_add_tail(&agg->list, &tp->rx_used);
2918 spin_unlock_irqrestore(&tp->rx_lock, flags);
2919 } else if (unlikely(ret < 0)) {
2920 spin_lock_irqsave(&tp->rx_lock, flags);
2921 list_add_tail(&agg->list, &tp->rx_done);
2922 spin_unlock_irqrestore(&tp->rx_lock, flags);
2923 } else {
2924 ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2925 }
2926 }
2927
2928 spin_lock_irqsave(&tp->rx_lock, flags);
2929 WARN_ON(!list_empty(&tp->rx_info));
2930 list_splice(&tmp_list, &tp->rx_info);
2931 spin_unlock_irqrestore(&tp->rx_lock, flags);
2932
2933 return ret;
2934}
2935
2936static int rtl_stop_rx(struct r8152 *tp)
2937{
2938 struct rx_agg *agg, *agg_next;
2939 struct list_head tmp_list;
2940 unsigned long flags;
2941
2942 INIT_LIST_HEAD(&tmp_list);
2943
2944 /* The usb_kill_urb() couldn't be used in atomic.
2945 * Therefore, move the list of rx_info to a tmp one.
2946 * Then, list_for_each_entry_safe could be used without
2947 * spin lock.
2948 */
2949
2950 spin_lock_irqsave(&tp->rx_lock, flags);
2951 list_splice_init(&tp->rx_info, &tmp_list);
2952 spin_unlock_irqrestore(&tp->rx_lock, flags);
2953
2954 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2955 /* At least RTL8152_MAX_RX rx_agg have the page_count being
2956 * equal to 1, so the other ones could be freed safely.
2957 */
2958 if (page_count(agg->page) > 1)
2959 free_rx_agg(tp, agg);
2960 else
2961 usb_kill_urb(agg->urb);
2962 }
2963
2964 /* Move back the list of temp to the rx_info */
2965 spin_lock_irqsave(&tp->rx_lock, flags);
2966 WARN_ON(!list_empty(&tp->rx_info));
2967 list_splice(&tmp_list, &tp->rx_info);
2968 spin_unlock_irqrestore(&tp->rx_lock, flags);
2969
2970 while (!skb_queue_empty(&tp->rx_queue))
2971 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2972
2973 return 0;
2974}
2975
2976static void rtl_set_ifg(struct r8152 *tp, u16 speed)
2977{
2978 u32 ocp_data;
2979
2980 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
2981 ocp_data &= ~IFG_MASK;
2982 if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {
2983 ocp_data |= IFG_144NS;
2984 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
2985
2986 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
2987 ocp_data &= ~TX10MIDLE_EN;
2988 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
2989 } else {
2990 ocp_data |= IFG_96NS;
2991 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
2992
2993 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
2994 ocp_data |= TX10MIDLE_EN;
2995 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
2996 }
2997}
2998
2999static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
3000{
3001 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
3002 OWN_UPDATE | OWN_CLEAR);
3003}
3004
3005static int rtl_enable(struct r8152 *tp)
3006{
3007 u32 ocp_data;
3008
3009 r8152b_reset_packet_filter(tp);
3010
3011 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
3012 ocp_data |= CR_RE | CR_TE;
3013 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
3014
3015 switch (tp->version) {
3016 case RTL_VER_08:
3017 case RTL_VER_09:
3018 case RTL_VER_14:
3019 r8153b_rx_agg_chg_indicate(tp);
3020 break;
3021 default:
3022 break;
3023 }
3024
3025 rxdy_gated_en(tp, false);
3026
3027 return 0;
3028}
3029
3030static int rtl8152_enable(struct r8152 *tp)
3031{
3032 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3033 return -ENODEV;
3034
3035 set_tx_qlen(tp);
3036 rtl_set_eee_plus(tp);
3037
3038 return rtl_enable(tp);
3039}
3040
3041static void r8153_set_rx_early_timeout(struct r8152 *tp)
3042{
3043 u32 ocp_data = tp->coalesce / 8;
3044
3045 switch (tp->version) {
3046 case RTL_VER_03:
3047 case RTL_VER_04:
3048 case RTL_VER_05:
3049 case RTL_VER_06:
3050 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3051 ocp_data);
3052 break;
3053
3054 case RTL_VER_08:
3055 case RTL_VER_09:
3056 case RTL_VER_14:
3057 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
3058 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
3059 */
3060 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3061 128 / 8);
3062 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3063 ocp_data);
3064 break;
3065
3066 case RTL_VER_10:
3067 case RTL_VER_11:
3068 case RTL_VER_12:
3069 case RTL_VER_13:
3070 case RTL_VER_15:
3071 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3072 640 / 8);
3073 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3074 ocp_data);
3075 r8153b_rx_agg_chg_indicate(tp);
3076 break;
3077
3078 default:
3079 break;
3080 }
3081}
3082
3083static void r8153_set_rx_early_size(struct r8152 *tp)
3084{
3085 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
3086
3087 switch (tp->version) {
3088 case RTL_VER_03:
3089 case RTL_VER_04:
3090 case RTL_VER_05:
3091 case RTL_VER_06:
3092 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3093 ocp_data / 4);
3094 break;
3095 case RTL_VER_08:
3096 case RTL_VER_09:
3097 case RTL_VER_14:
3098 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3099 ocp_data / 8);
3100 break;
3101 case RTL_TEST_01:
3102 case RTL_VER_10:
3103 case RTL_VER_11:
3104 case RTL_VER_12:
3105 case RTL_VER_13:
3106 case RTL_VER_15:
3107 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3108 ocp_data / 8);
3109 r8153b_rx_agg_chg_indicate(tp);
3110 break;
3111 default:
3112 WARN_ON_ONCE(1);
3113 break;
3114 }
3115}
3116
3117static int rtl8153_enable(struct r8152 *tp)
3118{
3119 u32 ocp_data;
3120
3121 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3122 return -ENODEV;
3123
3124 set_tx_qlen(tp);
3125 rtl_set_eee_plus(tp);
3126 r8153_set_rx_early_timeout(tp);
3127 r8153_set_rx_early_size(tp);
3128
3129 rtl_set_ifg(tp, rtl8152_get_speed(tp));
3130
3131 switch (tp->version) {
3132 case RTL_VER_09:
3133 case RTL_VER_14:
3134 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
3135 ocp_data &= ~FC_PATCH_TASK;
3136 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3137 usleep_range(1000, 2000);
3138 ocp_data |= FC_PATCH_TASK;
3139 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3140 break;
3141 default:
3142 break;
3143 }
3144
3145 return rtl_enable(tp);
3146}
3147
3148static void rtl_disable(struct r8152 *tp)
3149{
3150 u32 ocp_data;
3151 int i;
3152
3153 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3154 rtl_drop_queued_tx(tp);
3155 return;
3156 }
3157
3158 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3159 ocp_data &= ~RCR_ACPT_ALL;
3160 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3161
3162 rtl_drop_queued_tx(tp);
3163
3164 for (i = 0; i < RTL8152_MAX_TX; i++)
3165 usb_kill_urb(tp->tx_info[i].urb);
3166
3167 rxdy_gated_en(tp, true);
3168
3169 for (i = 0; i < 1000; i++) {
3170 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3171 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
3172 break;
3173 usleep_range(1000, 2000);
3174 }
3175
3176 for (i = 0; i < 1000; i++) {
3177 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
3178 break;
3179 usleep_range(1000, 2000);
3180 }
3181
3182 rtl_stop_rx(tp);
3183
3184 rtl8152_nic_reset(tp);
3185}
3186
3187static void r8152_power_cut_en(struct r8152 *tp, bool enable)
3188{
3189 u32 ocp_data;
3190
3191 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
3192 if (enable)
3193 ocp_data |= POWER_CUT;
3194 else
3195 ocp_data &= ~POWER_CUT;
3196 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
3197
3198 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
3199 ocp_data &= ~RESUME_INDICATE;
3200 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
3201}
3202
3203static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
3204{
3205 u32 ocp_data;
3206
3207 switch (tp->version) {
3208 case RTL_VER_01:
3209 case RTL_VER_02:
3210 case RTL_VER_03:
3211 case RTL_VER_04:
3212 case RTL_VER_05:
3213 case RTL_VER_06:
3214 case RTL_VER_07:
3215 case RTL_VER_08:
3216 case RTL_VER_09:
3217 case RTL_VER_14:
3218 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
3219 if (enable)
3220 ocp_data |= CPCR_RX_VLAN;
3221 else
3222 ocp_data &= ~CPCR_RX_VLAN;
3223 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
3224 break;
3225
3226 case RTL_TEST_01:
3227 case RTL_VER_10:
3228 case RTL_VER_11:
3229 case RTL_VER_12:
3230 case RTL_VER_13:
3231 case RTL_VER_15:
3232 default:
3233 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
3234 if (enable)
3235 ocp_data |= OUTER_VLAN | INNER_VLAN;
3236 else
3237 ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
3238 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data);
3239 break;
3240 }
3241}
3242
3243static int rtl8152_set_features(struct net_device *dev,
3244 netdev_features_t features)
3245{
3246 netdev_features_t changed = features ^ dev->features;
3247 struct r8152 *tp = netdev_priv(dev);
3248 int ret;
3249
3250 ret = usb_autopm_get_interface(tp->intf);
3251 if (ret < 0)
3252 goto out;
3253
3254 mutex_lock(&tp->control);
3255
3256 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
3257 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3258 rtl_rx_vlan_en(tp, true);
3259 else
3260 rtl_rx_vlan_en(tp, false);
3261 }
3262
3263 mutex_unlock(&tp->control);
3264
3265 usb_autopm_put_interface(tp->intf);
3266
3267out:
3268 return ret;
3269}
3270
3271#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
3272
3273static u32 __rtl_get_wol(struct r8152 *tp)
3274{
3275 u32 ocp_data;
3276 u32 wolopts = 0;
3277
3278 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3279 if (ocp_data & LINK_ON_WAKE_EN)
3280 wolopts |= WAKE_PHY;
3281
3282 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3283 if (ocp_data & UWF_EN)
3284 wolopts |= WAKE_UCAST;
3285 if (ocp_data & BWF_EN)
3286 wolopts |= WAKE_BCAST;
3287 if (ocp_data & MWF_EN)
3288 wolopts |= WAKE_MCAST;
3289
3290 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3291 if (ocp_data & MAGIC_EN)
3292 wolopts |= WAKE_MAGIC;
3293
3294 return wolopts;
3295}
3296
3297static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3298{
3299 u32 ocp_data;
3300
3301 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3302
3303 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3304 ocp_data &= ~LINK_ON_WAKE_EN;
3305 if (wolopts & WAKE_PHY)
3306 ocp_data |= LINK_ON_WAKE_EN;
3307 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3308
3309 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3310 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3311 if (wolopts & WAKE_UCAST)
3312 ocp_data |= UWF_EN;
3313 if (wolopts & WAKE_BCAST)
3314 ocp_data |= BWF_EN;
3315 if (wolopts & WAKE_MCAST)
3316 ocp_data |= MWF_EN;
3317 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3318
3319 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3320
3321 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3322 ocp_data &= ~MAGIC_EN;
3323 if (wolopts & WAKE_MAGIC)
3324 ocp_data |= MAGIC_EN;
3325 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3326
3327 if (wolopts & WAKE_ANY)
3328 device_set_wakeup_enable(&tp->udev->dev, true);
3329 else
3330 device_set_wakeup_enable(&tp->udev->dev, false);
3331}
3332
3333static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)
3334{
3335 u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3336
3337 /* MAC clock speed down */
3338 if (enable)
3339 ocp_data |= MAC_CLK_SPDWN_EN;
3340 else
3341 ocp_data &= ~MAC_CLK_SPDWN_EN;
3342
3343 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3344}
3345
3346static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)
3347{
3348 u32 ocp_data;
3349
3350 /* MAC clock speed down */
3351 if (enable) {
3352 /* aldps_spdwn_ratio, tp10_spdwn_ratio */
3353 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3354 0x0403);
3355
3356 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3357 ocp_data &= ~EEE_SPDWN_RATIO_MASK;
3358 ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */
3359 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3360 } else {
3361 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3362 ocp_data &= ~MAC_CLK_SPDWN_EN;
3363 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3364 }
3365}
3366
3367static void r8153_u1u2en(struct r8152 *tp, bool enable)
3368{
3369 u8 u1u2[8];
3370
3371 if (enable)
3372 memset(u1u2, 0xff, sizeof(u1u2));
3373 else
3374 memset(u1u2, 0x00, sizeof(u1u2));
3375
3376 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3377}
3378
3379static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3380{
3381 u32 ocp_data;
3382
3383 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3384 if (enable)
3385 ocp_data |= LPM_U1U2_EN;
3386 else
3387 ocp_data &= ~LPM_U1U2_EN;
3388
3389 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3390}
3391
3392static void r8153_u2p3en(struct r8152 *tp, bool enable)
3393{
3394 u32 ocp_data;
3395
3396 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3397 if (enable)
3398 ocp_data |= U2P3_ENABLE;
3399 else
3400 ocp_data &= ~U2P3_ENABLE;
3401 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3402}
3403
3404static void r8153b_ups_flags(struct r8152 *tp)
3405{
3406 u32 ups_flags = 0;
3407
3408 if (tp->ups_info.green)
3409 ups_flags |= UPS_FLAGS_EN_GREEN;
3410
3411 if (tp->ups_info.aldps)
3412 ups_flags |= UPS_FLAGS_EN_ALDPS;
3413
3414 if (tp->ups_info.eee)
3415 ups_flags |= UPS_FLAGS_EN_EEE;
3416
3417 if (tp->ups_info.flow_control)
3418 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3419
3420 if (tp->ups_info.eee_ckdiv)
3421 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3422
3423 if (tp->ups_info.eee_cmod_lv)
3424 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3425
3426 if (tp->ups_info.r_tune)
3427 ups_flags |= UPS_FLAGS_R_TUNE;
3428
3429 if (tp->ups_info._10m_ckdiv)
3430 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3431
3432 if (tp->ups_info.eee_plloff_100)
3433 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3434
3435 if (tp->ups_info.eee_plloff_giga)
3436 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3437
3438 if (tp->ups_info._250m_ckdiv)
3439 ups_flags |= UPS_FLAGS_250M_CKDIV;
3440
3441 if (tp->ups_info.ctap_short_off)
3442 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3443
3444 switch (tp->ups_info.speed_duplex) {
3445 case NWAY_10M_HALF:
3446 ups_flags |= ups_flags_speed(1);
3447 break;
3448 case NWAY_10M_FULL:
3449 ups_flags |= ups_flags_speed(2);
3450 break;
3451 case NWAY_100M_HALF:
3452 ups_flags |= ups_flags_speed(3);
3453 break;
3454 case NWAY_100M_FULL:
3455 ups_flags |= ups_flags_speed(4);
3456 break;
3457 case NWAY_1000M_FULL:
3458 ups_flags |= ups_flags_speed(5);
3459 break;
3460 case FORCE_10M_HALF:
3461 ups_flags |= ups_flags_speed(6);
3462 break;
3463 case FORCE_10M_FULL:
3464 ups_flags |= ups_flags_speed(7);
3465 break;
3466 case FORCE_100M_HALF:
3467 ups_flags |= ups_flags_speed(8);
3468 break;
3469 case FORCE_100M_FULL:
3470 ups_flags |= ups_flags_speed(9);
3471 break;
3472 default:
3473 break;
3474 }
3475
3476 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3477}
3478
3479static void r8156_ups_flags(struct r8152 *tp)
3480{
3481 u32 ups_flags = 0;
3482
3483 if (tp->ups_info.green)
3484 ups_flags |= UPS_FLAGS_EN_GREEN;
3485
3486 if (tp->ups_info.aldps)
3487 ups_flags |= UPS_FLAGS_EN_ALDPS;
3488
3489 if (tp->ups_info.eee)
3490 ups_flags |= UPS_FLAGS_EN_EEE;
3491
3492 if (tp->ups_info.flow_control)
3493 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3494
3495 if (tp->ups_info.eee_ckdiv)
3496 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3497
3498 if (tp->ups_info._10m_ckdiv)
3499 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3500
3501 if (tp->ups_info.eee_plloff_100)
3502 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3503
3504 if (tp->ups_info.eee_plloff_giga)
3505 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3506
3507 if (tp->ups_info._250m_ckdiv)
3508 ups_flags |= UPS_FLAGS_250M_CKDIV;
3509
3510 switch (tp->ups_info.speed_duplex) {
3511 case FORCE_10M_HALF:
3512 ups_flags |= ups_flags_speed(0);
3513 break;
3514 case FORCE_10M_FULL:
3515 ups_flags |= ups_flags_speed(1);
3516 break;
3517 case FORCE_100M_HALF:
3518 ups_flags |= ups_flags_speed(2);
3519 break;
3520 case FORCE_100M_FULL:
3521 ups_flags |= ups_flags_speed(3);
3522 break;
3523 case NWAY_10M_HALF:
3524 ups_flags |= ups_flags_speed(4);
3525 break;
3526 case NWAY_10M_FULL:
3527 ups_flags |= ups_flags_speed(5);
3528 break;
3529 case NWAY_100M_HALF:
3530 ups_flags |= ups_flags_speed(6);
3531 break;
3532 case NWAY_100M_FULL:
3533 ups_flags |= ups_flags_speed(7);
3534 break;
3535 case NWAY_1000M_FULL:
3536 ups_flags |= ups_flags_speed(8);
3537 break;
3538 case NWAY_2500M_FULL:
3539 ups_flags |= ups_flags_speed(9);
3540 break;
3541 default:
3542 break;
3543 }
3544
3545 switch (tp->ups_info.lite_mode) {
3546 case 1:
3547 ups_flags |= 0 << 5;
3548 break;
3549 case 2:
3550 ups_flags |= 2 << 5;
3551 break;
3552 case 0:
3553 default:
3554 ups_flags |= 1 << 5;
3555 break;
3556 }
3557
3558 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3559}
3560
3561static void rtl_green_en(struct r8152 *tp, bool enable)
3562{
3563 u16 data;
3564
3565 data = sram_read(tp, SRAM_GREEN_CFG);
3566 if (enable)
3567 data |= GREEN_ETH_EN;
3568 else
3569 data &= ~GREEN_ETH_EN;
3570 sram_write(tp, SRAM_GREEN_CFG, data);
3571
3572 tp->ups_info.green = enable;
3573}
3574
3575static void r8153b_green_en(struct r8152 *tp, bool enable)
3576{
3577 if (enable) {
3578 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
3579 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3580 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3581 } else {
3582 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3583 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3584 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3585 }
3586
3587 rtl_green_en(tp, true);
3588}
3589
3590static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3591{
3592 u16 data;
3593 int i;
3594
3595 for (i = 0; i < 500; i++) {
3596 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3597 data &= PHY_STAT_MASK;
3598 if (desired) {
3599 if (data == desired)
3600 break;
3601 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3602 data == PHY_STAT_EXT_INIT) {
3603 break;
3604 }
3605
3606 msleep(20);
3607 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3608 break;
3609 }
3610
3611 return data;
3612}
3613
3614static void r8153b_ups_en(struct r8152 *tp, bool enable)
3615{
3616 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3617
3618 if (enable) {
3619 r8153b_ups_flags(tp);
3620
3621 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3622 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3623
3624 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3625 ocp_data |= UPS_FORCE_PWR_DOWN;
3626 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3627 } else {
3628 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3629 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3630
3631 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3632 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3633 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3634
3635 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3636 int i;
3637
3638 for (i = 0; i < 500; i++) {
3639 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3640 AUTOLOAD_DONE)
3641 break;
3642 msleep(20);
3643 }
3644
3645 tp->rtl_ops.hw_phy_cfg(tp);
3646
3647 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3648 tp->duplex, tp->advertising);
3649 }
3650 }
3651}
3652
3653static void r8153c_ups_en(struct r8152 *tp, bool enable)
3654{
3655 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3656
3657 if (enable) {
3658 r8153b_ups_flags(tp);
3659
3660 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3661 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3662
3663 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3664 ocp_data |= UPS_FORCE_PWR_DOWN;
3665 ocp_data &= ~BIT(7);
3666 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3667 } else {
3668 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3669 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3670
3671 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3672 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3673 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3674
3675 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3676 int i;
3677
3678 for (i = 0; i < 500; i++) {
3679 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3680 AUTOLOAD_DONE)
3681 break;
3682 msleep(20);
3683 }
3684
3685 tp->rtl_ops.hw_phy_cfg(tp);
3686
3687 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3688 tp->duplex, tp->advertising);
3689 }
3690
3691 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3692
3693 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3694 ocp_data |= BIT(8);
3695 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3696
3697 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3698 }
3699}
3700
3701static void r8156_ups_en(struct r8152 *tp, bool enable)
3702{
3703 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3704
3705 if (enable) {
3706 r8156_ups_flags(tp);
3707
3708 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3709 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3710
3711 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3712 ocp_data |= UPS_FORCE_PWR_DOWN;
3713 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3714
3715 switch (tp->version) {
3716 case RTL_VER_13:
3717 case RTL_VER_15:
3718 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
3719 ocp_data &= ~OOBS_POLLING;
3720 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);
3721 break;
3722 default:
3723 break;
3724 }
3725 } else {
3726 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3727 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3728
3729 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3730 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3731 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3732
3733 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3734 tp->rtl_ops.hw_phy_cfg(tp);
3735
3736 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3737 tp->duplex, tp->advertising);
3738 }
3739 }
3740}
3741
3742static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3743{
3744 u32 ocp_data;
3745
3746 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3747 if (enable)
3748 ocp_data |= PWR_EN | PHASE2_EN;
3749 else
3750 ocp_data &= ~(PWR_EN | PHASE2_EN);
3751 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3752
3753 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3754 ocp_data &= ~PCUT_STATUS;
3755 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3756}
3757
3758static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3759{
3760 u32 ocp_data;
3761
3762 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3763 if (enable)
3764 ocp_data |= PWR_EN | PHASE2_EN;
3765 else
3766 ocp_data &= ~PWR_EN;
3767 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3768
3769 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3770 ocp_data &= ~PCUT_STATUS;
3771 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3772}
3773
3774static void r8153_queue_wake(struct r8152 *tp, bool enable)
3775{
3776 u32 ocp_data;
3777
3778 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3779 if (enable)
3780 ocp_data |= UPCOMING_RUNTIME_D3;
3781 else
3782 ocp_data &= ~UPCOMING_RUNTIME_D3;
3783 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3784
3785 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3786 ocp_data &= ~LINK_CHG_EVENT;
3787 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3788
3789 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3790 ocp_data &= ~LINK_CHANGE_FLAG;
3791 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3792}
3793
3794static bool rtl_can_wakeup(struct r8152 *tp)
3795{
3796 struct usb_device *udev = tp->udev;
3797
3798 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3799}
3800
3801static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3802{
3803 if (enable) {
3804 u32 ocp_data;
3805
3806 __rtl_set_wol(tp, WAKE_ANY);
3807
3808 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3809
3810 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3811 ocp_data |= LINK_OFF_WAKE_EN;
3812 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3813
3814 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3815 } else {
3816 u32 ocp_data;
3817
3818 __rtl_set_wol(tp, tp->saved_wolopts);
3819
3820 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3821
3822 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3823 ocp_data &= ~LINK_OFF_WAKE_EN;
3824 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3825
3826 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3827 }
3828}
3829
3830static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3831{
3832 if (enable) {
3833 r8153_u1u2en(tp, false);
3834 r8153_u2p3en(tp, false);
3835 rtl_runtime_suspend_enable(tp, true);
3836 } else {
3837 rtl_runtime_suspend_enable(tp, false);
3838
3839 switch (tp->version) {
3840 case RTL_VER_03:
3841 case RTL_VER_04:
3842 break;
3843 case RTL_VER_05:
3844 case RTL_VER_06:
3845 default:
3846 r8153_u2p3en(tp, true);
3847 break;
3848 }
3849
3850 r8153_u1u2en(tp, true);
3851 }
3852}
3853
3854static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3855{
3856 if (enable) {
3857 r8153_queue_wake(tp, true);
3858 r8153b_u1u2en(tp, false);
3859 r8153_u2p3en(tp, false);
3860 rtl_runtime_suspend_enable(tp, true);
3861 r8153b_ups_en(tp, true);
3862 } else {
3863 r8153b_ups_en(tp, false);
3864 r8153_queue_wake(tp, false);
3865 rtl_runtime_suspend_enable(tp, false);
3866 if (tp->udev->speed >= USB_SPEED_SUPER)
3867 r8153b_u1u2en(tp, true);
3868 }
3869}
3870
3871static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)
3872{
3873 if (enable) {
3874 r8153_queue_wake(tp, true);
3875 r8153b_u1u2en(tp, false);
3876 r8153_u2p3en(tp, false);
3877 rtl_runtime_suspend_enable(tp, true);
3878 r8153c_ups_en(tp, true);
3879 } else {
3880 r8153c_ups_en(tp, false);
3881 r8153_queue_wake(tp, false);
3882 rtl_runtime_suspend_enable(tp, false);
3883 r8153b_u1u2en(tp, true);
3884 }
3885}
3886
3887static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)
3888{
3889 if (enable) {
3890 r8153_queue_wake(tp, true);
3891 r8153b_u1u2en(tp, false);
3892 r8153_u2p3en(tp, false);
3893 rtl_runtime_suspend_enable(tp, true);
3894 } else {
3895 r8153_queue_wake(tp, false);
3896 rtl_runtime_suspend_enable(tp, false);
3897 r8153_u2p3en(tp, true);
3898 if (tp->udev->speed >= USB_SPEED_SUPER)
3899 r8153b_u1u2en(tp, true);
3900 }
3901}
3902
3903static void r8153_teredo_off(struct r8152 *tp)
3904{
3905 u32 ocp_data;
3906
3907 switch (tp->version) {
3908 case RTL_VER_01:
3909 case RTL_VER_02:
3910 case RTL_VER_03:
3911 case RTL_VER_04:
3912 case RTL_VER_05:
3913 case RTL_VER_06:
3914 case RTL_VER_07:
3915 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3916 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3917 OOB_TEREDO_EN);
3918 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3919 break;
3920
3921 case RTL_VER_08:
3922 case RTL_VER_09:
3923 case RTL_TEST_01:
3924 case RTL_VER_10:
3925 case RTL_VER_11:
3926 case RTL_VER_12:
3927 case RTL_VER_13:
3928 case RTL_VER_14:
3929 case RTL_VER_15:
3930 default:
3931 /* The bit 0 ~ 7 are relative with teredo settings. They are
3932 * W1C (write 1 to clear), so set all 1 to disable it.
3933 */
3934 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3935 break;
3936 }
3937
3938 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3939 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3940 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3941}
3942
3943static void rtl_reset_bmu(struct r8152 *tp)
3944{
3945 u32 ocp_data;
3946
3947 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3948 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3949 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3950 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3951 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3952}
3953
3954/* Clear the bp to stop the firmware before loading a new one */
3955static void rtl_clear_bp(struct r8152 *tp, u16 type)
3956{
3957 switch (tp->version) {
3958 case RTL_VER_01:
3959 case RTL_VER_02:
3960 case RTL_VER_07:
3961 break;
3962 case RTL_VER_03:
3963 case RTL_VER_04:
3964 case RTL_VER_05:
3965 case RTL_VER_06:
3966 ocp_write_byte(tp, type, PLA_BP_EN, 0);
3967 break;
3968 case RTL_VER_14:
3969 ocp_write_word(tp, type, USB_BP2_EN, 0);
3970
3971 ocp_write_word(tp, type, USB_BP_8, 0);
3972 ocp_write_word(tp, type, USB_BP_9, 0);
3973 ocp_write_word(tp, type, USB_BP_10, 0);
3974 ocp_write_word(tp, type, USB_BP_11, 0);
3975 ocp_write_word(tp, type, USB_BP_12, 0);
3976 ocp_write_word(tp, type, USB_BP_13, 0);
3977 ocp_write_word(tp, type, USB_BP_14, 0);
3978 ocp_write_word(tp, type, USB_BP_15, 0);
3979 break;
3980 case RTL_VER_08:
3981 case RTL_VER_09:
3982 case RTL_VER_10:
3983 case RTL_VER_11:
3984 case RTL_VER_12:
3985 case RTL_VER_13:
3986 case RTL_VER_15:
3987 default:
3988 if (type == MCU_TYPE_USB) {
3989 ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
3990
3991 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
3992 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
3993 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
3994 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
3995 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
3996 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
3997 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
3998 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
3999 } else {
4000 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
4001 }
4002 break;
4003 }
4004
4005 ocp_write_word(tp, type, PLA_BP_0, 0);
4006 ocp_write_word(tp, type, PLA_BP_1, 0);
4007 ocp_write_word(tp, type, PLA_BP_2, 0);
4008 ocp_write_word(tp, type, PLA_BP_3, 0);
4009 ocp_write_word(tp, type, PLA_BP_4, 0);
4010 ocp_write_word(tp, type, PLA_BP_5, 0);
4011 ocp_write_word(tp, type, PLA_BP_6, 0);
4012 ocp_write_word(tp, type, PLA_BP_7, 0);
4013
4014 /* wait 3 ms to make sure the firmware is stopped */
4015 usleep_range(3000, 6000);
4016 ocp_write_word(tp, type, PLA_BP_BA, 0);
4017}
4018
4019static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
4020{
4021 u16 data, check;
4022 int i;
4023
4024 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
4025 if (request) {
4026 data |= PATCH_REQUEST;
4027 check = 0;
4028 } else {
4029 data &= ~PATCH_REQUEST;
4030 check = PATCH_READY;
4031 }
4032 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
4033
4034 for (i = 0; wait && i < 5000; i++) {
4035 u32 ocp_data;
4036
4037 usleep_range(1000, 2000);
4038 ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
4039 if ((ocp_data & PATCH_READY) ^ check)
4040 break;
4041 }
4042
4043 if (request && wait &&
4044 !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
4045 dev_err(&tp->intf->dev, "PHY patch request fail\n");
4046 rtl_phy_patch_request(tp, false, false);
4047 return -ETIME;
4048 } else {
4049 return 0;
4050 }
4051}
4052
4053static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)
4054{
4055 if (patch_key && key_addr) {
4056 sram_write(tp, key_addr, patch_key);
4057 sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
4058 } else if (key_addr) {
4059 u16 data;
4060
4061 sram_write(tp, 0x0000, 0x0000);
4062
4063 data = ocp_reg_read(tp, OCP_PHY_LOCK);
4064 data &= ~PATCH_LOCK;
4065 ocp_reg_write(tp, OCP_PHY_LOCK, data);
4066
4067 sram_write(tp, key_addr, 0x0000);
4068 } else {
4069 WARN_ON_ONCE(1);
4070 }
4071}
4072
4073static int
4074rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)
4075{
4076 if (rtl_phy_patch_request(tp, true, wait))
4077 return -ETIME;
4078
4079 rtl_patch_key_set(tp, key_addr, patch_key);
4080
4081 return 0;
4082}
4083
4084static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)
4085{
4086 rtl_patch_key_set(tp, key_addr, 0);
4087
4088 rtl_phy_patch_request(tp, false, wait);
4089
4090 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
4091
4092 return 0;
4093}
4094
4095static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy)
4096{
4097 u16 fw_offset;
4098 u32 length;
4099 bool rc = false;
4100
4101 switch (tp->version) {
4102 case RTL_VER_01:
4103 case RTL_VER_02:
4104 case RTL_VER_03:
4105 case RTL_VER_04:
4106 case RTL_VER_05:
4107 case RTL_VER_06:
4108 case RTL_VER_07:
4109 case RTL_VER_08:
4110 case RTL_VER_09:
4111 case RTL_VER_10:
4112 case RTL_VER_11:
4113 case RTL_VER_12:
4114 case RTL_VER_14:
4115 goto out;
4116 case RTL_VER_13:
4117 case RTL_VER_15:
4118 default:
4119 break;
4120 }
4121
4122 fw_offset = __le16_to_cpu(phy->fw_offset);
4123 length = __le32_to_cpu(phy->blk_hdr.length);
4124 if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4125 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4126 goto out;
4127 }
4128
4129 length -= fw_offset;
4130 if (length & 3) {
4131 dev_err(&tp->intf->dev, "invalid block length\n");
4132 goto out;
4133 }
4134
4135 if (__le16_to_cpu(phy->fw_reg) != 0x9A00) {
4136 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4137 goto out;
4138 }
4139
4140 rc = true;
4141out:
4142 return rc;
4143}
4144
4145static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver)
4146{
4147 bool rc = false;
4148
4149 switch (tp->version) {
4150 case RTL_VER_10:
4151 case RTL_VER_11:
4152 case RTL_VER_12:
4153 case RTL_VER_13:
4154 case RTL_VER_15:
4155 break;
4156 default:
4157 goto out;
4158 }
4159
4160 if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) {
4161 dev_err(&tp->intf->dev, "invalid block length\n");
4162 goto out;
4163 }
4164
4165 if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) {
4166 dev_err(&tp->intf->dev, "invalid phy ver addr\n");
4167 goto out;
4168 }
4169
4170 rc = true;
4171out:
4172 return rc;
4173}
4174
4175static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix)
4176{
4177 bool rc = false;
4178
4179 switch (tp->version) {
4180 case RTL_VER_10:
4181 case RTL_VER_11:
4182 case RTL_VER_12:
4183 case RTL_VER_13:
4184 case RTL_VER_15:
4185 break;
4186 default:
4187 goto out;
4188 }
4189
4190 if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) {
4191 dev_err(&tp->intf->dev, "invalid block length\n");
4192 goto out;
4193 }
4194
4195 if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD ||
4196 __le16_to_cpu(fix->setting.data) != BIT(7)) {
4197 dev_err(&tp->intf->dev, "invalid phy fixup\n");
4198 goto out;
4199 }
4200
4201 rc = true;
4202out:
4203 return rc;
4204}
4205
4206static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy)
4207{
4208 u16 fw_offset;
4209 u32 length;
4210 bool rc = false;
4211
4212 switch (tp->version) {
4213 case RTL_VER_10:
4214 case RTL_VER_11:
4215 case RTL_VER_12:
4216 case RTL_VER_13:
4217 case RTL_VER_15:
4218 break;
4219 default:
4220 goto out;
4221 }
4222
4223 fw_offset = __le16_to_cpu(phy->fw_offset);
4224 length = __le32_to_cpu(phy->blk_hdr.length);
4225 if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4226 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4227 goto out;
4228 }
4229
4230 length -= fw_offset;
4231 if (length & 1) {
4232 dev_err(&tp->intf->dev, "invalid block length\n");
4233 goto out;
4234 }
4235
4236 if (phy->pre_num > 2) {
4237 dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num);
4238 goto out;
4239 }
4240
4241 if (phy->bp_num > 8) {
4242 dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num);
4243 goto out;
4244 }
4245
4246 rc = true;
4247out:
4248 return rc;
4249}
4250
4251static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
4252{
4253 u32 length;
4254 u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
4255 bool rc = false;
4256
4257 switch (tp->version) {
4258 case RTL_VER_04:
4259 case RTL_VER_05:
4260 case RTL_VER_06:
4261 fw_reg = 0xa014;
4262 ba_reg = 0xa012;
4263 patch_en_addr = 0xa01a;
4264 mode_reg = 0xb820;
4265 bp_start = 0xa000;
4266 break;
4267 default:
4268 goto out;
4269 }
4270
4271 fw_offset = __le16_to_cpu(phy->fw_offset);
4272 if (fw_offset < sizeof(*phy)) {
4273 dev_err(&tp->intf->dev, "fw_offset too small\n");
4274 goto out;
4275 }
4276
4277 length = __le32_to_cpu(phy->blk_hdr.length);
4278 if (length < fw_offset) {
4279 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4280 goto out;
4281 }
4282
4283 length -= __le16_to_cpu(phy->fw_offset);
4284 if (!length || (length & 1)) {
4285 dev_err(&tp->intf->dev, "invalid block length\n");
4286 goto out;
4287 }
4288
4289 if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
4290 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4291 goto out;
4292 }
4293
4294 if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
4295 dev_err(&tp->intf->dev, "invalid base address register\n");
4296 goto out;
4297 }
4298
4299 if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
4300 dev_err(&tp->intf->dev,
4301 "invalid patch mode enabled register\n");
4302 goto out;
4303 }
4304
4305 if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
4306 dev_err(&tp->intf->dev,
4307 "invalid register to switch the mode\n");
4308 goto out;
4309 }
4310
4311 if (__le16_to_cpu(phy->bp_start) != bp_start) {
4312 dev_err(&tp->intf->dev,
4313 "invalid start register of break point\n");
4314 goto out;
4315 }
4316
4317 if (__le16_to_cpu(phy->bp_num) > 4) {
4318 dev_err(&tp->intf->dev, "invalid break point number\n");
4319 goto out;
4320 }
4321
4322 rc = true;
4323out:
4324 return rc;
4325}
4326
4327static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
4328{
4329 u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
4330 bool rc = false;
4331 u32 length, type;
4332 int i, max_bp;
4333
4334 type = __le32_to_cpu(mac->blk_hdr.type);
4335 if (type == RTL_FW_PLA) {
4336 switch (tp->version) {
4337 case RTL_VER_01:
4338 case RTL_VER_02:
4339 case RTL_VER_07:
4340 fw_reg = 0xf800;
4341 bp_ba_addr = PLA_BP_BA;
4342 bp_en_addr = 0;
4343 bp_start = PLA_BP_0;
4344 max_bp = 8;
4345 break;
4346 case RTL_VER_03:
4347 case RTL_VER_04:
4348 case RTL_VER_05:
4349 case RTL_VER_06:
4350 case RTL_VER_08:
4351 case RTL_VER_09:
4352 case RTL_VER_11:
4353 case RTL_VER_12:
4354 case RTL_VER_13:
4355 case RTL_VER_15:
4356 fw_reg = 0xf800;
4357 bp_ba_addr = PLA_BP_BA;
4358 bp_en_addr = PLA_BP_EN;
4359 bp_start = PLA_BP_0;
4360 max_bp = 8;
4361 break;
4362 case RTL_VER_14:
4363 fw_reg = 0xf800;
4364 bp_ba_addr = PLA_BP_BA;
4365 bp_en_addr = USB_BP2_EN;
4366 bp_start = PLA_BP_0;
4367 max_bp = 16;
4368 break;
4369 default:
4370 goto out;
4371 }
4372 } else if (type == RTL_FW_USB) {
4373 switch (tp->version) {
4374 case RTL_VER_03:
4375 case RTL_VER_04:
4376 case RTL_VER_05:
4377 case RTL_VER_06:
4378 fw_reg = 0xf800;
4379 bp_ba_addr = USB_BP_BA;
4380 bp_en_addr = USB_BP_EN;
4381 bp_start = USB_BP_0;
4382 max_bp = 8;
4383 break;
4384 case RTL_VER_08:
4385 case RTL_VER_09:
4386 case RTL_VER_11:
4387 case RTL_VER_12:
4388 case RTL_VER_13:
4389 case RTL_VER_14:
4390 case RTL_VER_15:
4391 fw_reg = 0xe600;
4392 bp_ba_addr = USB_BP_BA;
4393 bp_en_addr = USB_BP2_EN;
4394 bp_start = USB_BP_0;
4395 max_bp = 16;
4396 break;
4397 case RTL_VER_01:
4398 case RTL_VER_02:
4399 case RTL_VER_07:
4400 default:
4401 goto out;
4402 }
4403 } else {
4404 goto out;
4405 }
4406
4407 fw_offset = __le16_to_cpu(mac->fw_offset);
4408 if (fw_offset < sizeof(*mac)) {
4409 dev_err(&tp->intf->dev, "fw_offset too small\n");
4410 goto out;
4411 }
4412
4413 length = __le32_to_cpu(mac->blk_hdr.length);
4414 if (length < fw_offset) {
4415 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4416 goto out;
4417 }
4418
4419 length -= fw_offset;
4420 if (length < 4 || (length & 3)) {
4421 dev_err(&tp->intf->dev, "invalid block length\n");
4422 goto out;
4423 }
4424
4425 if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
4426 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4427 goto out;
4428 }
4429
4430 if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
4431 dev_err(&tp->intf->dev, "invalid base address register\n");
4432 goto out;
4433 }
4434
4435 if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
4436 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
4437 goto out;
4438 }
4439
4440 if (__le16_to_cpu(mac->bp_start) != bp_start) {
4441 dev_err(&tp->intf->dev,
4442 "invalid start register of break point\n");
4443 goto out;
4444 }
4445
4446 if (__le16_to_cpu(mac->bp_num) > max_bp) {
4447 dev_err(&tp->intf->dev, "invalid break point number\n");
4448 goto out;
4449 }
4450
4451 for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
4452 if (mac->bp[i]) {
4453 dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
4454 goto out;
4455 }
4456 }
4457
4458 rc = true;
4459out:
4460 return rc;
4461}
4462
4463/* Verify the checksum for the firmware file. It is calculated from the version
4464 * field to the end of the file. Compare the result with the checksum field to
4465 * make sure the file is correct.
4466 */
4467static long rtl8152_fw_verify_checksum(struct r8152 *tp,
4468 struct fw_header *fw_hdr, size_t size)
4469{
4470 unsigned char checksum[sizeof(fw_hdr->checksum)];
4471 struct crypto_shash *alg;
4472 struct shash_desc *sdesc;
4473 size_t len;
4474 long rc;
4475
4476 alg = crypto_alloc_shash("sha256", 0, 0);
4477 if (IS_ERR(alg)) {
4478 rc = PTR_ERR(alg);
4479 goto out;
4480 }
4481
4482 if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
4483 rc = -EFAULT;
4484 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
4485 crypto_shash_digestsize(alg));
4486 goto free_shash;
4487 }
4488
4489 len = sizeof(*sdesc) + crypto_shash_descsize(alg);
4490 sdesc = kmalloc(len, GFP_KERNEL);
4491 if (!sdesc) {
4492 rc = -ENOMEM;
4493 goto free_shash;
4494 }
4495 sdesc->tfm = alg;
4496
4497 len = size - sizeof(fw_hdr->checksum);
4498 rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
4499 kfree(sdesc);
4500 if (rc)
4501 goto free_shash;
4502
4503 if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
4504 dev_err(&tp->intf->dev, "checksum fail\n");
4505 rc = -EFAULT;
4506 }
4507
4508free_shash:
4509 crypto_free_shash(alg);
4510out:
4511 return rc;
4512}
4513
4514static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
4515{
4516 const struct firmware *fw = rtl_fw->fw;
4517 struct fw_header *fw_hdr = (struct fw_header *)fw->data;
4518 unsigned long fw_flags = 0;
4519 long ret = -EFAULT;
4520 int i;
4521
4522 if (fw->size < sizeof(*fw_hdr)) {
4523 dev_err(&tp->intf->dev, "file too small\n");
4524 goto fail;
4525 }
4526
4527 ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
4528 if (ret)
4529 goto fail;
4530
4531 ret = -EFAULT;
4532
4533 for (i = sizeof(*fw_hdr); i < fw->size;) {
4534 struct fw_block *block = (struct fw_block *)&fw->data[i];
4535 u32 type;
4536
4537 if ((i + sizeof(*block)) > fw->size)
4538 goto fail;
4539
4540 type = __le32_to_cpu(block->type);
4541 switch (type) {
4542 case RTL_FW_END:
4543 if (__le32_to_cpu(block->length) != sizeof(*block))
4544 goto fail;
4545 goto fw_end;
4546 case RTL_FW_PLA:
4547 if (test_bit(FW_FLAGS_PLA, &fw_flags)) {
4548 dev_err(&tp->intf->dev,
4549 "multiple PLA firmware encountered");
4550 goto fail;
4551 }
4552
4553 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4554 dev_err(&tp->intf->dev,
4555 "check PLA firmware failed\n");
4556 goto fail;
4557 }
4558 __set_bit(FW_FLAGS_PLA, &fw_flags);
4559 break;
4560 case RTL_FW_USB:
4561 if (test_bit(FW_FLAGS_USB, &fw_flags)) {
4562 dev_err(&tp->intf->dev,
4563 "multiple USB firmware encountered");
4564 goto fail;
4565 }
4566
4567 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4568 dev_err(&tp->intf->dev,
4569 "check USB firmware failed\n");
4570 goto fail;
4571 }
4572 __set_bit(FW_FLAGS_USB, &fw_flags);
4573 break;
4574 case RTL_FW_PHY_START:
4575 if (test_bit(FW_FLAGS_START, &fw_flags) ||
4576 test_bit(FW_FLAGS_NC, &fw_flags) ||
4577 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4578 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4579 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4580 test_bit(FW_FLAGS_UC, &fw_flags) ||
4581 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4582 dev_err(&tp->intf->dev,
4583 "check PHY_START fail\n");
4584 goto fail;
4585 }
4586
4587 if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) {
4588 dev_err(&tp->intf->dev,
4589 "Invalid length for PHY_START\n");
4590 goto fail;
4591 }
4592 __set_bit(FW_FLAGS_START, &fw_flags);
4593 break;
4594 case RTL_FW_PHY_STOP:
4595 if (test_bit(FW_FLAGS_STOP, &fw_flags) ||
4596 !test_bit(FW_FLAGS_START, &fw_flags)) {
4597 dev_err(&tp->intf->dev,
4598 "Check PHY_STOP fail\n");
4599 goto fail;
4600 }
4601
4602 if (__le32_to_cpu(block->length) != sizeof(*block)) {
4603 dev_err(&tp->intf->dev,
4604 "Invalid length for PHY_STOP\n");
4605 goto fail;
4606 }
4607 __set_bit(FW_FLAGS_STOP, &fw_flags);
4608 break;
4609 case RTL_FW_PHY_NC:
4610 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4611 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4612 dev_err(&tp->intf->dev,
4613 "check PHY_NC fail\n");
4614 goto fail;
4615 }
4616
4617 if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4618 dev_err(&tp->intf->dev,
4619 "multiple PHY NC encountered\n");
4620 goto fail;
4621 }
4622
4623 if (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) {
4624 dev_err(&tp->intf->dev,
4625 "check PHY NC firmware failed\n");
4626 goto fail;
4627 }
4628 __set_bit(FW_FLAGS_NC, &fw_flags);
4629 break;
4630 case RTL_FW_PHY_UNION_NC:
4631 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4632 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4633 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4634 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4635 test_bit(FW_FLAGS_UC, &fw_flags) ||
4636 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4637 dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n");
4638 goto fail;
4639 }
4640
4641 if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4642 dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n");
4643 goto fail;
4644 }
4645
4646 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4647 dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n");
4648 goto fail;
4649 }
4650 __set_bit(FW_FLAGS_NC, &fw_flags);
4651 break;
4652 case RTL_FW_PHY_UNION_NC1:
4653 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4654 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4655 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4656 test_bit(FW_FLAGS_UC, &fw_flags) ||
4657 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4658 dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n");
4659 goto fail;
4660 }
4661
4662 if (test_bit(FW_FLAGS_NC1, &fw_flags)) {
4663 dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n");
4664 goto fail;
4665 }
4666
4667 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4668 dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n");
4669 goto fail;
4670 }
4671 __set_bit(FW_FLAGS_NC1, &fw_flags);
4672 break;
4673 case RTL_FW_PHY_UNION_NC2:
4674 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4675 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4676 test_bit(FW_FLAGS_UC, &fw_flags) ||
4677 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4678 dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n");
4679 goto fail;
4680 }
4681
4682 if (test_bit(FW_FLAGS_NC2, &fw_flags)) {
4683 dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n");
4684 goto fail;
4685 }
4686
4687 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4688 dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n");
4689 goto fail;
4690 }
4691 __set_bit(FW_FLAGS_NC2, &fw_flags);
4692 break;
4693 case RTL_FW_PHY_UNION_UC2:
4694 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4695 test_bit(FW_FLAGS_UC, &fw_flags) ||
4696 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4697 dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n");
4698 goto fail;
4699 }
4700
4701 if (test_bit(FW_FLAGS_UC2, &fw_flags)) {
4702 dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n");
4703 goto fail;
4704 }
4705
4706 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4707 dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n");
4708 goto fail;
4709 }
4710 __set_bit(FW_FLAGS_UC2, &fw_flags);
4711 break;
4712 case RTL_FW_PHY_UNION_UC:
4713 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4714 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4715 dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n");
4716 goto fail;
4717 }
4718
4719 if (test_bit(FW_FLAGS_UC, &fw_flags)) {
4720 dev_err(&tp->intf->dev, "multiple PHY UC encountered\n");
4721 goto fail;
4722 }
4723
4724 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4725 dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n");
4726 goto fail;
4727 }
4728 __set_bit(FW_FLAGS_UC, &fw_flags);
4729 break;
4730 case RTL_FW_PHY_UNION_MISC:
4731 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4732 dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n");
4733 goto fail;
4734 }
4735 break;
4736 case RTL_FW_PHY_FIXUP:
4737 if (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) {
4738 dev_err(&tp->intf->dev, "check PHY fixup failed\n");
4739 goto fail;
4740 }
4741 break;
4742 case RTL_FW_PHY_SPEED_UP:
4743 if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) {
4744 dev_err(&tp->intf->dev, "multiple PHY firmware encountered");
4745 goto fail;
4746 }
4747
4748 if (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) {
4749 dev_err(&tp->intf->dev, "check PHY speed up failed\n");
4750 goto fail;
4751 }
4752 __set_bit(FW_FLAGS_SPEED_UP, &fw_flags);
4753 break;
4754 case RTL_FW_PHY_VER:
4755 if (test_bit(FW_FLAGS_START, &fw_flags) ||
4756 test_bit(FW_FLAGS_NC, &fw_flags) ||
4757 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4758 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4759 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4760 test_bit(FW_FLAGS_UC, &fw_flags) ||
4761 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4762 dev_err(&tp->intf->dev, "Invalid order to set PHY version\n");
4763 goto fail;
4764 }
4765
4766 if (test_bit(FW_FLAGS_VER, &fw_flags)) {
4767 dev_err(&tp->intf->dev, "multiple PHY version encountered");
4768 goto fail;
4769 }
4770
4771 if (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) {
4772 dev_err(&tp->intf->dev, "check PHY version failed\n");
4773 goto fail;
4774 }
4775 __set_bit(FW_FLAGS_VER, &fw_flags);
4776 break;
4777 default:
4778 dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
4779 type);
4780 break;
4781 }
4782
4783 /* next block */
4784 i += ALIGN(__le32_to_cpu(block->length), 8);
4785 }
4786
4787fw_end:
4788 if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) {
4789 dev_err(&tp->intf->dev, "without PHY_STOP\n");
4790 goto fail;
4791 }
4792
4793 return 0;
4794fail:
4795 return ret;
4796}
4797
4798static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)
4799{
4800 u32 len;
4801 u8 *data;
4802
4803 if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) {
4804 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4805 return;
4806 }
4807
4808 len = __le32_to_cpu(phy->blk_hdr.length);
4809 len -= __le16_to_cpu(phy->fw_offset);
4810 data = (u8 *)phy + __le16_to_cpu(phy->fw_offset);
4811
4812 if (rtl_phy_patch_request(tp, true, wait))
4813 return;
4814
4815 while (len) {
4816 u32 ocp_data, size;
4817 int i;
4818
4819 if (len < 2048)
4820 size = len;
4821 else
4822 size = 2048;
4823
4824 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);
4825 ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;
4826 ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data);
4827
4828 generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB);
4829
4830 data += size;
4831 len -= size;
4832
4833 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);
4834 ocp_data |= POL_GPHY_PATCH;
4835 ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data);
4836
4837 for (i = 0; i < 1000; i++) {
4838 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))
4839 break;
4840 }
4841
4842 if (i == 1000) {
4843 dev_err(&tp->intf->dev, "ram code speedup mode timeout\n");
4844 break;
4845 }
4846 }
4847
4848 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
4849 rtl_phy_patch_request(tp, false, wait);
4850
4851 if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version))
4852 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4853 else
4854 dev_err(&tp->intf->dev, "ram code speedup mode fail\n");
4855}
4856
4857static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver)
4858{
4859 u16 ver_addr, ver;
4860
4861 ver_addr = __le16_to_cpu(phy_ver->ver.addr);
4862 ver = __le16_to_cpu(phy_ver->ver.data);
4863
4864 if (sram_read(tp, ver_addr) >= ver) {
4865 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4866 return 0;
4867 }
4868
4869 sram_write(tp, ver_addr, ver);
4870
4871 dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver);
4872
4873 return ver;
4874}
4875
4876static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix)
4877{
4878 u16 addr, data;
4879
4880 addr = __le16_to_cpu(fix->setting.addr);
4881 data = ocp_reg_read(tp, addr);
4882
4883 switch (__le16_to_cpu(fix->bit_cmd)) {
4884 case FW_FIXUP_AND:
4885 data &= __le16_to_cpu(fix->setting.data);
4886 break;
4887 case FW_FIXUP_OR:
4888 data |= __le16_to_cpu(fix->setting.data);
4889 break;
4890 case FW_FIXUP_NOT:
4891 data &= ~__le16_to_cpu(fix->setting.data);
4892 break;
4893 case FW_FIXUP_XOR:
4894 data ^= __le16_to_cpu(fix->setting.data);
4895 break;
4896 default:
4897 return;
4898 }
4899
4900 ocp_reg_write(tp, addr, data);
4901
4902 dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data);
4903}
4904
4905static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy)
4906{
4907 __le16 *data;
4908 u32 length;
4909 int i, num;
4910
4911 num = phy->pre_num;
4912 for (i = 0; i < num; i++)
4913 sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr),
4914 __le16_to_cpu(phy->pre_set[i].data));
4915
4916 length = __le32_to_cpu(phy->blk_hdr.length);
4917 length -= __le16_to_cpu(phy->fw_offset);
4918 num = length / 2;
4919 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
4920
4921 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
4922 for (i = 0; i < num; i++)
4923 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
4924
4925 num = phy->bp_num;
4926 for (i = 0; i < num; i++)
4927 sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data));
4928
4929 if (phy->bp_num && phy->bp_en.addr)
4930 sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data));
4931
4932 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4933}
4934
4935static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
4936{
4937 u16 mode_reg, bp_index;
4938 u32 length, i, num;
4939 __le16 *data;
4940
4941 mode_reg = __le16_to_cpu(phy->mode_reg);
4942 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
4943 sram_write(tp, __le16_to_cpu(phy->ba_reg),
4944 __le16_to_cpu(phy->ba_data));
4945
4946 length = __le32_to_cpu(phy->blk_hdr.length);
4947 length -= __le16_to_cpu(phy->fw_offset);
4948 num = length / 2;
4949 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
4950
4951 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
4952 for (i = 0; i < num; i++)
4953 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
4954
4955 sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
4956 __le16_to_cpu(phy->patch_en_value));
4957
4958 bp_index = __le16_to_cpu(phy->bp_start);
4959 num = __le16_to_cpu(phy->bp_num);
4960 for (i = 0; i < num; i++) {
4961 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
4962 bp_index += 2;
4963 }
4964
4965 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
4966
4967 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4968}
4969
4970static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
4971{
4972 u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
4973 u32 length;
4974 u8 *data;
4975 int i;
4976
4977 switch (__le32_to_cpu(mac->blk_hdr.type)) {
4978 case RTL_FW_PLA:
4979 type = MCU_TYPE_PLA;
4980 break;
4981 case RTL_FW_USB:
4982 type = MCU_TYPE_USB;
4983 break;
4984 default:
4985 return;
4986 }
4987
4988 fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
4989 if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) {
4990 dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB");
4991 return;
4992 }
4993
4994 rtl_clear_bp(tp, type);
4995
4996 /* Enable backup/restore of MACDBG. This is required after clearing PLA
4997 * break points and before applying the PLA firmware.
4998 */
4999 if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
5000 !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
5001 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
5002 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
5003 }
5004
5005 length = __le32_to_cpu(mac->blk_hdr.length);
5006 length -= __le16_to_cpu(mac->fw_offset);
5007
5008 data = (u8 *)mac;
5009 data += __le16_to_cpu(mac->fw_offset);
5010
5011 generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
5012 type);
5013
5014 ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
5015 __le16_to_cpu(mac->bp_ba_value));
5016
5017 bp_index = __le16_to_cpu(mac->bp_start);
5018 bp_num = __le16_to_cpu(mac->bp_num);
5019 for (i = 0; i < bp_num; i++) {
5020 ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
5021 bp_index += 2;
5022 }
5023
5024 bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
5025 if (bp_en_addr)
5026 ocp_write_word(tp, type, bp_en_addr,
5027 __le16_to_cpu(mac->bp_en_value));
5028
5029 if (fw_ver_reg)
5030 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
5031 mac->fw_ver_data);
5032
5033 dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
5034}
5035
5036static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)
5037{
5038 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5039 const struct firmware *fw;
5040 struct fw_header *fw_hdr;
5041 struct fw_phy_patch_key *key;
5042 u16 key_addr = 0;
5043 int i, patch_phy = 1;
5044
5045 if (IS_ERR_OR_NULL(rtl_fw->fw))
5046 return;
5047
5048 fw = rtl_fw->fw;
5049 fw_hdr = (struct fw_header *)fw->data;
5050
5051 if (rtl_fw->pre_fw)
5052 rtl_fw->pre_fw(tp);
5053
5054 for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
5055 struct fw_block *block = (struct fw_block *)&fw->data[i];
5056
5057 switch (__le32_to_cpu(block->type)) {
5058 case RTL_FW_END:
5059 goto post_fw;
5060 case RTL_FW_PLA:
5061 case RTL_FW_USB:
5062 rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
5063 break;
5064 case RTL_FW_PHY_START:
5065 if (!patch_phy)
5066 break;
5067 key = (struct fw_phy_patch_key *)block;
5068 key_addr = __le16_to_cpu(key->key_reg);
5069 rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut);
5070 break;
5071 case RTL_FW_PHY_STOP:
5072 if (!patch_phy)
5073 break;
5074 WARN_ON(!key_addr);
5075 rtl_post_ram_code(tp, key_addr, !power_cut);
5076 break;
5077 case RTL_FW_PHY_NC:
5078 rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
5079 break;
5080 case RTL_FW_PHY_VER:
5081 patch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block);
5082 break;
5083 case RTL_FW_PHY_UNION_NC:
5084 case RTL_FW_PHY_UNION_NC1:
5085 case RTL_FW_PHY_UNION_NC2:
5086 case RTL_FW_PHY_UNION_UC2:
5087 case RTL_FW_PHY_UNION_UC:
5088 case RTL_FW_PHY_UNION_MISC:
5089 if (patch_phy)
5090 rtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block);
5091 break;
5092 case RTL_FW_PHY_FIXUP:
5093 if (patch_phy)
5094 rtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block);
5095 break;
5096 case RTL_FW_PHY_SPEED_UP:
5097 rtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut);
5098 break;
5099 default:
5100 break;
5101 }
5102
5103 i += ALIGN(__le32_to_cpu(block->length), 8);
5104 }
5105
5106post_fw:
5107 if (rtl_fw->post_fw)
5108 rtl_fw->post_fw(tp);
5109
5110 strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
5111 dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
5112}
5113
5114static void rtl8152_release_firmware(struct r8152 *tp)
5115{
5116 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5117
5118 if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
5119 release_firmware(rtl_fw->fw);
5120 rtl_fw->fw = NULL;
5121 }
5122}
5123
5124static int rtl8152_request_firmware(struct r8152 *tp)
5125{
5126 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5127 long rc;
5128
5129 if (rtl_fw->fw || !rtl_fw->fw_name) {
5130 dev_info(&tp->intf->dev, "skip request firmware\n");
5131 rc = 0;
5132 goto result;
5133 }
5134
5135 rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
5136 if (rc < 0)
5137 goto result;
5138
5139 rc = rtl8152_check_firmware(tp, rtl_fw);
5140 if (rc < 0)
5141 release_firmware(rtl_fw->fw);
5142
5143result:
5144 if (rc) {
5145 rtl_fw->fw = ERR_PTR(rc);
5146
5147 dev_warn(&tp->intf->dev,
5148 "unable to load firmware patch %s (%ld)\n",
5149 rtl_fw->fw_name, rc);
5150 }
5151
5152 return rc;
5153}
5154
5155static void r8152_aldps_en(struct r8152 *tp, bool enable)
5156{
5157 if (enable) {
5158 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
5159 LINKENA | DIS_SDSAVE);
5160 } else {
5161 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
5162 DIS_SDSAVE);
5163 msleep(20);
5164 }
5165}
5166
5167static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
5168{
5169 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
5170 ocp_reg_write(tp, OCP_EEE_DATA, reg);
5171 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
5172}
5173
5174static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
5175{
5176 u16 data;
5177
5178 r8152_mmd_indirect(tp, dev, reg);
5179 data = ocp_reg_read(tp, OCP_EEE_DATA);
5180 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5181
5182 return data;
5183}
5184
5185static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
5186{
5187 r8152_mmd_indirect(tp, dev, reg);
5188 ocp_reg_write(tp, OCP_EEE_DATA, data);
5189 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5190}
5191
5192static void r8152_eee_en(struct r8152 *tp, bool enable)
5193{
5194 u16 config1, config2, config3;
5195 u32 ocp_data;
5196
5197 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5198 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
5199 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
5200 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
5201
5202 if (enable) {
5203 ocp_data |= EEE_RX_EN | EEE_TX_EN;
5204 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
5205 config1 |= sd_rise_time(1);
5206 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
5207 config3 |= fast_snr(42);
5208 } else {
5209 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5210 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
5211 RX_QUIET_EN);
5212 config1 |= sd_rise_time(7);
5213 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
5214 config3 |= fast_snr(511);
5215 }
5216
5217 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5218 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
5219 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
5220 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
5221}
5222
5223static void r8153_eee_en(struct r8152 *tp, bool enable)
5224{
5225 u32 ocp_data;
5226 u16 config;
5227
5228 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5229 config = ocp_reg_read(tp, OCP_EEE_CFG);
5230
5231 if (enable) {
5232 ocp_data |= EEE_RX_EN | EEE_TX_EN;
5233 config |= EEE10_EN;
5234 } else {
5235 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5236 config &= ~EEE10_EN;
5237 }
5238
5239 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5240 ocp_reg_write(tp, OCP_EEE_CFG, config);
5241
5242 tp->ups_info.eee = enable;
5243}
5244
5245static void r8156_eee_en(struct r8152 *tp, bool enable)
5246{
5247 u16 config;
5248
5249 r8153_eee_en(tp, enable);
5250
5251 config = ocp_reg_read(tp, OCP_EEE_ADV2);
5252
5253 if (enable)
5254 config |= MDIO_EEE_2_5GT;
5255 else
5256 config &= ~MDIO_EEE_2_5GT;
5257
5258 ocp_reg_write(tp, OCP_EEE_ADV2, config);
5259}
5260
5261static void rtl_eee_enable(struct r8152 *tp, bool enable)
5262{
5263 switch (tp->version) {
5264 case RTL_VER_01:
5265 case RTL_VER_02:
5266 case RTL_VER_07:
5267 if (enable) {
5268 r8152_eee_en(tp, true);
5269 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
5270 tp->eee_adv);
5271 } else {
5272 r8152_eee_en(tp, false);
5273 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
5274 }
5275 break;
5276 case RTL_VER_03:
5277 case RTL_VER_04:
5278 case RTL_VER_05:
5279 case RTL_VER_06:
5280 case RTL_VER_08:
5281 case RTL_VER_09:
5282 case RTL_VER_14:
5283 if (enable) {
5284 r8153_eee_en(tp, true);
5285 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5286 } else {
5287 r8153_eee_en(tp, false);
5288 ocp_reg_write(tp, OCP_EEE_ADV, 0);
5289 }
5290 break;
5291 case RTL_VER_10:
5292 case RTL_VER_11:
5293 case RTL_VER_12:
5294 case RTL_VER_13:
5295 case RTL_VER_15:
5296 if (enable) {
5297 r8156_eee_en(tp, true);
5298 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5299 } else {
5300 r8156_eee_en(tp, false);
5301 ocp_reg_write(tp, OCP_EEE_ADV, 0);
5302 }
5303 break;
5304 default:
5305 break;
5306 }
5307}
5308
5309static void r8152b_enable_fc(struct r8152 *tp)
5310{
5311 u16 anar;
5312
5313 anar = r8152_mdio_read(tp, MII_ADVERTISE);
5314 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
5315 r8152_mdio_write(tp, MII_ADVERTISE, anar);
5316
5317 tp->ups_info.flow_control = true;
5318}
5319
5320static void rtl8152_disable(struct r8152 *tp)
5321{
5322 r8152_aldps_en(tp, false);
5323 rtl_disable(tp);
5324 r8152_aldps_en(tp, true);
5325}
5326
5327static void r8152b_hw_phy_cfg(struct r8152 *tp)
5328{
5329 rtl8152_apply_firmware(tp, false);
5330 rtl_eee_enable(tp, tp->eee_en);
5331 r8152_aldps_en(tp, true);
5332 r8152b_enable_fc(tp);
5333
5334 set_bit(PHY_RESET, &tp->flags);
5335}
5336
5337static void wait_oob_link_list_ready(struct r8152 *tp)
5338{
5339 u32 ocp_data;
5340 int i;
5341
5342 for (i = 0; i < 1000; i++) {
5343 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5344 if (ocp_data & LINK_LIST_READY)
5345 break;
5346 usleep_range(1000, 2000);
5347 }
5348}
5349
5350static void r8156b_wait_loading_flash(struct r8152 *tp)
5351{
5352 if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&
5353 !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {
5354 int i;
5355
5356 for (i = 0; i < 100; i++) {
5357 if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)
5358 break;
5359 usleep_range(1000, 2000);
5360 }
5361 }
5362}
5363
5364static void r8152b_exit_oob(struct r8152 *tp)
5365{
5366 u32 ocp_data;
5367
5368 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5369 ocp_data &= ~RCR_ACPT_ALL;
5370 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5371
5372 rxdy_gated_en(tp, true);
5373 r8153_teredo_off(tp);
5374 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
5375 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
5376
5377 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5378 ocp_data &= ~NOW_IS_OOB;
5379 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5380
5381 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5382 ocp_data &= ~MCU_BORW_EN;
5383 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5384
5385 wait_oob_link_list_ready(tp);
5386
5387 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5388 ocp_data |= RE_INIT_LL;
5389 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5390
5391 wait_oob_link_list_ready(tp);
5392
5393 rtl8152_nic_reset(tp);
5394
5395 /* rx share fifo credit full threshold */
5396 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5397
5398 if (tp->udev->speed == USB_SPEED_FULL ||
5399 tp->udev->speed == USB_SPEED_LOW) {
5400 /* rx share fifo credit near full threshold */
5401 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5402 RXFIFO_THR2_FULL);
5403 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5404 RXFIFO_THR3_FULL);
5405 } else {
5406 /* rx share fifo credit near full threshold */
5407 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5408 RXFIFO_THR2_HIGH);
5409 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5410 RXFIFO_THR3_HIGH);
5411 }
5412
5413 /* TX share fifo free credit full threshold */
5414 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5415
5416 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
5417 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
5418 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
5419 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
5420
5421 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5422
5423 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5424
5425 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5426 ocp_data |= TCR0_AUTO_FIFO;
5427 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5428}
5429
5430static void r8152b_enter_oob(struct r8152 *tp)
5431{
5432 u32 ocp_data;
5433
5434 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5435 ocp_data &= ~NOW_IS_OOB;
5436 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5437
5438 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
5439 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
5440 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
5441
5442 rtl_disable(tp);
5443
5444 wait_oob_link_list_ready(tp);
5445
5446 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5447 ocp_data |= RE_INIT_LL;
5448 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5449
5450 wait_oob_link_list_ready(tp);
5451
5452 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5453
5454 rtl_rx_vlan_en(tp, true);
5455
5456 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5457 ocp_data |= ALDPS_PROXY_MODE;
5458 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
5459
5460 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5461 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5462 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5463
5464 rxdy_gated_en(tp, false);
5465
5466 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5467 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5468 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5469}
5470
5471static int r8153_pre_firmware_1(struct r8152 *tp)
5472{
5473 int i;
5474
5475 /* Wait till the WTD timer is ready. It would take at most 104 ms. */
5476 for (i = 0; i < 104; i++) {
5477 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
5478
5479 if (!(ocp_data & WTD1_EN))
5480 break;
5481 usleep_range(1000, 2000);
5482 }
5483
5484 return 0;
5485}
5486
5487static int r8153_post_firmware_1(struct r8152 *tp)
5488{
5489 /* set USB_BP_4 to support USB_SPEED_SUPER only */
5490 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
5491 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
5492
5493 /* reset UPHY timer to 36 ms */
5494 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5495
5496 return 0;
5497}
5498
5499static int r8153_pre_firmware_2(struct r8152 *tp)
5500{
5501 u32 ocp_data;
5502
5503 r8153_pre_firmware_1(tp);
5504
5505 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5506 ocp_data &= ~FW_FIX_SUSPEND;
5507 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5508
5509 return 0;
5510}
5511
5512static int r8153_post_firmware_2(struct r8152 *tp)
5513{
5514 u32 ocp_data;
5515
5516 /* enable bp0 if support USB_SPEED_SUPER only */
5517 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
5518 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5519 ocp_data |= BIT(0);
5520 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5521 }
5522
5523 /* reset UPHY timer to 36 ms */
5524 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5525
5526 /* enable U3P3 check, set the counter to 4 */
5527 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
5528
5529 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5530 ocp_data |= FW_FIX_SUSPEND;
5531 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5532
5533 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5534 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5535 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5536
5537 return 0;
5538}
5539
5540static int r8153_post_firmware_3(struct r8152 *tp)
5541{
5542 u32 ocp_data;
5543
5544 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5545 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5546 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5547
5548 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5549 ocp_data |= FW_IP_RESET_EN;
5550 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5551
5552 return 0;
5553}
5554
5555static int r8153b_pre_firmware_1(struct r8152 *tp)
5556{
5557 /* enable fc timer and set timer to 1 second. */
5558 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
5559 CTRL_TIMER_EN | (1000 / 8));
5560
5561 return 0;
5562}
5563
5564static int r8153b_post_firmware_1(struct r8152 *tp)
5565{
5566 u32 ocp_data;
5567
5568 /* enable bp0 for RTL8153-BND */
5569 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
5570 if (ocp_data & BND_MASK) {
5571 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5572 ocp_data |= BIT(0);
5573 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5574 }
5575
5576 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5577 ocp_data |= FLOW_CTRL_PATCH_OPT;
5578 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5579
5580 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5581 ocp_data |= FC_PATCH_TASK;
5582 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5583
5584 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5585 ocp_data |= FW_IP_RESET_EN;
5586 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5587
5588 return 0;
5589}
5590
5591static int r8153c_post_firmware_1(struct r8152 *tp)
5592{
5593 u32 ocp_data;
5594
5595 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5596 ocp_data |= FLOW_CTRL_PATCH_2;
5597 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5598
5599 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5600 ocp_data |= FC_PATCH_TASK;
5601 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5602
5603 return 0;
5604}
5605
5606static int r8156a_post_firmware_1(struct r8152 *tp)
5607{
5608 u32 ocp_data;
5609
5610 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5611 ocp_data |= FW_IP_RESET_EN;
5612 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5613
5614 /* Modify U3PHY parameter for compatibility issue */
5615 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e);
5616 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9);
5617
5618 return 0;
5619}
5620
5621static void r8153_aldps_en(struct r8152 *tp, bool enable)
5622{
5623 u16 data;
5624
5625 data = ocp_reg_read(tp, OCP_POWER_CFG);
5626 if (enable) {
5627 data |= EN_ALDPS;
5628 ocp_reg_write(tp, OCP_POWER_CFG, data);
5629 } else {
5630 int i;
5631
5632 data &= ~EN_ALDPS;
5633 ocp_reg_write(tp, OCP_POWER_CFG, data);
5634 for (i = 0; i < 20; i++) {
5635 usleep_range(1000, 2000);
5636 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
5637 break;
5638 }
5639 }
5640
5641 tp->ups_info.aldps = enable;
5642}
5643
5644static void r8153_hw_phy_cfg(struct r8152 *tp)
5645{
5646 u32 ocp_data;
5647 u16 data;
5648
5649 /* disable ALDPS before updating the PHY parameters */
5650 r8153_aldps_en(tp, false);
5651
5652 /* disable EEE before updating the PHY parameters */
5653 rtl_eee_enable(tp, false);
5654
5655 rtl8152_apply_firmware(tp, false);
5656
5657 if (tp->version == RTL_VER_03) {
5658 data = ocp_reg_read(tp, OCP_EEE_CFG);
5659 data &= ~CTAP_SHORT_EN;
5660 ocp_reg_write(tp, OCP_EEE_CFG, data);
5661 }
5662
5663 data = ocp_reg_read(tp, OCP_POWER_CFG);
5664 data |= EEE_CLKDIV_EN;
5665 ocp_reg_write(tp, OCP_POWER_CFG, data);
5666
5667 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5668 data |= EN_10M_BGOFF;
5669 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5670 data = ocp_reg_read(tp, OCP_POWER_CFG);
5671 data |= EN_10M_PLLOFF;
5672 ocp_reg_write(tp, OCP_POWER_CFG, data);
5673 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
5674
5675 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5676 ocp_data |= PFM_PWM_SWITCH;
5677 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5678
5679 /* Enable LPF corner auto tune */
5680 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
5681
5682 /* Adjust 10M Amplitude */
5683 sram_write(tp, SRAM_10M_AMP1, 0x00af);
5684 sram_write(tp, SRAM_10M_AMP2, 0x0208);
5685
5686 if (tp->eee_en)
5687 rtl_eee_enable(tp, true);
5688
5689 r8153_aldps_en(tp, true);
5690 r8152b_enable_fc(tp);
5691
5692 switch (tp->version) {
5693 case RTL_VER_03:
5694 case RTL_VER_04:
5695 break;
5696 case RTL_VER_05:
5697 case RTL_VER_06:
5698 default:
5699 r8153_u2p3en(tp, true);
5700 break;
5701 }
5702
5703 set_bit(PHY_RESET, &tp->flags);
5704}
5705
5706static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
5707{
5708 u32 ocp_data;
5709
5710 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
5711 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
5712 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
5713 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
5714
5715 return ocp_data;
5716}
5717
5718static void r8153b_hw_phy_cfg(struct r8152 *tp)
5719{
5720 u32 ocp_data;
5721 u16 data;
5722
5723 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
5724 if (ocp_data & PCUT_STATUS) {
5725 ocp_data &= ~PCUT_STATUS;
5726 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
5727 }
5728
5729 /* disable ALDPS before updating the PHY parameters */
5730 r8153_aldps_en(tp, false);
5731
5732 /* disable EEE before updating the PHY parameters */
5733 rtl_eee_enable(tp, false);
5734
5735 /* U1/U2/L1 idle timer. 500 us */
5736 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5737
5738 data = r8153_phy_status(tp, 0);
5739
5740 switch (data) {
5741 case PHY_STAT_PWRDN:
5742 case PHY_STAT_EXT_INIT:
5743 rtl8152_apply_firmware(tp, true);
5744
5745 data = r8152_mdio_read(tp, MII_BMCR);
5746 data &= ~BMCR_PDOWN;
5747 r8152_mdio_write(tp, MII_BMCR, data);
5748 break;
5749 case PHY_STAT_LAN_ON:
5750 default:
5751 rtl8152_apply_firmware(tp, false);
5752 break;
5753 }
5754
5755 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
5756
5757 data = sram_read(tp, SRAM_GREEN_CFG);
5758 data |= R_TUNE_EN;
5759 sram_write(tp, SRAM_GREEN_CFG, data);
5760 data = ocp_reg_read(tp, OCP_NCTL_CFG);
5761 data |= PGA_RETURN_EN;
5762 ocp_reg_write(tp, OCP_NCTL_CFG, data);
5763
5764 /* ADC Bias Calibration:
5765 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
5766 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
5767 * ADC ioffset.
5768 */
5769 ocp_data = r8152_efuse_read(tp, 0x7d);
5770 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
5771 if (data != 0xffff)
5772 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
5773
5774 /* ups mode tx-link-pulse timing adjustment:
5775 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
5776 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
5777 */
5778 ocp_data = ocp_reg_read(tp, 0xc426);
5779 ocp_data &= 0x3fff;
5780 if (ocp_data) {
5781 u32 swr_cnt_1ms_ini;
5782
5783 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
5784 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
5785 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
5786 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
5787 }
5788
5789 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5790 ocp_data |= PFM_PWM_SWITCH;
5791 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5792
5793 /* Advnace EEE */
5794 if (!rtl_phy_patch_request(tp, true, true)) {
5795 data = ocp_reg_read(tp, OCP_POWER_CFG);
5796 data |= EEE_CLKDIV_EN;
5797 ocp_reg_write(tp, OCP_POWER_CFG, data);
5798 tp->ups_info.eee_ckdiv = true;
5799
5800 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5801 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
5802 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5803 tp->ups_info.eee_cmod_lv = true;
5804 tp->ups_info._10m_ckdiv = true;
5805 tp->ups_info.eee_plloff_giga = true;
5806
5807 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
5808 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
5809 tp->ups_info._250m_ckdiv = true;
5810
5811 rtl_phy_patch_request(tp, false, true);
5812 }
5813
5814 if (tp->eee_en)
5815 rtl_eee_enable(tp, true);
5816
5817 r8153_aldps_en(tp, true);
5818 r8152b_enable_fc(tp);
5819
5820 set_bit(PHY_RESET, &tp->flags);
5821}
5822
5823static void r8153c_hw_phy_cfg(struct r8152 *tp)
5824{
5825 r8153b_hw_phy_cfg(tp);
5826
5827 tp->ups_info.r_tune = true;
5828}
5829
5830static void rtl8153_change_mtu(struct r8152 *tp)
5831{
5832 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
5833 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
5834}
5835
5836static void r8153_first_init(struct r8152 *tp)
5837{
5838 u32 ocp_data;
5839
5840 rxdy_gated_en(tp, true);
5841 r8153_teredo_off(tp);
5842
5843 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5844 ocp_data &= ~RCR_ACPT_ALL;
5845 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5846
5847 rtl8152_nic_reset(tp);
5848 rtl_reset_bmu(tp);
5849
5850 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5851 ocp_data &= ~NOW_IS_OOB;
5852 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5853
5854 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5855 ocp_data &= ~MCU_BORW_EN;
5856 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5857
5858 wait_oob_link_list_ready(tp);
5859
5860 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5861 ocp_data |= RE_INIT_LL;
5862 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5863
5864 wait_oob_link_list_ready(tp);
5865
5866 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5867
5868 rtl8153_change_mtu(tp);
5869
5870 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5871 ocp_data |= TCR0_AUTO_FIFO;
5872 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5873
5874 rtl8152_nic_reset(tp);
5875
5876 /* rx share fifo credit full threshold */
5877 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5878 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
5879 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
5880 /* TX share fifo free credit full threshold */
5881 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5882}
5883
5884static void r8153_enter_oob(struct r8152 *tp)
5885{
5886 u32 ocp_data;
5887
5888 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5889 ocp_data &= ~NOW_IS_OOB;
5890 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5891
5892 rtl_disable(tp);
5893 rtl_reset_bmu(tp);
5894
5895 wait_oob_link_list_ready(tp);
5896
5897 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5898 ocp_data |= RE_INIT_LL;
5899 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5900
5901 wait_oob_link_list_ready(tp);
5902
5903 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
5904
5905 switch (tp->version) {
5906 case RTL_VER_03:
5907 case RTL_VER_04:
5908 case RTL_VER_05:
5909 case RTL_VER_06:
5910 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
5911 ocp_data &= ~TEREDO_WAKE_MASK;
5912 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
5913 break;
5914
5915 case RTL_VER_08:
5916 case RTL_VER_09:
5917 case RTL_VER_14:
5918 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
5919 * type. Set it to zero. bits[7:0] are the W1C bits about
5920 * the events. Set them to all 1 to clear them.
5921 */
5922 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
5923 break;
5924
5925 default:
5926 break;
5927 }
5928
5929 rtl_rx_vlan_en(tp, true);
5930
5931 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5932 ocp_data |= ALDPS_PROXY_MODE;
5933 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
5934
5935 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5936 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5937 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5938
5939 rxdy_gated_en(tp, false);
5940
5941 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5942 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5943 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5944}
5945
5946static void rtl8153_disable(struct r8152 *tp)
5947{
5948 r8153_aldps_en(tp, false);
5949 rtl_disable(tp);
5950 rtl_reset_bmu(tp);
5951 r8153_aldps_en(tp, true);
5952}
5953
5954static int rtl8156_enable(struct r8152 *tp)
5955{
5956 u32 ocp_data;
5957 u16 speed;
5958
5959 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5960 return -ENODEV;
5961
5962 set_tx_qlen(tp);
5963 rtl_set_eee_plus(tp);
5964 r8153_set_rx_early_timeout(tp);
5965 r8153_set_rx_early_size(tp);
5966
5967 speed = rtl8152_get_speed(tp);
5968 rtl_set_ifg(tp, speed);
5969
5970 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
5971 if (speed & _2500bps)
5972 ocp_data &= ~IDLE_SPDWN_EN;
5973 else
5974 ocp_data |= IDLE_SPDWN_EN;
5975 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
5976
5977 if (speed & _1000bps)
5978 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11);
5979 else if (speed & _500bps)
5980 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d);
5981
5982 if (tp->udev->speed == USB_SPEED_HIGH) {
5983 /* USB 0xb45e[3:0] l1_nyet_hird */
5984 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
5985 ocp_data &= ~0xf;
5986 if (is_flow_control(speed))
5987 ocp_data |= 0xf;
5988 else
5989 ocp_data |= 0x1;
5990 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
5991 }
5992
5993 return rtl_enable(tp);
5994}
5995
5996static int rtl8156b_enable(struct r8152 *tp)
5997{
5998 u32 ocp_data;
5999 u16 speed;
6000
6001 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6002 return -ENODEV;
6003
6004 set_tx_qlen(tp);
6005 rtl_set_eee_plus(tp);
6006
6007 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);
6008 ocp_data &= ~RX_AGGR_NUM_MASK;
6009 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data);
6010
6011 r8153_set_rx_early_timeout(tp);
6012 r8153_set_rx_early_size(tp);
6013
6014 speed = rtl8152_get_speed(tp);
6015 rtl_set_ifg(tp, speed);
6016
6017 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6018 if (speed & _2500bps)
6019 ocp_data &= ~IDLE_SPDWN_EN;
6020 else
6021 ocp_data |= IDLE_SPDWN_EN;
6022 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
6023
6024 if (tp->udev->speed == USB_SPEED_HIGH) {
6025 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6026 ocp_data &= ~0xf;
6027 if (is_flow_control(speed))
6028 ocp_data |= 0xf;
6029 else
6030 ocp_data |= 0x1;
6031 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
6032 }
6033
6034 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6035 ocp_data &= ~FC_PATCH_TASK;
6036 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6037 usleep_range(1000, 2000);
6038 ocp_data |= FC_PATCH_TASK;
6039 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6040
6041 return rtl_enable(tp);
6042}
6043
6044static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
6045 u32 advertising)
6046{
6047 u16 bmcr;
6048 int ret = 0;
6049
6050 if (autoneg == AUTONEG_DISABLE) {
6051 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
6052 return -EINVAL;
6053
6054 switch (speed) {
6055 case SPEED_10:
6056 bmcr = BMCR_SPEED10;
6057 if (duplex == DUPLEX_FULL) {
6058 bmcr |= BMCR_FULLDPLX;
6059 tp->ups_info.speed_duplex = FORCE_10M_FULL;
6060 } else {
6061 tp->ups_info.speed_duplex = FORCE_10M_HALF;
6062 }
6063 break;
6064 case SPEED_100:
6065 bmcr = BMCR_SPEED100;
6066 if (duplex == DUPLEX_FULL) {
6067 bmcr |= BMCR_FULLDPLX;
6068 tp->ups_info.speed_duplex = FORCE_100M_FULL;
6069 } else {
6070 tp->ups_info.speed_duplex = FORCE_100M_HALF;
6071 }
6072 break;
6073 case SPEED_1000:
6074 if (tp->mii.supports_gmii) {
6075 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
6076 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6077 break;
6078 }
6079 fallthrough;
6080 default:
6081 ret = -EINVAL;
6082 goto out;
6083 }
6084
6085 if (duplex == DUPLEX_FULL)
6086 tp->mii.full_duplex = 1;
6087 else
6088 tp->mii.full_duplex = 0;
6089
6090 tp->mii.force_media = 1;
6091 } else {
6092 u16 orig, new1;
6093 u32 support;
6094
6095 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6096 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6097
6098 if (tp->mii.supports_gmii) {
6099 support |= RTL_ADVERTISED_1000_FULL;
6100
6101 if (tp->support_2500full)
6102 support |= RTL_ADVERTISED_2500_FULL;
6103 }
6104
6105 if (!(advertising & support))
6106 return -EINVAL;
6107
6108 orig = r8152_mdio_read(tp, MII_ADVERTISE);
6109 new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
6110 ADVERTISE_100HALF | ADVERTISE_100FULL);
6111 if (advertising & RTL_ADVERTISED_10_HALF) {
6112 new1 |= ADVERTISE_10HALF;
6113 tp->ups_info.speed_duplex = NWAY_10M_HALF;
6114 }
6115 if (advertising & RTL_ADVERTISED_10_FULL) {
6116 new1 |= ADVERTISE_10FULL;
6117 tp->ups_info.speed_duplex = NWAY_10M_FULL;
6118 }
6119
6120 if (advertising & RTL_ADVERTISED_100_HALF) {
6121 new1 |= ADVERTISE_100HALF;
6122 tp->ups_info.speed_duplex = NWAY_100M_HALF;
6123 }
6124 if (advertising & RTL_ADVERTISED_100_FULL) {
6125 new1 |= ADVERTISE_100FULL;
6126 tp->ups_info.speed_duplex = NWAY_100M_FULL;
6127 }
6128
6129 if (orig != new1) {
6130 r8152_mdio_write(tp, MII_ADVERTISE, new1);
6131 tp->mii.advertising = new1;
6132 }
6133
6134 if (tp->mii.supports_gmii) {
6135 orig = r8152_mdio_read(tp, MII_CTRL1000);
6136 new1 = orig & ~(ADVERTISE_1000FULL |
6137 ADVERTISE_1000HALF);
6138
6139 if (advertising & RTL_ADVERTISED_1000_FULL) {
6140 new1 |= ADVERTISE_1000FULL;
6141 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6142 }
6143
6144 if (orig != new1)
6145 r8152_mdio_write(tp, MII_CTRL1000, new1);
6146 }
6147
6148 if (tp->support_2500full) {
6149 orig = ocp_reg_read(tp, OCP_10GBT_CTRL);
6150 new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;
6151
6152 if (advertising & RTL_ADVERTISED_2500_FULL) {
6153 new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;
6154 tp->ups_info.speed_duplex = NWAY_2500M_FULL;
6155 }
6156
6157 if (orig != new1)
6158 ocp_reg_write(tp, OCP_10GBT_CTRL, new1);
6159 }
6160
6161 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
6162
6163 tp->mii.force_media = 0;
6164 }
6165
6166 if (test_and_clear_bit(PHY_RESET, &tp->flags))
6167 bmcr |= BMCR_RESET;
6168
6169 r8152_mdio_write(tp, MII_BMCR, bmcr);
6170
6171 if (bmcr & BMCR_RESET) {
6172 int i;
6173
6174 for (i = 0; i < 50; i++) {
6175 msleep(20);
6176 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
6177 break;
6178 }
6179 }
6180
6181out:
6182 return ret;
6183}
6184
6185static void rtl8152_up(struct r8152 *tp)
6186{
6187 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6188 return;
6189
6190 r8152_aldps_en(tp, false);
6191 r8152b_exit_oob(tp);
6192 r8152_aldps_en(tp, true);
6193}
6194
6195static void rtl8152_down(struct r8152 *tp)
6196{
6197 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6198 rtl_drop_queued_tx(tp);
6199 return;
6200 }
6201
6202 r8152_power_cut_en(tp, false);
6203 r8152_aldps_en(tp, false);
6204 r8152b_enter_oob(tp);
6205 r8152_aldps_en(tp, true);
6206}
6207
6208static void rtl8153_up(struct r8152 *tp)
6209{
6210 u32 ocp_data;
6211
6212 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6213 return;
6214
6215 r8153_u1u2en(tp, false);
6216 r8153_u2p3en(tp, false);
6217 r8153_aldps_en(tp, false);
6218 r8153_first_init(tp);
6219
6220 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6221 ocp_data |= LANWAKE_CLR_EN;
6222 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6223
6224 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6225 ocp_data &= ~LANWAKE_PIN;
6226 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
6227
6228 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
6229 ocp_data &= ~DELAY_PHY_PWR_CHG;
6230 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
6231
6232 r8153_aldps_en(tp, true);
6233
6234 switch (tp->version) {
6235 case RTL_VER_03:
6236 case RTL_VER_04:
6237 break;
6238 case RTL_VER_05:
6239 case RTL_VER_06:
6240 default:
6241 r8153_u2p3en(tp, true);
6242 break;
6243 }
6244
6245 r8153_u1u2en(tp, true);
6246}
6247
6248static void rtl8153_down(struct r8152 *tp)
6249{
6250 u32 ocp_data;
6251
6252 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6253 rtl_drop_queued_tx(tp);
6254 return;
6255 }
6256
6257 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6258 ocp_data &= ~LANWAKE_CLR_EN;
6259 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6260
6261 r8153_u1u2en(tp, false);
6262 r8153_u2p3en(tp, false);
6263 r8153_power_cut_en(tp, false);
6264 r8153_aldps_en(tp, false);
6265 r8153_enter_oob(tp);
6266 r8153_aldps_en(tp, true);
6267}
6268
6269static void rtl8153b_up(struct r8152 *tp)
6270{
6271 u32 ocp_data;
6272
6273 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6274 return;
6275
6276 r8153b_u1u2en(tp, false);
6277 r8153_u2p3en(tp, false);
6278 r8153_aldps_en(tp, false);
6279
6280 r8153_first_init(tp);
6281 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6282
6283 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6284 ocp_data &= ~PLA_MCU_SPDWN_EN;
6285 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6286
6287 r8153_aldps_en(tp, true);
6288
6289 if (tp->udev->speed >= USB_SPEED_SUPER)
6290 r8153b_u1u2en(tp, true);
6291}
6292
6293static void rtl8153b_down(struct r8152 *tp)
6294{
6295 u32 ocp_data;
6296
6297 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6298 rtl_drop_queued_tx(tp);
6299 return;
6300 }
6301
6302 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6303 ocp_data |= PLA_MCU_SPDWN_EN;
6304 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6305
6306 r8153b_u1u2en(tp, false);
6307 r8153_u2p3en(tp, false);
6308 r8153b_power_cut_en(tp, false);
6309 r8153_aldps_en(tp, false);
6310 r8153_enter_oob(tp);
6311 r8153_aldps_en(tp, true);
6312}
6313
6314static void rtl8153c_change_mtu(struct r8152 *tp)
6315{
6316 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
6317 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64);
6318
6319 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6320
6321 /* Adjust the tx fifo free credit full threshold, otherwise
6322 * the fifo would be too small to send a jumbo frame packet.
6323 */
6324 if (tp->netdev->mtu < 8000)
6325 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8);
6326 else
6327 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8);
6328}
6329
6330static void rtl8153c_up(struct r8152 *tp)
6331{
6332 u32 ocp_data;
6333
6334 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6335 return;
6336
6337 r8153b_u1u2en(tp, false);
6338 r8153_u2p3en(tp, false);
6339 r8153_aldps_en(tp, false);
6340
6341 rxdy_gated_en(tp, true);
6342 r8153_teredo_off(tp);
6343
6344 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6345 ocp_data &= ~RCR_ACPT_ALL;
6346 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6347
6348 rtl8152_nic_reset(tp);
6349 rtl_reset_bmu(tp);
6350
6351 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6352 ocp_data &= ~NOW_IS_OOB;
6353 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6354
6355 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6356 ocp_data &= ~MCU_BORW_EN;
6357 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6358
6359 wait_oob_link_list_ready(tp);
6360
6361 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6362 ocp_data |= RE_INIT_LL;
6363 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6364
6365 wait_oob_link_list_ready(tp);
6366
6367 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6368
6369 rtl8153c_change_mtu(tp);
6370
6371 rtl8152_nic_reset(tp);
6372
6373 /* rx share fifo credit full threshold */
6374 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02);
6375 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08);
6376 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
6377 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
6378
6379 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6380
6381 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
6382
6383 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
6384 ocp_data |= BIT(8);
6385 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
6386
6387 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
6388
6389 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6390 ocp_data &= ~PLA_MCU_SPDWN_EN;
6391 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6392
6393 r8153_aldps_en(tp, true);
6394 r8153b_u1u2en(tp, true);
6395}
6396
6397static inline u32 fc_pause_on_auto(struct r8152 *tp)
6398{
6399 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);
6400}
6401
6402static inline u32 fc_pause_off_auto(struct r8152 *tp)
6403{
6404 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);
6405}
6406
6407static void r8156_fc_parameter(struct r8152 *tp)
6408{
6409 u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);
6410 u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);
6411
6412 switch (tp->version) {
6413 case RTL_VER_10:
6414 case RTL_VER_11:
6415 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 8);
6416 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 8);
6417 break;
6418 case RTL_VER_12:
6419 case RTL_VER_13:
6420 case RTL_VER_15:
6421 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16);
6422 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16);
6423 break;
6424 default:
6425 break;
6426 }
6427}
6428
6429static void rtl8156_change_mtu(struct r8152 *tp)
6430{
6431 u32 rx_max_size = mtu_to_size(tp->netdev->mtu);
6432
6433 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size);
6434 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
6435 r8156_fc_parameter(tp);
6436
6437 /* TX share fifo free credit full threshold */
6438 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6439 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,
6440 ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);
6441}
6442
6443static void rtl8156_up(struct r8152 *tp)
6444{
6445 u32 ocp_data;
6446
6447 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6448 return;
6449
6450 r8153b_u1u2en(tp, false);
6451 r8153_u2p3en(tp, false);
6452 r8153_aldps_en(tp, false);
6453
6454 rxdy_gated_en(tp, true);
6455 r8153_teredo_off(tp);
6456
6457 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6458 ocp_data &= ~RCR_ACPT_ALL;
6459 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6460
6461 rtl8152_nic_reset(tp);
6462 rtl_reset_bmu(tp);
6463
6464 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6465 ocp_data &= ~NOW_IS_OOB;
6466 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6467
6468 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6469 ocp_data &= ~MCU_BORW_EN;
6470 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6471
6472 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6473
6474 rtl8156_change_mtu(tp);
6475
6476 switch (tp->version) {
6477 case RTL_TEST_01:
6478 case RTL_VER_10:
6479 case RTL_VER_11:
6480 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
6481 ocp_data |= ACT_ODMA;
6482 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
6483 break;
6484 default:
6485 break;
6486 }
6487
6488 /* share FIFO settings */
6489 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);
6490 ocp_data &= ~RXFIFO_FULL_MASK;
6491 ocp_data |= 0x08;
6492 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data);
6493
6494 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6495 ocp_data &= ~PLA_MCU_SPDWN_EN;
6496 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6497
6498 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);
6499 ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);
6500 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data);
6501
6502 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400);
6503
6504 if (tp->saved_wolopts != __rtl_get_wol(tp)) {
6505 netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n");
6506 __rtl_set_wol(tp, tp->saved_wolopts);
6507 }
6508
6509 r8153_aldps_en(tp, true);
6510 r8153_u2p3en(tp, true);
6511
6512 if (tp->udev->speed >= USB_SPEED_SUPER)
6513 r8153b_u1u2en(tp, true);
6514}
6515
6516static void rtl8156_down(struct r8152 *tp)
6517{
6518 u32 ocp_data;
6519
6520 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6521 rtl_drop_queued_tx(tp);
6522 return;
6523 }
6524
6525 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6526 ocp_data |= PLA_MCU_SPDWN_EN;
6527 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6528
6529 r8153b_u1u2en(tp, false);
6530 r8153_u2p3en(tp, false);
6531 r8153b_power_cut_en(tp, false);
6532 r8153_aldps_en(tp, false);
6533
6534 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6535 ocp_data &= ~NOW_IS_OOB;
6536 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6537
6538 rtl_disable(tp);
6539 rtl_reset_bmu(tp);
6540
6541 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
6542 * type. Set it to zero. bits[7:0] are the W1C bits about
6543 * the events. Set them to all 1 to clear them.
6544 */
6545 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
6546
6547 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6548 ocp_data |= NOW_IS_OOB;
6549 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6550
6551 rtl_rx_vlan_en(tp, true);
6552 rxdy_gated_en(tp, false);
6553
6554 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6555 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6556 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6557
6558 r8153_aldps_en(tp, true);
6559}
6560
6561static bool rtl8152_in_nway(struct r8152 *tp)
6562{
6563 u16 nway_state;
6564
6565 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
6566 tp->ocp_base = 0x2000;
6567 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
6568 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
6569
6570 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
6571 if (nway_state & 0xc000)
6572 return false;
6573 else
6574 return true;
6575}
6576
6577static bool rtl8153_in_nway(struct r8152 *tp)
6578{
6579 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
6580
6581 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
6582 return false;
6583 else
6584 return true;
6585}
6586
6587static void set_carrier(struct r8152 *tp)
6588{
6589 struct net_device *netdev = tp->netdev;
6590 struct napi_struct *napi = &tp->napi;
6591 u16 speed;
6592
6593 speed = rtl8152_get_speed(tp);
6594
6595 if (speed & LINK_STATUS) {
6596 if (!netif_carrier_ok(netdev)) {
6597 tp->rtl_ops.enable(tp);
6598 netif_stop_queue(netdev);
6599 napi_disable(napi);
6600 netif_carrier_on(netdev);
6601 rtl_start_rx(tp);
6602 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6603 _rtl8152_set_rx_mode(netdev);
6604 napi_enable(napi);
6605 netif_wake_queue(netdev);
6606 netif_info(tp, link, netdev, "carrier on\n");
6607 } else if (netif_queue_stopped(netdev) &&
6608 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
6609 netif_wake_queue(netdev);
6610 }
6611 } else {
6612 if (netif_carrier_ok(netdev)) {
6613 netif_carrier_off(netdev);
6614 tasklet_disable(&tp->tx_tl);
6615 napi_disable(napi);
6616 tp->rtl_ops.disable(tp);
6617 napi_enable(napi);
6618 tasklet_enable(&tp->tx_tl);
6619 netif_info(tp, link, netdev, "carrier off\n");
6620 }
6621 }
6622}
6623
6624static void rtl_work_func_t(struct work_struct *work)
6625{
6626 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
6627
6628 /* If the device is unplugged or !netif_running(), the workqueue
6629 * doesn't need to wake the device, and could return directly.
6630 */
6631 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
6632 return;
6633
6634 if (usb_autopm_get_interface(tp->intf) < 0)
6635 return;
6636
6637 if (!test_bit(WORK_ENABLE, &tp->flags))
6638 goto out1;
6639
6640 if (!mutex_trylock(&tp->control)) {
6641 schedule_delayed_work(&tp->schedule, 0);
6642 goto out1;
6643 }
6644
6645 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
6646 set_carrier(tp);
6647
6648 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
6649 _rtl8152_set_rx_mode(tp->netdev);
6650
6651 /* don't schedule tasket before linking */
6652 if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
6653 netif_carrier_ok(tp->netdev))
6654 tasklet_schedule(&tp->tx_tl);
6655
6656 if (test_and_clear_bit(RX_EPROTO, &tp->flags) &&
6657 !list_empty(&tp->rx_done))
6658 napi_schedule(&tp->napi);
6659
6660 mutex_unlock(&tp->control);
6661
6662out1:
6663 usb_autopm_put_interface(tp->intf);
6664}
6665
6666static void rtl_hw_phy_work_func_t(struct work_struct *work)
6667{
6668 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
6669
6670 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6671 return;
6672
6673 if (usb_autopm_get_interface(tp->intf) < 0)
6674 return;
6675
6676 mutex_lock(&tp->control);
6677
6678 if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
6679 tp->rtl_fw.retry = false;
6680 tp->rtl_fw.fw = NULL;
6681
6682 /* Delay execution in case request_firmware() is not ready yet.
6683 */
6684 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
6685 goto ignore_once;
6686 }
6687
6688 tp->rtl_ops.hw_phy_cfg(tp);
6689
6690 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
6691 tp->advertising);
6692
6693ignore_once:
6694 mutex_unlock(&tp->control);
6695
6696 usb_autopm_put_interface(tp->intf);
6697}
6698
6699#ifdef CONFIG_PM_SLEEP
6700static int rtl_notifier(struct notifier_block *nb, unsigned long action,
6701 void *data)
6702{
6703 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
6704
6705 switch (action) {
6706 case PM_HIBERNATION_PREPARE:
6707 case PM_SUSPEND_PREPARE:
6708 usb_autopm_get_interface(tp->intf);
6709 break;
6710
6711 case PM_POST_HIBERNATION:
6712 case PM_POST_SUSPEND:
6713 usb_autopm_put_interface(tp->intf);
6714 break;
6715
6716 case PM_POST_RESTORE:
6717 case PM_RESTORE_PREPARE:
6718 default:
6719 break;
6720 }
6721
6722 return NOTIFY_DONE;
6723}
6724#endif
6725
6726static int rtl8152_open(struct net_device *netdev)
6727{
6728 struct r8152 *tp = netdev_priv(netdev);
6729 int res = 0;
6730
6731 if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
6732 cancel_delayed_work_sync(&tp->hw_phy_work);
6733 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
6734 }
6735
6736 res = alloc_all_mem(tp);
6737 if (res)
6738 goto out;
6739
6740 res = usb_autopm_get_interface(tp->intf);
6741 if (res < 0)
6742 goto out_free;
6743
6744 mutex_lock(&tp->control);
6745
6746 tp->rtl_ops.up(tp);
6747
6748 netif_carrier_off(netdev);
6749 netif_start_queue(netdev);
6750 set_bit(WORK_ENABLE, &tp->flags);
6751
6752 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
6753 if (res) {
6754 if (res == -ENODEV)
6755 netif_device_detach(tp->netdev);
6756 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
6757 res);
6758 goto out_unlock;
6759 }
6760 napi_enable(&tp->napi);
6761 tasklet_enable(&tp->tx_tl);
6762
6763 mutex_unlock(&tp->control);
6764
6765 usb_autopm_put_interface(tp->intf);
6766#ifdef CONFIG_PM_SLEEP
6767 tp->pm_notifier.notifier_call = rtl_notifier;
6768 register_pm_notifier(&tp->pm_notifier);
6769#endif
6770 return 0;
6771
6772out_unlock:
6773 mutex_unlock(&tp->control);
6774 usb_autopm_put_interface(tp->intf);
6775out_free:
6776 free_all_mem(tp);
6777out:
6778 return res;
6779}
6780
6781static int rtl8152_close(struct net_device *netdev)
6782{
6783 struct r8152 *tp = netdev_priv(netdev);
6784 int res = 0;
6785
6786#ifdef CONFIG_PM_SLEEP
6787 unregister_pm_notifier(&tp->pm_notifier);
6788#endif
6789 tasklet_disable(&tp->tx_tl);
6790 clear_bit(WORK_ENABLE, &tp->flags);
6791 usb_kill_urb(tp->intr_urb);
6792 cancel_delayed_work_sync(&tp->schedule);
6793 napi_disable(&tp->napi);
6794 netif_stop_queue(netdev);
6795
6796 res = usb_autopm_get_interface(tp->intf);
6797 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
6798 rtl_drop_queued_tx(tp);
6799 rtl_stop_rx(tp);
6800 } else {
6801 mutex_lock(&tp->control);
6802
6803 tp->rtl_ops.down(tp);
6804
6805 mutex_unlock(&tp->control);
6806 }
6807
6808 if (!res)
6809 usb_autopm_put_interface(tp->intf);
6810
6811 free_all_mem(tp);
6812
6813 return res;
6814}
6815
6816static void rtl_tally_reset(struct r8152 *tp)
6817{
6818 u32 ocp_data;
6819
6820 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
6821 ocp_data |= TALLY_RESET;
6822 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
6823}
6824
6825static void r8152b_init(struct r8152 *tp)
6826{
6827 u32 ocp_data;
6828 u16 data;
6829
6830 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6831 return;
6832
6833 data = r8152_mdio_read(tp, MII_BMCR);
6834 if (data & BMCR_PDOWN) {
6835 data &= ~BMCR_PDOWN;
6836 r8152_mdio_write(tp, MII_BMCR, data);
6837 }
6838
6839 r8152_aldps_en(tp, false);
6840
6841 if (tp->version == RTL_VER_01) {
6842 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
6843 ocp_data &= ~LED_MODE_MASK;
6844 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
6845 }
6846
6847 r8152_power_cut_en(tp, false);
6848
6849 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
6850 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
6851 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
6852 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
6853 ocp_data &= ~MCU_CLK_RATIO_MASK;
6854 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
6855 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
6856 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
6857 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
6858 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
6859
6860 rtl_tally_reset(tp);
6861
6862 /* enable rx aggregation */
6863 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
6864 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
6865 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
6866}
6867
6868static void r8153_init(struct r8152 *tp)
6869{
6870 u32 ocp_data;
6871 u16 data;
6872 int i;
6873
6874 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6875 return;
6876
6877 r8153_u1u2en(tp, false);
6878
6879 for (i = 0; i < 500; i++) {
6880 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
6881 AUTOLOAD_DONE)
6882 break;
6883
6884 msleep(20);
6885 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6886 break;
6887 }
6888
6889 data = r8153_phy_status(tp, 0);
6890
6891 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
6892 tp->version == RTL_VER_05)
6893 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
6894
6895 data = r8152_mdio_read(tp, MII_BMCR);
6896 if (data & BMCR_PDOWN) {
6897 data &= ~BMCR_PDOWN;
6898 r8152_mdio_write(tp, MII_BMCR, data);
6899 }
6900
6901 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
6902
6903 r8153_u2p3en(tp, false);
6904
6905 if (tp->version == RTL_VER_04) {
6906 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
6907 ocp_data &= ~pwd_dn_scale_mask;
6908 ocp_data |= pwd_dn_scale(96);
6909 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
6910
6911 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
6912 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
6913 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
6914 } else if (tp->version == RTL_VER_05) {
6915 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
6916 ocp_data &= ~ECM_ALDPS;
6917 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
6918
6919 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
6920 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
6921 ocp_data &= ~DYNAMIC_BURST;
6922 else
6923 ocp_data |= DYNAMIC_BURST;
6924 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
6925 } else if (tp->version == RTL_VER_06) {
6926 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
6927 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
6928 ocp_data &= ~DYNAMIC_BURST;
6929 else
6930 ocp_data |= DYNAMIC_BURST;
6931 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
6932
6933 r8153_queue_wake(tp, false);
6934
6935 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
6936 if (rtl8152_get_speed(tp) & LINK_STATUS)
6937 ocp_data |= CUR_LINK_OK;
6938 else
6939 ocp_data &= ~CUR_LINK_OK;
6940 ocp_data |= POLL_LINK_CHG;
6941 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
6942 }
6943
6944 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
6945 ocp_data |= EP4_FULL_FC;
6946 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
6947
6948 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
6949 ocp_data &= ~TIMER11_EN;
6950 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
6951
6952 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
6953 ocp_data &= ~LED_MODE_MASK;
6954 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
6955
6956 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
6957 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
6958 ocp_data |= LPM_TIMER_500MS;
6959 else
6960 ocp_data |= LPM_TIMER_500US;
6961 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
6962
6963 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
6964 ocp_data &= ~SEN_VAL_MASK;
6965 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
6966 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
6967
6968 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
6969
6970 r8153_power_cut_en(tp, false);
6971 rtl_runtime_suspend_enable(tp, false);
6972 r8153_mac_clk_speed_down(tp, false);
6973 r8153_u1u2en(tp, true);
6974 usb_enable_lpm(tp->udev);
6975
6976 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6977 ocp_data |= LANWAKE_CLR_EN;
6978 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6979
6980 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6981 ocp_data &= ~LANWAKE_PIN;
6982 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
6983
6984 /* rx aggregation */
6985 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
6986 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
6987 if (tp->dell_tb_rx_agg_bug)
6988 ocp_data |= RX_AGG_DISABLE;
6989
6990 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
6991
6992 rtl_tally_reset(tp);
6993
6994 switch (tp->udev->speed) {
6995 case USB_SPEED_SUPER:
6996 case USB_SPEED_SUPER_PLUS:
6997 tp->coalesce = COALESCE_SUPER;
6998 break;
6999 case USB_SPEED_HIGH:
7000 tp->coalesce = COALESCE_HIGH;
7001 break;
7002 default:
7003 tp->coalesce = COALESCE_SLOW;
7004 break;
7005 }
7006}
7007
7008static void r8153b_init(struct r8152 *tp)
7009{
7010 u32 ocp_data;
7011 u16 data;
7012 int i;
7013
7014 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7015 return;
7016
7017 r8153b_u1u2en(tp, false);
7018
7019 for (i = 0; i < 500; i++) {
7020 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7021 AUTOLOAD_DONE)
7022 break;
7023
7024 msleep(20);
7025 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7026 break;
7027 }
7028
7029 data = r8153_phy_status(tp, 0);
7030
7031 data = r8152_mdio_read(tp, MII_BMCR);
7032 if (data & BMCR_PDOWN) {
7033 data &= ~BMCR_PDOWN;
7034 r8152_mdio_write(tp, MII_BMCR, data);
7035 }
7036
7037 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7038
7039 r8153_u2p3en(tp, false);
7040
7041 /* MSC timer = 0xfff * 8ms = 32760 ms */
7042 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7043
7044 r8153b_power_cut_en(tp, false);
7045 r8153b_ups_en(tp, false);
7046 r8153_queue_wake(tp, false);
7047 rtl_runtime_suspend_enable(tp, false);
7048
7049 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7050 if (rtl8152_get_speed(tp) & LINK_STATUS)
7051 ocp_data |= CUR_LINK_OK;
7052 else
7053 ocp_data &= ~CUR_LINK_OK;
7054 ocp_data |= POLL_LINK_CHG;
7055 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7056
7057 if (tp->udev->speed >= USB_SPEED_SUPER)
7058 r8153b_u1u2en(tp, true);
7059
7060 usb_enable_lpm(tp->udev);
7061
7062 /* MAC clock speed down */
7063 r8153_mac_clk_speed_down(tp, true);
7064
7065 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7066 ocp_data &= ~PLA_MCU_SPDWN_EN;
7067 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
7068
7069 if (tp->version == RTL_VER_09) {
7070 /* Disable Test IO for 32QFN */
7071 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
7072 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7073 ocp_data |= TEST_IO_OFF;
7074 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7075 }
7076 }
7077
7078 set_bit(GREEN_ETHERNET, &tp->flags);
7079
7080 /* rx aggregation */
7081 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7082 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7083 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7084
7085 rtl_tally_reset(tp);
7086
7087 tp->coalesce = 15000; /* 15 us */
7088}
7089
7090static void r8153c_init(struct r8152 *tp)
7091{
7092 u32 ocp_data;
7093 u16 data;
7094 int i;
7095
7096 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7097 return;
7098
7099 r8153b_u1u2en(tp, false);
7100
7101 /* Disable spi_en */
7102 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
7103 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
7104 ocp_data &= ~BIT(3);
7105 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
7106 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0);
7107 ocp_data |= BIT(1);
7108 ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data);
7109
7110 for (i = 0; i < 500; i++) {
7111 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7112 AUTOLOAD_DONE)
7113 break;
7114
7115 msleep(20);
7116 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7117 return;
7118 }
7119
7120 data = r8153_phy_status(tp, 0);
7121
7122 data = r8152_mdio_read(tp, MII_BMCR);
7123 if (data & BMCR_PDOWN) {
7124 data &= ~BMCR_PDOWN;
7125 r8152_mdio_write(tp, MII_BMCR, data);
7126 }
7127
7128 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7129
7130 r8153_u2p3en(tp, false);
7131
7132 /* MSC timer = 0xfff * 8ms = 32760 ms */
7133 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7134
7135 r8153b_power_cut_en(tp, false);
7136 r8153c_ups_en(tp, false);
7137 r8153_queue_wake(tp, false);
7138 rtl_runtime_suspend_enable(tp, false);
7139
7140 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7141 if (rtl8152_get_speed(tp) & LINK_STATUS)
7142 ocp_data |= CUR_LINK_OK;
7143 else
7144 ocp_data &= ~CUR_LINK_OK;
7145
7146 ocp_data |= POLL_LINK_CHG;
7147 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7148
7149 r8153b_u1u2en(tp, true);
7150
7151 usb_enable_lpm(tp->udev);
7152
7153 /* MAC clock speed down */
7154 r8153_mac_clk_speed_down(tp, true);
7155
7156 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
7157 ocp_data &= ~BIT(7);
7158 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
7159
7160 set_bit(GREEN_ETHERNET, &tp->flags);
7161
7162 /* rx aggregation */
7163 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7164 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7165 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7166
7167 rtl_tally_reset(tp);
7168
7169 tp->coalesce = 15000; /* 15 us */
7170}
7171
7172static void r8156_hw_phy_cfg(struct r8152 *tp)
7173{
7174 u32 ocp_data;
7175 u16 data;
7176
7177 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7178 if (ocp_data & PCUT_STATUS) {
7179 ocp_data &= ~PCUT_STATUS;
7180 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7181 }
7182
7183 data = r8153_phy_status(tp, 0);
7184 switch (data) {
7185 case PHY_STAT_EXT_INIT:
7186 rtl8152_apply_firmware(tp, true);
7187
7188 data = ocp_reg_read(tp, 0xa468);
7189 data &= ~(BIT(3) | BIT(1));
7190 ocp_reg_write(tp, 0xa468, data);
7191 break;
7192 case PHY_STAT_LAN_ON:
7193 case PHY_STAT_PWRDN:
7194 default:
7195 rtl8152_apply_firmware(tp, false);
7196 break;
7197 }
7198
7199 /* disable ALDPS before updating the PHY parameters */
7200 r8153_aldps_en(tp, false);
7201
7202 /* disable EEE before updating the PHY parameters */
7203 rtl_eee_enable(tp, false);
7204
7205 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7206 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7207
7208 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7209 ocp_data |= PFM_PWM_SWITCH;
7210 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7211
7212 switch (tp->version) {
7213 case RTL_VER_10:
7214 data = ocp_reg_read(tp, 0xad40);
7215 data &= ~0x3ff;
7216 data |= BIT(7) | BIT(2);
7217 ocp_reg_write(tp, 0xad40, data);
7218
7219 data = ocp_reg_read(tp, 0xad4e);
7220 data |= BIT(4);
7221 ocp_reg_write(tp, 0xad4e, data);
7222 data = ocp_reg_read(tp, 0xad16);
7223 data &= ~0x3ff;
7224 data |= 0x6;
7225 ocp_reg_write(tp, 0xad16, data);
7226 data = ocp_reg_read(tp, 0xad32);
7227 data &= ~0x3f;
7228 data |= 6;
7229 ocp_reg_write(tp, 0xad32, data);
7230 data = ocp_reg_read(tp, 0xac08);
7231 data &= ~(BIT(12) | BIT(8));
7232 ocp_reg_write(tp, 0xac08, data);
7233 data = ocp_reg_read(tp, 0xac8a);
7234 data |= BIT(12) | BIT(13) | BIT(14);
7235 data &= ~BIT(15);
7236 ocp_reg_write(tp, 0xac8a, data);
7237 data = ocp_reg_read(tp, 0xad18);
7238 data |= BIT(10);
7239 ocp_reg_write(tp, 0xad18, data);
7240 data = ocp_reg_read(tp, 0xad1a);
7241 data |= 0x3ff;
7242 ocp_reg_write(tp, 0xad1a, data);
7243 data = ocp_reg_read(tp, 0xad1c);
7244 data |= 0x3ff;
7245 ocp_reg_write(tp, 0xad1c, data);
7246
7247 data = sram_read(tp, 0x80ea);
7248 data &= ~0xff00;
7249 data |= 0xc400;
7250 sram_write(tp, 0x80ea, data);
7251 data = sram_read(tp, 0x80eb);
7252 data &= ~0x0700;
7253 data |= 0x0300;
7254 sram_write(tp, 0x80eb, data);
7255 data = sram_read(tp, 0x80f8);
7256 data &= ~0xff00;
7257 data |= 0x1c00;
7258 sram_write(tp, 0x80f8, data);
7259 data = sram_read(tp, 0x80f1);
7260 data &= ~0xff00;
7261 data |= 0x3000;
7262 sram_write(tp, 0x80f1, data);
7263
7264 data = sram_read(tp, 0x80fe);
7265 data &= ~0xff00;
7266 data |= 0xa500;
7267 sram_write(tp, 0x80fe, data);
7268 data = sram_read(tp, 0x8102);
7269 data &= ~0xff00;
7270 data |= 0x5000;
7271 sram_write(tp, 0x8102, data);
7272 data = sram_read(tp, 0x8015);
7273 data &= ~0xff00;
7274 data |= 0x3300;
7275 sram_write(tp, 0x8015, data);
7276 data = sram_read(tp, 0x8100);
7277 data &= ~0xff00;
7278 data |= 0x7000;
7279 sram_write(tp, 0x8100, data);
7280 data = sram_read(tp, 0x8014);
7281 data &= ~0xff00;
7282 data |= 0xf000;
7283 sram_write(tp, 0x8014, data);
7284 data = sram_read(tp, 0x8016);
7285 data &= ~0xff00;
7286 data |= 0x6500;
7287 sram_write(tp, 0x8016, data);
7288 data = sram_read(tp, 0x80dc);
7289 data &= ~0xff00;
7290 data |= 0xed00;
7291 sram_write(tp, 0x80dc, data);
7292 data = sram_read(tp, 0x80df);
7293 data |= BIT(8);
7294 sram_write(tp, 0x80df, data);
7295 data = sram_read(tp, 0x80e1);
7296 data &= ~BIT(8);
7297 sram_write(tp, 0x80e1, data);
7298
7299 data = ocp_reg_read(tp, 0xbf06);
7300 data &= ~0x003f;
7301 data |= 0x0038;
7302 ocp_reg_write(tp, 0xbf06, data);
7303
7304 sram_write(tp, 0x819f, 0xddb6);
7305
7306 ocp_reg_write(tp, 0xbc34, 0x5555);
7307 data = ocp_reg_read(tp, 0xbf0a);
7308 data &= ~0x0e00;
7309 data |= 0x0a00;
7310 ocp_reg_write(tp, 0xbf0a, data);
7311
7312 data = ocp_reg_read(tp, 0xbd2c);
7313 data &= ~BIT(13);
7314 ocp_reg_write(tp, 0xbd2c, data);
7315 break;
7316 case RTL_VER_11:
7317 data = ocp_reg_read(tp, 0xad16);
7318 data |= 0x3ff;
7319 ocp_reg_write(tp, 0xad16, data);
7320 data = ocp_reg_read(tp, 0xad32);
7321 data &= ~0x3f;
7322 data |= 6;
7323 ocp_reg_write(tp, 0xad32, data);
7324 data = ocp_reg_read(tp, 0xac08);
7325 data &= ~(BIT(12) | BIT(8));
7326 ocp_reg_write(tp, 0xac08, data);
7327 data = ocp_reg_read(tp, 0xacc0);
7328 data &= ~0x3;
7329 data |= BIT(1);
7330 ocp_reg_write(tp, 0xacc0, data);
7331 data = ocp_reg_read(tp, 0xad40);
7332 data &= ~0xe7;
7333 data |= BIT(6) | BIT(2);
7334 ocp_reg_write(tp, 0xad40, data);
7335 data = ocp_reg_read(tp, 0xac14);
7336 data &= ~BIT(7);
7337 ocp_reg_write(tp, 0xac14, data);
7338 data = ocp_reg_read(tp, 0xac80);
7339 data &= ~(BIT(8) | BIT(9));
7340 ocp_reg_write(tp, 0xac80, data);
7341 data = ocp_reg_read(tp, 0xac5e);
7342 data &= ~0x7;
7343 data |= BIT(1);
7344 ocp_reg_write(tp, 0xac5e, data);
7345 ocp_reg_write(tp, 0xad4c, 0x00a8);
7346 ocp_reg_write(tp, 0xac5c, 0x01ff);
7347 data = ocp_reg_read(tp, 0xac8a);
7348 data &= ~0xf0;
7349 data |= BIT(4) | BIT(5);
7350 ocp_reg_write(tp, 0xac8a, data);
7351 ocp_reg_write(tp, 0xb87c, 0x8157);
7352 data = ocp_reg_read(tp, 0xb87e);
7353 data &= ~0xff00;
7354 data |= 0x0500;
7355 ocp_reg_write(tp, 0xb87e, data);
7356 ocp_reg_write(tp, 0xb87c, 0x8159);
7357 data = ocp_reg_read(tp, 0xb87e);
7358 data &= ~0xff00;
7359 data |= 0x0700;
7360 ocp_reg_write(tp, 0xb87e, data);
7361
7362 /* AAGC */
7363 ocp_reg_write(tp, 0xb87c, 0x80a2);
7364 ocp_reg_write(tp, 0xb87e, 0x0153);
7365 ocp_reg_write(tp, 0xb87c, 0x809c);
7366 ocp_reg_write(tp, 0xb87e, 0x0153);
7367
7368 /* EEE parameter */
7369 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);
7370
7371 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7372 ocp_data |= EN_XG_LIP | EN_G_LIP;
7373 ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7374
7375 sram_write(tp, 0x8257, 0x020f); /* XG PLL */
7376 sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */
7377
7378 if (rtl_phy_patch_request(tp, true, true))
7379 return;
7380
7381 /* Advance EEE */
7382 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7383 ocp_data |= EEE_SPDWN_EN;
7384 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
7385
7386 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7387 data &= ~(EN_EEE_100 | EN_EEE_1000);
7388 data |= EN_10M_CLKDIV;
7389 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7390 tp->ups_info._10m_ckdiv = true;
7391 tp->ups_info.eee_plloff_100 = false;
7392 tp->ups_info.eee_plloff_giga = false;
7393
7394 data = ocp_reg_read(tp, OCP_POWER_CFG);
7395 data &= ~EEE_CLKDIV_EN;
7396 ocp_reg_write(tp, OCP_POWER_CFG, data);
7397 tp->ups_info.eee_ckdiv = false;
7398
7399 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
7400 ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));
7401 tp->ups_info._250m_ckdiv = false;
7402
7403 rtl_phy_patch_request(tp, false, true);
7404
7405 /* enable ADC Ibias Cal */
7406 data = ocp_reg_read(tp, 0xd068);
7407 data |= BIT(13);
7408 ocp_reg_write(tp, 0xd068, data);
7409
7410 /* enable Thermal Sensor */
7411 data = sram_read(tp, 0x81a2);
7412 data &= ~BIT(8);
7413 sram_write(tp, 0x81a2, data);
7414 data = ocp_reg_read(tp, 0xb54c);
7415 data &= ~0xff00;
7416 data |= 0xdb00;
7417 ocp_reg_write(tp, 0xb54c, data);
7418
7419 /* Nway 2.5G Lite */
7420 data = ocp_reg_read(tp, 0xa454);
7421 data &= ~BIT(0);
7422 ocp_reg_write(tp, 0xa454, data);
7423
7424 /* CS DSP solution */
7425 data = ocp_reg_read(tp, OCP_10GBT_CTRL);
7426 data |= RTL_ADV2_5G_F_R;
7427 ocp_reg_write(tp, OCP_10GBT_CTRL, data);
7428 data = ocp_reg_read(tp, 0xad4e);
7429 data &= ~BIT(4);
7430 ocp_reg_write(tp, 0xad4e, data);
7431 data = ocp_reg_read(tp, 0xa86a);
7432 data &= ~BIT(0);
7433 ocp_reg_write(tp, 0xa86a, data);
7434
7435 /* MDI SWAP */
7436 if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&
7437 (ocp_reg_read(tp, 0xd068) & BIT(1))) {
7438 u16 swap_a, swap_b;
7439
7440 data = ocp_reg_read(tp, 0xd068);
7441 data &= ~0x1f;
7442 data |= 0x1; /* p0 */
7443 ocp_reg_write(tp, 0xd068, data);
7444 swap_a = ocp_reg_read(tp, 0xd06a);
7445 data &= ~0x18;
7446 data |= 0x18; /* p3 */
7447 ocp_reg_write(tp, 0xd068, data);
7448 swap_b = ocp_reg_read(tp, 0xd06a);
7449 data &= ~0x18; /* p0 */
7450 ocp_reg_write(tp, 0xd068, data);
7451 ocp_reg_write(tp, 0xd06a,
7452 (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7453 data |= 0x18; /* p3 */
7454 ocp_reg_write(tp, 0xd068, data);
7455 ocp_reg_write(tp, 0xd06a,
7456 (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7457 data &= ~0x18;
7458 data |= 0x08; /* p1 */
7459 ocp_reg_write(tp, 0xd068, data);
7460 swap_a = ocp_reg_read(tp, 0xd06a);
7461 data &= ~0x18;
7462 data |= 0x10; /* p2 */
7463 ocp_reg_write(tp, 0xd068, data);
7464 swap_b = ocp_reg_read(tp, 0xd06a);
7465 data &= ~0x18;
7466 data |= 0x08; /* p1 */
7467 ocp_reg_write(tp, 0xd068, data);
7468 ocp_reg_write(tp, 0xd06a,
7469 (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7470 data &= ~0x18;
7471 data |= 0x10; /* p2 */
7472 ocp_reg_write(tp, 0xd068, data);
7473 ocp_reg_write(tp, 0xd06a,
7474 (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7475 swap_a = ocp_reg_read(tp, 0xbd5a);
7476 swap_b = ocp_reg_read(tp, 0xbd5c);
7477 ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) |
7478 ((swap_b & 0x1f) << 8) |
7479 ((swap_b >> 8) & 0x1f));
7480 ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) |
7481 ((swap_a & 0x1f) << 8) |
7482 ((swap_a >> 8) & 0x1f));
7483 swap_a = ocp_reg_read(tp, 0xbc18);
7484 swap_b = ocp_reg_read(tp, 0xbc1a);
7485 ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) |
7486 ((swap_b & 0x1f) << 8) |
7487 ((swap_b >> 8) & 0x1f));
7488 ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) |
7489 ((swap_a & 0x1f) << 8) |
7490 ((swap_a >> 8) & 0x1f));
7491 }
7492 break;
7493 default:
7494 break;
7495 }
7496
7497 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7498
7499 data = ocp_reg_read(tp, 0xa428);
7500 data &= ~BIT(9);
7501 ocp_reg_write(tp, 0xa428, data);
7502 data = ocp_reg_read(tp, 0xa5ea);
7503 data &= ~BIT(0);
7504 ocp_reg_write(tp, 0xa5ea, data);
7505 tp->ups_info.lite_mode = 0;
7506
7507 if (tp->eee_en)
7508 rtl_eee_enable(tp, true);
7509
7510 r8153_aldps_en(tp, true);
7511 r8152b_enable_fc(tp);
7512 r8153_u2p3en(tp, true);
7513
7514 set_bit(PHY_RESET, &tp->flags);
7515}
7516
7517static void r8156b_hw_phy_cfg(struct r8152 *tp)
7518{
7519 u32 ocp_data;
7520 u16 data;
7521
7522 switch (tp->version) {
7523 case RTL_VER_12:
7524 ocp_reg_write(tp, 0xbf86, 0x9000);
7525 data = ocp_reg_read(tp, 0xc402);
7526 data |= BIT(10);
7527 ocp_reg_write(tp, 0xc402, data);
7528 data &= ~BIT(10);
7529 ocp_reg_write(tp, 0xc402, data);
7530 ocp_reg_write(tp, 0xbd86, 0x1010);
7531 ocp_reg_write(tp, 0xbd88, 0x1010);
7532 data = ocp_reg_read(tp, 0xbd4e);
7533 data &= ~(BIT(10) | BIT(11));
7534 data |= BIT(11);
7535 ocp_reg_write(tp, 0xbd4e, data);
7536 data = ocp_reg_read(tp, 0xbf46);
7537 data &= ~0xf00;
7538 data |= 0x700;
7539 ocp_reg_write(tp, 0xbf46, data);
7540 break;
7541 case RTL_VER_13:
7542 case RTL_VER_15:
7543 r8156b_wait_loading_flash(tp);
7544 break;
7545 default:
7546 break;
7547 }
7548
7549 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7550 if (ocp_data & PCUT_STATUS) {
7551 ocp_data &= ~PCUT_STATUS;
7552 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7553 }
7554
7555 data = r8153_phy_status(tp, 0);
7556 switch (data) {
7557 case PHY_STAT_EXT_INIT:
7558 rtl8152_apply_firmware(tp, true);
7559
7560 data = ocp_reg_read(tp, 0xa466);
7561 data &= ~BIT(0);
7562 ocp_reg_write(tp, 0xa466, data);
7563
7564 data = ocp_reg_read(tp, 0xa468);
7565 data &= ~(BIT(3) | BIT(1));
7566 ocp_reg_write(tp, 0xa468, data);
7567 break;
7568 case PHY_STAT_LAN_ON:
7569 case PHY_STAT_PWRDN:
7570 default:
7571 rtl8152_apply_firmware(tp, false);
7572 break;
7573 }
7574
7575 data = r8152_mdio_read(tp, MII_BMCR);
7576 if (data & BMCR_PDOWN) {
7577 data &= ~BMCR_PDOWN;
7578 r8152_mdio_write(tp, MII_BMCR, data);
7579 }
7580
7581 /* disable ALDPS before updating the PHY parameters */
7582 r8153_aldps_en(tp, false);
7583
7584 /* disable EEE before updating the PHY parameters */
7585 rtl_eee_enable(tp, false);
7586
7587 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7588 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7589
7590 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7591 ocp_data |= PFM_PWM_SWITCH;
7592 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7593
7594 switch (tp->version) {
7595 case RTL_VER_12:
7596 data = ocp_reg_read(tp, 0xbc08);
7597 data |= BIT(3) | BIT(2);
7598 ocp_reg_write(tp, 0xbc08, data);
7599
7600 data = sram_read(tp, 0x8fff);
7601 data &= ~0xff00;
7602 data |= 0x0400;
7603 sram_write(tp, 0x8fff, data);
7604
7605 data = ocp_reg_read(tp, 0xacda);
7606 data |= 0xff00;
7607 ocp_reg_write(tp, 0xacda, data);
7608 data = ocp_reg_read(tp, 0xacde);
7609 data |= 0xf000;
7610 ocp_reg_write(tp, 0xacde, data);
7611 ocp_reg_write(tp, 0xac8c, 0x0ffc);
7612 ocp_reg_write(tp, 0xac46, 0xb7b4);
7613 ocp_reg_write(tp, 0xac50, 0x0fbc);
7614 ocp_reg_write(tp, 0xac3c, 0x9240);
7615 ocp_reg_write(tp, 0xac4e, 0x0db4);
7616 ocp_reg_write(tp, 0xacc6, 0x0707);
7617 ocp_reg_write(tp, 0xacc8, 0xa0d3);
7618 ocp_reg_write(tp, 0xad08, 0x0007);
7619
7620 ocp_reg_write(tp, 0xb87c, 0x8560);
7621 ocp_reg_write(tp, 0xb87e, 0x19cc);
7622 ocp_reg_write(tp, 0xb87c, 0x8562);
7623 ocp_reg_write(tp, 0xb87e, 0x19cc);
7624 ocp_reg_write(tp, 0xb87c, 0x8564);
7625 ocp_reg_write(tp, 0xb87e, 0x19cc);
7626 ocp_reg_write(tp, 0xb87c, 0x8566);
7627 ocp_reg_write(tp, 0xb87e, 0x147d);
7628 ocp_reg_write(tp, 0xb87c, 0x8568);
7629 ocp_reg_write(tp, 0xb87e, 0x147d);
7630 ocp_reg_write(tp, 0xb87c, 0x856a);
7631 ocp_reg_write(tp, 0xb87e, 0x147d);
7632 ocp_reg_write(tp, 0xb87c, 0x8ffe);
7633 ocp_reg_write(tp, 0xb87e, 0x0907);
7634 ocp_reg_write(tp, 0xb87c, 0x80d6);
7635 ocp_reg_write(tp, 0xb87e, 0x2801);
7636 ocp_reg_write(tp, 0xb87c, 0x80f2);
7637 ocp_reg_write(tp, 0xb87e, 0x2801);
7638 ocp_reg_write(tp, 0xb87c, 0x80f4);
7639 ocp_reg_write(tp, 0xb87e, 0x6077);
7640 ocp_reg_write(tp, 0xb506, 0x01e7);
7641
7642 ocp_reg_write(tp, 0xb87c, 0x8013);
7643 ocp_reg_write(tp, 0xb87e, 0x0700);
7644 ocp_reg_write(tp, 0xb87c, 0x8fb9);
7645 ocp_reg_write(tp, 0xb87e, 0x2801);
7646 ocp_reg_write(tp, 0xb87c, 0x8fba);
7647 ocp_reg_write(tp, 0xb87e, 0x0100);
7648 ocp_reg_write(tp, 0xb87c, 0x8fbc);
7649 ocp_reg_write(tp, 0xb87e, 0x1900);
7650 ocp_reg_write(tp, 0xb87c, 0x8fbe);
7651 ocp_reg_write(tp, 0xb87e, 0xe100);
7652 ocp_reg_write(tp, 0xb87c, 0x8fc0);
7653 ocp_reg_write(tp, 0xb87e, 0x0800);
7654 ocp_reg_write(tp, 0xb87c, 0x8fc2);
7655 ocp_reg_write(tp, 0xb87e, 0xe500);
7656 ocp_reg_write(tp, 0xb87c, 0x8fc4);
7657 ocp_reg_write(tp, 0xb87e, 0x0f00);
7658 ocp_reg_write(tp, 0xb87c, 0x8fc6);
7659 ocp_reg_write(tp, 0xb87e, 0xf100);
7660 ocp_reg_write(tp, 0xb87c, 0x8fc8);
7661 ocp_reg_write(tp, 0xb87e, 0x0400);
7662 ocp_reg_write(tp, 0xb87c, 0x8fca);
7663 ocp_reg_write(tp, 0xb87e, 0xf300);
7664 ocp_reg_write(tp, 0xb87c, 0x8fcc);
7665 ocp_reg_write(tp, 0xb87e, 0xfd00);
7666 ocp_reg_write(tp, 0xb87c, 0x8fce);
7667 ocp_reg_write(tp, 0xb87e, 0xff00);
7668 ocp_reg_write(tp, 0xb87c, 0x8fd0);
7669 ocp_reg_write(tp, 0xb87e, 0xfb00);
7670 ocp_reg_write(tp, 0xb87c, 0x8fd2);
7671 ocp_reg_write(tp, 0xb87e, 0x0100);
7672 ocp_reg_write(tp, 0xb87c, 0x8fd4);
7673 ocp_reg_write(tp, 0xb87e, 0xf400);
7674 ocp_reg_write(tp, 0xb87c, 0x8fd6);
7675 ocp_reg_write(tp, 0xb87e, 0xff00);
7676 ocp_reg_write(tp, 0xb87c, 0x8fd8);
7677 ocp_reg_write(tp, 0xb87e, 0xf600);
7678
7679 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7680 ocp_data |= EN_XG_LIP | EN_G_LIP;
7681 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7682 ocp_reg_write(tp, 0xb87c, 0x813d);
7683 ocp_reg_write(tp, 0xb87e, 0x390e);
7684 ocp_reg_write(tp, 0xb87c, 0x814f);
7685 ocp_reg_write(tp, 0xb87e, 0x790e);
7686 ocp_reg_write(tp, 0xb87c, 0x80b0);
7687 ocp_reg_write(tp, 0xb87e, 0x0f31);
7688 data = ocp_reg_read(tp, 0xbf4c);
7689 data |= BIT(1);
7690 ocp_reg_write(tp, 0xbf4c, data);
7691 data = ocp_reg_read(tp, 0xbcca);
7692 data |= BIT(9) | BIT(8);
7693 ocp_reg_write(tp, 0xbcca, data);
7694 ocp_reg_write(tp, 0xb87c, 0x8141);
7695 ocp_reg_write(tp, 0xb87e, 0x320e);
7696 ocp_reg_write(tp, 0xb87c, 0x8153);
7697 ocp_reg_write(tp, 0xb87e, 0x720e);
7698 ocp_reg_write(tp, 0xb87c, 0x8529);
7699 ocp_reg_write(tp, 0xb87e, 0x050e);
7700 data = ocp_reg_read(tp, OCP_EEE_CFG);
7701 data &= ~CTAP_SHORT_EN;
7702 ocp_reg_write(tp, OCP_EEE_CFG, data);
7703
7704 sram_write(tp, 0x816c, 0xc4a0);
7705 sram_write(tp, 0x8170, 0xc4a0);
7706 sram_write(tp, 0x8174, 0x04a0);
7707 sram_write(tp, 0x8178, 0x04a0);
7708 sram_write(tp, 0x817c, 0x0719);
7709 sram_write(tp, 0x8ff4, 0x0400);
7710 sram_write(tp, 0x8ff1, 0x0404);
7711
7712 ocp_reg_write(tp, 0xbf4a, 0x001b);
7713 ocp_reg_write(tp, 0xb87c, 0x8033);
7714 ocp_reg_write(tp, 0xb87e, 0x7c13);
7715 ocp_reg_write(tp, 0xb87c, 0x8037);
7716 ocp_reg_write(tp, 0xb87e, 0x7c13);
7717 ocp_reg_write(tp, 0xb87c, 0x803b);
7718 ocp_reg_write(tp, 0xb87e, 0xfc32);
7719 ocp_reg_write(tp, 0xb87c, 0x803f);
7720 ocp_reg_write(tp, 0xb87e, 0x7c13);
7721 ocp_reg_write(tp, 0xb87c, 0x8043);
7722 ocp_reg_write(tp, 0xb87e, 0x7c13);
7723 ocp_reg_write(tp, 0xb87c, 0x8047);
7724 ocp_reg_write(tp, 0xb87e, 0x7c13);
7725
7726 ocp_reg_write(tp, 0xb87c, 0x8145);
7727 ocp_reg_write(tp, 0xb87e, 0x370e);
7728 ocp_reg_write(tp, 0xb87c, 0x8157);
7729 ocp_reg_write(tp, 0xb87e, 0x770e);
7730 ocp_reg_write(tp, 0xb87c, 0x8169);
7731 ocp_reg_write(tp, 0xb87e, 0x0d0a);
7732 ocp_reg_write(tp, 0xb87c, 0x817b);
7733 ocp_reg_write(tp, 0xb87e, 0x1d0a);
7734
7735 data = sram_read(tp, 0x8217);
7736 data &= ~0xff00;
7737 data |= 0x5000;
7738 sram_write(tp, 0x8217, data);
7739 data = sram_read(tp, 0x821a);
7740 data &= ~0xff00;
7741 data |= 0x5000;
7742 sram_write(tp, 0x821a, data);
7743 sram_write(tp, 0x80da, 0x0403);
7744 data = sram_read(tp, 0x80dc);
7745 data &= ~0xff00;
7746 data |= 0x1000;
7747 sram_write(tp, 0x80dc, data);
7748 sram_write(tp, 0x80b3, 0x0384);
7749 sram_write(tp, 0x80b7, 0x2007);
7750 data = sram_read(tp, 0x80ba);
7751 data &= ~0xff00;
7752 data |= 0x6c00;
7753 sram_write(tp, 0x80ba, data);
7754 sram_write(tp, 0x80b5, 0xf009);
7755 data = sram_read(tp, 0x80bd);
7756 data &= ~0xff00;
7757 data |= 0x9f00;
7758 sram_write(tp, 0x80bd, data);
7759 sram_write(tp, 0x80c7, 0xf083);
7760 sram_write(tp, 0x80dd, 0x03f0);
7761 data = sram_read(tp, 0x80df);
7762 data &= ~0xff00;
7763 data |= 0x1000;
7764 sram_write(tp, 0x80df, data);
7765 sram_write(tp, 0x80cb, 0x2007);
7766 data = sram_read(tp, 0x80ce);
7767 data &= ~0xff00;
7768 data |= 0x6c00;
7769 sram_write(tp, 0x80ce, data);
7770 sram_write(tp, 0x80c9, 0x8009);
7771 data = sram_read(tp, 0x80d1);
7772 data &= ~0xff00;
7773 data |= 0x8000;
7774 sram_write(tp, 0x80d1, data);
7775 sram_write(tp, 0x80a3, 0x200a);
7776 sram_write(tp, 0x80a5, 0xf0ad);
7777 sram_write(tp, 0x809f, 0x6073);
7778 sram_write(tp, 0x80a1, 0x000b);
7779 data = sram_read(tp, 0x80a9);
7780 data &= ~0xff00;
7781 data |= 0xc000;
7782 sram_write(tp, 0x80a9, data);
7783
7784 if (rtl_phy_patch_request(tp, true, true))
7785 return;
7786
7787 data = ocp_reg_read(tp, 0xb896);
7788 data &= ~BIT(0);
7789 ocp_reg_write(tp, 0xb896, data);
7790 data = ocp_reg_read(tp, 0xb892);
7791 data &= ~0xff00;
7792 ocp_reg_write(tp, 0xb892, data);
7793 ocp_reg_write(tp, 0xb88e, 0xc23e);
7794 ocp_reg_write(tp, 0xb890, 0x0000);
7795 ocp_reg_write(tp, 0xb88e, 0xc240);
7796 ocp_reg_write(tp, 0xb890, 0x0103);
7797 ocp_reg_write(tp, 0xb88e, 0xc242);
7798 ocp_reg_write(tp, 0xb890, 0x0507);
7799 ocp_reg_write(tp, 0xb88e, 0xc244);
7800 ocp_reg_write(tp, 0xb890, 0x090b);
7801 ocp_reg_write(tp, 0xb88e, 0xc246);
7802 ocp_reg_write(tp, 0xb890, 0x0c0e);
7803 ocp_reg_write(tp, 0xb88e, 0xc248);
7804 ocp_reg_write(tp, 0xb890, 0x1012);
7805 ocp_reg_write(tp, 0xb88e, 0xc24a);
7806 ocp_reg_write(tp, 0xb890, 0x1416);
7807 data = ocp_reg_read(tp, 0xb896);
7808 data |= BIT(0);
7809 ocp_reg_write(tp, 0xb896, data);
7810
7811 rtl_phy_patch_request(tp, false, true);
7812
7813 data = ocp_reg_read(tp, 0xa86a);
7814 data |= BIT(0);
7815 ocp_reg_write(tp, 0xa86a, data);
7816 data = ocp_reg_read(tp, 0xa6f0);
7817 data |= BIT(0);
7818 ocp_reg_write(tp, 0xa6f0, data);
7819
7820 ocp_reg_write(tp, 0xbfa0, 0xd70d);
7821 ocp_reg_write(tp, 0xbfa2, 0x4100);
7822 ocp_reg_write(tp, 0xbfa4, 0xe868);
7823 ocp_reg_write(tp, 0xbfa6, 0xdc59);
7824 ocp_reg_write(tp, 0xb54c, 0x3c18);
7825 data = ocp_reg_read(tp, 0xbfa4);
7826 data &= ~BIT(5);
7827 ocp_reg_write(tp, 0xbfa4, data);
7828 data = sram_read(tp, 0x817d);
7829 data |= BIT(12);
7830 sram_write(tp, 0x817d, data);
7831 break;
7832 case RTL_VER_13:
7833 /* 2.5G INRX */
7834 data = ocp_reg_read(tp, 0xac46);
7835 data &= ~0x00f0;
7836 data |= 0x0090;
7837 ocp_reg_write(tp, 0xac46, data);
7838 data = ocp_reg_read(tp, 0xad30);
7839 data &= ~0x0003;
7840 data |= 0x0001;
7841 ocp_reg_write(tp, 0xad30, data);
7842 fallthrough;
7843 case RTL_VER_15:
7844 /* EEE parameter */
7845 ocp_reg_write(tp, 0xb87c, 0x80f5);
7846 ocp_reg_write(tp, 0xb87e, 0x760e);
7847 ocp_reg_write(tp, 0xb87c, 0x8107);
7848 ocp_reg_write(tp, 0xb87e, 0x360e);
7849 ocp_reg_write(tp, 0xb87c, 0x8551);
7850 data = ocp_reg_read(tp, 0xb87e);
7851 data &= ~0xff00;
7852 data |= 0x0800;
7853 ocp_reg_write(tp, 0xb87e, data);
7854
7855 /* ADC_PGA parameter */
7856 data = ocp_reg_read(tp, 0xbf00);
7857 data &= ~0xe000;
7858 data |= 0xa000;
7859 ocp_reg_write(tp, 0xbf00, data);
7860 data = ocp_reg_read(tp, 0xbf46);
7861 data &= ~0x0f00;
7862 data |= 0x0300;
7863 ocp_reg_write(tp, 0xbf46, data);
7864
7865 /* Green Table-PGA, 1G full viterbi */
7866 sram_write(tp, 0x8044, 0x2417);
7867 sram_write(tp, 0x804a, 0x2417);
7868 sram_write(tp, 0x8050, 0x2417);
7869 sram_write(tp, 0x8056, 0x2417);
7870 sram_write(tp, 0x805c, 0x2417);
7871 sram_write(tp, 0x8062, 0x2417);
7872 sram_write(tp, 0x8068, 0x2417);
7873 sram_write(tp, 0x806e, 0x2417);
7874 sram_write(tp, 0x8074, 0x2417);
7875 sram_write(tp, 0x807a, 0x2417);
7876
7877 /* XG PLL */
7878 data = ocp_reg_read(tp, 0xbf84);
7879 data &= ~0xe000;
7880 data |= 0xa000;
7881 ocp_reg_write(tp, 0xbf84, data);
7882 break;
7883 default:
7884 break;
7885 }
7886
7887 if (rtl_phy_patch_request(tp, true, true))
7888 return;
7889
7890 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7891 ocp_data |= EEE_SPDWN_EN;
7892 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
7893
7894 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7895 data &= ~(EN_EEE_100 | EN_EEE_1000);
7896 data |= EN_10M_CLKDIV;
7897 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7898 tp->ups_info._10m_ckdiv = true;
7899 tp->ups_info.eee_plloff_100 = false;
7900 tp->ups_info.eee_plloff_giga = false;
7901
7902 data = ocp_reg_read(tp, OCP_POWER_CFG);
7903 data &= ~EEE_CLKDIV_EN;
7904 ocp_reg_write(tp, OCP_POWER_CFG, data);
7905 tp->ups_info.eee_ckdiv = false;
7906
7907 rtl_phy_patch_request(tp, false, true);
7908
7909 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7910
7911 data = ocp_reg_read(tp, 0xa428);
7912 data &= ~BIT(9);
7913 ocp_reg_write(tp, 0xa428, data);
7914 data = ocp_reg_read(tp, 0xa5ea);
7915 data &= ~BIT(0);
7916 ocp_reg_write(tp, 0xa5ea, data);
7917 tp->ups_info.lite_mode = 0;
7918
7919 if (tp->eee_en)
7920 rtl_eee_enable(tp, true);
7921
7922 r8153_aldps_en(tp, true);
7923 r8152b_enable_fc(tp);
7924 r8153_u2p3en(tp, true);
7925
7926 set_bit(PHY_RESET, &tp->flags);
7927}
7928
7929static void r8156_init(struct r8152 *tp)
7930{
7931 u32 ocp_data;
7932 u16 data;
7933 int i;
7934
7935 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7936 return;
7937
7938 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
7939 ocp_data &= ~EN_ALL_SPEED;
7940 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
7941
7942 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
7943
7944 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
7945 ocp_data |= BYPASS_MAC_RESET;
7946 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
7947
7948 r8153b_u1u2en(tp, false);
7949
7950 for (i = 0; i < 500; i++) {
7951 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7952 AUTOLOAD_DONE)
7953 break;
7954
7955 msleep(20);
7956 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7957 return;
7958 }
7959
7960 data = r8153_phy_status(tp, 0);
7961 if (data == PHY_STAT_EXT_INIT) {
7962 data = ocp_reg_read(tp, 0xa468);
7963 data &= ~(BIT(3) | BIT(1));
7964 ocp_reg_write(tp, 0xa468, data);
7965 }
7966
7967 data = r8152_mdio_read(tp, MII_BMCR);
7968 if (data & BMCR_PDOWN) {
7969 data &= ~BMCR_PDOWN;
7970 r8152_mdio_write(tp, MII_BMCR, data);
7971 }
7972
7973 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7974 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7975
7976 r8153_u2p3en(tp, false);
7977
7978 /* MSC timer = 0xfff * 8ms = 32760 ms */
7979 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7980
7981 /* U1/U2/L1 idle timer. 500 us */
7982 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
7983
7984 r8153b_power_cut_en(tp, false);
7985 r8156_ups_en(tp, false);
7986 r8153_queue_wake(tp, false);
7987 rtl_runtime_suspend_enable(tp, false);
7988
7989 if (tp->udev->speed >= USB_SPEED_SUPER)
7990 r8153b_u1u2en(tp, true);
7991
7992 usb_enable_lpm(tp->udev);
7993
7994 r8156_mac_clk_spd(tp, true);
7995
7996 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7997 ocp_data &= ~PLA_MCU_SPDWN_EN;
7998 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
7999
8000 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8001 if (rtl8152_get_speed(tp) & LINK_STATUS)
8002 ocp_data |= CUR_LINK_OK;
8003 else
8004 ocp_data &= ~CUR_LINK_OK;
8005 ocp_data |= POLL_LINK_CHG;
8006 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8007
8008 set_bit(GREEN_ETHERNET, &tp->flags);
8009
8010 /* rx aggregation */
8011 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8012 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8013 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8014
8015 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
8016 ocp_data |= ACT_ODMA;
8017 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
8018
8019 rtl_tally_reset(tp);
8020
8021 tp->coalesce = 15000; /* 15 us */
8022}
8023
8024static void r8156b_init(struct r8152 *tp)
8025{
8026 u32 ocp_data;
8027 u16 data;
8028 int i;
8029
8030 if (test_bit(RTL8152_UNPLUG, &tp->flags))
8031 return;
8032
8033 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8034 ocp_data &= ~EN_ALL_SPEED;
8035 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
8036
8037 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
8038
8039 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8040 ocp_data |= BYPASS_MAC_RESET;
8041 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
8042
8043 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
8044 ocp_data |= RX_DETECT8;
8045 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
8046
8047 r8153b_u1u2en(tp, false);
8048
8049 switch (tp->version) {
8050 case RTL_VER_13:
8051 case RTL_VER_15:
8052 r8156b_wait_loading_flash(tp);
8053 break;
8054 default:
8055 break;
8056 }
8057
8058 for (i = 0; i < 500; i++) {
8059 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8060 AUTOLOAD_DONE)
8061 break;
8062
8063 msleep(20);
8064 if (test_bit(RTL8152_UNPLUG, &tp->flags))
8065 return;
8066 }
8067
8068 data = r8153_phy_status(tp, 0);
8069 if (data == PHY_STAT_EXT_INIT) {
8070 data = ocp_reg_read(tp, 0xa468);
8071 data &= ~(BIT(3) | BIT(1));
8072 ocp_reg_write(tp, 0xa468, data);
8073
8074 data = ocp_reg_read(tp, 0xa466);
8075 data &= ~BIT(0);
8076 ocp_reg_write(tp, 0xa466, data);
8077 }
8078
8079 data = r8152_mdio_read(tp, MII_BMCR);
8080 if (data & BMCR_PDOWN) {
8081 data &= ~BMCR_PDOWN;
8082 r8152_mdio_write(tp, MII_BMCR, data);
8083 }
8084
8085 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8086
8087 r8153_u2p3en(tp, false);
8088
8089 /* MSC timer = 0xfff * 8ms = 32760 ms */
8090 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
8091
8092 /* U1/U2/L1 idle timer. 500 us */
8093 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
8094
8095 r8153b_power_cut_en(tp, false);
8096 r8156_ups_en(tp, false);
8097 r8153_queue_wake(tp, false);
8098 rtl_runtime_suspend_enable(tp, false);
8099
8100 if (tp->udev->speed >= USB_SPEED_SUPER)
8101 r8153b_u1u2en(tp, true);
8102
8103 usb_enable_lpm(tp->udev);
8104
8105 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);
8106 ocp_data &= ~SLOT_EN;
8107 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8108
8109 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
8110 ocp_data |= FLOW_CTRL_EN;
8111 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
8112
8113 /* enable fc timer and set timer to 600 ms. */
8114 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
8115 CTRL_TIMER_EN | (600 / 8));
8116
8117 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
8118 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))
8119 ocp_data |= FLOW_CTRL_PATCH_2;
8120 ocp_data &= ~AUTO_SPEEDUP;
8121 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
8122
8123 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
8124 ocp_data |= FC_PATCH_TASK;
8125 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
8126
8127 r8156_mac_clk_spd(tp, true);
8128
8129 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8130 ocp_data &= ~PLA_MCU_SPDWN_EN;
8131 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
8132
8133 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8134 if (rtl8152_get_speed(tp) & LINK_STATUS)
8135 ocp_data |= CUR_LINK_OK;
8136 else
8137 ocp_data &= ~CUR_LINK_OK;
8138 ocp_data |= POLL_LINK_CHG;
8139 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8140
8141 set_bit(GREEN_ETHERNET, &tp->flags);
8142
8143 /* rx aggregation */
8144 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8145 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8146 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8147
8148 rtl_tally_reset(tp);
8149
8150 tp->coalesce = 15000; /* 15 us */
8151}
8152
8153static bool rtl_check_vendor_ok(struct usb_interface *intf)
8154{
8155 struct usb_host_interface *alt = intf->cur_altsetting;
8156 struct usb_endpoint_descriptor *in, *out, *intr;
8157
8158 if (usb_find_common_endpoints(alt, &in, &out, &intr, NULL) < 0) {
8159 dev_err(&intf->dev, "Expected endpoints are not found\n");
8160 return false;
8161 }
8162
8163 /* Check Rx endpoint address */
8164 if (usb_endpoint_num(in) != 1) {
8165 dev_err(&intf->dev, "Invalid Rx endpoint address\n");
8166 return false;
8167 }
8168
8169 /* Check Tx endpoint address */
8170 if (usb_endpoint_num(out) != 2) {
8171 dev_err(&intf->dev, "Invalid Tx endpoint address\n");
8172 return false;
8173 }
8174
8175 /* Check interrupt endpoint address */
8176 if (usb_endpoint_num(intr) != 3) {
8177 dev_err(&intf->dev, "Invalid interrupt endpoint address\n");
8178 return false;
8179 }
8180
8181 return true;
8182}
8183
8184static bool rtl_vendor_mode(struct usb_interface *intf)
8185{
8186 struct usb_host_interface *alt = intf->cur_altsetting;
8187 struct usb_device *udev;
8188 struct usb_host_config *c;
8189 int i, num_configs;
8190
8191 if (alt->desc.bInterfaceClass == USB_CLASS_VENDOR_SPEC)
8192 return rtl_check_vendor_ok(intf);
8193
8194 /* The vendor mode is not always config #1, so to find it out. */
8195 udev = interface_to_usbdev(intf);
8196 c = udev->config;
8197 num_configs = udev->descriptor.bNumConfigurations;
8198 if (num_configs < 2)
8199 return false;
8200
8201 for (i = 0; i < num_configs; (i++, c++)) {
8202 struct usb_interface_descriptor *desc = NULL;
8203
8204 if (c->desc.bNumInterfaces > 0)
8205 desc = &c->intf_cache[0]->altsetting->desc;
8206 else
8207 continue;
8208
8209 if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC) {
8210 usb_driver_set_configuration(udev, c->desc.bConfigurationValue);
8211 break;
8212 }
8213 }
8214
8215 if (i == num_configs)
8216 dev_err(&intf->dev, "Unexpected Device\n");
8217
8218 return false;
8219}
8220
8221static int rtl8152_pre_reset(struct usb_interface *intf)
8222{
8223 struct r8152 *tp = usb_get_intfdata(intf);
8224 struct net_device *netdev;
8225
8226 if (!tp)
8227 return 0;
8228
8229 netdev = tp->netdev;
8230 if (!netif_running(netdev))
8231 return 0;
8232
8233 netif_stop_queue(netdev);
8234 tasklet_disable(&tp->tx_tl);
8235 clear_bit(WORK_ENABLE, &tp->flags);
8236 usb_kill_urb(tp->intr_urb);
8237 cancel_delayed_work_sync(&tp->schedule);
8238 napi_disable(&tp->napi);
8239 if (netif_carrier_ok(netdev)) {
8240 mutex_lock(&tp->control);
8241 tp->rtl_ops.disable(tp);
8242 mutex_unlock(&tp->control);
8243 }
8244
8245 return 0;
8246}
8247
8248static int rtl8152_post_reset(struct usb_interface *intf)
8249{
8250 struct r8152 *tp = usb_get_intfdata(intf);
8251 struct net_device *netdev;
8252 struct sockaddr sa;
8253
8254 if (!tp)
8255 return 0;
8256
8257 /* reset the MAC address in case of policy change */
8258 if (determine_ethernet_addr(tp, &sa) >= 0) {
8259 rtnl_lock();
8260 dev_set_mac_address (tp->netdev, &sa, NULL);
8261 rtnl_unlock();
8262 }
8263
8264 netdev = tp->netdev;
8265 if (!netif_running(netdev))
8266 return 0;
8267
8268 set_bit(WORK_ENABLE, &tp->flags);
8269 if (netif_carrier_ok(netdev)) {
8270 mutex_lock(&tp->control);
8271 tp->rtl_ops.enable(tp);
8272 rtl_start_rx(tp);
8273 _rtl8152_set_rx_mode(netdev);
8274 mutex_unlock(&tp->control);
8275 }
8276
8277 napi_enable(&tp->napi);
8278 tasklet_enable(&tp->tx_tl);
8279 netif_wake_queue(netdev);
8280 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
8281
8282 if (!list_empty(&tp->rx_done))
8283 napi_schedule(&tp->napi);
8284
8285 return 0;
8286}
8287
8288static bool delay_autosuspend(struct r8152 *tp)
8289{
8290 bool sw_linking = !!netif_carrier_ok(tp->netdev);
8291 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
8292
8293 /* This means a linking change occurs and the driver doesn't detect it,
8294 * yet. If the driver has disabled tx/rx and hw is linking on, the
8295 * device wouldn't wake up by receiving any packet.
8296 */
8297 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
8298 return true;
8299
8300 /* If the linking down is occurred by nway, the device may miss the
8301 * linking change event. And it wouldn't wake when linking on.
8302 */
8303 if (!sw_linking && tp->rtl_ops.in_nway(tp))
8304 return true;
8305 else if (!skb_queue_empty(&tp->tx_queue))
8306 return true;
8307 else
8308 return false;
8309}
8310
8311static int rtl8152_runtime_resume(struct r8152 *tp)
8312{
8313 struct net_device *netdev = tp->netdev;
8314
8315 if (netif_running(netdev) && netdev->flags & IFF_UP) {
8316 struct napi_struct *napi = &tp->napi;
8317
8318 tp->rtl_ops.autosuspend_en(tp, false);
8319 napi_disable(napi);
8320 set_bit(WORK_ENABLE, &tp->flags);
8321
8322 if (netif_carrier_ok(netdev)) {
8323 if (rtl8152_get_speed(tp) & LINK_STATUS) {
8324 rtl_start_rx(tp);
8325 } else {
8326 netif_carrier_off(netdev);
8327 tp->rtl_ops.disable(tp);
8328 netif_info(tp, link, netdev, "linking down\n");
8329 }
8330 }
8331
8332 napi_enable(napi);
8333 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8334 smp_mb__after_atomic();
8335
8336 if (!list_empty(&tp->rx_done))
8337 napi_schedule(&tp->napi);
8338
8339 usb_submit_urb(tp->intr_urb, GFP_NOIO);
8340 } else {
8341 if (netdev->flags & IFF_UP)
8342 tp->rtl_ops.autosuspend_en(tp, false);
8343
8344 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8345 }
8346
8347 return 0;
8348}
8349
8350static int rtl8152_system_resume(struct r8152 *tp)
8351{
8352 struct net_device *netdev = tp->netdev;
8353
8354 netif_device_attach(netdev);
8355
8356 if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
8357 tp->rtl_ops.up(tp);
8358 netif_carrier_off(netdev);
8359 set_bit(WORK_ENABLE, &tp->flags);
8360 usb_submit_urb(tp->intr_urb, GFP_NOIO);
8361 }
8362
8363 return 0;
8364}
8365
8366static int rtl8152_runtime_suspend(struct r8152 *tp)
8367{
8368 struct net_device *netdev = tp->netdev;
8369 int ret = 0;
8370
8371 if (!tp->rtl_ops.autosuspend_en)
8372 return -EBUSY;
8373
8374 set_bit(SELECTIVE_SUSPEND, &tp->flags);
8375 smp_mb__after_atomic();
8376
8377 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8378 u32 rcr = 0;
8379
8380 if (netif_carrier_ok(netdev)) {
8381 u32 ocp_data;
8382
8383 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
8384 ocp_data = rcr & ~RCR_ACPT_ALL;
8385 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8386 rxdy_gated_en(tp, true);
8387 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
8388 PLA_OOB_CTRL);
8389 if (!(ocp_data & RXFIFO_EMPTY)) {
8390 rxdy_gated_en(tp, false);
8391 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8392 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8393 smp_mb__after_atomic();
8394 ret = -EBUSY;
8395 goto out1;
8396 }
8397 }
8398
8399 clear_bit(WORK_ENABLE, &tp->flags);
8400 usb_kill_urb(tp->intr_urb);
8401
8402 tp->rtl_ops.autosuspend_en(tp, true);
8403
8404 if (netif_carrier_ok(netdev)) {
8405 struct napi_struct *napi = &tp->napi;
8406
8407 napi_disable(napi);
8408 rtl_stop_rx(tp);
8409 rxdy_gated_en(tp, false);
8410 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8411 napi_enable(napi);
8412 }
8413
8414 if (delay_autosuspend(tp)) {
8415 rtl8152_runtime_resume(tp);
8416 ret = -EBUSY;
8417 }
8418 }
8419
8420out1:
8421 return ret;
8422}
8423
8424static int rtl8152_system_suspend(struct r8152 *tp)
8425{
8426 struct net_device *netdev = tp->netdev;
8427
8428 netif_device_detach(netdev);
8429
8430 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8431 struct napi_struct *napi = &tp->napi;
8432
8433 clear_bit(WORK_ENABLE, &tp->flags);
8434 usb_kill_urb(tp->intr_urb);
8435 tasklet_disable(&tp->tx_tl);
8436 napi_disable(napi);
8437 cancel_delayed_work_sync(&tp->schedule);
8438 tp->rtl_ops.down(tp);
8439 napi_enable(napi);
8440 tasklet_enable(&tp->tx_tl);
8441 }
8442
8443 return 0;
8444}
8445
8446static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
8447{
8448 struct r8152 *tp = usb_get_intfdata(intf);
8449 int ret;
8450
8451 mutex_lock(&tp->control);
8452
8453 if (PMSG_IS_AUTO(message))
8454 ret = rtl8152_runtime_suspend(tp);
8455 else
8456 ret = rtl8152_system_suspend(tp);
8457
8458 mutex_unlock(&tp->control);
8459
8460 return ret;
8461}
8462
8463static int rtl8152_resume(struct usb_interface *intf)
8464{
8465 struct r8152 *tp = usb_get_intfdata(intf);
8466 int ret;
8467
8468 mutex_lock(&tp->control);
8469
8470 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
8471 ret = rtl8152_runtime_resume(tp);
8472 else
8473 ret = rtl8152_system_resume(tp);
8474
8475 mutex_unlock(&tp->control);
8476
8477 return ret;
8478}
8479
8480static int rtl8152_reset_resume(struct usb_interface *intf)
8481{
8482 struct r8152 *tp = usb_get_intfdata(intf);
8483
8484 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8485 tp->rtl_ops.init(tp);
8486 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
8487 set_ethernet_addr(tp, true);
8488 return rtl8152_resume(intf);
8489}
8490
8491static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8492{
8493 struct r8152 *tp = netdev_priv(dev);
8494
8495 if (usb_autopm_get_interface(tp->intf) < 0)
8496 return;
8497
8498 if (!rtl_can_wakeup(tp)) {
8499 wol->supported = 0;
8500 wol->wolopts = 0;
8501 } else {
8502 mutex_lock(&tp->control);
8503 wol->supported = WAKE_ANY;
8504 wol->wolopts = __rtl_get_wol(tp);
8505 mutex_unlock(&tp->control);
8506 }
8507
8508 usb_autopm_put_interface(tp->intf);
8509}
8510
8511static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8512{
8513 struct r8152 *tp = netdev_priv(dev);
8514 int ret;
8515
8516 if (!rtl_can_wakeup(tp))
8517 return -EOPNOTSUPP;
8518
8519 if (wol->wolopts & ~WAKE_ANY)
8520 return -EINVAL;
8521
8522 ret = usb_autopm_get_interface(tp->intf);
8523 if (ret < 0)
8524 goto out_set_wol;
8525
8526 mutex_lock(&tp->control);
8527
8528 __rtl_set_wol(tp, wol->wolopts);
8529 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
8530
8531 mutex_unlock(&tp->control);
8532
8533 usb_autopm_put_interface(tp->intf);
8534
8535out_set_wol:
8536 return ret;
8537}
8538
8539static u32 rtl8152_get_msglevel(struct net_device *dev)
8540{
8541 struct r8152 *tp = netdev_priv(dev);
8542
8543 return tp->msg_enable;
8544}
8545
8546static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
8547{
8548 struct r8152 *tp = netdev_priv(dev);
8549
8550 tp->msg_enable = value;
8551}
8552
8553static void rtl8152_get_drvinfo(struct net_device *netdev,
8554 struct ethtool_drvinfo *info)
8555{
8556 struct r8152 *tp = netdev_priv(netdev);
8557
8558 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
8559 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
8560 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
8561 if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
8562 strlcpy(info->fw_version, tp->rtl_fw.version,
8563 sizeof(info->fw_version));
8564}
8565
8566static
8567int rtl8152_get_link_ksettings(struct net_device *netdev,
8568 struct ethtool_link_ksettings *cmd)
8569{
8570 struct r8152 *tp = netdev_priv(netdev);
8571 int ret;
8572
8573 if (!tp->mii.mdio_read)
8574 return -EOPNOTSUPP;
8575
8576 ret = usb_autopm_get_interface(tp->intf);
8577 if (ret < 0)
8578 goto out;
8579
8580 mutex_lock(&tp->control);
8581
8582 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
8583
8584 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8585 cmd->link_modes.supported, tp->support_2500full);
8586
8587 if (tp->support_2500full) {
8588 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8589 cmd->link_modes.advertising,
8590 ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);
8591
8592 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8593 cmd->link_modes.lp_advertising,
8594 ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);
8595
8596 if (is_speed_2500(rtl8152_get_speed(tp)))
8597 cmd->base.speed = SPEED_2500;
8598 }
8599
8600 mutex_unlock(&tp->control);
8601
8602 usb_autopm_put_interface(tp->intf);
8603
8604out:
8605 return ret;
8606}
8607
8608static int rtl8152_set_link_ksettings(struct net_device *dev,
8609 const struct ethtool_link_ksettings *cmd)
8610{
8611 struct r8152 *tp = netdev_priv(dev);
8612 u32 advertising = 0;
8613 int ret;
8614
8615 ret = usb_autopm_get_interface(tp->intf);
8616 if (ret < 0)
8617 goto out;
8618
8619 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
8620 cmd->link_modes.advertising))
8621 advertising |= RTL_ADVERTISED_10_HALF;
8622
8623 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
8624 cmd->link_modes.advertising))
8625 advertising |= RTL_ADVERTISED_10_FULL;
8626
8627 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
8628 cmd->link_modes.advertising))
8629 advertising |= RTL_ADVERTISED_100_HALF;
8630
8631 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
8632 cmd->link_modes.advertising))
8633 advertising |= RTL_ADVERTISED_100_FULL;
8634
8635 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
8636 cmd->link_modes.advertising))
8637 advertising |= RTL_ADVERTISED_1000_HALF;
8638
8639 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
8640 cmd->link_modes.advertising))
8641 advertising |= RTL_ADVERTISED_1000_FULL;
8642
8643 if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8644 cmd->link_modes.advertising))
8645 advertising |= RTL_ADVERTISED_2500_FULL;
8646
8647 mutex_lock(&tp->control);
8648
8649 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
8650 cmd->base.duplex, advertising);
8651 if (!ret) {
8652 tp->autoneg = cmd->base.autoneg;
8653 tp->speed = cmd->base.speed;
8654 tp->duplex = cmd->base.duplex;
8655 tp->advertising = advertising;
8656 }
8657
8658 mutex_unlock(&tp->control);
8659
8660 usb_autopm_put_interface(tp->intf);
8661
8662out:
8663 return ret;
8664}
8665
8666static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
8667 "tx_packets",
8668 "rx_packets",
8669 "tx_errors",
8670 "rx_errors",
8671 "rx_missed",
8672 "align_errors",
8673 "tx_single_collisions",
8674 "tx_multi_collisions",
8675 "rx_unicast",
8676 "rx_broadcast",
8677 "rx_multicast",
8678 "tx_aborted",
8679 "tx_underrun",
8680};
8681
8682static int rtl8152_get_sset_count(struct net_device *dev, int sset)
8683{
8684 switch (sset) {
8685 case ETH_SS_STATS:
8686 return ARRAY_SIZE(rtl8152_gstrings);
8687 default:
8688 return -EOPNOTSUPP;
8689 }
8690}
8691
8692static void rtl8152_get_ethtool_stats(struct net_device *dev,
8693 struct ethtool_stats *stats, u64 *data)
8694{
8695 struct r8152 *tp = netdev_priv(dev);
8696 struct tally_counter tally;
8697
8698 if (usb_autopm_get_interface(tp->intf) < 0)
8699 return;
8700
8701 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
8702
8703 usb_autopm_put_interface(tp->intf);
8704
8705 data[0] = le64_to_cpu(tally.tx_packets);
8706 data[1] = le64_to_cpu(tally.rx_packets);
8707 data[2] = le64_to_cpu(tally.tx_errors);
8708 data[3] = le32_to_cpu(tally.rx_errors);
8709 data[4] = le16_to_cpu(tally.rx_missed);
8710 data[5] = le16_to_cpu(tally.align_errors);
8711 data[6] = le32_to_cpu(tally.tx_one_collision);
8712 data[7] = le32_to_cpu(tally.tx_multi_collision);
8713 data[8] = le64_to_cpu(tally.rx_unicast);
8714 data[9] = le64_to_cpu(tally.rx_broadcast);
8715 data[10] = le32_to_cpu(tally.rx_multicast);
8716 data[11] = le16_to_cpu(tally.tx_aborted);
8717 data[12] = le16_to_cpu(tally.tx_underrun);
8718}
8719
8720static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
8721{
8722 switch (stringset) {
8723 case ETH_SS_STATS:
8724 memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
8725 break;
8726 }
8727}
8728
8729static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8730{
8731 u32 lp, adv, supported = 0;
8732 u16 val;
8733
8734 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
8735 supported = mmd_eee_cap_to_ethtool_sup_t(val);
8736
8737 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
8738 adv = mmd_eee_adv_to_ethtool_adv_t(val);
8739
8740 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
8741 lp = mmd_eee_adv_to_ethtool_adv_t(val);
8742
8743 eee->eee_enabled = tp->eee_en;
8744 eee->eee_active = !!(supported & adv & lp);
8745 eee->supported = supported;
8746 eee->advertised = tp->eee_adv;
8747 eee->lp_advertised = lp;
8748
8749 return 0;
8750}
8751
8752static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
8753{
8754 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
8755
8756 tp->eee_en = eee->eee_enabled;
8757 tp->eee_adv = val;
8758
8759 rtl_eee_enable(tp, tp->eee_en);
8760
8761 return 0;
8762}
8763
8764static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8765{
8766 u32 lp, adv, supported = 0;
8767 u16 val;
8768
8769 val = ocp_reg_read(tp, OCP_EEE_ABLE);
8770 supported = mmd_eee_cap_to_ethtool_sup_t(val);
8771
8772 val = ocp_reg_read(tp, OCP_EEE_ADV);
8773 adv = mmd_eee_adv_to_ethtool_adv_t(val);
8774
8775 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
8776 lp = mmd_eee_adv_to_ethtool_adv_t(val);
8777
8778 eee->eee_enabled = tp->eee_en;
8779 eee->eee_active = !!(supported & adv & lp);
8780 eee->supported = supported;
8781 eee->advertised = tp->eee_adv;
8782 eee->lp_advertised = lp;
8783
8784 return 0;
8785}
8786
8787static int
8788rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
8789{
8790 struct r8152 *tp = netdev_priv(net);
8791 int ret;
8792
8793 if (!tp->rtl_ops.eee_get) {
8794 ret = -EOPNOTSUPP;
8795 goto out;
8796 }
8797
8798 ret = usb_autopm_get_interface(tp->intf);
8799 if (ret < 0)
8800 goto out;
8801
8802 mutex_lock(&tp->control);
8803
8804 ret = tp->rtl_ops.eee_get(tp, edata);
8805
8806 mutex_unlock(&tp->control);
8807
8808 usb_autopm_put_interface(tp->intf);
8809
8810out:
8811 return ret;
8812}
8813
8814static int
8815rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
8816{
8817 struct r8152 *tp = netdev_priv(net);
8818 int ret;
8819
8820 if (!tp->rtl_ops.eee_set) {
8821 ret = -EOPNOTSUPP;
8822 goto out;
8823 }
8824
8825 ret = usb_autopm_get_interface(tp->intf);
8826 if (ret < 0)
8827 goto out;
8828
8829 mutex_lock(&tp->control);
8830
8831 ret = tp->rtl_ops.eee_set(tp, edata);
8832 if (!ret)
8833 ret = mii_nway_restart(&tp->mii);
8834
8835 mutex_unlock(&tp->control);
8836
8837 usb_autopm_put_interface(tp->intf);
8838
8839out:
8840 return ret;
8841}
8842
8843static int rtl8152_nway_reset(struct net_device *dev)
8844{
8845 struct r8152 *tp = netdev_priv(dev);
8846 int ret;
8847
8848 ret = usb_autopm_get_interface(tp->intf);
8849 if (ret < 0)
8850 goto out;
8851
8852 mutex_lock(&tp->control);
8853
8854 ret = mii_nway_restart(&tp->mii);
8855
8856 mutex_unlock(&tp->control);
8857
8858 usb_autopm_put_interface(tp->intf);
8859
8860out:
8861 return ret;
8862}
8863
8864static int rtl8152_get_coalesce(struct net_device *netdev,
8865 struct ethtool_coalesce *coalesce)
8866{
8867 struct r8152 *tp = netdev_priv(netdev);
8868
8869 switch (tp->version) {
8870 case RTL_VER_01:
8871 case RTL_VER_02:
8872 case RTL_VER_07:
8873 return -EOPNOTSUPP;
8874 default:
8875 break;
8876 }
8877
8878 coalesce->rx_coalesce_usecs = tp->coalesce;
8879
8880 return 0;
8881}
8882
8883static int rtl8152_set_coalesce(struct net_device *netdev,
8884 struct ethtool_coalesce *coalesce)
8885{
8886 struct r8152 *tp = netdev_priv(netdev);
8887 int ret;
8888
8889 switch (tp->version) {
8890 case RTL_VER_01:
8891 case RTL_VER_02:
8892 case RTL_VER_07:
8893 return -EOPNOTSUPP;
8894 default:
8895 break;
8896 }
8897
8898 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
8899 return -EINVAL;
8900
8901 ret = usb_autopm_get_interface(tp->intf);
8902 if (ret < 0)
8903 return ret;
8904
8905 mutex_lock(&tp->control);
8906
8907 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
8908 tp->coalesce = coalesce->rx_coalesce_usecs;
8909
8910 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
8911 netif_stop_queue(netdev);
8912 napi_disable(&tp->napi);
8913 tp->rtl_ops.disable(tp);
8914 tp->rtl_ops.enable(tp);
8915 rtl_start_rx(tp);
8916 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
8917 _rtl8152_set_rx_mode(netdev);
8918 napi_enable(&tp->napi);
8919 netif_wake_queue(netdev);
8920 }
8921 }
8922
8923 mutex_unlock(&tp->control);
8924
8925 usb_autopm_put_interface(tp->intf);
8926
8927 return ret;
8928}
8929
8930static int rtl8152_get_tunable(struct net_device *netdev,
8931 const struct ethtool_tunable *tunable, void *d)
8932{
8933 struct r8152 *tp = netdev_priv(netdev);
8934
8935 switch (tunable->id) {
8936 case ETHTOOL_RX_COPYBREAK:
8937 *(u32 *)d = tp->rx_copybreak;
8938 break;
8939 default:
8940 return -EOPNOTSUPP;
8941 }
8942
8943 return 0;
8944}
8945
8946static int rtl8152_set_tunable(struct net_device *netdev,
8947 const struct ethtool_tunable *tunable,
8948 const void *d)
8949{
8950 struct r8152 *tp = netdev_priv(netdev);
8951 u32 val;
8952
8953 switch (tunable->id) {
8954 case ETHTOOL_RX_COPYBREAK:
8955 val = *(u32 *)d;
8956 if (val < ETH_ZLEN) {
8957 netif_err(tp, rx_err, netdev,
8958 "Invalid rx copy break value\n");
8959 return -EINVAL;
8960 }
8961
8962 if (tp->rx_copybreak != val) {
8963 if (netdev->flags & IFF_UP) {
8964 mutex_lock(&tp->control);
8965 napi_disable(&tp->napi);
8966 tp->rx_copybreak = val;
8967 napi_enable(&tp->napi);
8968 mutex_unlock(&tp->control);
8969 } else {
8970 tp->rx_copybreak = val;
8971 }
8972 }
8973 break;
8974 default:
8975 return -EOPNOTSUPP;
8976 }
8977
8978 return 0;
8979}
8980
8981static void rtl8152_get_ringparam(struct net_device *netdev,
8982 struct ethtool_ringparam *ring)
8983{
8984 struct r8152 *tp = netdev_priv(netdev);
8985
8986 ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
8987 ring->rx_pending = tp->rx_pending;
8988}
8989
8990static int rtl8152_set_ringparam(struct net_device *netdev,
8991 struct ethtool_ringparam *ring)
8992{
8993 struct r8152 *tp = netdev_priv(netdev);
8994
8995 if (ring->rx_pending < (RTL8152_MAX_RX * 2))
8996 return -EINVAL;
8997
8998 if (tp->rx_pending != ring->rx_pending) {
8999 if (netdev->flags & IFF_UP) {
9000 mutex_lock(&tp->control);
9001 napi_disable(&tp->napi);
9002 tp->rx_pending = ring->rx_pending;
9003 napi_enable(&tp->napi);
9004 mutex_unlock(&tp->control);
9005 } else {
9006 tp->rx_pending = ring->rx_pending;
9007 }
9008 }
9009
9010 return 0;
9011}
9012
9013static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9014{
9015 struct r8152 *tp = netdev_priv(netdev);
9016 u16 bmcr, lcladv, rmtadv;
9017 u8 cap;
9018
9019 if (usb_autopm_get_interface(tp->intf) < 0)
9020 return;
9021
9022 mutex_lock(&tp->control);
9023
9024 bmcr = r8152_mdio_read(tp, MII_BMCR);
9025 lcladv = r8152_mdio_read(tp, MII_ADVERTISE);
9026 rmtadv = r8152_mdio_read(tp, MII_LPA);
9027
9028 mutex_unlock(&tp->control);
9029
9030 usb_autopm_put_interface(tp->intf);
9031
9032 if (!(bmcr & BMCR_ANENABLE)) {
9033 pause->autoneg = 0;
9034 pause->rx_pause = 0;
9035 pause->tx_pause = 0;
9036 return;
9037 }
9038
9039 pause->autoneg = 1;
9040
9041 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
9042
9043 if (cap & FLOW_CTRL_RX)
9044 pause->rx_pause = 1;
9045
9046 if (cap & FLOW_CTRL_TX)
9047 pause->tx_pause = 1;
9048}
9049
9050static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9051{
9052 struct r8152 *tp = netdev_priv(netdev);
9053 u16 old, new1;
9054 u8 cap = 0;
9055 int ret;
9056
9057 ret = usb_autopm_get_interface(tp->intf);
9058 if (ret < 0)
9059 return ret;
9060
9061 mutex_lock(&tp->control);
9062
9063 if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) {
9064 ret = -EINVAL;
9065 goto out;
9066 }
9067
9068 if (pause->rx_pause)
9069 cap |= FLOW_CTRL_RX;
9070
9071 if (pause->tx_pause)
9072 cap |= FLOW_CTRL_TX;
9073
9074 old = r8152_mdio_read(tp, MII_ADVERTISE);
9075 new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap);
9076 if (old != new1)
9077 r8152_mdio_write(tp, MII_ADVERTISE, new1);
9078
9079out:
9080 mutex_unlock(&tp->control);
9081 usb_autopm_put_interface(tp->intf);
9082
9083 return ret;
9084}
9085
9086static const struct ethtool_ops ops = {
9087 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
9088 .get_drvinfo = rtl8152_get_drvinfo,
9089 .get_link = ethtool_op_get_link,
9090 .nway_reset = rtl8152_nway_reset,
9091 .get_msglevel = rtl8152_get_msglevel,
9092 .set_msglevel = rtl8152_set_msglevel,
9093 .get_wol = rtl8152_get_wol,
9094 .set_wol = rtl8152_set_wol,
9095 .get_strings = rtl8152_get_strings,
9096 .get_sset_count = rtl8152_get_sset_count,
9097 .get_ethtool_stats = rtl8152_get_ethtool_stats,
9098 .get_coalesce = rtl8152_get_coalesce,
9099 .set_coalesce = rtl8152_set_coalesce,
9100 .get_eee = rtl_ethtool_get_eee,
9101 .set_eee = rtl_ethtool_set_eee,
9102 .get_link_ksettings = rtl8152_get_link_ksettings,
9103 .set_link_ksettings = rtl8152_set_link_ksettings,
9104 .get_tunable = rtl8152_get_tunable,
9105 .set_tunable = rtl8152_set_tunable,
9106 .get_ringparam = rtl8152_get_ringparam,
9107 .set_ringparam = rtl8152_set_ringparam,
9108 .get_pauseparam = rtl8152_get_pauseparam,
9109 .set_pauseparam = rtl8152_set_pauseparam,
9110};
9111
9112static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
9113{
9114 struct r8152 *tp = netdev_priv(netdev);
9115 struct mii_ioctl_data *data = if_mii(rq);
9116 int res;
9117
9118 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9119 return -ENODEV;
9120
9121 res = usb_autopm_get_interface(tp->intf);
9122 if (res < 0)
9123 goto out;
9124
9125 switch (cmd) {
9126 case SIOCGMIIPHY:
9127 data->phy_id = R8152_PHY_ID; /* Internal PHY */
9128 break;
9129
9130 case SIOCGMIIREG:
9131 mutex_lock(&tp->control);
9132 data->val_out = r8152_mdio_read(tp, data->reg_num);
9133 mutex_unlock(&tp->control);
9134 break;
9135
9136 case SIOCSMIIREG:
9137 if (!capable(CAP_NET_ADMIN)) {
9138 res = -EPERM;
9139 break;
9140 }
9141 mutex_lock(&tp->control);
9142 r8152_mdio_write(tp, data->reg_num, data->val_in);
9143 mutex_unlock(&tp->control);
9144 break;
9145
9146 default:
9147 res = -EOPNOTSUPP;
9148 }
9149
9150 usb_autopm_put_interface(tp->intf);
9151
9152out:
9153 return res;
9154}
9155
9156static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
9157{
9158 struct r8152 *tp = netdev_priv(dev);
9159 int ret;
9160
9161 switch (tp->version) {
9162 case RTL_VER_01:
9163 case RTL_VER_02:
9164 case RTL_VER_07:
9165 dev->mtu = new_mtu;
9166 return 0;
9167 default:
9168 break;
9169 }
9170
9171 ret = usb_autopm_get_interface(tp->intf);
9172 if (ret < 0)
9173 return ret;
9174
9175 mutex_lock(&tp->control);
9176
9177 dev->mtu = new_mtu;
9178
9179 if (netif_running(dev)) {
9180 if (tp->rtl_ops.change_mtu)
9181 tp->rtl_ops.change_mtu(tp);
9182
9183 if (netif_carrier_ok(dev)) {
9184 netif_stop_queue(dev);
9185 napi_disable(&tp->napi);
9186 tasklet_disable(&tp->tx_tl);
9187 tp->rtl_ops.disable(tp);
9188 tp->rtl_ops.enable(tp);
9189 rtl_start_rx(tp);
9190 tasklet_enable(&tp->tx_tl);
9191 napi_enable(&tp->napi);
9192 rtl8152_set_rx_mode(dev);
9193 netif_wake_queue(dev);
9194 }
9195 }
9196
9197 mutex_unlock(&tp->control);
9198
9199 usb_autopm_put_interface(tp->intf);
9200
9201 return ret;
9202}
9203
9204static const struct net_device_ops rtl8152_netdev_ops = {
9205 .ndo_open = rtl8152_open,
9206 .ndo_stop = rtl8152_close,
9207 .ndo_do_ioctl = rtl8152_ioctl,
9208 .ndo_start_xmit = rtl8152_start_xmit,
9209 .ndo_tx_timeout = rtl8152_tx_timeout,
9210 .ndo_set_features = rtl8152_set_features,
9211 .ndo_set_rx_mode = rtl8152_set_rx_mode,
9212 .ndo_set_mac_address = rtl8152_set_mac_address,
9213 .ndo_change_mtu = rtl8152_change_mtu,
9214 .ndo_validate_addr = eth_validate_addr,
9215 .ndo_features_check = rtl8152_features_check,
9216};
9217
9218static void rtl8152_unload(struct r8152 *tp)
9219{
9220 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9221 return;
9222
9223 if (tp->version != RTL_VER_01)
9224 r8152_power_cut_en(tp, true);
9225}
9226
9227static void rtl8153_unload(struct r8152 *tp)
9228{
9229 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9230 return;
9231
9232 r8153_power_cut_en(tp, false);
9233}
9234
9235static void rtl8153b_unload(struct r8152 *tp)
9236{
9237 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9238 return;
9239
9240 r8153b_power_cut_en(tp, false);
9241}
9242
9243static int rtl_ops_init(struct r8152 *tp)
9244{
9245 struct rtl_ops *ops = &tp->rtl_ops;
9246 int ret = 0;
9247
9248 switch (tp->version) {
9249 case RTL_VER_01:
9250 case RTL_VER_02:
9251 case RTL_VER_07:
9252 ops->init = r8152b_init;
9253 ops->enable = rtl8152_enable;
9254 ops->disable = rtl8152_disable;
9255 ops->up = rtl8152_up;
9256 ops->down = rtl8152_down;
9257 ops->unload = rtl8152_unload;
9258 ops->eee_get = r8152_get_eee;
9259 ops->eee_set = r8152_set_eee;
9260 ops->in_nway = rtl8152_in_nway;
9261 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
9262 ops->autosuspend_en = rtl_runtime_suspend_enable;
9263 tp->rx_buf_sz = 16 * 1024;
9264 tp->eee_en = true;
9265 tp->eee_adv = MDIO_EEE_100TX;
9266 break;
9267
9268 case RTL_VER_03:
9269 case RTL_VER_04:
9270 case RTL_VER_05:
9271 case RTL_VER_06:
9272 ops->init = r8153_init;
9273 ops->enable = rtl8153_enable;
9274 ops->disable = rtl8153_disable;
9275 ops->up = rtl8153_up;
9276 ops->down = rtl8153_down;
9277 ops->unload = rtl8153_unload;
9278 ops->eee_get = r8153_get_eee;
9279 ops->eee_set = r8152_set_eee;
9280 ops->in_nway = rtl8153_in_nway;
9281 ops->hw_phy_cfg = r8153_hw_phy_cfg;
9282 ops->autosuspend_en = rtl8153_runtime_enable;
9283 ops->change_mtu = rtl8153_change_mtu;
9284 if (tp->udev->speed < USB_SPEED_SUPER)
9285 tp->rx_buf_sz = 16 * 1024;
9286 else
9287 tp->rx_buf_sz = 32 * 1024;
9288 tp->eee_en = true;
9289 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9290 break;
9291
9292 case RTL_VER_08:
9293 case RTL_VER_09:
9294 ops->init = r8153b_init;
9295 ops->enable = rtl8153_enable;
9296 ops->disable = rtl8153_disable;
9297 ops->up = rtl8153b_up;
9298 ops->down = rtl8153b_down;
9299 ops->unload = rtl8153b_unload;
9300 ops->eee_get = r8153_get_eee;
9301 ops->eee_set = r8152_set_eee;
9302 ops->in_nway = rtl8153_in_nway;
9303 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
9304 ops->autosuspend_en = rtl8153b_runtime_enable;
9305 ops->change_mtu = rtl8153_change_mtu;
9306 tp->rx_buf_sz = 32 * 1024;
9307 tp->eee_en = true;
9308 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9309 break;
9310
9311 case RTL_VER_11:
9312 tp->eee_en = true;
9313 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9314 fallthrough;
9315 case RTL_VER_10:
9316 ops->init = r8156_init;
9317 ops->enable = rtl8156_enable;
9318 ops->disable = rtl8153_disable;
9319 ops->up = rtl8156_up;
9320 ops->down = rtl8156_down;
9321 ops->unload = rtl8153_unload;
9322 ops->eee_get = r8153_get_eee;
9323 ops->eee_set = r8152_set_eee;
9324 ops->in_nway = rtl8153_in_nway;
9325 ops->hw_phy_cfg = r8156_hw_phy_cfg;
9326 ops->autosuspend_en = rtl8156_runtime_enable;
9327 ops->change_mtu = rtl8156_change_mtu;
9328 tp->rx_buf_sz = 48 * 1024;
9329 tp->support_2500full = 1;
9330 break;
9331
9332 case RTL_VER_12:
9333 case RTL_VER_13:
9334 tp->support_2500full = 1;
9335 fallthrough;
9336 case RTL_VER_15:
9337 tp->eee_en = true;
9338 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9339 ops->init = r8156b_init;
9340 ops->enable = rtl8156b_enable;
9341 ops->disable = rtl8153_disable;
9342 ops->up = rtl8156_up;
9343 ops->down = rtl8156_down;
9344 ops->unload = rtl8153_unload;
9345 ops->eee_get = r8153_get_eee;
9346 ops->eee_set = r8152_set_eee;
9347 ops->in_nway = rtl8153_in_nway;
9348 ops->hw_phy_cfg = r8156b_hw_phy_cfg;
9349 ops->autosuspend_en = rtl8156_runtime_enable;
9350 ops->change_mtu = rtl8156_change_mtu;
9351 tp->rx_buf_sz = 48 * 1024;
9352 break;
9353
9354 case RTL_VER_14:
9355 ops->init = r8153c_init;
9356 ops->enable = rtl8153_enable;
9357 ops->disable = rtl8153_disable;
9358 ops->up = rtl8153c_up;
9359 ops->down = rtl8153b_down;
9360 ops->unload = rtl8153_unload;
9361 ops->eee_get = r8153_get_eee;
9362 ops->eee_set = r8152_set_eee;
9363 ops->in_nway = rtl8153_in_nway;
9364 ops->hw_phy_cfg = r8153c_hw_phy_cfg;
9365 ops->autosuspend_en = rtl8153c_runtime_enable;
9366 ops->change_mtu = rtl8153c_change_mtu;
9367 tp->rx_buf_sz = 32 * 1024;
9368 tp->eee_en = true;
9369 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9370 break;
9371
9372 default:
9373 ret = -ENODEV;
9374 dev_err(&tp->intf->dev, "Unknown Device\n");
9375 break;
9376 }
9377
9378 return ret;
9379}
9380
9381#define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw"
9382#define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
9383#define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
9384#define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
9385#define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw"
9386#define FIRMWARE_8156A_2 "rtl_nic/rtl8156a-2.fw"
9387#define FIRMWARE_8156B_2 "rtl_nic/rtl8156b-2.fw"
9388
9389MODULE_FIRMWARE(FIRMWARE_8153A_2);
9390MODULE_FIRMWARE(FIRMWARE_8153A_3);
9391MODULE_FIRMWARE(FIRMWARE_8153A_4);
9392MODULE_FIRMWARE(FIRMWARE_8153B_2);
9393MODULE_FIRMWARE(FIRMWARE_8153C_1);
9394MODULE_FIRMWARE(FIRMWARE_8156A_2);
9395MODULE_FIRMWARE(FIRMWARE_8156B_2);
9396
9397static int rtl_fw_init(struct r8152 *tp)
9398{
9399 struct rtl_fw *rtl_fw = &tp->rtl_fw;
9400
9401 switch (tp->version) {
9402 case RTL_VER_04:
9403 rtl_fw->fw_name = FIRMWARE_8153A_2;
9404 rtl_fw->pre_fw = r8153_pre_firmware_1;
9405 rtl_fw->post_fw = r8153_post_firmware_1;
9406 break;
9407 case RTL_VER_05:
9408 rtl_fw->fw_name = FIRMWARE_8153A_3;
9409 rtl_fw->pre_fw = r8153_pre_firmware_2;
9410 rtl_fw->post_fw = r8153_post_firmware_2;
9411 break;
9412 case RTL_VER_06:
9413 rtl_fw->fw_name = FIRMWARE_8153A_4;
9414 rtl_fw->post_fw = r8153_post_firmware_3;
9415 break;
9416 case RTL_VER_09:
9417 rtl_fw->fw_name = FIRMWARE_8153B_2;
9418 rtl_fw->pre_fw = r8153b_pre_firmware_1;
9419 rtl_fw->post_fw = r8153b_post_firmware_1;
9420 break;
9421 case RTL_VER_11:
9422 rtl_fw->fw_name = FIRMWARE_8156A_2;
9423 rtl_fw->post_fw = r8156a_post_firmware_1;
9424 break;
9425 case RTL_VER_13:
9426 case RTL_VER_15:
9427 rtl_fw->fw_name = FIRMWARE_8156B_2;
9428 break;
9429 case RTL_VER_14:
9430 rtl_fw->fw_name = FIRMWARE_8153C_1;
9431 rtl_fw->pre_fw = r8153b_pre_firmware_1;
9432 rtl_fw->post_fw = r8153c_post_firmware_1;
9433 break;
9434 default:
9435 break;
9436 }
9437
9438 return 0;
9439}
9440
9441u8 rtl8152_get_version(struct usb_interface *intf)
9442{
9443 struct usb_device *udev = interface_to_usbdev(intf);
9444 u32 ocp_data = 0;
9445 __le32 *tmp;
9446 u8 version;
9447 int ret;
9448
9449 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
9450 if (!tmp)
9451 return 0;
9452
9453 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
9454 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
9455 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
9456 if (ret > 0)
9457 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
9458
9459 kfree(tmp);
9460
9461 switch (ocp_data) {
9462 case 0x4c00:
9463 version = RTL_VER_01;
9464 break;
9465 case 0x4c10:
9466 version = RTL_VER_02;
9467 break;
9468 case 0x5c00:
9469 version = RTL_VER_03;
9470 break;
9471 case 0x5c10:
9472 version = RTL_VER_04;
9473 break;
9474 case 0x5c20:
9475 version = RTL_VER_05;
9476 break;
9477 case 0x5c30:
9478 version = RTL_VER_06;
9479 break;
9480 case 0x4800:
9481 version = RTL_VER_07;
9482 break;
9483 case 0x6000:
9484 version = RTL_VER_08;
9485 break;
9486 case 0x6010:
9487 version = RTL_VER_09;
9488 break;
9489 case 0x7010:
9490 version = RTL_TEST_01;
9491 break;
9492 case 0x7020:
9493 version = RTL_VER_10;
9494 break;
9495 case 0x7030:
9496 version = RTL_VER_11;
9497 break;
9498 case 0x7400:
9499 version = RTL_VER_12;
9500 break;
9501 case 0x7410:
9502 version = RTL_VER_13;
9503 break;
9504 case 0x6400:
9505 version = RTL_VER_14;
9506 break;
9507 case 0x7420:
9508 version = RTL_VER_15;
9509 break;
9510 default:
9511 version = RTL_VER_UNKNOWN;
9512 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
9513 break;
9514 }
9515
9516 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
9517
9518 return version;
9519}
9520EXPORT_SYMBOL_GPL(rtl8152_get_version);
9521
9522static int rtl8152_probe(struct usb_interface *intf,
9523 const struct usb_device_id *id)
9524{
9525 struct usb_device *udev = interface_to_usbdev(intf);
9526 u8 version = rtl8152_get_version(intf);
9527 struct r8152 *tp;
9528 struct net_device *netdev;
9529 int ret;
9530
9531 if (version == RTL_VER_UNKNOWN)
9532 return -ENODEV;
9533
9534 if (!rtl_vendor_mode(intf))
9535 return -ENODEV;
9536
9537 usb_reset_device(udev);
9538 netdev = alloc_etherdev(sizeof(struct r8152));
9539 if (!netdev) {
9540 dev_err(&intf->dev, "Out of memory\n");
9541 return -ENOMEM;
9542 }
9543
9544 SET_NETDEV_DEV(netdev, &intf->dev);
9545 tp = netdev_priv(netdev);
9546 tp->msg_enable = 0x7FFF;
9547
9548 tp->udev = udev;
9549 tp->netdev = netdev;
9550 tp->intf = intf;
9551 tp->version = version;
9552
9553 tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0);
9554 tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0);
9555 tp->pipe_in = usb_rcvbulkpipe(udev, 1);
9556 tp->pipe_out = usb_sndbulkpipe(udev, 2);
9557 tp->pipe_intr = usb_rcvintpipe(udev, 3);
9558
9559 switch (version) {
9560 case RTL_VER_01:
9561 case RTL_VER_02:
9562 case RTL_VER_07:
9563 tp->mii.supports_gmii = 0;
9564 break;
9565 default:
9566 tp->mii.supports_gmii = 1;
9567 break;
9568 }
9569
9570 ret = rtl_ops_init(tp);
9571 if (ret)
9572 goto out;
9573
9574 rtl_fw_init(tp);
9575
9576 mutex_init(&tp->control);
9577 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
9578 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
9579 tasklet_setup(&tp->tx_tl, bottom_half);
9580 tasklet_disable(&tp->tx_tl);
9581
9582 netdev->netdev_ops = &rtl8152_netdev_ops;
9583 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
9584
9585 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9586 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
9587 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
9588 NETIF_F_HW_VLAN_CTAG_TX;
9589 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9590 NETIF_F_TSO | NETIF_F_FRAGLIST |
9591 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
9592 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
9593 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
9594 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
9595 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
9596
9597 if (tp->version == RTL_VER_01) {
9598 netdev->features &= ~NETIF_F_RXCSUM;
9599 netdev->hw_features &= ~NETIF_F_RXCSUM;
9600 }
9601
9602 if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO) {
9603 switch (le16_to_cpu(udev->descriptor.idProduct)) {
9604 case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
9605 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
9606 tp->lenovo_macpassthru = 1;
9607 }
9608 }
9609
9610 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
9611 (!strcmp(udev->serial, "000001000000") ||
9612 !strcmp(udev->serial, "000002000000"))) {
9613 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
9614 tp->dell_tb_rx_agg_bug = 1;
9615 }
9616
9617 netdev->ethtool_ops = &ops;
9618 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
9619
9620 /* MTU range: 68 - 1500 or 9194 */
9621 netdev->min_mtu = ETH_MIN_MTU;
9622 switch (tp->version) {
9623 case RTL_VER_03:
9624 case RTL_VER_04:
9625 case RTL_VER_05:
9626 case RTL_VER_06:
9627 case RTL_VER_08:
9628 case RTL_VER_09:
9629 case RTL_VER_14:
9630 netdev->max_mtu = size_to_mtu(9 * 1024);
9631 break;
9632 case RTL_VER_10:
9633 case RTL_VER_11:
9634 netdev->max_mtu = size_to_mtu(15 * 1024);
9635 break;
9636 case RTL_VER_12:
9637 case RTL_VER_13:
9638 case RTL_VER_15:
9639 netdev->max_mtu = size_to_mtu(16 * 1024);
9640 break;
9641 case RTL_VER_01:
9642 case RTL_VER_02:
9643 case RTL_VER_07:
9644 default:
9645 netdev->max_mtu = ETH_DATA_LEN;
9646 break;
9647 }
9648
9649 tp->mii.dev = netdev;
9650 tp->mii.mdio_read = read_mii_word;
9651 tp->mii.mdio_write = write_mii_word;
9652 tp->mii.phy_id_mask = 0x3f;
9653 tp->mii.reg_num_mask = 0x1f;
9654 tp->mii.phy_id = R8152_PHY_ID;
9655
9656 tp->autoneg = AUTONEG_ENABLE;
9657 tp->speed = SPEED_100;
9658 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
9659 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
9660 if (tp->mii.supports_gmii) {
9661 if (tp->support_2500full &&
9662 tp->udev->speed >= USB_SPEED_SUPER) {
9663 tp->speed = SPEED_2500;
9664 tp->advertising |= RTL_ADVERTISED_2500_FULL;
9665 } else {
9666 tp->speed = SPEED_1000;
9667 }
9668 tp->advertising |= RTL_ADVERTISED_1000_FULL;
9669 }
9670 tp->duplex = DUPLEX_FULL;
9671
9672 tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
9673 tp->rx_pending = 10 * RTL8152_MAX_RX;
9674
9675 intf->needs_remote_wakeup = 1;
9676
9677 if (!rtl_can_wakeup(tp))
9678 __rtl_set_wol(tp, 0);
9679 else
9680 tp->saved_wolopts = __rtl_get_wol(tp);
9681
9682 tp->rtl_ops.init(tp);
9683#if IS_BUILTIN(CONFIG_USB_RTL8152)
9684 /* Retry in case request_firmware() is not ready yet. */
9685 tp->rtl_fw.retry = true;
9686#endif
9687 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
9688 set_ethernet_addr(tp, false);
9689
9690 usb_set_intfdata(intf, tp);
9691
9692 if (tp->support_2500full)
9693 netif_napi_add(netdev, &tp->napi, r8152_poll, 256);
9694 else
9695 netif_napi_add(netdev, &tp->napi, r8152_poll, 64);
9696
9697 ret = register_netdev(netdev);
9698 if (ret != 0) {
9699 dev_err(&intf->dev, "couldn't register the device\n");
9700 goto out1;
9701 }
9702
9703 if (tp->saved_wolopts)
9704 device_set_wakeup_enable(&udev->dev, true);
9705 else
9706 device_set_wakeup_enable(&udev->dev, false);
9707
9708 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
9709
9710 return 0;
9711
9712out1:
9713 tasklet_kill(&tp->tx_tl);
9714 usb_set_intfdata(intf, NULL);
9715out:
9716 free_netdev(netdev);
9717 return ret;
9718}
9719
9720static void rtl8152_disconnect(struct usb_interface *intf)
9721{
9722 struct r8152 *tp = usb_get_intfdata(intf);
9723
9724 usb_set_intfdata(intf, NULL);
9725 if (tp) {
9726 rtl_set_unplug(tp);
9727
9728 unregister_netdev(tp->netdev);
9729 tasklet_kill(&tp->tx_tl);
9730 cancel_delayed_work_sync(&tp->hw_phy_work);
9731 if (tp->rtl_ops.unload)
9732 tp->rtl_ops.unload(tp);
9733 rtl8152_release_firmware(tp);
9734 free_netdev(tp->netdev);
9735 }
9736}
9737
9738#define REALTEK_USB_DEVICE(vend, prod) { \
9739 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC), \
9740}, \
9741{ \
9742 USB_DEVICE_AND_INTERFACE_INFO(vend, prod, USB_CLASS_COMM, \
9743 USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE), \
9744}
9745
9746/* table of devices that work with this driver */
9747static const struct usb_device_id rtl8152_table[] = {
9748 /* Realtek */
9749 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050),
9750 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8053),
9751 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152),
9752 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153),
9753 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8155),
9754 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8156),
9755
9756 /* Microsoft */
9757 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab),
9758 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6),
9759 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927),
9760 REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101),
9761 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f),
9762 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062),
9763 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069),
9764 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3082),
9765 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205),
9766 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c),
9767 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214),
9768 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x721e),
9769 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387),
9770 REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041),
9771 REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff),
9772 REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601),
9773 {}
9774};
9775
9776MODULE_DEVICE_TABLE(usb, rtl8152_table);
9777
9778static struct usb_driver rtl8152_driver = {
9779 .name = MODULENAME,
9780 .id_table = rtl8152_table,
9781 .probe = rtl8152_probe,
9782 .disconnect = rtl8152_disconnect,
9783 .suspend = rtl8152_suspend,
9784 .resume = rtl8152_resume,
9785 .reset_resume = rtl8152_reset_resume,
9786 .pre_reset = rtl8152_pre_reset,
9787 .post_reset = rtl8152_post_reset,
9788 .supports_autosuspend = 1,
9789 .disable_hub_initiated_lpm = 1,
9790};
9791
9792module_usb_driver(rtl8152_driver);
9793
9794MODULE_AUTHOR(DRIVER_AUTHOR);
9795MODULE_DESCRIPTION(DRIVER_DESC);
9796MODULE_LICENSE("GPL");
9797MODULE_VERSION(DRIVER_VERSION);