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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare XPCS helpers
5 *
6 * Author: Jose Abreu <Jose.Abreu@synopsys.com>
7 */
8
9#include <linux/delay.h>
10#include <linux/pcs/pcs-xpcs.h>
11#include <linux/mdio.h>
12#include <linux/phylink.h>
13#include <linux/workqueue.h>
14#include "pcs-xpcs.h"
15
16#define phylink_pcs_to_xpcs(pl_pcs) \
17 container_of((pl_pcs), struct dw_xpcs, pcs)
18
19static const int xpcs_usxgmii_features[] = {
20 ETHTOOL_LINK_MODE_Pause_BIT,
21 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
22 ETHTOOL_LINK_MODE_Autoneg_BIT,
23 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
24 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
25 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
26 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
27 __ETHTOOL_LINK_MODE_MASK_NBITS,
28};
29
30static const int xpcs_10gkr_features[] = {
31 ETHTOOL_LINK_MODE_Pause_BIT,
32 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
33 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
34 __ETHTOOL_LINK_MODE_MASK_NBITS,
35};
36
37static const int xpcs_xlgmii_features[] = {
38 ETHTOOL_LINK_MODE_Pause_BIT,
39 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
40 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
41 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
42 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
43 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
44 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
45 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
46 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
47 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
48 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
49 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
50 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
51 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
52 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
53 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
54 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
55 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
56 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
57 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
58 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
59 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
60 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
61 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
62 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
63 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
64 __ETHTOOL_LINK_MODE_MASK_NBITS,
65};
66
67static const int xpcs_sgmii_features[] = {
68 ETHTOOL_LINK_MODE_10baseT_Half_BIT,
69 ETHTOOL_LINK_MODE_10baseT_Full_BIT,
70 ETHTOOL_LINK_MODE_100baseT_Half_BIT,
71 ETHTOOL_LINK_MODE_100baseT_Full_BIT,
72 ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
73 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
74 __ETHTOOL_LINK_MODE_MASK_NBITS,
75};
76
77static const int xpcs_2500basex_features[] = {
78 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
79 ETHTOOL_LINK_MODE_Autoneg_BIT,
80 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
81 ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
82 __ETHTOOL_LINK_MODE_MASK_NBITS,
83};
84
85static const phy_interface_t xpcs_usxgmii_interfaces[] = {
86 PHY_INTERFACE_MODE_USXGMII,
87};
88
89static const phy_interface_t xpcs_10gkr_interfaces[] = {
90 PHY_INTERFACE_MODE_10GKR,
91};
92
93static const phy_interface_t xpcs_xlgmii_interfaces[] = {
94 PHY_INTERFACE_MODE_XLGMII,
95};
96
97static const phy_interface_t xpcs_sgmii_interfaces[] = {
98 PHY_INTERFACE_MODE_SGMII,
99};
100
101static const phy_interface_t xpcs_2500basex_interfaces[] = {
102 PHY_INTERFACE_MODE_2500BASEX,
103 PHY_INTERFACE_MODE_MAX,
104};
105
106enum {
107 DW_XPCS_USXGMII,
108 DW_XPCS_10GKR,
109 DW_XPCS_XLGMII,
110 DW_XPCS_SGMII,
111 DW_XPCS_2500BASEX,
112 DW_XPCS_INTERFACE_MAX,
113};
114
115struct xpcs_compat {
116 const int *supported;
117 const phy_interface_t *interface;
118 int num_interfaces;
119 int an_mode;
120 int (*pma_config)(struct dw_xpcs *xpcs);
121};
122
123struct xpcs_id {
124 u32 id;
125 u32 mask;
126 const struct xpcs_compat *compat;
127};
128
129static const struct xpcs_compat *xpcs_find_compat(const struct xpcs_id *id,
130 phy_interface_t interface)
131{
132 int i, j;
133
134 for (i = 0; i < DW_XPCS_INTERFACE_MAX; i++) {
135 const struct xpcs_compat *compat = &id->compat[i];
136
137 for (j = 0; j < compat->num_interfaces; j++)
138 if (compat->interface[j] == interface)
139 return compat;
140 }
141
142 return NULL;
143}
144
145int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface)
146{
147 const struct xpcs_compat *compat;
148
149 compat = xpcs_find_compat(xpcs->id, interface);
150 if (!compat)
151 return -ENODEV;
152
153 return compat->an_mode;
154}
155EXPORT_SYMBOL_GPL(xpcs_get_an_mode);
156
157static bool __xpcs_linkmode_supported(const struct xpcs_compat *compat,
158 enum ethtool_link_mode_bit_indices linkmode)
159{
160 int i;
161
162 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
163 if (compat->supported[i] == linkmode)
164 return true;
165
166 return false;
167}
168
169#define xpcs_linkmode_supported(compat, mode) \
170 __xpcs_linkmode_supported(compat, ETHTOOL_LINK_MODE_ ## mode ## _BIT)
171
172int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg)
173{
174 u32 reg_addr = mdiobus_c45_addr(dev, reg);
175 struct mii_bus *bus = xpcs->mdiodev->bus;
176 int addr = xpcs->mdiodev->addr;
177
178 return mdiobus_read(bus, addr, reg_addr);
179}
180
181int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val)
182{
183 u32 reg_addr = mdiobus_c45_addr(dev, reg);
184 struct mii_bus *bus = xpcs->mdiodev->bus;
185 int addr = xpcs->mdiodev->addr;
186
187 return mdiobus_write(bus, addr, reg_addr, val);
188}
189
190static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg)
191{
192 return xpcs_read(xpcs, dev, DW_VENDOR | reg);
193}
194
195static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg,
196 u16 val)
197{
198 return xpcs_write(xpcs, dev, DW_VENDOR | reg, val);
199}
200
201static int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg)
202{
203 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg);
204}
205
206static int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val)
207{
208 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val);
209}
210
211static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev)
212{
213 /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
214 unsigned int retries = 12;
215 int ret;
216
217 do {
218 msleep(50);
219 ret = xpcs_read(xpcs, dev, MDIO_CTRL1);
220 if (ret < 0)
221 return ret;
222 } while (ret & MDIO_CTRL1_RESET && --retries);
223
224 return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0;
225}
226
227static int xpcs_soft_reset(struct dw_xpcs *xpcs,
228 const struct xpcs_compat *compat)
229{
230 int ret, dev;
231
232 switch (compat->an_mode) {
233 case DW_AN_C73:
234 dev = MDIO_MMD_PCS;
235 break;
236 case DW_AN_C37_SGMII:
237 case DW_2500BASEX:
238 dev = MDIO_MMD_VEND2;
239 break;
240 default:
241 return -1;
242 }
243
244 ret = xpcs_write(xpcs, dev, MDIO_CTRL1, MDIO_CTRL1_RESET);
245 if (ret < 0)
246 return ret;
247
248 return xpcs_poll_reset(xpcs, dev);
249}
250
251#define xpcs_warn(__xpcs, __state, __args...) \
252({ \
253 if ((__state)->link) \
254 dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \
255})
256
257static int xpcs_read_fault_c73(struct dw_xpcs *xpcs,
258 struct phylink_link_state *state)
259{
260 int ret;
261
262 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1);
263 if (ret < 0)
264 return ret;
265
266 if (ret & MDIO_STAT1_FAULT) {
267 xpcs_warn(xpcs, state, "Link fault condition detected!\n");
268 return -EFAULT;
269 }
270
271 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2);
272 if (ret < 0)
273 return ret;
274
275 if (ret & MDIO_STAT2_RXFAULT)
276 xpcs_warn(xpcs, state, "Receiver fault detected!\n");
277 if (ret & MDIO_STAT2_TXFAULT)
278 xpcs_warn(xpcs, state, "Transmitter fault detected!\n");
279
280 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS);
281 if (ret < 0)
282 return ret;
283
284 if (ret & DW_RXFIFO_ERR) {
285 xpcs_warn(xpcs, state, "FIFO fault condition detected!\n");
286 return -EFAULT;
287 }
288
289 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1);
290 if (ret < 0)
291 return ret;
292
293 if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK))
294 xpcs_warn(xpcs, state, "Link is not locked!\n");
295
296 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2);
297 if (ret < 0)
298 return ret;
299
300 if (ret & MDIO_PCS_10GBRT_STAT2_ERR) {
301 xpcs_warn(xpcs, state, "Link has errors!\n");
302 return -EFAULT;
303 }
304
305 return 0;
306}
307
308static int xpcs_read_link_c73(struct dw_xpcs *xpcs, bool an)
309{
310 bool link = true;
311 int ret;
312
313 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1);
314 if (ret < 0)
315 return ret;
316
317 if (!(ret & MDIO_STAT1_LSTATUS))
318 link = false;
319
320 if (an) {
321 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
322 if (ret < 0)
323 return ret;
324
325 if (!(ret & MDIO_STAT1_LSTATUS))
326 link = false;
327 }
328
329 return link;
330}
331
332static int xpcs_get_max_usxgmii_speed(const unsigned long *supported)
333{
334 int max = SPEED_UNKNOWN;
335
336 if (phylink_test(supported, 1000baseKX_Full))
337 max = SPEED_1000;
338 if (phylink_test(supported, 2500baseX_Full))
339 max = SPEED_2500;
340 if (phylink_test(supported, 10000baseKX4_Full))
341 max = SPEED_10000;
342 if (phylink_test(supported, 10000baseKR_Full))
343 max = SPEED_10000;
344
345 return max;
346}
347
348static void xpcs_config_usxgmii(struct dw_xpcs *xpcs, int speed)
349{
350 int ret, speed_sel;
351
352 switch (speed) {
353 case SPEED_10:
354 speed_sel = DW_USXGMII_10;
355 break;
356 case SPEED_100:
357 speed_sel = DW_USXGMII_100;
358 break;
359 case SPEED_1000:
360 speed_sel = DW_USXGMII_1000;
361 break;
362 case SPEED_2500:
363 speed_sel = DW_USXGMII_2500;
364 break;
365 case SPEED_5000:
366 speed_sel = DW_USXGMII_5000;
367 break;
368 case SPEED_10000:
369 speed_sel = DW_USXGMII_10000;
370 break;
371 default:
372 /* Nothing to do here */
373 return;
374 }
375
376 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
377 if (ret < 0)
378 goto out;
379
380 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_EN);
381 if (ret < 0)
382 goto out;
383
384 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
385 if (ret < 0)
386 goto out;
387
388 ret &= ~DW_USXGMII_SS_MASK;
389 ret |= speed_sel | DW_USXGMII_FULL;
390
391 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);
392 if (ret < 0)
393 goto out;
394
395 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
396 if (ret < 0)
397 goto out;
398
399 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_RST);
400 if (ret < 0)
401 goto out;
402
403 return;
404
405out:
406 pr_err("%s: XPCS access returned %pe\n", __func__, ERR_PTR(ret));
407}
408
409static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
410 const struct xpcs_compat *compat)
411{
412 int ret, adv;
413
414 /* By default, in USXGMII mode XPCS operates at 10G baud and
415 * replicates data to achieve lower speeds. Hereby, in this
416 * default configuration we need to advertise all supported
417 * modes and not only the ones we want to use.
418 */
419
420 /* SR_AN_ADV3 */
421 adv = 0;
422 if (xpcs_linkmode_supported(compat, 2500baseX_Full))
423 adv |= DW_C73_2500KX;
424
425 /* TODO: 5000baseKR */
426
427 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv);
428 if (ret < 0)
429 return ret;
430
431 /* SR_AN_ADV2 */
432 adv = 0;
433 if (xpcs_linkmode_supported(compat, 1000baseKX_Full))
434 adv |= DW_C73_1000KX;
435 if (xpcs_linkmode_supported(compat, 10000baseKX4_Full))
436 adv |= DW_C73_10000KX4;
437 if (xpcs_linkmode_supported(compat, 10000baseKR_Full))
438 adv |= DW_C73_10000KR;
439
440 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv);
441 if (ret < 0)
442 return ret;
443
444 /* SR_AN_ADV1 */
445 adv = DW_C73_AN_ADV_SF;
446 if (xpcs_linkmode_supported(compat, Pause))
447 adv |= DW_C73_PAUSE;
448 if (xpcs_linkmode_supported(compat, Asym_Pause))
449 adv |= DW_C73_ASYM_PAUSE;
450
451 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv);
452}
453
454static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
455 const struct xpcs_compat *compat)
456{
457 int ret;
458
459 ret = _xpcs_config_aneg_c73(xpcs, compat);
460 if (ret < 0)
461 return ret;
462
463 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1);
464 if (ret < 0)
465 return ret;
466
467 ret |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART;
468
469 return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret);
470}
471
472static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs,
473 struct phylink_link_state *state,
474 const struct xpcs_compat *compat)
475{
476 int ret;
477
478 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
479 if (ret < 0)
480 return ret;
481
482 if (ret & MDIO_AN_STAT1_COMPLETE) {
483 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL1);
484 if (ret < 0)
485 return ret;
486
487 /* Check if Aneg outcome is valid */
488 if (!(ret & DW_C73_AN_ADV_SF)) {
489 xpcs_config_aneg_c73(xpcs, compat);
490 return 0;
491 }
492
493 return 1;
494 }
495
496 return 0;
497}
498
499static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs,
500 struct phylink_link_state *state)
501{
502 int ret;
503
504 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
505 if (ret < 0)
506 return ret;
507
508 if (!(ret & MDIO_AN_STAT1_LPABLE)) {
509 phylink_clear(state->lp_advertising, Autoneg);
510 return 0;
511 }
512
513 phylink_set(state->lp_advertising, Autoneg);
514
515 /* Clause 73 outcome */
516 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL3);
517 if (ret < 0)
518 return ret;
519
520 if (ret & DW_C73_2500KX)
521 phylink_set(state->lp_advertising, 2500baseX_Full);
522
523 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL2);
524 if (ret < 0)
525 return ret;
526
527 if (ret & DW_C73_1000KX)
528 phylink_set(state->lp_advertising, 1000baseKX_Full);
529 if (ret & DW_C73_10000KX4)
530 phylink_set(state->lp_advertising, 10000baseKX4_Full);
531 if (ret & DW_C73_10000KR)
532 phylink_set(state->lp_advertising, 10000baseKR_Full);
533
534 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL1);
535 if (ret < 0)
536 return ret;
537
538 if (ret & DW_C73_PAUSE)
539 phylink_set(state->lp_advertising, Pause);
540 if (ret & DW_C73_ASYM_PAUSE)
541 phylink_set(state->lp_advertising, Asym_Pause);
542
543 linkmode_and(state->lp_advertising, state->lp_advertising,
544 state->advertising);
545 return 0;
546}
547
548static void xpcs_resolve_lpa_c73(struct dw_xpcs *xpcs,
549 struct phylink_link_state *state)
550{
551 int max_speed = xpcs_get_max_usxgmii_speed(state->lp_advertising);
552
553 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX;
554 state->speed = max_speed;
555 state->duplex = DUPLEX_FULL;
556}
557
558static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs,
559 struct phylink_link_state *state)
560{
561 unsigned long *adv = state->advertising;
562 int speed = SPEED_UNKNOWN;
563 int bit;
564
565 for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) {
566 int new_speed = SPEED_UNKNOWN;
567
568 switch (bit) {
569 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT:
570 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT:
571 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT:
572 new_speed = SPEED_25000;
573 break;
574 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT:
575 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT:
576 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT:
577 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT:
578 new_speed = SPEED_40000;
579 break;
580 case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT:
581 case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT:
582 case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT:
583 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT:
584 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT:
585 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT:
586 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT:
587 case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT:
588 new_speed = SPEED_50000;
589 break;
590 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT:
591 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT:
592 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT:
593 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT:
594 case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT:
595 case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT:
596 case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT:
597 case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT:
598 case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT:
599 new_speed = SPEED_100000;
600 break;
601 default:
602 continue;
603 }
604
605 if (new_speed > speed)
606 speed = new_speed;
607 }
608
609 return speed;
610}
611
612static void xpcs_resolve_pma(struct dw_xpcs *xpcs,
613 struct phylink_link_state *state)
614{
615 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX;
616 state->duplex = DUPLEX_FULL;
617
618 switch (state->interface) {
619 case PHY_INTERFACE_MODE_10GKR:
620 state->speed = SPEED_10000;
621 break;
622 case PHY_INTERFACE_MODE_XLGMII:
623 state->speed = xpcs_get_max_xlgmii_speed(xpcs, state);
624 break;
625 default:
626 state->speed = SPEED_UNKNOWN;
627 break;
628 }
629}
630
631void xpcs_validate(struct dw_xpcs *xpcs, unsigned long *supported,
632 struct phylink_link_state *state)
633{
634 __ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported);
635 const struct xpcs_compat *compat;
636 int i;
637
638 /* phylink expects us to report all supported modes with
639 * PHY_INTERFACE_MODE_NA, just don't limit the supported and
640 * advertising masks and exit.
641 */
642 if (state->interface == PHY_INTERFACE_MODE_NA)
643 return;
644
645 bitmap_zero(xpcs_supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
646
647 compat = xpcs_find_compat(xpcs->id, state->interface);
648
649 /* Populate the supported link modes for this
650 * PHY interface type
651 */
652 if (compat)
653 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
654 set_bit(compat->supported[i], xpcs_supported);
655
656 linkmode_and(supported, supported, xpcs_supported);
657 linkmode_and(state->advertising, state->advertising, xpcs_supported);
658}
659EXPORT_SYMBOL_GPL(xpcs_validate);
660
661int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable)
662{
663 int ret;
664
665 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0);
666 if (ret < 0)
667 return ret;
668
669 if (enable) {
670 /* Enable EEE */
671 ret = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
672 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
673 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
674 mult_fact_100ns << DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT;
675 } else {
676 ret &= ~(DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
677 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
678 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
679 DW_VR_MII_EEE_MULT_FACT_100NS);
680 }
681
682 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, ret);
683 if (ret < 0)
684 return ret;
685
686 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1);
687 if (ret < 0)
688 return ret;
689
690 if (enable)
691 ret |= DW_VR_MII_EEE_TRN_LPI;
692 else
693 ret &= ~DW_VR_MII_EEE_TRN_LPI;
694
695 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, ret);
696}
697EXPORT_SYMBOL_GPL(xpcs_config_eee);
698
699static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, unsigned int mode)
700{
701 int ret, mdio_ctrl;
702
703 /* For AN for C37 SGMII mode, the settings are :-
704 * 1) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 0b (Disable SGMII AN in case
705 it is already enabled)
706 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN)
707 * 3) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII)
708 * DW xPCS used with DW EQoS MAC is always MAC side SGMII.
709 * 4) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic
710 * speed/duplex mode change by HW after SGMII AN complete)
711 * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN)
712 *
713 * Note: Since it is MAC side SGMII, there is no need to set
714 * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from
715 * PHY about the link state change after C28 AN is completed
716 * between PHY and Link Partner. There is also no need to
717 * trigger AN restart for MAC-side SGMII.
718 */
719 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
720 if (mdio_ctrl < 0)
721 return mdio_ctrl;
722
723 if (mdio_ctrl & AN_CL37_EN) {
724 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
725 mdio_ctrl & ~AN_CL37_EN);
726 if (ret < 0)
727 return ret;
728 }
729
730 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
731 if (ret < 0)
732 return ret;
733
734 ret &= ~(DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK);
735 ret |= (DW_VR_MII_PCS_MODE_C37_SGMII <<
736 DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT &
737 DW_VR_MII_PCS_MODE_MASK);
738 ret |= (DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII <<
739 DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT &
740 DW_VR_MII_TX_CONFIG_MASK);
741 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);
742 if (ret < 0)
743 return ret;
744
745 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
746 if (ret < 0)
747 return ret;
748
749 if (phylink_autoneg_inband(mode))
750 ret |= DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
751 else
752 ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
753
754 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
755 if (ret < 0)
756 return ret;
757
758 if (phylink_autoneg_inband(mode))
759 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
760 mdio_ctrl | AN_CL37_EN);
761
762 return ret;
763}
764
765static int xpcs_config_2500basex(struct dw_xpcs *xpcs)
766{
767 int ret;
768
769 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
770 if (ret < 0)
771 return ret;
772 ret |= DW_VR_MII_DIG_CTRL1_2G5_EN;
773 ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
774 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
775 if (ret < 0)
776 return ret;
777
778 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
779 if (ret < 0)
780 return ret;
781 ret &= ~AN_CL37_EN;
782 ret |= SGMII_SPEED_SS6;
783 ret &= ~SGMII_SPEED_SS13;
784 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, ret);
785}
786
787int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,
788 unsigned int mode)
789{
790 const struct xpcs_compat *compat;
791 int ret;
792
793 compat = xpcs_find_compat(xpcs->id, interface);
794 if (!compat)
795 return -ENODEV;
796
797 switch (compat->an_mode) {
798 case DW_AN_C73:
799 if (phylink_autoneg_inband(mode)) {
800 ret = xpcs_config_aneg_c73(xpcs, compat);
801 if (ret)
802 return ret;
803 }
804 break;
805 case DW_AN_C37_SGMII:
806 ret = xpcs_config_aneg_c37_sgmii(xpcs, mode);
807 if (ret)
808 return ret;
809 break;
810 case DW_2500BASEX:
811 ret = xpcs_config_2500basex(xpcs);
812 if (ret)
813 return ret;
814 break;
815 default:
816 return -1;
817 }
818
819 if (compat->pma_config) {
820 ret = compat->pma_config(xpcs);
821 if (ret)
822 return ret;
823 }
824
825 return 0;
826}
827EXPORT_SYMBOL_GPL(xpcs_do_config);
828
829static int xpcs_config(struct phylink_pcs *pcs, unsigned int mode,
830 phy_interface_t interface,
831 const unsigned long *advertising,
832 bool permit_pause_to_mac)
833{
834 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
835
836 return xpcs_do_config(xpcs, interface, mode);
837}
838
839static int xpcs_get_state_c73(struct dw_xpcs *xpcs,
840 struct phylink_link_state *state,
841 const struct xpcs_compat *compat)
842{
843 int ret;
844
845 /* Link needs to be read first ... */
846 state->link = xpcs_read_link_c73(xpcs, state->an_enabled) > 0 ? 1 : 0;
847
848 /* ... and then we check the faults. */
849 ret = xpcs_read_fault_c73(xpcs, state);
850 if (ret) {
851 ret = xpcs_soft_reset(xpcs, compat);
852 if (ret)
853 return ret;
854
855 state->link = 0;
856
857 return xpcs_do_config(xpcs, state->interface, MLO_AN_INBAND);
858 }
859
860 if (state->an_enabled && xpcs_aneg_done_c73(xpcs, state, compat)) {
861 state->an_complete = true;
862 xpcs_read_lpa_c73(xpcs, state);
863 xpcs_resolve_lpa_c73(xpcs, state);
864 } else if (state->an_enabled) {
865 state->link = 0;
866 } else if (state->link) {
867 xpcs_resolve_pma(xpcs, state);
868 }
869
870 return 0;
871}
872
873static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
874 struct phylink_link_state *state)
875{
876 int ret;
877
878 /* Reset link_state */
879 state->link = false;
880 state->speed = SPEED_UNKNOWN;
881 state->duplex = DUPLEX_UNKNOWN;
882 state->pause = 0;
883
884 /* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link
885 * status, speed and duplex.
886 */
887 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS);
888 if (ret < 0)
889 return false;
890
891 if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) {
892 int speed_value;
893
894 state->link = true;
895
896 speed_value = (ret & DW_VR_MII_AN_STS_C37_ANSGM_SP) >>
897 DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT;
898 if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000)
899 state->speed = SPEED_1000;
900 else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100)
901 state->speed = SPEED_100;
902 else
903 state->speed = SPEED_10;
904
905 if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD)
906 state->duplex = DUPLEX_FULL;
907 else
908 state->duplex = DUPLEX_HALF;
909 }
910
911 return 0;
912}
913
914static void xpcs_get_state(struct phylink_pcs *pcs,
915 struct phylink_link_state *state)
916{
917 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
918 const struct xpcs_compat *compat;
919 int ret;
920
921 compat = xpcs_find_compat(xpcs->id, state->interface);
922 if (!compat)
923 return;
924
925 switch (compat->an_mode) {
926 case DW_AN_C73:
927 ret = xpcs_get_state_c73(xpcs, state, compat);
928 if (ret) {
929 pr_err("xpcs_get_state_c73 returned %pe\n",
930 ERR_PTR(ret));
931 return;
932 }
933 break;
934 case DW_AN_C37_SGMII:
935 ret = xpcs_get_state_c37_sgmii(xpcs, state);
936 if (ret) {
937 pr_err("xpcs_get_state_c37_sgmii returned %pe\n",
938 ERR_PTR(ret));
939 }
940 break;
941 default:
942 return;
943 }
944}
945
946static void xpcs_link_up_sgmii(struct dw_xpcs *xpcs, unsigned int mode,
947 int speed, int duplex)
948{
949 int val, ret;
950
951 if (phylink_autoneg_inband(mode))
952 return;
953
954 switch (speed) {
955 case SPEED_1000:
956 val = BMCR_SPEED1000;
957 break;
958 case SPEED_100:
959 val = BMCR_SPEED100;
960 break;
961 case SPEED_10:
962 val = BMCR_SPEED10;
963 break;
964 default:
965 return;
966 }
967
968 if (duplex == DUPLEX_FULL)
969 val |= BMCR_FULLDPLX;
970
971 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
972 if (ret)
973 pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));
974}
975
976void xpcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
977 phy_interface_t interface, int speed, int duplex)
978{
979 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
980
981 if (interface == PHY_INTERFACE_MODE_USXGMII)
982 return xpcs_config_usxgmii(xpcs, speed);
983 if (interface == PHY_INTERFACE_MODE_SGMII)
984 return xpcs_link_up_sgmii(xpcs, mode, speed, duplex);
985}
986EXPORT_SYMBOL_GPL(xpcs_link_up);
987
988static u32 xpcs_get_id(struct dw_xpcs *xpcs)
989{
990 int ret;
991 u32 id;
992
993 /* First, search C73 PCS using PCS MMD */
994 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1);
995 if (ret < 0)
996 return 0xffffffff;
997
998 id = ret << 16;
999
1000 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2);
1001 if (ret < 0)
1002 return 0xffffffff;
1003
1004 /* If Device IDs are not all zeros or all ones,
1005 * we found C73 AN-type device
1006 */
1007 if ((id | ret) && (id | ret) != 0xffffffff)
1008 return id | ret;
1009
1010 /* Next, search C37 PCS using Vendor-Specific MII MMD */
1011 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1);
1012 if (ret < 0)
1013 return 0xffffffff;
1014
1015 id = ret << 16;
1016
1017 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2);
1018 if (ret < 0)
1019 return 0xffffffff;
1020
1021 /* If Device IDs are not all zeros, we found C37 AN-type device */
1022 if (id | ret)
1023 return id | ret;
1024
1025 return 0xffffffff;
1026}
1027
1028static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1029 [DW_XPCS_USXGMII] = {
1030 .supported = xpcs_usxgmii_features,
1031 .interface = xpcs_usxgmii_interfaces,
1032 .num_interfaces = ARRAY_SIZE(xpcs_usxgmii_interfaces),
1033 .an_mode = DW_AN_C73,
1034 },
1035 [DW_XPCS_10GKR] = {
1036 .supported = xpcs_10gkr_features,
1037 .interface = xpcs_10gkr_interfaces,
1038 .num_interfaces = ARRAY_SIZE(xpcs_10gkr_interfaces),
1039 .an_mode = DW_AN_C73,
1040 },
1041 [DW_XPCS_XLGMII] = {
1042 .supported = xpcs_xlgmii_features,
1043 .interface = xpcs_xlgmii_interfaces,
1044 .num_interfaces = ARRAY_SIZE(xpcs_xlgmii_interfaces),
1045 .an_mode = DW_AN_C73,
1046 },
1047 [DW_XPCS_SGMII] = {
1048 .supported = xpcs_sgmii_features,
1049 .interface = xpcs_sgmii_interfaces,
1050 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1051 .an_mode = DW_AN_C37_SGMII,
1052 },
1053 [DW_XPCS_2500BASEX] = {
1054 .supported = xpcs_2500basex_features,
1055 .interface = xpcs_2500basex_interfaces,
1056 .num_interfaces = ARRAY_SIZE(xpcs_2500basex_features),
1057 .an_mode = DW_2500BASEX,
1058 },
1059};
1060
1061static const struct xpcs_compat nxp_sja1105_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1062 [DW_XPCS_SGMII] = {
1063 .supported = xpcs_sgmii_features,
1064 .interface = xpcs_sgmii_interfaces,
1065 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1066 .an_mode = DW_AN_C37_SGMII,
1067 .pma_config = nxp_sja1105_sgmii_pma_config,
1068 },
1069};
1070
1071static const struct xpcs_compat nxp_sja1110_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1072 [DW_XPCS_SGMII] = {
1073 .supported = xpcs_sgmii_features,
1074 .interface = xpcs_sgmii_interfaces,
1075 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1076 .an_mode = DW_AN_C37_SGMII,
1077 .pma_config = nxp_sja1110_sgmii_pma_config,
1078 },
1079 [DW_XPCS_2500BASEX] = {
1080 .supported = xpcs_2500basex_features,
1081 .interface = xpcs_2500basex_interfaces,
1082 .num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces),
1083 .an_mode = DW_2500BASEX,
1084 .pma_config = nxp_sja1110_2500basex_pma_config,
1085 },
1086};
1087
1088static const struct xpcs_id xpcs_id_list[] = {
1089 {
1090 .id = SYNOPSYS_XPCS_ID,
1091 .mask = SYNOPSYS_XPCS_MASK,
1092 .compat = synopsys_xpcs_compat,
1093 }, {
1094 .id = NXP_SJA1105_XPCS_ID,
1095 .mask = SYNOPSYS_XPCS_MASK,
1096 .compat = nxp_sja1105_xpcs_compat,
1097 }, {
1098 .id = NXP_SJA1110_XPCS_ID,
1099 .mask = SYNOPSYS_XPCS_MASK,
1100 .compat = nxp_sja1110_xpcs_compat,
1101 },
1102};
1103
1104static const struct phylink_pcs_ops xpcs_phylink_ops = {
1105 .pcs_config = xpcs_config,
1106 .pcs_get_state = xpcs_get_state,
1107 .pcs_link_up = xpcs_link_up,
1108};
1109
1110struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev,
1111 phy_interface_t interface)
1112{
1113 struct dw_xpcs *xpcs;
1114 u32 xpcs_id;
1115 int i, ret;
1116
1117 xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL);
1118 if (!xpcs)
1119 return ERR_PTR(-ENOMEM);
1120
1121 xpcs->mdiodev = mdiodev;
1122
1123 xpcs_id = xpcs_get_id(xpcs);
1124
1125 for (i = 0; i < ARRAY_SIZE(xpcs_id_list); i++) {
1126 const struct xpcs_id *entry = &xpcs_id_list[i];
1127 const struct xpcs_compat *compat;
1128
1129 if ((xpcs_id & entry->mask) != entry->id)
1130 continue;
1131
1132 xpcs->id = entry;
1133
1134 compat = xpcs_find_compat(entry, interface);
1135 if (!compat) {
1136 ret = -ENODEV;
1137 goto out;
1138 }
1139
1140 xpcs->pcs.ops = &xpcs_phylink_ops;
1141 xpcs->pcs.poll = true;
1142
1143 ret = xpcs_soft_reset(xpcs, compat);
1144 if (ret)
1145 goto out;
1146
1147 return xpcs;
1148 }
1149
1150 ret = -ENODEV;
1151
1152out:
1153 kfree(xpcs);
1154
1155 return ERR_PTR(ret);
1156}
1157EXPORT_SYMBOL_GPL(xpcs_create);
1158
1159void xpcs_destroy(struct dw_xpcs *xpcs)
1160{
1161 kfree(xpcs);
1162}
1163EXPORT_SYMBOL_GPL(xpcs_destroy);
1164
1165MODULE_LICENSE("GPL v2");