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1/*
2 * B53 register definitions
3 *
4 * Copyright (C) 2004 Broadcom Corporation
5 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#ifndef __B53_REGS_H
21#define __B53_REGS_H
22
23/* Management Port (SMP) Page offsets */
24#define B53_CTRL_PAGE 0x00 /* Control */
25#define B53_STAT_PAGE 0x01 /* Status */
26#define B53_MGMT_PAGE 0x02 /* Management Mode */
27#define B53_MIB_AC_PAGE 0x03 /* MIB Autocast */
28#define B53_ARLCTRL_PAGE 0x04 /* ARL Control */
29#define B53_ARLIO_PAGE 0x05 /* ARL Access */
30#define B53_FRAMEBUF_PAGE 0x06 /* Management frame access */
31#define B53_MEM_ACCESS_PAGE 0x08 /* Memory access */
32
33/* PHY Registers */
34#define B53_PORT_MII_PAGE(i) (0x10 + (i)) /* Port i MII Registers */
35#define B53_IM_PORT_PAGE 0x18 /* Inverse MII Port (to EMAC) */
36#define B53_ALL_PORT_PAGE 0x19 /* All ports MII (broadcast) */
37
38/* MIB registers */
39#define B53_MIB_PAGE(i) (0x20 + (i))
40
41/* Quality of Service (QoS) Registers */
42#define B53_QOS_PAGE 0x30
43
44/* Port VLAN Page */
45#define B53_PVLAN_PAGE 0x31
46
47/* VLAN Registers */
48#define B53_VLAN_PAGE 0x34
49
50/* Jumbo Frame Registers */
51#define B53_JUMBO_PAGE 0x40
52
53/* EEE Control Registers Page */
54#define B53_EEE_PAGE 0x92
55
56/* CFP Configuration Registers Page */
57#define B53_CFP_PAGE 0xa1
58
59/*************************************************************************
60 * Control Page registers
61 *************************************************************************/
62
63/* Port Control Register (8 bit) */
64#define B53_PORT_CTRL(i) (0x00 + (i))
65#define PORT_CTRL_RX_DISABLE BIT(0)
66#define PORT_CTRL_TX_DISABLE BIT(1)
67#define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */
68#define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */
69#define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */
70#define PORT_CTRL_STP_STATE_S 5
71#define PORT_CTRL_NO_STP (0 << PORT_CTRL_STP_STATE_S)
72#define PORT_CTRL_DIS_STATE (1 << PORT_CTRL_STP_STATE_S)
73#define PORT_CTRL_BLOCK_STATE (2 << PORT_CTRL_STP_STATE_S)
74#define PORT_CTRL_LISTEN_STATE (3 << PORT_CTRL_STP_STATE_S)
75#define PORT_CTRL_LEARN_STATE (4 << PORT_CTRL_STP_STATE_S)
76#define PORT_CTRL_FWD_STATE (5 << PORT_CTRL_STP_STATE_S)
77#define PORT_CTRL_STP_STATE_MASK (0x7 << PORT_CTRL_STP_STATE_S)
78
79/* SMP Control Register (8 bit) */
80#define B53_SMP_CTRL 0x0a
81
82/* Switch Mode Control Register (8 bit) */
83#define B53_SWITCH_MODE 0x0b
84#define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */
85#define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */
86
87/* IMP Port state override register (8 bit) */
88#define B53_PORT_OVERRIDE_CTRL 0x0e
89#define PORT_OVERRIDE_LINK BIT(0)
90#define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */
91#define PORT_OVERRIDE_SPEED_S 2
92#define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S)
93#define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S)
94#define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S)
95#define PORT_OVERRIDE_RV_MII_25 BIT(4) /* BCM5325 only */
96#define PORT_OVERRIDE_RX_FLOW BIT(4)
97#define PORT_OVERRIDE_TX_FLOW BIT(5)
98#define PORT_OVERRIDE_SPEED_2000M BIT(6) /* BCM5301X only, requires setting 1000M */
99#define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */
100
101/* Power-down mode control */
102#define B53_PD_MODE_CTRL_25 0x0f
103
104/* IP Multicast control (8 bit) */
105#define B53_IP_MULTICAST_CTRL 0x21
106#define B53_IPMC_FWD_EN BIT(1)
107#define B53_UC_FWD_EN BIT(6)
108#define B53_MC_FWD_EN BIT(7)
109
110/* Switch control (8 bit) */
111#define B53_SWITCH_CTRL 0x22
112#define B53_MII_DUMB_FWDG_EN BIT(6)
113
114/* (16 bit) */
115#define B53_UC_FLOOD_MASK 0x32
116#define B53_MC_FLOOD_MASK 0x34
117#define B53_IPMC_FLOOD_MASK 0x36
118#define B53_DIS_LEARNING 0x3c
119
120/*
121 * Override Ports 0-7 State on devices with xMII interfaces (8 bit)
122 *
123 * For port 8 still use B53_PORT_OVERRIDE_CTRL
124 * Please note that not all ports are available on every hardware, e.g. BCM5301X
125 * don't include overriding port 6, BCM63xx also have some limitations.
126 */
127#define B53_GMII_PORT_OVERRIDE_CTRL(i) (0x58 + (i))
128#define GMII_PO_LINK BIT(0)
129#define GMII_PO_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */
130#define GMII_PO_SPEED_S 2
131#define GMII_PO_SPEED_10M (0 << GMII_PO_SPEED_S)
132#define GMII_PO_SPEED_100M (1 << GMII_PO_SPEED_S)
133#define GMII_PO_SPEED_1000M (2 << GMII_PO_SPEED_S)
134#define GMII_PO_RX_FLOW BIT(4)
135#define GMII_PO_TX_FLOW BIT(5)
136#define GMII_PO_EN BIT(6) /* Use the register contents */
137#define GMII_PO_SPEED_2000M BIT(7) /* BCM5301X only, requires setting 1000M */
138
139#define B53_RGMII_CTRL_IMP 0x60
140#define RGMII_CTRL_ENABLE_GMII BIT(7)
141#define RGMII_CTRL_TIMING_SEL BIT(2)
142#define RGMII_CTRL_DLL_RXC BIT(1)
143#define RGMII_CTRL_DLL_TXC BIT(0)
144
145#define B53_RGMII_CTRL_P(i) (B53_RGMII_CTRL_IMP + (i))
146
147/* Software reset register (8 bit) */
148#define B53_SOFTRESET 0x79
149#define SW_RST BIT(7)
150#define EN_CH_RST BIT(6)
151#define EN_SW_RST BIT(4)
152
153/* Fast Aging Control register (8 bit) */
154#define B53_FAST_AGE_CTRL 0x88
155#define FAST_AGE_STATIC BIT(0)
156#define FAST_AGE_DYNAMIC BIT(1)
157#define FAST_AGE_PORT BIT(2)
158#define FAST_AGE_VLAN BIT(3)
159#define FAST_AGE_STP BIT(4)
160#define FAST_AGE_MC BIT(5)
161#define FAST_AGE_DONE BIT(7)
162
163/* Fast Aging Port Control register (8 bit) */
164#define B53_FAST_AGE_PORT_CTRL 0x89
165
166/* Fast Aging VID Control register (16 bit) */
167#define B53_FAST_AGE_VID_CTRL 0x8a
168
169/*************************************************************************
170 * Status Page registers
171 *************************************************************************/
172
173/* Link Status Summary Register (16bit) */
174#define B53_LINK_STAT 0x00
175
176/* Link Status Change Register (16 bit) */
177#define B53_LINK_STAT_CHANGE 0x02
178
179/* Port Speed Summary Register (16 bit for FE, 32 bit for GE) */
180#define B53_SPEED_STAT 0x04
181#define SPEED_PORT_FE(reg, port) (((reg) >> (port)) & 1)
182#define SPEED_PORT_GE(reg, port) (((reg) >> 2 * (port)) & 3)
183#define SPEED_STAT_10M 0
184#define SPEED_STAT_100M 1
185#define SPEED_STAT_1000M 2
186
187/* Duplex Status Summary (16 bit) */
188#define B53_DUPLEX_STAT_FE 0x06
189#define B53_DUPLEX_STAT_GE 0x08
190#define B53_DUPLEX_STAT_63XX 0x0c
191
192/* Revision ID register for BCM5325 */
193#define B53_REV_ID_25 0x50
194
195/* Strap Value (48 bit) */
196#define B53_STRAP_VALUE 0x70
197#define SV_GMII_CTRL_115 BIT(27)
198
199/*************************************************************************
200 * Management Mode Page Registers
201 *************************************************************************/
202
203/* Global Management Config Register (8 bit) */
204#define B53_GLOBAL_CONFIG 0x00
205#define GC_RESET_MIB 0x01
206#define GC_RX_BPDU_EN 0x02
207#define GC_MIB_AC_HDR_EN 0x10
208#define GC_MIB_AC_EN 0x20
209#define GC_FRM_MGMT_PORT_M 0xC0
210#define GC_FRM_MGMT_PORT_04 0x00
211#define GC_FRM_MGMT_PORT_MII 0x80
212
213/* Broadcom Header control register (8 bit) */
214#define B53_BRCM_HDR 0x03
215#define BRCM_HDR_P8_EN BIT(0) /* Enable tagging on port 8 */
216#define BRCM_HDR_P5_EN BIT(1) /* Enable tagging on port 5 */
217#define BRCM_HDR_P7_EN BIT(2) /* Enable tagging on port 7 */
218
219/* Mirror capture control register (16 bit) */
220#define B53_MIR_CAP_CTL 0x10
221#define CAP_PORT_MASK 0xf
222#define BLK_NOT_MIR BIT(14)
223#define MIRROR_EN BIT(15)
224
225/* Ingress mirror control register (16 bit) */
226#define B53_IG_MIR_CTL 0x12
227#define MIRROR_MASK 0x1ff
228#define DIV_EN BIT(13)
229#define MIRROR_FILTER_MASK 0x3
230#define MIRROR_FILTER_SHIFT 14
231#define MIRROR_ALL 0
232#define MIRROR_DA 1
233#define MIRROR_SA 2
234
235/* Ingress mirror divider register (16 bit) */
236#define B53_IG_MIR_DIV 0x14
237#define IN_MIRROR_DIV_MASK 0x3ff
238
239/* Ingress mirror MAC address register (48 bit) */
240#define B53_IG_MIR_MAC 0x16
241
242/* Egress mirror control register (16 bit) */
243#define B53_EG_MIR_CTL 0x1C
244
245/* Egress mirror divider register (16 bit) */
246#define B53_EG_MIR_DIV 0x1E
247
248/* Egress mirror MAC address register (48 bit) */
249#define B53_EG_MIR_MAC 0x20
250
251/* Device ID register (8 or 32 bit) */
252#define B53_DEVICE_ID 0x30
253
254/* Revision ID register (8 bit) */
255#define B53_REV_ID 0x40
256
257/* Broadcom header RX control (16 bit) */
258#define B53_BRCM_HDR_RX_DIS 0x60
259
260/* Broadcom header TX control (16 bit) */
261#define B53_BRCM_HDR_TX_DIS 0x62
262
263/*************************************************************************
264 * ARL Access Page Registers
265 *************************************************************************/
266
267/* VLAN Table Access Register (8 bit) */
268#define B53_VT_ACCESS 0x80
269#define B53_VT_ACCESS_9798 0x60 /* for BCM5397/BCM5398 */
270#define B53_VT_ACCESS_63XX 0x60 /* for BCM6328/62/68 */
271#define VTA_CMD_WRITE 0
272#define VTA_CMD_READ 1
273#define VTA_CMD_CLEAR 2
274#define VTA_START_CMD BIT(7)
275
276/* VLAN Table Index Register (16 bit) */
277#define B53_VT_INDEX 0x81
278#define B53_VT_INDEX_9798 0x61
279#define B53_VT_INDEX_63XX 0x62
280
281/* VLAN Table Entry Register (32 bit) */
282#define B53_VT_ENTRY 0x83
283#define B53_VT_ENTRY_9798 0x63
284#define B53_VT_ENTRY_63XX 0x64
285#define VTE_MEMBERS 0x1ff
286#define VTE_UNTAG_S 9
287#define VTE_UNTAG (0x1ff << 9)
288
289/*************************************************************************
290 * ARL I/O Registers
291 *************************************************************************/
292
293/* ARL Table Read/Write Register (8 bit) */
294#define B53_ARLTBL_RW_CTRL 0x00
295#define ARLTBL_RW BIT(0)
296#define ARLTBL_IVL_SVL_SELECT BIT(6)
297#define ARLTBL_START_DONE BIT(7)
298
299/* MAC Address Index Register (48 bit) */
300#define B53_MAC_ADDR_IDX 0x02
301
302/* VLAN ID Index Register (16 bit) */
303#define B53_VLAN_ID_IDX 0x08
304
305/* ARL Table MAC/VID Entry N Registers (64 bit)
306 *
307 * BCM5325 and BCM5365 share most definitions below
308 */
309#define B53_ARLTBL_MAC_VID_ENTRY(n) ((0x10 * (n)) + 0x10)
310#define ARLTBL_MAC_MASK 0xffffffffffffULL
311#define ARLTBL_VID_S 48
312#define ARLTBL_VID_MASK_25 0xff
313#define ARLTBL_VID_MASK 0xfff
314#define ARLTBL_DATA_PORT_ID_S_25 48
315#define ARLTBL_DATA_PORT_ID_MASK_25 0xf
316#define ARLTBL_AGE_25 BIT(61)
317#define ARLTBL_STATIC_25 BIT(62)
318#define ARLTBL_VALID_25 BIT(63)
319
320/* ARL Table Data Entry N Registers (32 bit) */
321#define B53_ARLTBL_DATA_ENTRY(n) ((0x10 * (n)) + 0x18)
322#define ARLTBL_DATA_PORT_ID_MASK 0x1ff
323#define ARLTBL_TC(tc) ((3 & tc) << 11)
324#define ARLTBL_AGE BIT(14)
325#define ARLTBL_STATIC BIT(15)
326#define ARLTBL_VALID BIT(16)
327
328/* Maximum number of bin entries in the ARL for all switches */
329#define B53_ARLTBL_MAX_BIN_ENTRIES 4
330
331/* ARL Search Control Register (8 bit) */
332#define B53_ARL_SRCH_CTL 0x50
333#define B53_ARL_SRCH_CTL_25 0x20
334#define ARL_SRCH_VLID BIT(0)
335#define ARL_SRCH_STDN BIT(7)
336
337/* ARL Search Address Register (16 bit) */
338#define B53_ARL_SRCH_ADDR 0x51
339#define B53_ARL_SRCH_ADDR_25 0x22
340#define B53_ARL_SRCH_ADDR_65 0x24
341#define ARL_ADDR_MASK GENMASK(14, 0)
342
343/* ARL Search MAC/VID Result (64 bit) */
344#define B53_ARL_SRCH_RSTL_0_MACVID 0x60
345
346/* Single register search result on 5325 */
347#define B53_ARL_SRCH_RSTL_0_MACVID_25 0x24
348/* Single register search result on 5365 */
349#define B53_ARL_SRCH_RSTL_0_MACVID_65 0x30
350
351/* ARL Search Data Result (32 bit) */
352#define B53_ARL_SRCH_RSTL_0 0x68
353
354#define B53_ARL_SRCH_RSTL_MACVID(x) (B53_ARL_SRCH_RSTL_0_MACVID + ((x) * 0x10))
355#define B53_ARL_SRCH_RSTL(x) (B53_ARL_SRCH_RSTL_0 + ((x) * 0x10))
356
357/*************************************************************************
358 * Port VLAN Registers
359 *************************************************************************/
360
361/* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */
362#define B53_PVLAN_PORT_MASK(i) ((i) * 2)
363
364/* Join all VLANs register (16 bit) */
365#define B53_JOIN_ALL_VLAN_EN 0x50
366
367/*************************************************************************
368 * 802.1Q Page Registers
369 *************************************************************************/
370
371/* Global QoS Control (8 bit) */
372#define B53_QOS_GLOBAL_CTL 0x00
373
374/* Enable 802.1Q for individual Ports (16 bit) */
375#define B53_802_1P_EN 0x04
376
377/*************************************************************************
378 * VLAN Page Registers
379 *************************************************************************/
380
381/* VLAN Control 0 (8 bit) */
382#define B53_VLAN_CTRL0 0x00
383#define VC0_8021PF_CTRL_MASK 0x3
384#define VC0_8021PF_CTRL_NONE 0x0
385#define VC0_8021PF_CTRL_CHANGE_PRI 0x1
386#define VC0_8021PF_CTRL_CHANGE_VID 0x2
387#define VC0_8021PF_CTRL_CHANGE_BOTH 0x3
388#define VC0_8021QF_CTRL_MASK 0xc
389#define VC0_8021QF_CTRL_CHANGE_PRI 0x1
390#define VC0_8021QF_CTRL_CHANGE_VID 0x2
391#define VC0_8021QF_CTRL_CHANGE_BOTH 0x3
392#define VC0_RESERVED_1 BIT(1)
393#define VC0_DROP_VID_MISS BIT(4)
394#define VC0_VID_HASH_VID BIT(5)
395#define VC0_VID_CHK_EN BIT(6) /* Use VID,DA or VID,SA */
396#define VC0_VLAN_EN BIT(7) /* 802.1Q VLAN Enabled */
397
398/* VLAN Control 1 (8 bit) */
399#define B53_VLAN_CTRL1 0x01
400#define VC1_RX_MCST_TAG_EN BIT(1)
401#define VC1_RX_MCST_FWD_EN BIT(2)
402#define VC1_RX_MCST_UNTAG_EN BIT(3)
403
404/* VLAN Control 2 (8 bit) */
405#define B53_VLAN_CTRL2 0x02
406
407/* VLAN Control 3 (8 bit when BCM5325, 16 bit else) */
408#define B53_VLAN_CTRL3 0x03
409#define B53_VLAN_CTRL3_63XX 0x04
410#define VC3_MAXSIZE_1532 BIT(6) /* 5325 only */
411#define VC3_HIGH_8BIT_EN BIT(7) /* 5325 only */
412
413/* VLAN Control 4 (8 bit) */
414#define B53_VLAN_CTRL4 0x05
415#define B53_VLAN_CTRL4_25 0x04
416#define B53_VLAN_CTRL4_63XX 0x06
417#define VC4_ING_VID_CHECK_S 6
418#define VC4_ING_VID_CHECK_MASK (0x3 << VC4_ING_VID_CHECK_S)
419#define VC4_ING_VID_VIO_FWD 0 /* forward, but do not learn */
420#define VC4_ING_VID_VIO_DROP 1 /* drop VID violations */
421#define VC4_NO_ING_VID_CHK 2 /* do not check */
422#define VC4_ING_VID_VIO_TO_IMP 3 /* redirect to MII port */
423
424/* VLAN Control 5 (8 bit) */
425#define B53_VLAN_CTRL5 0x06
426#define B53_VLAN_CTRL5_25 0x05
427#define B53_VLAN_CTRL5_63XX 0x07
428#define VC5_VID_FFF_EN BIT(2)
429#define VC5_DROP_VTABLE_MISS BIT(3)
430
431/* VLAN Control 6 (8 bit) */
432#define B53_VLAN_CTRL6 0x07
433#define B53_VLAN_CTRL6_63XX 0x08
434
435/* VLAN Table Access Register (16 bit) */
436#define B53_VLAN_TABLE_ACCESS_25 0x06 /* BCM5325E/5350 */
437#define B53_VLAN_TABLE_ACCESS_65 0x08 /* BCM5365 */
438#define VTA_VID_LOW_MASK_25 0xf
439#define VTA_VID_LOW_MASK_65 0xff
440#define VTA_VID_HIGH_S_25 4
441#define VTA_VID_HIGH_S_65 8
442#define VTA_VID_HIGH_MASK_25 (0xff << VTA_VID_HIGH_S_25E)
443#define VTA_VID_HIGH_MASK_65 (0xf << VTA_VID_HIGH_S_65)
444#define VTA_RW_STATE BIT(12)
445#define VTA_RW_STATE_RD 0
446#define VTA_RW_STATE_WR BIT(12)
447#define VTA_RW_OP_EN BIT(13)
448
449/* VLAN Read/Write Registers for (16/32 bit) */
450#define B53_VLAN_WRITE_25 0x08
451#define B53_VLAN_WRITE_65 0x0a
452#define B53_VLAN_READ 0x0c
453#define VA_MEMBER_MASK 0x3f
454#define VA_UNTAG_S_25 6
455#define VA_UNTAG_MASK_25 0x3f
456#define VA_UNTAG_S_65 7
457#define VA_UNTAG_MASK_65 0x1f
458#define VA_VID_HIGH_S 12
459#define VA_VID_HIGH_MASK (0xffff << VA_VID_HIGH_S)
460#define VA_VALID_25 BIT(20)
461#define VA_VALID_25_R4 BIT(24)
462#define VA_VALID_65 BIT(14)
463
464/* VLAN Port Default Tag (16 bit) */
465#define B53_VLAN_PORT_DEF_TAG(i) (0x10 + 2 * (i))
466
467/*************************************************************************
468 * Jumbo Frame Page Registers
469 *************************************************************************/
470
471/* Jumbo Enable Port Mask (bit i == port i enabled) (32 bit) */
472#define B53_JUMBO_PORT_MASK 0x01
473#define B53_JUMBO_PORT_MASK_63XX 0x04
474#define JPM_10_100_JUMBO_EN BIT(24) /* GigE always enabled */
475
476/* Good Frame Max Size without 802.1Q TAG (16 bit) */
477#define B53_JUMBO_MAX_SIZE 0x05
478#define B53_JUMBO_MAX_SIZE_63XX 0x08
479#define JMS_MIN_SIZE 1518
480#define JMS_MAX_SIZE 9724
481
482/*************************************************************************
483 * EEE Configuration Page Registers
484 *************************************************************************/
485
486/* EEE Enable control register (16 bit) */
487#define B53_EEE_EN_CTRL 0x00
488
489/* EEE LPI assert status register (16 bit) */
490#define B53_EEE_LPI_ASSERT_STS 0x02
491
492/* EEE LPI indicate status register (16 bit) */
493#define B53_EEE_LPI_INDICATE 0x4
494
495/* EEE Receiving idle symbols status register (16 bit) */
496#define B53_EEE_RX_IDLE_SYM_STS 0x6
497
498/* EEE Pipeline timer register (32 bit) */
499#define B53_EEE_PIP_TIMER 0xC
500
501/* EEE Sleep timer Gig register (32 bit) */
502#define B53_EEE_SLEEP_TIMER_GIG(i) (0x10 + 4 * (i))
503
504/* EEE Sleep timer FE register (32 bit) */
505#define B53_EEE_SLEEP_TIMER_FE(i) (0x34 + 4 * (i))
506
507/* EEE Minimum LP timer Gig register (32 bit) */
508#define B53_EEE_MIN_LP_TIMER_GIG(i) (0x58 + 4 * (i))
509
510/* EEE Minimum LP timer FE register (32 bit) */
511#define B53_EEE_MIN_LP_TIMER_FE(i) (0x7c + 4 * (i))
512
513/* EEE Wake timer Gig register (16 bit) */
514#define B53_EEE_WAKE_TIMER_GIG(i) (0xa0 + 2 * (i))
515
516/* EEE Wake timer FE register (16 bit) */
517#define B53_EEE_WAKE_TIMER_FE(i) (0xb2 + 2 * (i))
518
519
520/*************************************************************************
521 * CFP Configuration Page Registers
522 *************************************************************************/
523
524/* CFP Control Register with ports map (8 bit) */
525#define B53_CFP_CTRL 0x00
526
527#endif /* !__B53_REGS_H */