1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 *  Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
  4 *  Loongson HyperTransport Interrupt Vector support
  5 */
  6
  7#define pr_fmt(fmt) "htvec: " fmt
  8
  9#include <linux/interrupt.h>
 10#include <linux/irq.h>
 11#include <linux/irqchip.h>
 12#include <linux/irqdomain.h>
 13#include <linux/irqchip/chained_irq.h>
 14#include <linux/kernel.h>
 15#include <linux/platform_device.h>
 16#include <linux/of_address.h>
 17#include <linux/of_irq.h>
 18#include <linux/of_platform.h>
 19
 20/* Registers */
 21#define HTVEC_EN_OFF		0x20
 22#define HTVEC_MAX_PARENT_IRQ	8
 23
 24#define VEC_COUNT_PER_REG	32
 25#define VEC_REG_IDX(irq_id)	((irq_id) / VEC_COUNT_PER_REG)
 26#define VEC_REG_BIT(irq_id)	((irq_id) % VEC_COUNT_PER_REG)
 27
 28struct htvec {
 29	int			num_parents;
 30	void __iomem		*base;
 31	struct irq_domain	*htvec_domain;
 32	raw_spinlock_t		htvec_lock;
 33};
 34
 35static void htvec_irq_dispatch(struct irq_desc *desc)
 36{
 37	int i;
 38	u32 pending;
 39	bool handled = false;
 40	struct irq_chip *chip = irq_desc_get_chip(desc);
 41	struct htvec *priv = irq_desc_get_handler_data(desc);
 42
 43	chained_irq_enter(chip, desc);
 44
 45	for (i = 0; i < priv->num_parents; i++) {
 46		pending = readl(priv->base + 4 * i);
 47		while (pending) {
 48			int bit = __ffs(pending);
 49
 50			generic_handle_domain_irq(priv->htvec_domain,
 51						  bit + VEC_COUNT_PER_REG * i);
 52			pending &= ~BIT(bit);
 53			handled = true;
 54		}
 55	}
 56
 57	if (!handled)
 58		spurious_interrupt();
 59
 60	chained_irq_exit(chip, desc);
 61}
 62
 63static void htvec_ack_irq(struct irq_data *d)
 64{
 65	struct htvec *priv = irq_data_get_irq_chip_data(d);
 66
 67	writel(BIT(VEC_REG_BIT(d->hwirq)),
 68	       priv->base + VEC_REG_IDX(d->hwirq) * 4);
 69}
 70
 71static void htvec_mask_irq(struct irq_data *d)
 72{
 73	u32 reg;
 74	void __iomem *addr;
 75	struct htvec *priv = irq_data_get_irq_chip_data(d);
 76
 77	raw_spin_lock(&priv->htvec_lock);
 78	addr = priv->base + HTVEC_EN_OFF;
 79	addr += VEC_REG_IDX(d->hwirq) * 4;
 80	reg = readl(addr);
 81	reg &= ~BIT(VEC_REG_BIT(d->hwirq));
 82	writel(reg, addr);
 83	raw_spin_unlock(&priv->htvec_lock);
 84}
 85
 86static void htvec_unmask_irq(struct irq_data *d)
 87{
 88	u32 reg;
 89	void __iomem *addr;
 90	struct htvec *priv = irq_data_get_irq_chip_data(d);
 91
 92	raw_spin_lock(&priv->htvec_lock);
 93	addr = priv->base + HTVEC_EN_OFF;
 94	addr += VEC_REG_IDX(d->hwirq) * 4;
 95	reg = readl(addr);
 96	reg |= BIT(VEC_REG_BIT(d->hwirq));
 97	writel(reg, addr);
 98	raw_spin_unlock(&priv->htvec_lock);
 99}
100
101static struct irq_chip htvec_irq_chip = {
102	.name			= "LOONGSON_HTVEC",
103	.irq_mask		= htvec_mask_irq,
104	.irq_unmask		= htvec_unmask_irq,
105	.irq_ack		= htvec_ack_irq,
106};
107
108static int htvec_domain_alloc(struct irq_domain *domain, unsigned int virq,
109			      unsigned int nr_irqs, void *arg)
110{
111	int ret;
112	unsigned long hwirq;
113	unsigned int type, i;
114	struct htvec *priv = domain->host_data;
115
116	ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type);
117	if (ret)
118		return ret;
119
120	for (i = 0; i < nr_irqs; i++) {
121		irq_domain_set_info(domain, virq + i, hwirq + i, &htvec_irq_chip,
122				    priv, handle_edge_irq, NULL, NULL);
123	}
124
125	return 0;
126}
127
128static void htvec_domain_free(struct irq_domain *domain, unsigned int virq,
129				  unsigned int nr_irqs)
130{
131	int i;
132
133	for (i = 0; i < nr_irqs; i++) {
134		struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
135
136		irq_set_handler(virq + i, NULL);
137		irq_domain_reset_irq_data(d);
138	}
139}
140
141static const struct irq_domain_ops htvec_domain_ops = {
142	.translate	= irq_domain_translate_onecell,
143	.alloc		= htvec_domain_alloc,
144	.free		= htvec_domain_free,
145};
146
147static void htvec_reset(struct htvec *priv)
148{
149	u32 idx;
150
151	/* Clear IRQ cause registers, mask all interrupts */
152	for (idx = 0; idx < priv->num_parents; idx++) {
153		writel_relaxed(0x0, priv->base + HTVEC_EN_OFF + 4 * idx);
154		writel_relaxed(0xFFFFFFFF, priv->base + 4 * idx);
155	}
156}
157
158static int htvec_of_init(struct device_node *node,
159				struct device_node *parent)
160{
161	struct htvec *priv;
162	int err, parent_irq[8], i;
163
164	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
165	if (!priv)
166		return -ENOMEM;
167
168	raw_spin_lock_init(&priv->htvec_lock);
169	priv->base = of_iomap(node, 0);
170	if (!priv->base) {
171		err = -ENOMEM;
172		goto free_priv;
173	}
174
175	/* Interrupt may come from any of the 8 interrupt lines */
176	for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) {
177		parent_irq[i] = irq_of_parse_and_map(node, i);
178		if (parent_irq[i] <= 0)
179			break;
180
181		priv->num_parents++;
182	}
183
184	if (!priv->num_parents) {
185		pr_err("Failed to get parent irqs\n");
186		err = -ENODEV;
187		goto iounmap_base;
188	}
189
190	priv->htvec_domain = irq_domain_create_linear(of_node_to_fwnode(node),
191					(VEC_COUNT_PER_REG * priv->num_parents),
192					&htvec_domain_ops, priv);
193	if (!priv->htvec_domain) {
194		pr_err("Failed to create IRQ domain\n");
195		err = -ENOMEM;
196		goto irq_dispose;
197	}
198
199	htvec_reset(priv);
200
201	for (i = 0; i < priv->num_parents; i++)
202		irq_set_chained_handler_and_data(parent_irq[i],
203						 htvec_irq_dispatch, priv);
204
205	return 0;
206
207irq_dispose:
208	for (; i > 0; i--)
209		irq_dispose_mapping(parent_irq[i - 1]);
210iounmap_base:
211	iounmap(priv->base);
212free_priv:
213	kfree(priv);
214
215	return err;
216}
217
218IRQCHIP_DECLARE(htvec, "loongson,htvec-1.0", htvec_of_init);