1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
  4 */
  5
  6#ifndef _CORESIGHT_PRIV_H
  7#define _CORESIGHT_PRIV_H
  8
  9#include <linux/amba/bus.h>
 10#include <linux/bitops.h>
 11#include <linux/io.h>
 12#include <linux/coresight.h>
 13#include <linux/pm_runtime.h>
 14
 15/*
 16 * Coresight management registers (0xf00-0xfcc)
 17 * 0xfa0 - 0xfa4: Management	registers in PFTv1.0
 18 *		  Trace		registers in PFTv1.1
 19 */
 20#define CORESIGHT_ITCTRL	0xf00
 21#define CORESIGHT_CLAIMSET	0xfa0
 22#define CORESIGHT_CLAIMCLR	0xfa4
 23#define CORESIGHT_LAR		0xfb0
 24#define CORESIGHT_LSR		0xfb4
 25#define CORESIGHT_DEVARCH	0xfbc
 26#define CORESIGHT_AUTHSTATUS	0xfb8
 27#define CORESIGHT_DEVID		0xfc8
 28#define CORESIGHT_DEVTYPE	0xfcc
 29
 30
 31/*
 32 * Coresight device CLAIM protocol.
 33 * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore.
 34 */
 35#define CORESIGHT_CLAIM_SELF_HOSTED	BIT(1)
 36
 37#define TIMEOUT_US		100
 38#define BMVAL(val, lsb, msb)	((val & GENMASK(msb, lsb)) >> lsb)
 39
 40#define ETM_MODE_EXCL_KERN	BIT(30)
 41#define ETM_MODE_EXCL_USER	BIT(31)
 42
 43typedef u32 (*coresight_read_fn)(const struct device *, u32 offset);
 44#define __coresight_simple_func(type, func, name, lo_off, hi_off)	\
 45static ssize_t name##_show(struct device *_dev,				\
 46			   struct device_attribute *attr, char *buf)	\
 47{									\
 48	type *drvdata = dev_get_drvdata(_dev->parent);			\
 49	coresight_read_fn fn = func;					\
 50	u64 val;							\
 51	pm_runtime_get_sync(_dev->parent);				\
 52	if (fn)								\
 53		val = (u64)fn(_dev->parent, lo_off);			\
 54	else								\
 55		val = coresight_read_reg_pair(drvdata->base,		\
 56						 lo_off, hi_off);	\
 57	pm_runtime_put_sync(_dev->parent);				\
 58	return scnprintf(buf, PAGE_SIZE, "0x%llx\n", val);		\
 59}									\
 60static DEVICE_ATTR_RO(name)
 61
 62#define coresight_simple_func(type, func, name, offset)			\
 63	__coresight_simple_func(type, func, name, offset, -1)
 64#define coresight_simple_reg32(type, name, offset)			\
 65	__coresight_simple_func(type, NULL, name, offset, -1)
 66#define coresight_simple_reg64(type, name, lo_off, hi_off)		\
 67	__coresight_simple_func(type, NULL, name, lo_off, hi_off)
 68
 69extern const u32 coresight_barrier_pkt[4];
 70#define CORESIGHT_BARRIER_PKT_SIZE (sizeof(coresight_barrier_pkt))
 71
 72enum etm_addr_type {
 73	ETM_ADDR_TYPE_NONE,
 74	ETM_ADDR_TYPE_SINGLE,
 75	ETM_ADDR_TYPE_RANGE,
 76	ETM_ADDR_TYPE_START,
 77	ETM_ADDR_TYPE_STOP,
 78};
 79
 80enum cs_mode {
 81	CS_MODE_DISABLED,
 82	CS_MODE_SYSFS,
 83	CS_MODE_PERF,
 84};
 85
 86/**
 87 * struct cs_buffer - keep track of a recording session' specifics
 88 * @cur:	index of the current buffer
 89 * @nr_pages:	max number of pages granted to us
 90 * @pid:	PID this cs_buffer belongs to
 91 * @offset:	offset within the current buffer
 92 * @data_size:	how much we collected in this run
 93 * @snapshot:	is this run in snapshot mode
 94 * @data_pages:	a handle the ring buffer
 95 */
 96struct cs_buffers {
 97	unsigned int		cur;
 98	unsigned int		nr_pages;
 99	pid_t			pid;
100	unsigned long		offset;
101	local_t			data_size;
102	bool			snapshot;
103	void			**data_pages;
104};
105
106static inline void coresight_insert_barrier_packet(void *buf)
107{
108	if (buf)
109		memcpy(buf, coresight_barrier_pkt, CORESIGHT_BARRIER_PKT_SIZE);
110}
111
112static inline void CS_LOCK(void __iomem *addr)
113{
114	do {
115		/* Wait for things to settle */
116		mb();
117		writel_relaxed(0x0, addr + CORESIGHT_LAR);
118	} while (0);
119}
120
121static inline void CS_UNLOCK(void __iomem *addr)
122{
123	do {
124		writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
125		/* Make sure everyone has seen this */
126		mb();
127	} while (0);
128}
129
130static inline u64
131coresight_read_reg_pair(void __iomem *addr, s32 lo_offset, s32 hi_offset)
132{
133	u64 val;
134
135	val = readl_relaxed(addr + lo_offset);
136	val |= (hi_offset < 0) ? 0 :
137	       (u64)readl_relaxed(addr + hi_offset) << 32;
138	return val;
139}
140
141static inline void coresight_write_reg_pair(void __iomem *addr, u64 val,
142						 s32 lo_offset, s32 hi_offset)
143{
144	writel_relaxed((u32)val, addr + lo_offset);
145	if (hi_offset >= 0)
146		writel_relaxed((u32)(val >> 32), addr + hi_offset);
147}
148
149void coresight_disable_path(struct list_head *path);
150int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data);
151struct coresight_device *coresight_get_sink(struct list_head *path);
152struct coresight_device *
153coresight_get_enabled_sink(struct coresight_device *source);
154struct coresight_device *coresight_get_sink_by_id(u32 id);
155struct coresight_device *
156coresight_find_default_sink(struct coresight_device *csdev);
157struct list_head *coresight_build_path(struct coresight_device *csdev,
158				       struct coresight_device *sink);
159void coresight_release_path(struct list_head *path);
160int coresight_add_sysfs_link(struct coresight_sysfs_link *info);
161void coresight_remove_sysfs_link(struct coresight_sysfs_link *info);
162int coresight_create_conns_sysfs_group(struct coresight_device *csdev);
163void coresight_remove_conns_sysfs_group(struct coresight_device *csdev);
164int coresight_make_links(struct coresight_device *orig,
165			 struct coresight_connection *conn,
166			 struct coresight_device *target);
167void coresight_remove_links(struct coresight_device *orig,
168			    struct coresight_connection *conn);
169
170#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X)
171extern int etm_readl_cp14(u32 off, unsigned int *val);
172extern int etm_writel_cp14(u32 off, u32 val);
173#else
174static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; }
175static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
176#endif
177
178struct cti_assoc_op {
179	void (*add)(struct coresight_device *csdev);
180	void (*remove)(struct coresight_device *csdev);
181};
182
183extern void coresight_set_cti_ops(const struct cti_assoc_op *cti_op);
184extern void coresight_remove_cti_ops(void);
185
186/*
187 * Macros and inline functions to handle CoreSight UCI data and driver
188 * private data in AMBA ID table entries, and extract data values.
189 */
190
191/* coresight AMBA ID, no UCI, no driver data: id table entry */
192#define CS_AMBA_ID(pid)			\
193	{				\
194		.id	= pid,		\
195		.mask	= 0x000fffff,	\
196	}
197
198/* coresight AMBA ID, UCI with driver data only: id table entry. */
199#define CS_AMBA_ID_DATA(pid, dval)				\
200	{							\
201		.id	= pid,					\
202		.mask	= 0x000fffff,				\
203		.data	=  (void *)&(struct amba_cs_uci_id)	\
204			{				\
205				.data = (void *)dval,	\
206			}				\
207	}
208
209/* coresight AMBA ID, full UCI structure: id table entry. */
210#define CS_AMBA_UCI_ID(pid, uci_ptr)		\
211	{					\
212		.id	= pid,			\
213		.mask	= 0x000fffff,		\
214		.data	= (void *)uci_ptr	\
215	}
216
217/* extract the data value from a UCI structure given amba_id pointer. */
218static inline void *coresight_get_uci_data(const struct amba_id *id)
219{
220	struct amba_cs_uci_id *uci_id = id->data;
221
222	if (!uci_id)
223		return NULL;
224
225	return uci_id->data;
226}
227
228void coresight_release_platform_data(struct coresight_device *csdev,
229				     struct coresight_platform_data *pdata);
230struct coresight_device *
231coresight_find_csdev_by_fwnode(struct fwnode_handle *r_fwnode);
232void coresight_set_assoc_ectdev_mutex(struct coresight_device *csdev,
233				      struct coresight_device *ect_csdev);
234
235void coresight_set_percpu_sink(int cpu, struct coresight_device *csdev);
236struct coresight_device *coresight_get_percpu_sink(int cpu);
237
238#endif