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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/bitops.h>
7#include <linux/kernel.h>
8#include <linux/moduleparam.h>
9#include <linux/init.h>
10#include <linux/types.h>
11#include <linux/device.h>
12#include <linux/io.h>
13#include <linux/err.h>
14#include <linux/fs.h>
15#include <linux/slab.h>
16#include <linux/delay.h>
17#include <linux/smp.h>
18#include <linux/sysfs.h>
19#include <linux/stat.h>
20#include <linux/clk.h>
21#include <linux/cpu.h>
22#include <linux/cpu_pm.h>
23#include <linux/coresight.h>
24#include <linux/coresight-pmu.h>
25#include <linux/pm_wakeup.h>
26#include <linux/amba/bus.h>
27#include <linux/seq_file.h>
28#include <linux/uaccess.h>
29#include <linux/perf_event.h>
30#include <linux/platform_device.h>
31#include <linux/pm_runtime.h>
32#include <linux/property.h>
33
34#include <asm/barrier.h>
35#include <asm/sections.h>
36#include <asm/sysreg.h>
37#include <asm/local.h>
38#include <asm/virt.h>
39
40#include "coresight-etm4x.h"
41#include "coresight-etm-perf.h"
42
43static int boot_enable;
44module_param(boot_enable, int, 0444);
45MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
46
47#define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */
48#define PARAM_PM_SAVE_NEVER 1 /* never save any state */
49#define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
50
51static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
52module_param(pm_save_enable, int, 0444);
53MODULE_PARM_DESC(pm_save_enable,
54 "Save/restore state on power down: 1 = never, 2 = self-hosted");
55
56static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
57static void etm4_set_default_config(struct etmv4_config *config);
58static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
59 struct perf_event *event);
60static u64 etm4_get_access_type(struct etmv4_config *config);
61
62static enum cpuhp_state hp_online;
63
64struct etm4_init_arg {
65 unsigned int pid;
66 struct etmv4_drvdata *drvdata;
67 struct csdev_access *csa;
68};
69
70/*
71 * Check if TRCSSPCICRn(i) is implemented for a given instance.
72 *
73 * TRCSSPCICRn is implemented only if :
74 * TRCSSPCICR<n> is present only if all of the following are true:
75 * TRCIDR4.NUMSSCC > n.
76 * TRCIDR4.NUMPC > 0b0000 .
77 * TRCSSCSR<n>.PC == 0b1
78 */
79static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
80{
81 return (n < drvdata->nr_ss_cmp) &&
82 drvdata->nr_pe &&
83 (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
84}
85
86u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
87{
88 u64 res = 0;
89
90 switch (offset) {
91 ETM4x_READ_SYSREG_CASES(res)
92 default :
93 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n",
94 offset);
95 }
96
97 if (!_relaxed)
98 __iormb(res); /* Imitate the !relaxed I/O helpers */
99
100 return res;
101}
102
103void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
104{
105 if (!_relaxed)
106 __iowmb(); /* Imitate the !relaxed I/O helpers */
107 if (!_64bit)
108 val &= GENMASK(31, 0);
109
110 switch (offset) {
111 ETM4x_WRITE_SYSREG_CASES(val)
112 default :
113 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n",
114 offset);
115 }
116}
117
118static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
119{
120 u64 res = 0;
121
122 switch (offset) {
123 ETE_READ_CASES(res)
124 default :
125 pr_warn_ratelimited("ete: trying to read unsupported register @%x\n",
126 offset);
127 }
128
129 if (!_relaxed)
130 __iormb(res); /* Imitate the !relaxed I/O helpers */
131
132 return res;
133}
134
135static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
136{
137 if (!_relaxed)
138 __iowmb(); /* Imitate the !relaxed I/O helpers */
139 if (!_64bit)
140 val &= GENMASK(31, 0);
141
142 switch (offset) {
143 ETE_WRITE_CASES(val)
144 default :
145 pr_warn_ratelimited("ete: trying to write to unsupported register @%x\n",
146 offset);
147 }
148}
149
150static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
151 struct csdev_access *csa)
152{
153 u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
154
155 drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
156}
157
158static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
159 struct csdev_access *csa, u32 val)
160{
161 val = !!val;
162
163 switch (drvdata->os_lock_model) {
164 case ETM_OSLOCK_PRESENT:
165 etm4x_relaxed_write32(csa, val, TRCOSLAR);
166 break;
167 case ETM_OSLOCK_PE:
168 write_sysreg_s(val, SYS_OSLAR_EL1);
169 break;
170 default:
171 pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
172 smp_processor_id(), drvdata->os_lock_model);
173 fallthrough;
174 case ETM_OSLOCK_NI:
175 return;
176 }
177 isb();
178}
179
180static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
181 struct csdev_access *csa)
182{
183 WARN_ON(drvdata->cpu != smp_processor_id());
184
185 /* Writing 0 to OS Lock unlocks the trace unit registers */
186 etm_write_os_lock(drvdata, csa, 0x0);
187 drvdata->os_unlock = true;
188}
189
190static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
191{
192 if (!WARN_ON(!drvdata->csdev))
193 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
194}
195
196static void etm4_os_lock(struct etmv4_drvdata *drvdata)
197{
198 if (WARN_ON(!drvdata->csdev))
199 return;
200 /* Writing 0x1 to OS Lock locks the trace registers */
201 etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
202 drvdata->os_unlock = false;
203}
204
205static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
206 struct csdev_access *csa)
207{
208 /* Software Lock is only accessible via memory mapped interface */
209 if (csa->io_mem)
210 CS_LOCK(csa->base);
211}
212
213static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
214 struct csdev_access *csa)
215{
216 if (csa->io_mem)
217 CS_UNLOCK(csa->base);
218}
219
220static int etm4_cpu_id(struct coresight_device *csdev)
221{
222 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
223
224 return drvdata->cpu;
225}
226
227static int etm4_trace_id(struct coresight_device *csdev)
228{
229 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
230
231 return drvdata->trcid;
232}
233
234struct etm4_enable_arg {
235 struct etmv4_drvdata *drvdata;
236 int rc;
237};
238
239#ifdef CONFIG_ETM4X_IMPDEF_FEATURE
240
241#define HISI_HIP08_AMBA_ID 0x000b6d01
242#define ETM4_AMBA_MASK 0xfffff
243#define HISI_HIP08_CORE_COMMIT_MASK 0x3000
244#define HISI_HIP08_CORE_COMMIT_SHIFT 12
245#define HISI_HIP08_CORE_COMMIT_FULL 0b00
246#define HISI_HIP08_CORE_COMMIT_LVL_1 0b01
247#define HISI_HIP08_CORE_COMMIT_REG sys_reg(3, 1, 15, 2, 5)
248
249struct etm4_arch_features {
250 void (*arch_callback)(bool enable);
251};
252
253static bool etm4_hisi_match_pid(unsigned int id)
254{
255 return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
256}
257
258static void etm4_hisi_config_core_commit(bool enable)
259{
260 u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :
261 HISI_HIP08_CORE_COMMIT_FULL;
262 u64 val;
263
264 /*
265 * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
266 * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
267 * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
268 * speed(minimun value). So bit 12 and 13 should be cleared together.
269 */
270 val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
271 val &= ~HISI_HIP08_CORE_COMMIT_MASK;
272 val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
273 write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
274}
275
276static struct etm4_arch_features etm4_features[] = {
277 [ETM4_IMPDEF_HISI_CORE_COMMIT] = {
278 .arch_callback = etm4_hisi_config_core_commit,
279 },
280 {},
281};
282
283static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
284{
285 struct etm4_arch_features *ftr;
286 int bit;
287
288 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
289 ftr = &etm4_features[bit];
290
291 if (ftr->arch_callback)
292 ftr->arch_callback(true);
293 }
294}
295
296static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
297{
298 struct etm4_arch_features *ftr;
299 int bit;
300
301 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
302 ftr = &etm4_features[bit];
303
304 if (ftr->arch_callback)
305 ftr->arch_callback(false);
306 }
307}
308
309static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
310 unsigned int id)
311{
312 if (etm4_hisi_match_pid(id))
313 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
314}
315#else
316static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
317{
318}
319
320static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
321{
322}
323
324static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
325 unsigned int id)
326{
327}
328#endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
329
330static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
331{
332 int i, rc;
333 struct etmv4_config *config = &drvdata->config;
334 struct coresight_device *csdev = drvdata->csdev;
335 struct device *etm_dev = &csdev->dev;
336 struct csdev_access *csa = &csdev->access;
337
338
339 etm4_cs_unlock(drvdata, csa);
340 etm4_enable_arch_specific(drvdata);
341
342 etm4_os_unlock(drvdata);
343
344 rc = coresight_claim_device_unlocked(csdev);
345 if (rc)
346 goto done;
347
348 /* Disable the trace unit before programming trace registers */
349 etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
350
351 /*
352 * If we use system instructions, we need to synchronize the
353 * write to the TRCPRGCTLR, before accessing the TRCSTATR.
354 * See ARM IHI0064F, section
355 * "4.3.7 Synchronization of register updates"
356 */
357 if (!csa->io_mem)
358 isb();
359
360 /* wait for TRCSTATR.IDLE to go up */
361 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
362 dev_err(etm_dev,
363 "timeout while waiting for Idle Trace Status\n");
364 if (drvdata->nr_pe)
365 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
366 etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
367 /* nothing specific implemented */
368 etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
369 etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
370 etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
371 if (drvdata->stallctl)
372 etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
373 etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
374 etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
375 etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
376 etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR);
377 etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR);
378 etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
379 etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
380 etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
381 if (drvdata->nr_pe_cmp)
382 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
383 for (i = 0; i < drvdata->nrseqstate - 1; i++)
384 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
385 etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
386 etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
387 etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
388 for (i = 0; i < drvdata->nr_cntr; i++) {
389 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
390 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
391 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
392 }
393
394 /*
395 * Resource selector pair 0 is always implemented and reserved. As
396 * such start at 2.
397 */
398 for (i = 2; i < drvdata->nr_resource * 2; i++)
399 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
400
401 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
402 /* always clear status bit on restart if using single-shot */
403 if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
404 config->ss_status[i] &= ~BIT(31);
405 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
406 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
407 if (etm4x_sspcicrn_present(drvdata, i))
408 etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
409 }
410 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
411 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
412 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
413 }
414 for (i = 0; i < drvdata->numcidc; i++)
415 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
416 etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
417 if (drvdata->numcidc > 4)
418 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
419
420 for (i = 0; i < drvdata->numvmidc; i++)
421 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
422 etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
423 if (drvdata->numvmidc > 4)
424 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
425
426 if (!drvdata->skip_power_up) {
427 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
428
429 /*
430 * Request to keep the trace unit powered and also
431 * emulation of powerdown
432 */
433 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
434 }
435
436 /*
437 * ETE mandates that the TRCRSR is written to before
438 * enabling it.
439 */
440 if (etm4x_is_ete(drvdata))
441 etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
442
443 /* Enable the trace unit */
444 etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
445
446 /* Synchronize the register updates for sysreg access */
447 if (!csa->io_mem)
448 isb();
449
450 /* wait for TRCSTATR.IDLE to go back down to '0' */
451 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
452 dev_err(etm_dev,
453 "timeout while waiting for Idle Trace Status\n");
454
455 /*
456 * As recommended by section 4.3.7 ("Synchronization when using the
457 * memory-mapped interface") of ARM IHI 0064D
458 */
459 dsb(sy);
460 isb();
461
462done:
463 etm4_cs_lock(drvdata, csa);
464
465 dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
466 drvdata->cpu, rc);
467 return rc;
468}
469
470static void etm4_enable_hw_smp_call(void *info)
471{
472 struct etm4_enable_arg *arg = info;
473
474 if (WARN_ON(!arg))
475 return;
476 arg->rc = etm4_enable_hw(arg->drvdata);
477}
478
479/*
480 * The goal of function etm4_config_timestamp_event() is to configure a
481 * counter that will tell the tracer to emit a timestamp packet when it
482 * reaches zero. This is done in order to get a more fine grained idea
483 * of when instructions are executed so that they can be correlated
484 * with execution on other CPUs.
485 *
486 * To do this the counter itself is configured to self reload and
487 * TRCRSCTLR1 (always true) used to get the counter to decrement. From
488 * there a resource selector is configured with the counter and the
489 * timestamp control register to use the resource selector to trigger the
490 * event that will insert a timestamp packet in the stream.
491 */
492static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
493{
494 int ctridx, ret = -EINVAL;
495 int counter, rselector;
496 u32 val = 0;
497 struct etmv4_config *config = &drvdata->config;
498
499 /* No point in trying if we don't have at least one counter */
500 if (!drvdata->nr_cntr)
501 goto out;
502
503 /* Find a counter that hasn't been initialised */
504 for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
505 if (config->cntr_val[ctridx] == 0)
506 break;
507
508 /* All the counters have been configured already, bail out */
509 if (ctridx == drvdata->nr_cntr) {
510 pr_debug("%s: no available counter found\n", __func__);
511 ret = -ENOSPC;
512 goto out;
513 }
514
515 /*
516 * Searching for an available resource selector to use, starting at
517 * '2' since every implementation has at least 2 resource selector.
518 * ETMIDR4 gives the number of resource selector _pairs_,
519 * hence multiply by 2.
520 */
521 for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
522 if (!config->res_ctrl[rselector])
523 break;
524
525 if (rselector == drvdata->nr_resource * 2) {
526 pr_debug("%s: no available resource selector found\n",
527 __func__);
528 ret = -ENOSPC;
529 goto out;
530 }
531
532 /* Remember what counter we used */
533 counter = 1 << ctridx;
534
535 /*
536 * Initialise original and reload counter value to the smallest
537 * possible value in order to get as much precision as we can.
538 */
539 config->cntr_val[ctridx] = 1;
540 config->cntrldvr[ctridx] = 1;
541
542 /* Set the trace counter control register */
543 val = 0x1 << 16 | /* Bit 16, reload counter automatically */
544 0x0 << 7 | /* Select single resource selector */
545 0x1; /* Resource selector 1, i.e always true */
546
547 config->cntr_ctrl[ctridx] = val;
548
549 val = 0x2 << 16 | /* Group 0b0010 - Counter and sequencers */
550 counter << 0; /* Counter to use */
551
552 config->res_ctrl[rselector] = val;
553
554 val = 0x0 << 7 | /* Select single resource selector */
555 rselector; /* Resource selector */
556
557 config->ts_ctrl = val;
558
559 ret = 0;
560out:
561 return ret;
562}
563
564static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
565 struct perf_event *event)
566{
567 int ret = 0;
568 struct etmv4_config *config = &drvdata->config;
569 struct perf_event_attr *attr = &event->attr;
570
571 /* Clear configuration from previous run */
572 memset(config, 0, sizeof(struct etmv4_config));
573
574 if (attr->exclude_kernel)
575 config->mode = ETM_MODE_EXCL_KERN;
576
577 if (attr->exclude_user)
578 config->mode = ETM_MODE_EXCL_USER;
579
580 /* Always start from the default config */
581 etm4_set_default_config(config);
582
583 /* Configure filters specified on the perf cmd line, if any. */
584 ret = etm4_set_event_filters(drvdata, event);
585 if (ret)
586 goto out;
587
588 /* Go from generic option to ETMv4 specifics */
589 if (attr->config & BIT(ETM_OPT_CYCACC)) {
590 config->cfg |= BIT(4);
591 /* TRM: Must program this for cycacc to work */
592 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
593 }
594 if (attr->config & BIT(ETM_OPT_TS)) {
595 /*
596 * Configure timestamps to be emitted at regular intervals in
597 * order to correlate instructions executed on different CPUs
598 * (CPU-wide trace scenarios).
599 */
600 ret = etm4_config_timestamp_event(drvdata);
601
602 /*
603 * No need to go further if timestamp intervals can't
604 * be configured.
605 */
606 if (ret)
607 goto out;
608
609 /* bit[11], Global timestamp tracing bit */
610 config->cfg |= BIT(11);
611 }
612
613 if (attr->config & BIT(ETM_OPT_CTXTID))
614 /* bit[6], Context ID tracing bit */
615 config->cfg |= BIT(ETM4_CFG_BIT_CTXTID);
616
617 /*
618 * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID
619 * for recording CONTEXTIDR_EL2. Do not enable VMID tracing if the
620 * kernel is not running in EL2.
621 */
622 if (attr->config & BIT(ETM_OPT_CTXTID2)) {
623 if (!is_kernel_in_hyp_mode()) {
624 ret = -EINVAL;
625 goto out;
626 }
627 config->cfg |= BIT(ETM4_CFG_BIT_VMID) | BIT(ETM4_CFG_BIT_VMID_OPT);
628 }
629
630 /* return stack - enable if selected and supported */
631 if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
632 /* bit[12], Return stack enable bit */
633 config->cfg |= BIT(12);
634
635out:
636 return ret;
637}
638
639static int etm4_enable_perf(struct coresight_device *csdev,
640 struct perf_event *event)
641{
642 int ret = 0;
643 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
644
645 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
646 ret = -EINVAL;
647 goto out;
648 }
649
650 /* Configure the tracer based on the session's specifics */
651 ret = etm4_parse_event_config(drvdata, event);
652 if (ret)
653 goto out;
654 /* And enable it */
655 ret = etm4_enable_hw(drvdata);
656
657out:
658 return ret;
659}
660
661static int etm4_enable_sysfs(struct coresight_device *csdev)
662{
663 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
664 struct etm4_enable_arg arg = { };
665 int ret;
666
667 spin_lock(&drvdata->spinlock);
668
669 /*
670 * Executing etm4_enable_hw on the cpu whose ETM is being enabled
671 * ensures that register writes occur when cpu is powered.
672 */
673 arg.drvdata = drvdata;
674 ret = smp_call_function_single(drvdata->cpu,
675 etm4_enable_hw_smp_call, &arg, 1);
676 if (!ret)
677 ret = arg.rc;
678 if (!ret)
679 drvdata->sticky_enable = true;
680 spin_unlock(&drvdata->spinlock);
681
682 if (!ret)
683 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
684 return ret;
685}
686
687static int etm4_enable(struct coresight_device *csdev,
688 struct perf_event *event, u32 mode)
689{
690 int ret;
691 u32 val;
692 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
693
694 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
695
696 /* Someone is already using the tracer */
697 if (val)
698 return -EBUSY;
699
700 switch (mode) {
701 case CS_MODE_SYSFS:
702 ret = etm4_enable_sysfs(csdev);
703 break;
704 case CS_MODE_PERF:
705 ret = etm4_enable_perf(csdev, event);
706 break;
707 default:
708 ret = -EINVAL;
709 }
710
711 /* The tracer didn't start */
712 if (ret)
713 local_set(&drvdata->mode, CS_MODE_DISABLED);
714
715 return ret;
716}
717
718static void etm4_disable_hw(void *info)
719{
720 u32 control;
721 u64 trfcr;
722 struct etmv4_drvdata *drvdata = info;
723 struct etmv4_config *config = &drvdata->config;
724 struct coresight_device *csdev = drvdata->csdev;
725 struct device *etm_dev = &csdev->dev;
726 struct csdev_access *csa = &csdev->access;
727 int i;
728
729 etm4_cs_unlock(drvdata, csa);
730 etm4_disable_arch_specific(drvdata);
731
732 if (!drvdata->skip_power_up) {
733 /* power can be removed from the trace unit now */
734 control = etm4x_relaxed_read32(csa, TRCPDCR);
735 control &= ~TRCPDCR_PU;
736 etm4x_relaxed_write32(csa, control, TRCPDCR);
737 }
738
739 control = etm4x_relaxed_read32(csa, TRCPRGCTLR);
740
741 /* EN, bit[0] Trace unit enable bit */
742 control &= ~0x1;
743
744 /*
745 * If the CPU supports v8.4 Trace filter Control,
746 * set the ETM to trace prohibited region.
747 */
748 if (drvdata->trfc) {
749 trfcr = read_sysreg_s(SYS_TRFCR_EL1);
750 write_sysreg_s(trfcr & ~(TRFCR_ELx_ExTRE | TRFCR_ELx_E0TRE),
751 SYS_TRFCR_EL1);
752 isb();
753 }
754 /*
755 * Make sure everything completes before disabling, as recommended
756 * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
757 * SSTATUS") of ARM IHI 0064D
758 */
759 dsb(sy);
760 isb();
761 /* Trace synchronization barrier, is a nop if not supported */
762 tsb_csync();
763 etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
764
765 /* wait for TRCSTATR.PMSTABLE to go to '1' */
766 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
767 dev_err(etm_dev,
768 "timeout while waiting for PM stable Trace Status\n");
769 if (drvdata->trfc)
770 write_sysreg_s(trfcr, SYS_TRFCR_EL1);
771
772 /* read the status of the single shot comparators */
773 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
774 config->ss_status[i] =
775 etm4x_relaxed_read32(csa, TRCSSCSRn(i));
776 }
777
778 /* read back the current counter values */
779 for (i = 0; i < drvdata->nr_cntr; i++) {
780 config->cntr_val[i] =
781 etm4x_relaxed_read32(csa, TRCCNTVRn(i));
782 }
783
784 coresight_disclaim_device_unlocked(csdev);
785 etm4_cs_lock(drvdata, csa);
786
787 dev_dbg(&drvdata->csdev->dev,
788 "cpu: %d disable smp call done\n", drvdata->cpu);
789}
790
791static int etm4_disable_perf(struct coresight_device *csdev,
792 struct perf_event *event)
793{
794 u32 control;
795 struct etm_filters *filters = event->hw.addr_filters;
796 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
797
798 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
799 return -EINVAL;
800
801 etm4_disable_hw(drvdata);
802
803 /*
804 * Check if the start/stop logic was active when the unit was stopped.
805 * That way we can re-enable the start/stop logic when the process is
806 * scheduled again. Configuration of the start/stop logic happens in
807 * function etm4_set_event_filters().
808 */
809 control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR);
810 /* TRCVICTLR::SSSTATUS, bit[9] */
811 filters->ssstatus = (control & BIT(9));
812
813 return 0;
814}
815
816static void etm4_disable_sysfs(struct coresight_device *csdev)
817{
818 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
819
820 /*
821 * Taking hotplug lock here protects from clocks getting disabled
822 * with tracing being left on (crash scenario) if user disable occurs
823 * after cpu online mask indicates the cpu is offline but before the
824 * DYING hotplug callback is serviced by the ETM driver.
825 */
826 cpus_read_lock();
827 spin_lock(&drvdata->spinlock);
828
829 /*
830 * Executing etm4_disable_hw on the cpu whose ETM is being disabled
831 * ensures that register writes occur when cpu is powered.
832 */
833 smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
834
835 spin_unlock(&drvdata->spinlock);
836 cpus_read_unlock();
837
838 dev_dbg(&csdev->dev, "ETM tracing disabled\n");
839}
840
841static void etm4_disable(struct coresight_device *csdev,
842 struct perf_event *event)
843{
844 u32 mode;
845 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
846
847 /*
848 * For as long as the tracer isn't disabled another entity can't
849 * change its status. As such we can read the status here without
850 * fearing it will change under us.
851 */
852 mode = local_read(&drvdata->mode);
853
854 switch (mode) {
855 case CS_MODE_DISABLED:
856 break;
857 case CS_MODE_SYSFS:
858 etm4_disable_sysfs(csdev);
859 break;
860 case CS_MODE_PERF:
861 etm4_disable_perf(csdev, event);
862 break;
863 }
864
865 if (mode)
866 local_set(&drvdata->mode, CS_MODE_DISABLED);
867}
868
869static const struct coresight_ops_source etm4_source_ops = {
870 .cpu_id = etm4_cpu_id,
871 .trace_id = etm4_trace_id,
872 .enable = etm4_enable,
873 .disable = etm4_disable,
874};
875
876static const struct coresight_ops etm4_cs_ops = {
877 .source_ops = &etm4_source_ops,
878};
879
880static inline bool cpu_supports_sysreg_trace(void)
881{
882 u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
883
884 return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) > 0;
885}
886
887static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
888 struct csdev_access *csa)
889{
890 u32 devarch;
891
892 if (!cpu_supports_sysreg_trace())
893 return false;
894
895 /*
896 * ETMs implementing sysreg access must implement TRCDEVARCH.
897 */
898 devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
899 switch (devarch & ETM_DEVARCH_ID_MASK) {
900 case ETM_DEVARCH_ETMv4x_ARCH:
901 *csa = (struct csdev_access) {
902 .io_mem = false,
903 .read = etm4x_sysreg_read,
904 .write = etm4x_sysreg_write,
905 };
906 break;
907 case ETM_DEVARCH_ETE_ARCH:
908 *csa = (struct csdev_access) {
909 .io_mem = false,
910 .read = ete_sysreg_read,
911 .write = ete_sysreg_write,
912 };
913 break;
914 default:
915 return false;
916 }
917
918 drvdata->arch = etm_devarch_to_arch(devarch);
919 return true;
920}
921
922static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata,
923 struct csdev_access *csa)
924{
925 u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);
926 u32 idr1 = readl_relaxed(drvdata->base + TRCIDR1);
927
928 /*
929 * All ETMs must implement TRCDEVARCH to indicate that
930 * the component is an ETMv4. To support any broken
931 * implementations we fall back to TRCIDR1 check, which
932 * is not really reliable.
933 */
934 if ((devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH) {
935 drvdata->arch = etm_devarch_to_arch(devarch);
936 } else {
937 pr_warn("CPU%d: ETM4x incompatible TRCDEVARCH: %x, falling back to TRCIDR1\n",
938 smp_processor_id(), devarch);
939
940 if (ETM_TRCIDR1_ARCH_MAJOR(idr1) != ETM_TRCIDR1_ARCH_ETMv4)
941 return false;
942 drvdata->arch = etm_trcidr_to_arch(idr1);
943 }
944
945 *csa = CSDEV_ACCESS_IOMEM(drvdata->base);
946 return true;
947}
948
949static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
950 struct csdev_access *csa)
951{
952 /*
953 * Always choose the memory mapped io, if there is
954 * a memory map to prevent sysreg access on broken
955 * systems.
956 */
957 if (drvdata->base)
958 return etm4_init_iomem_access(drvdata, csa);
959
960 if (etm4_init_sysreg_access(drvdata, csa))
961 return true;
962
963 return false;
964}
965
966static void cpu_enable_tracing(struct etmv4_drvdata *drvdata)
967{
968 u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
969 u64 trfcr;
970
971 if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_TRACE_FILT_SHIFT))
972 return;
973
974 drvdata->trfc = true;
975 /*
976 * If the CPU supports v8.4 SelfHosted Tracing, enable
977 * tracing at the kernel EL and EL0, forcing to use the
978 * virtual time as the timestamp.
979 */
980 trfcr = (TRFCR_ELx_TS_VIRTUAL |
981 TRFCR_ELx_ExTRE |
982 TRFCR_ELx_E0TRE);
983
984 /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */
985 if (is_kernel_in_hyp_mode())
986 trfcr |= TRFCR_EL2_CX;
987
988 write_sysreg_s(trfcr, SYS_TRFCR_EL1);
989}
990
991static void etm4_init_arch_data(void *info)
992{
993 u32 etmidr0;
994 u32 etmidr2;
995 u32 etmidr3;
996 u32 etmidr4;
997 u32 etmidr5;
998 struct etm4_init_arg *init_arg = info;
999 struct etmv4_drvdata *drvdata;
1000 struct csdev_access *csa;
1001 int i;
1002
1003 drvdata = init_arg->drvdata;
1004 csa = init_arg->csa;
1005
1006 /*
1007 * If we are unable to detect the access mechanism,
1008 * or unable to detect the trace unit type, fail
1009 * early.
1010 */
1011 if (!etm4_init_csdev_access(drvdata, csa))
1012 return;
1013
1014 /* Detect the support for OS Lock before we actually use it */
1015 etm_detect_os_lock(drvdata, csa);
1016
1017 /* Make sure all registers are accessible */
1018 etm4_os_unlock_csa(drvdata, csa);
1019 etm4_cs_unlock(drvdata, csa);
1020
1021 etm4_check_arch_features(drvdata, init_arg->pid);
1022
1023 /* find all capabilities of the tracing unit */
1024 etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
1025
1026 /* INSTP0, bits[2:1] P0 tracing support field */
1027 if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
1028 drvdata->instrp0 = true;
1029 else
1030 drvdata->instrp0 = false;
1031
1032 /* TRCBB, bit[5] Branch broadcast tracing support bit */
1033 if (BMVAL(etmidr0, 5, 5))
1034 drvdata->trcbb = true;
1035 else
1036 drvdata->trcbb = false;
1037
1038 /* TRCCOND, bit[6] Conditional instruction tracing support bit */
1039 if (BMVAL(etmidr0, 6, 6))
1040 drvdata->trccond = true;
1041 else
1042 drvdata->trccond = false;
1043
1044 /* TRCCCI, bit[7] Cycle counting instruction bit */
1045 if (BMVAL(etmidr0, 7, 7))
1046 drvdata->trccci = true;
1047 else
1048 drvdata->trccci = false;
1049
1050 /* RETSTACK, bit[9] Return stack bit */
1051 if (BMVAL(etmidr0, 9, 9))
1052 drvdata->retstack = true;
1053 else
1054 drvdata->retstack = false;
1055
1056 /* NUMEVENT, bits[11:10] Number of events field */
1057 drvdata->nr_event = BMVAL(etmidr0, 10, 11);
1058 /* QSUPP, bits[16:15] Q element support field */
1059 drvdata->q_support = BMVAL(etmidr0, 15, 16);
1060 /* TSSIZE, bits[28:24] Global timestamp size field */
1061 drvdata->ts_size = BMVAL(etmidr0, 24, 28);
1062
1063 /* maximum size of resources */
1064 etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
1065 /* CIDSIZE, bits[9:5] Indicates the Context ID size */
1066 drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
1067 /* VMIDSIZE, bits[14:10] Indicates the VMID size */
1068 drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
1069 /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
1070 drvdata->ccsize = BMVAL(etmidr2, 25, 28);
1071
1072 etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
1073 /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
1074 drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
1075 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
1076 drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
1077 drvdata->config.s_ex_level = drvdata->s_ex_level;
1078 /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
1079 drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
1080
1081 /*
1082 * TRCERR, bit[24] whether a trace unit can trace a
1083 * system error exception.
1084 */
1085 if (BMVAL(etmidr3, 24, 24))
1086 drvdata->trc_error = true;
1087 else
1088 drvdata->trc_error = false;
1089
1090 /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
1091 if (BMVAL(etmidr3, 25, 25))
1092 drvdata->syncpr = true;
1093 else
1094 drvdata->syncpr = false;
1095
1096 /* STALLCTL, bit[26] is stall control implemented? */
1097 if (BMVAL(etmidr3, 26, 26))
1098 drvdata->stallctl = true;
1099 else
1100 drvdata->stallctl = false;
1101
1102 /* SYSSTALL, bit[27] implementation can support stall control? */
1103 if (BMVAL(etmidr3, 27, 27))
1104 drvdata->sysstall = true;
1105 else
1106 drvdata->sysstall = false;
1107
1108 /*
1109 * NUMPROC - the number of PEs available for tracing, 5bits
1110 * = TRCIDR3.bits[13:12]bits[30:28]
1111 * bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
1112 * bits[3:0] = TRCIDR3.bits[30:28]
1113 */
1114 drvdata->nr_pe = (BMVAL(etmidr3, 12, 13) << 3) | BMVAL(etmidr3, 28, 30);
1115
1116 /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
1117 if (BMVAL(etmidr3, 31, 31))
1118 drvdata->nooverflow = true;
1119 else
1120 drvdata->nooverflow = false;
1121
1122 /* number of resources trace unit supports */
1123 etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
1124 /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
1125 drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
1126 /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
1127 drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
1128 /*
1129 * NUMRSPAIR, bits[19:16]
1130 * The number of resource pairs conveyed by the HW starts at 0, i.e a
1131 * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
1132 * As such add 1 to the value of NUMRSPAIR for a better representation.
1133 *
1134 * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
1135 * the default TRUE and FALSE resource selectors are omitted.
1136 * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
1137 */
1138 drvdata->nr_resource = BMVAL(etmidr4, 16, 19);
1139 if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
1140 drvdata->nr_resource += 1;
1141 /*
1142 * NUMSSCC, bits[23:20] the number of single-shot
1143 * comparator control for tracing. Read any status regs as these
1144 * also contain RO capability data.
1145 */
1146 drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
1147 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1148 drvdata->config.ss_status[i] =
1149 etm4x_relaxed_read32(csa, TRCSSCSRn(i));
1150 }
1151 /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
1152 drvdata->numcidc = BMVAL(etmidr4, 24, 27);
1153 /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
1154 drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
1155
1156 etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
1157 /* NUMEXTIN, bits[8:0] number of external inputs implemented */
1158 drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
1159 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
1160 drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
1161 /* ATBTRIG, bit[22] implementation can support ATB triggers? */
1162 if (BMVAL(etmidr5, 22, 22))
1163 drvdata->atbtrig = true;
1164 else
1165 drvdata->atbtrig = false;
1166 /*
1167 * LPOVERRIDE, bit[23] implementation supports
1168 * low-power state override
1169 */
1170 if (BMVAL(etmidr5, 23, 23) && (!drvdata->skip_power_up))
1171 drvdata->lpoverride = true;
1172 else
1173 drvdata->lpoverride = false;
1174 /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
1175 drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
1176 /* NUMCNTR, bits[30:28] number of counters available for tracing */
1177 drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
1178 etm4_cs_lock(drvdata, csa);
1179 cpu_enable_tracing(drvdata);
1180}
1181
1182static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
1183{
1184 return etm4_get_access_type(config) << TRCVICTLR_EXLEVEL_SHIFT;
1185}
1186
1187/* Set ELx trace filter access in the TRCVICTLR register */
1188static void etm4_set_victlr_access(struct etmv4_config *config)
1189{
1190 config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK;
1191 config->vinst_ctrl |= etm4_get_victlr_access_type(config);
1192}
1193
1194static void etm4_set_default_config(struct etmv4_config *config)
1195{
1196 /* disable all events tracing */
1197 config->eventctrl0 = 0x0;
1198 config->eventctrl1 = 0x0;
1199
1200 /* disable stalling */
1201 config->stall_ctrl = 0x0;
1202
1203 /* enable trace synchronization every 4096 bytes, if available */
1204 config->syncfreq = 0xC;
1205
1206 /* disable timestamp event */
1207 config->ts_ctrl = 0x0;
1208
1209 /* TRCVICTLR::EVENT = 0x01, select the always on logic */
1210 config->vinst_ctrl = BIT(0);
1211
1212 /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
1213 etm4_set_victlr_access(config);
1214}
1215
1216static u64 etm4_get_ns_access_type(struct etmv4_config *config)
1217{
1218 u64 access_type = 0;
1219
1220 /*
1221 * EXLEVEL_NS, for NonSecure Exception levels.
1222 * The mask here is a generic value and must be
1223 * shifted to the corresponding field for the registers
1224 */
1225 if (!is_kernel_in_hyp_mode()) {
1226 /* Stay away from hypervisor mode for non-VHE */
1227 access_type = ETM_EXLEVEL_NS_HYP;
1228 if (config->mode & ETM_MODE_EXCL_KERN)
1229 access_type |= ETM_EXLEVEL_NS_OS;
1230 } else if (config->mode & ETM_MODE_EXCL_KERN) {
1231 access_type = ETM_EXLEVEL_NS_HYP;
1232 }
1233
1234 if (config->mode & ETM_MODE_EXCL_USER)
1235 access_type |= ETM_EXLEVEL_NS_APP;
1236
1237 return access_type;
1238}
1239
1240/*
1241 * Construct the exception level masks for a given config.
1242 * This must be shifted to the corresponding register field
1243 * for usage.
1244 */
1245static u64 etm4_get_access_type(struct etmv4_config *config)
1246{
1247 /* All Secure exception levels are excluded from the trace */
1248 return etm4_get_ns_access_type(config) | (u64)config->s_ex_level;
1249}
1250
1251static u64 etm4_get_comparator_access_type(struct etmv4_config *config)
1252{
1253 return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT;
1254}
1255
1256static void etm4_set_comparator_filter(struct etmv4_config *config,
1257 u64 start, u64 stop, int comparator)
1258{
1259 u64 access_type = etm4_get_comparator_access_type(config);
1260
1261 /* First half of default address comparator */
1262 config->addr_val[comparator] = start;
1263 config->addr_acc[comparator] = access_type;
1264 config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
1265
1266 /* Second half of default address comparator */
1267 config->addr_val[comparator + 1] = stop;
1268 config->addr_acc[comparator + 1] = access_type;
1269 config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
1270
1271 /*
1272 * Configure the ViewInst function to include this address range
1273 * comparator.
1274 *
1275 * @comparator is divided by two since it is the index in the
1276 * etmv4_config::addr_val array but register TRCVIIECTLR deals with
1277 * address range comparator _pairs_.
1278 *
1279 * Therefore:
1280 * index 0 -> compatator pair 0
1281 * index 2 -> comparator pair 1
1282 * index 4 -> comparator pair 2
1283 * ...
1284 * index 14 -> comparator pair 7
1285 */
1286 config->viiectlr |= BIT(comparator / 2);
1287}
1288
1289static void etm4_set_start_stop_filter(struct etmv4_config *config,
1290 u64 address, int comparator,
1291 enum etm_addr_type type)
1292{
1293 int shift;
1294 u64 access_type = etm4_get_comparator_access_type(config);
1295
1296 /* Configure the comparator */
1297 config->addr_val[comparator] = address;
1298 config->addr_acc[comparator] = access_type;
1299 config->addr_type[comparator] = type;
1300
1301 /*
1302 * Configure ViewInst Start-Stop control register.
1303 * Addresses configured to start tracing go from bit 0 to n-1,
1304 * while those configured to stop tracing from 16 to 16 + n-1.
1305 */
1306 shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
1307 config->vissctlr |= BIT(shift + comparator);
1308}
1309
1310static void etm4_set_default_filter(struct etmv4_config *config)
1311{
1312 /* Trace everything 'default' filter achieved by no filtering */
1313 config->viiectlr = 0x0;
1314
1315 /*
1316 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1317 * in the started state
1318 */
1319 config->vinst_ctrl |= BIT(9);
1320 config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
1321
1322 /* No start-stop filtering for ViewInst */
1323 config->vissctlr = 0x0;
1324}
1325
1326static void etm4_set_default(struct etmv4_config *config)
1327{
1328 if (WARN_ON_ONCE(!config))
1329 return;
1330
1331 /*
1332 * Make default initialisation trace everything
1333 *
1334 * This is done by a minimum default config sufficient to enable
1335 * full instruction trace - with a default filter for trace all
1336 * achieved by having no filtering.
1337 */
1338 etm4_set_default_config(config);
1339 etm4_set_default_filter(config);
1340}
1341
1342static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
1343{
1344 int nr_comparator, index = 0;
1345 struct etmv4_config *config = &drvdata->config;
1346
1347 /*
1348 * nr_addr_cmp holds the number of comparator _pair_, so time 2
1349 * for the total number of comparators.
1350 */
1351 nr_comparator = drvdata->nr_addr_cmp * 2;
1352
1353 /* Go through the tally of comparators looking for a free one. */
1354 while (index < nr_comparator) {
1355 switch (type) {
1356 case ETM_ADDR_TYPE_RANGE:
1357 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
1358 config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
1359 return index;
1360
1361 /* Address range comparators go in pairs */
1362 index += 2;
1363 break;
1364 case ETM_ADDR_TYPE_START:
1365 case ETM_ADDR_TYPE_STOP:
1366 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
1367 return index;
1368
1369 /* Start/stop address can have odd indexes */
1370 index += 1;
1371 break;
1372 default:
1373 return -EINVAL;
1374 }
1375 }
1376
1377 /* If we are here all the comparators have been used. */
1378 return -ENOSPC;
1379}
1380
1381static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1382 struct perf_event *event)
1383{
1384 int i, comparator, ret = 0;
1385 u64 address;
1386 struct etmv4_config *config = &drvdata->config;
1387 struct etm_filters *filters = event->hw.addr_filters;
1388
1389 if (!filters)
1390 goto default_filter;
1391
1392 /* Sync events with what Perf got */
1393 perf_event_addr_filters_sync(event);
1394
1395 /*
1396 * If there are no filters to deal with simply go ahead with
1397 * the default filter, i.e the entire address range.
1398 */
1399 if (!filters->nr_filters)
1400 goto default_filter;
1401
1402 for (i = 0; i < filters->nr_filters; i++) {
1403 struct etm_filter *filter = &filters->etm_filter[i];
1404 enum etm_addr_type type = filter->type;
1405
1406 /* See if a comparator is free. */
1407 comparator = etm4_get_next_comparator(drvdata, type);
1408 if (comparator < 0) {
1409 ret = comparator;
1410 goto out;
1411 }
1412
1413 switch (type) {
1414 case ETM_ADDR_TYPE_RANGE:
1415 etm4_set_comparator_filter(config,
1416 filter->start_addr,
1417 filter->stop_addr,
1418 comparator);
1419 /*
1420 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1421 * in the started state
1422 */
1423 config->vinst_ctrl |= BIT(9);
1424
1425 /* No start-stop filtering for ViewInst */
1426 config->vissctlr = 0x0;
1427 break;
1428 case ETM_ADDR_TYPE_START:
1429 case ETM_ADDR_TYPE_STOP:
1430 /* Get the right start or stop address */
1431 address = (type == ETM_ADDR_TYPE_START ?
1432 filter->start_addr :
1433 filter->stop_addr);
1434
1435 /* Configure comparator */
1436 etm4_set_start_stop_filter(config, address,
1437 comparator, type);
1438
1439 /*
1440 * If filters::ssstatus == 1, trace acquisition was
1441 * started but the process was yanked away before the
1442 * the stop address was hit. As such the start/stop
1443 * logic needs to be re-started so that tracing can
1444 * resume where it left.
1445 *
1446 * The start/stop logic status when a process is
1447 * scheduled out is checked in function
1448 * etm4_disable_perf().
1449 */
1450 if (filters->ssstatus)
1451 config->vinst_ctrl |= BIT(9);
1452
1453 /* No include/exclude filtering for ViewInst */
1454 config->viiectlr = 0x0;
1455 break;
1456 default:
1457 ret = -EINVAL;
1458 goto out;
1459 }
1460 }
1461
1462 goto out;
1463
1464
1465default_filter:
1466 etm4_set_default_filter(config);
1467
1468out:
1469 return ret;
1470}
1471
1472void etm4_config_trace_mode(struct etmv4_config *config)
1473{
1474 u32 mode;
1475
1476 mode = config->mode;
1477 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1478
1479 /* excluding kernel AND user space doesn't make sense */
1480 WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1481
1482 /* nothing to do if neither flags are set */
1483 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1484 return;
1485
1486 etm4_set_victlr_access(config);
1487}
1488
1489static int etm4_online_cpu(unsigned int cpu)
1490{
1491 if (!etmdrvdata[cpu])
1492 return 0;
1493
1494 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1495 coresight_enable(etmdrvdata[cpu]->csdev);
1496 return 0;
1497}
1498
1499static int etm4_starting_cpu(unsigned int cpu)
1500{
1501 if (!etmdrvdata[cpu])
1502 return 0;
1503
1504 spin_lock(&etmdrvdata[cpu]->spinlock);
1505 if (!etmdrvdata[cpu]->os_unlock)
1506 etm4_os_unlock(etmdrvdata[cpu]);
1507
1508 if (local_read(&etmdrvdata[cpu]->mode))
1509 etm4_enable_hw(etmdrvdata[cpu]);
1510 spin_unlock(&etmdrvdata[cpu]->spinlock);
1511 return 0;
1512}
1513
1514static int etm4_dying_cpu(unsigned int cpu)
1515{
1516 if (!etmdrvdata[cpu])
1517 return 0;
1518
1519 spin_lock(&etmdrvdata[cpu]->spinlock);
1520 if (local_read(&etmdrvdata[cpu]->mode))
1521 etm4_disable_hw(etmdrvdata[cpu]);
1522 spin_unlock(&etmdrvdata[cpu]->spinlock);
1523 return 0;
1524}
1525
1526static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
1527{
1528 drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
1529}
1530
1531static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1532{
1533 int i, ret = 0;
1534 struct etmv4_save_state *state;
1535 struct coresight_device *csdev = drvdata->csdev;
1536 struct csdev_access *csa;
1537 struct device *etm_dev;
1538
1539 if (WARN_ON(!csdev))
1540 return -ENODEV;
1541
1542 etm_dev = &csdev->dev;
1543 csa = &csdev->access;
1544
1545 /*
1546 * As recommended by 3.4.1 ("The procedure when powering down the PE")
1547 * of ARM IHI 0064D
1548 */
1549 dsb(sy);
1550 isb();
1551
1552 etm4_cs_unlock(drvdata, csa);
1553 /* Lock the OS lock to disable trace and external debugger access */
1554 etm4_os_lock(drvdata);
1555
1556 /* wait for TRCSTATR.PMSTABLE to go up */
1557 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) {
1558 dev_err(etm_dev,
1559 "timeout while waiting for PM Stable Status\n");
1560 etm4_os_unlock(drvdata);
1561 ret = -EBUSY;
1562 goto out;
1563 }
1564
1565 state = drvdata->save_state;
1566
1567 state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR);
1568 if (drvdata->nr_pe)
1569 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
1570 state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
1571 state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
1572 state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
1573 state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
1574 if (drvdata->stallctl)
1575 state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
1576 state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
1577 state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
1578 state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
1579 state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
1580 state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
1581 state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
1582
1583 state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
1584 state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
1585 state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
1586 if (drvdata->nr_pe_cmp)
1587 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
1588 state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR);
1589 state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR);
1590 state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR);
1591
1592 for (i = 0; i < drvdata->nrseqstate - 1; i++)
1593 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
1594
1595 state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1596 state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1597 state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1598
1599 for (i = 0; i < drvdata->nr_cntr; i++) {
1600 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
1601 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
1602 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
1603 }
1604
1605 for (i = 0; i < drvdata->nr_resource * 2; i++)
1606 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
1607
1608 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1609 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
1610 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
1611 if (etm4x_sspcicrn_present(drvdata, i))
1612 state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
1613 }
1614
1615 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1616 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
1617 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
1618 }
1619
1620 /*
1621 * Data trace stream is architecturally prohibited for A profile cores
1622 * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1623 * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1624 * unit") of ARM IHI 0064D.
1625 */
1626
1627 for (i = 0; i < drvdata->numcidc; i++)
1628 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
1629
1630 for (i = 0; i < drvdata->numvmidc; i++)
1631 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
1632
1633 state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
1634 if (drvdata->numcidc > 4)
1635 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
1636
1637 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
1638 if (drvdata->numvmidc > 4)
1639 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
1640
1641 state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
1642
1643 if (!drvdata->skip_power_up)
1644 state->trcpdcr = etm4x_read32(csa, TRCPDCR);
1645
1646 /* wait for TRCSTATR.IDLE to go up */
1647 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
1648 dev_err(etm_dev,
1649 "timeout while waiting for Idle Trace Status\n");
1650 etm4_os_unlock(drvdata);
1651 ret = -EBUSY;
1652 goto out;
1653 }
1654
1655 drvdata->state_needs_restore = true;
1656
1657 /*
1658 * Power can be removed from the trace unit now. We do this to
1659 * potentially save power on systems that respect the TRCPDCR_PU
1660 * despite requesting software to save/restore state.
1661 */
1662 if (!drvdata->skip_power_up)
1663 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
1664 TRCPDCR);
1665out:
1666 etm4_cs_lock(drvdata, csa);
1667 return ret;
1668}
1669
1670static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1671{
1672 int i;
1673 struct etmv4_save_state *state = drvdata->save_state;
1674 struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1675 struct csdev_access *csa = &tmp_csa;
1676
1677 etm4_cs_unlock(drvdata, csa);
1678 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1679
1680 etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
1681 if (drvdata->nr_pe)
1682 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
1683 etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
1684 etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
1685 etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
1686 etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
1687 if (drvdata->stallctl)
1688 etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
1689 etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
1690 etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
1691 etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
1692 etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
1693 etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
1694 etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
1695
1696 etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
1697 etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
1698 etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
1699 if (drvdata->nr_pe_cmp)
1700 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
1701 etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR);
1702 etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR);
1703 etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR);
1704
1705 for (i = 0; i < drvdata->nrseqstate - 1; i++)
1706 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
1707
1708 etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1709 etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1710 etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1711
1712 for (i = 0; i < drvdata->nr_cntr; i++) {
1713 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
1714 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
1715 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
1716 }
1717
1718 for (i = 0; i < drvdata->nr_resource * 2; i++)
1719 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
1720
1721 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1722 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
1723 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
1724 if (etm4x_sspcicrn_present(drvdata, i))
1725 etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
1726 }
1727
1728 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1729 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
1730 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
1731 }
1732
1733 for (i = 0; i < drvdata->numcidc; i++)
1734 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
1735
1736 for (i = 0; i < drvdata->numvmidc; i++)
1737 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
1738
1739 etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
1740 if (drvdata->numcidc > 4)
1741 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
1742
1743 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
1744 if (drvdata->numvmidc > 4)
1745 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
1746
1747 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1748
1749 if (!drvdata->skip_power_up)
1750 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
1751
1752 drvdata->state_needs_restore = false;
1753
1754 /*
1755 * As recommended by section 4.3.7 ("Synchronization when using the
1756 * memory-mapped interface") of ARM IHI 0064D
1757 */
1758 dsb(sy);
1759 isb();
1760
1761 /* Unlock the OS lock to re-enable trace and external debug access */
1762 etm4_os_unlock(drvdata);
1763 etm4_cs_lock(drvdata, csa);
1764}
1765
1766static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1767 void *v)
1768{
1769 struct etmv4_drvdata *drvdata;
1770 unsigned int cpu = smp_processor_id();
1771
1772 if (!etmdrvdata[cpu])
1773 return NOTIFY_OK;
1774
1775 drvdata = etmdrvdata[cpu];
1776
1777 if (!drvdata->save_state)
1778 return NOTIFY_OK;
1779
1780 if (WARN_ON_ONCE(drvdata->cpu != cpu))
1781 return NOTIFY_BAD;
1782
1783 switch (cmd) {
1784 case CPU_PM_ENTER:
1785 /* save the state if self-hosted coresight is in use */
1786 if (local_read(&drvdata->mode))
1787 if (etm4_cpu_save(drvdata))
1788 return NOTIFY_BAD;
1789 break;
1790 case CPU_PM_EXIT:
1791 case CPU_PM_ENTER_FAILED:
1792 if (drvdata->state_needs_restore)
1793 etm4_cpu_restore(drvdata);
1794 break;
1795 default:
1796 return NOTIFY_DONE;
1797 }
1798
1799 return NOTIFY_OK;
1800}
1801
1802static struct notifier_block etm4_cpu_pm_nb = {
1803 .notifier_call = etm4_cpu_pm_notify,
1804};
1805
1806/* Setup PM. Deals with error conditions and counts */
1807static int __init etm4_pm_setup(void)
1808{
1809 int ret;
1810
1811 ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
1812 if (ret)
1813 return ret;
1814
1815 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
1816 "arm/coresight4:starting",
1817 etm4_starting_cpu, etm4_dying_cpu);
1818
1819 if (ret)
1820 goto unregister_notifier;
1821
1822 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
1823 "arm/coresight4:online",
1824 etm4_online_cpu, NULL);
1825
1826 /* HP dyn state ID returned in ret on success */
1827 if (ret > 0) {
1828 hp_online = ret;
1829 return 0;
1830 }
1831
1832 /* failed dyn state - remove others */
1833 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1834
1835unregister_notifier:
1836 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1837 return ret;
1838}
1839
1840static void etm4_pm_clear(void)
1841{
1842 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1843 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1844 if (hp_online) {
1845 cpuhp_remove_state_nocalls(hp_online);
1846 hp_online = 0;
1847 }
1848}
1849
1850static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
1851{
1852 int ret;
1853 struct coresight_platform_data *pdata = NULL;
1854 struct etmv4_drvdata *drvdata;
1855 struct coresight_desc desc = { 0 };
1856 struct etm4_init_arg init_arg = { 0 };
1857 u8 major, minor;
1858 char *type_name;
1859
1860 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1861 if (!drvdata)
1862 return -ENOMEM;
1863
1864 dev_set_drvdata(dev, drvdata);
1865
1866 if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
1867 pm_save_enable = coresight_loses_context_with_cpu(dev) ?
1868 PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
1869
1870 if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
1871 drvdata->save_state = devm_kmalloc(dev,
1872 sizeof(struct etmv4_save_state), GFP_KERNEL);
1873 if (!drvdata->save_state)
1874 return -ENOMEM;
1875 }
1876
1877 drvdata->base = base;
1878
1879 spin_lock_init(&drvdata->spinlock);
1880
1881 drvdata->cpu = coresight_get_cpu(dev);
1882 if (drvdata->cpu < 0)
1883 return drvdata->cpu;
1884
1885 init_arg.drvdata = drvdata;
1886 init_arg.csa = &desc.access;
1887 init_arg.pid = etm_pid;
1888
1889 if (smp_call_function_single(drvdata->cpu,
1890 etm4_init_arch_data, &init_arg, 1))
1891 dev_err(dev, "ETM arch init failed\n");
1892
1893 if (!drvdata->arch)
1894 return -EINVAL;
1895
1896 /* TRCPDCR is not accessible with system instructions. */
1897 if (!desc.access.io_mem ||
1898 fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
1899 drvdata->skip_power_up = true;
1900
1901 major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
1902 minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
1903
1904 if (etm4x_is_ete(drvdata)) {
1905 type_name = "ete";
1906 /* ETE v1 has major version == 0b101. Adjust this for logging.*/
1907 major -= 4;
1908 } else {
1909 type_name = "etm";
1910 }
1911
1912 desc.name = devm_kasprintf(dev, GFP_KERNEL,
1913 "%s%d", type_name, drvdata->cpu);
1914 if (!desc.name)
1915 return -ENOMEM;
1916
1917 etm4_init_trace_id(drvdata);
1918 etm4_set_default(&drvdata->config);
1919
1920 pdata = coresight_get_platform_data(dev);
1921 if (IS_ERR(pdata))
1922 return PTR_ERR(pdata);
1923
1924 dev->platform_data = pdata;
1925
1926 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1927 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1928 desc.ops = &etm4_cs_ops;
1929 desc.pdata = pdata;
1930 desc.dev = dev;
1931 desc.groups = coresight_etmv4_groups;
1932 drvdata->csdev = coresight_register(&desc);
1933 if (IS_ERR(drvdata->csdev))
1934 return PTR_ERR(drvdata->csdev);
1935
1936 ret = etm_perf_symlink(drvdata->csdev, true);
1937 if (ret) {
1938 coresight_unregister(drvdata->csdev);
1939 return ret;
1940 }
1941
1942 etmdrvdata[drvdata->cpu] = drvdata;
1943
1944 dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n",
1945 drvdata->cpu, type_name, major, minor);
1946
1947 if (boot_enable) {
1948 coresight_enable(drvdata->csdev);
1949 drvdata->boot_enable = true;
1950 }
1951
1952 return 0;
1953}
1954
1955static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id)
1956{
1957 void __iomem *base;
1958 struct device *dev = &adev->dev;
1959 struct resource *res = &adev->res;
1960 int ret;
1961
1962 /* Validity for the resource is already checked by the AMBA core */
1963 base = devm_ioremap_resource(dev, res);
1964 if (IS_ERR(base))
1965 return PTR_ERR(base);
1966
1967 ret = etm4_probe(dev, base, id->id);
1968 if (!ret)
1969 pm_runtime_put(&adev->dev);
1970
1971 return ret;
1972}
1973
1974static int etm4_probe_platform_dev(struct platform_device *pdev)
1975{
1976 int ret;
1977
1978 pm_runtime_get_noresume(&pdev->dev);
1979 pm_runtime_set_active(&pdev->dev);
1980 pm_runtime_enable(&pdev->dev);
1981
1982 /*
1983 * System register based devices could match the
1984 * HW by reading appropriate registers on the HW
1985 * and thus we could skip the PID.
1986 */
1987 ret = etm4_probe(&pdev->dev, NULL, 0);
1988
1989 pm_runtime_put(&pdev->dev);
1990 return ret;
1991}
1992
1993static struct amba_cs_uci_id uci_id_etm4[] = {
1994 {
1995 /* ETMv4 UCI data */
1996 .devarch = ETM_DEVARCH_ETMv4x_ARCH,
1997 .devarch_mask = ETM_DEVARCH_ID_MASK,
1998 .devtype = 0x00000013,
1999 }
2000};
2001
2002static void clear_etmdrvdata(void *info)
2003{
2004 int cpu = *(int *)info;
2005
2006 etmdrvdata[cpu] = NULL;
2007}
2008
2009static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata)
2010{
2011 etm_perf_symlink(drvdata->csdev, false);
2012 /*
2013 * Taking hotplug lock here to avoid racing between etm4_remove_dev()
2014 * and CPU hotplug call backs.
2015 */
2016 cpus_read_lock();
2017 /*
2018 * The readers for etmdrvdata[] are CPU hotplug call backs
2019 * and PM notification call backs. Change etmdrvdata[i] on
2020 * CPU i ensures these call backs has consistent view
2021 * inside one call back function.
2022 */
2023 if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
2024 etmdrvdata[drvdata->cpu] = NULL;
2025
2026 cpus_read_unlock();
2027
2028 coresight_unregister(drvdata->csdev);
2029
2030 return 0;
2031}
2032
2033static void __exit etm4_remove_amba(struct amba_device *adev)
2034{
2035 struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
2036
2037 if (drvdata)
2038 etm4_remove_dev(drvdata);
2039}
2040
2041static int __exit etm4_remove_platform_dev(struct platform_device *pdev)
2042{
2043 int ret = 0;
2044 struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
2045
2046 if (drvdata)
2047 ret = etm4_remove_dev(drvdata);
2048 pm_runtime_disable(&pdev->dev);
2049 return ret;
2050}
2051
2052static const struct amba_id etm4_ids[] = {
2053 CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */
2054 CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */
2055 CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */
2056 CS_AMBA_ID(0x000bb959), /* Cortex-A73 */
2057 CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
2058 CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
2059 CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
2060 CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
2061 CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */
2062 CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
2063 CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
2064 CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
2065 CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
2066 CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
2067 CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
2068 CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
2069 CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
2070 CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
2071 {},
2072};
2073
2074MODULE_DEVICE_TABLE(amba, etm4_ids);
2075
2076static struct amba_driver etm4x_amba_driver = {
2077 .drv = {
2078 .name = "coresight-etm4x",
2079 .owner = THIS_MODULE,
2080 .suppress_bind_attrs = true,
2081 },
2082 .probe = etm4_probe_amba,
2083 .remove = etm4_remove_amba,
2084 .id_table = etm4_ids,
2085};
2086
2087static const struct of_device_id etm4_sysreg_match[] = {
2088 { .compatible = "arm,coresight-etm4x-sysreg" },
2089 { .compatible = "arm,embedded-trace-extension" },
2090 {}
2091};
2092
2093static struct platform_driver etm4_platform_driver = {
2094 .probe = etm4_probe_platform_dev,
2095 .remove = etm4_remove_platform_dev,
2096 .driver = {
2097 .name = "coresight-etm4x",
2098 .of_match_table = etm4_sysreg_match,
2099 .suppress_bind_attrs = true,
2100 },
2101};
2102
2103static int __init etm4x_init(void)
2104{
2105 int ret;
2106
2107 ret = etm4_pm_setup();
2108
2109 /* etm4_pm_setup() does its own cleanup - exit on error */
2110 if (ret)
2111 return ret;
2112
2113 ret = amba_driver_register(&etm4x_amba_driver);
2114 if (ret) {
2115 pr_err("Error registering etm4x AMBA driver\n");
2116 goto clear_pm;
2117 }
2118
2119 ret = platform_driver_register(&etm4_platform_driver);
2120 if (!ret)
2121 return 0;
2122
2123 pr_err("Error registering etm4x platform driver\n");
2124 amba_driver_unregister(&etm4x_amba_driver);
2125
2126clear_pm:
2127 etm4_pm_clear();
2128 return ret;
2129}
2130
2131static void __exit etm4x_exit(void)
2132{
2133 amba_driver_unregister(&etm4x_amba_driver);
2134 platform_driver_unregister(&etm4_platform_driver);
2135 etm4_pm_clear();
2136}
2137
2138module_init(etm4x_init);
2139module_exit(etm4x_exit);
2140
2141MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
2142MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
2143MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
2144MODULE_LICENSE("GPL v2");