Loading...
Note: File does not exist in v3.15.
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __SMU_V11_0_H__
24#define __SMU_V11_0_H__
25
26#include "amdgpu_smu.h"
27
28#define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
29#define SMU11_DRIVER_IF_VERSION_ARCT 0x17
30#define SMU11_DRIVER_IF_VERSION_NV10 0x37
31#define SMU11_DRIVER_IF_VERSION_NV12 0x38
32#define SMU11_DRIVER_IF_VERSION_NV14 0x38
33#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3D
34#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xE
35#define SMU11_DRIVER_IF_VERSION_VANGOGH 0x03
36#define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xF
37#define SMU11_DRIVER_IF_VERSION_Beige_Goby 0xD
38
39/* MP Apertures */
40#define MP0_Public 0x03800000
41#define MP0_SRAM 0x03900000
42#define MP1_Public 0x03b00000
43#define MP1_SRAM 0x03c00004
44
45/* address block */
46#define smnMP1_FIRMWARE_FLAGS 0x3010024
47#define smnMP0_FW_INTF 0x30101c0
48#define smnMP1_PUB_CTRL 0x3010b14
49
50#define TEMP_RANGE_MIN (0)
51#define TEMP_RANGE_MAX (80 * 1000)
52
53#define SMU11_TOOL_SIZE 0x19000
54
55#define MAX_DPM_LEVELS 16
56#define MAX_PCIE_CONF 2
57
58#define CTF_OFFSET_EDGE 5
59#define CTF_OFFSET_HOTSPOT 5
60#define CTF_OFFSET_MEM 5
61
62#define LINK_WIDTH_MAX 6
63#define LINK_SPEED_MAX 3
64
65static const __maybe_unused uint16_t link_width[] = {0, 1, 2, 4, 8, 12, 16};
66static const __maybe_unused uint16_t link_speed[] = {25, 50, 80, 160};
67
68static const
69struct smu_temperature_range __maybe_unused smu11_thermal_policy[] =
70{
71 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
72 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
73};
74
75struct smu_11_0_max_sustainable_clocks {
76 uint32_t display_clock;
77 uint32_t phy_clock;
78 uint32_t pixel_clock;
79 uint32_t uclock;
80 uint32_t dcef_clock;
81 uint32_t soc_clock;
82};
83
84struct smu_11_0_dpm_clk_level {
85 bool enabled;
86 uint32_t value;
87};
88
89struct smu_11_0_dpm_table {
90 uint32_t min; /* MHz */
91 uint32_t max; /* MHz */
92 uint32_t count;
93 bool is_fine_grained;
94 struct smu_11_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS];
95};
96
97struct smu_11_0_pcie_table {
98 uint8_t pcie_gen[MAX_PCIE_CONF];
99 uint8_t pcie_lane[MAX_PCIE_CONF];
100};
101
102struct smu_11_0_dpm_tables {
103 struct smu_11_0_dpm_table soc_table;
104 struct smu_11_0_dpm_table gfx_table;
105 struct smu_11_0_dpm_table uclk_table;
106 struct smu_11_0_dpm_table eclk_table;
107 struct smu_11_0_dpm_table vclk_table;
108 struct smu_11_0_dpm_table vclk1_table;
109 struct smu_11_0_dpm_table dclk_table;
110 struct smu_11_0_dpm_table dclk1_table;
111 struct smu_11_0_dpm_table dcef_table;
112 struct smu_11_0_dpm_table pixel_table;
113 struct smu_11_0_dpm_table display_table;
114 struct smu_11_0_dpm_table phy_table;
115 struct smu_11_0_dpm_table fclk_table;
116 struct smu_11_0_pcie_table pcie_table;
117};
118
119struct smu_11_0_dpm_context {
120 struct smu_11_0_dpm_tables dpm_tables;
121 uint32_t workload_policy_mask;
122 uint32_t dcef_min_ds_clk;
123};
124
125enum smu_11_0_power_state {
126 SMU_11_0_POWER_STATE__D0 = 0,
127 SMU_11_0_POWER_STATE__D1,
128 SMU_11_0_POWER_STATE__D3, /* Sleep*/
129 SMU_11_0_POWER_STATE__D4, /* Hibernate*/
130 SMU_11_0_POWER_STATE__D5, /* Power off*/
131};
132
133struct smu_11_0_power_context {
134 uint32_t power_source;
135 uint8_t in_power_limit_boost_mode;
136 enum smu_11_0_power_state power_state;
137};
138
139struct smu_11_5_power_context {
140 uint32_t power_source;
141 uint8_t in_power_limit_boost_mode;
142 enum smu_11_0_power_state power_state;
143
144 uint32_t current_fast_ppt_limit;
145 uint32_t default_fast_ppt_limit;
146 uint32_t max_fast_ppt_limit;
147};
148
149enum smu_v11_0_baco_seq {
150 BACO_SEQ_BACO = 0,
151 BACO_SEQ_MSR,
152 BACO_SEQ_BAMACO,
153 BACO_SEQ_ULPS,
154 BACO_SEQ_COUNT,
155};
156
157#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
158
159int smu_v11_0_init_microcode(struct smu_context *smu);
160
161void smu_v11_0_fini_microcode(struct smu_context *smu);
162
163int smu_v11_0_load_microcode(struct smu_context *smu);
164
165int smu_v11_0_init_smc_tables(struct smu_context *smu);
166
167int smu_v11_0_fini_smc_tables(struct smu_context *smu);
168
169int smu_v11_0_init_power(struct smu_context *smu);
170
171int smu_v11_0_fini_power(struct smu_context *smu);
172
173int smu_v11_0_check_fw_status(struct smu_context *smu);
174
175int smu_v11_0_setup_pptable(struct smu_context *smu);
176
177int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu);
178
179int smu_v11_0_check_fw_version(struct smu_context *smu);
180
181int smu_v11_0_set_driver_table_location(struct smu_context *smu);
182
183int smu_v11_0_set_tool_table_location(struct smu_context *smu);
184
185int smu_v11_0_notify_memory_pool_location(struct smu_context *smu);
186
187int smu_v11_0_system_features_control(struct smu_context *smu,
188 bool en);
189
190int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count);
191
192int smu_v11_0_set_allowed_mask(struct smu_context *smu);
193
194int smu_v11_0_notify_display_change(struct smu_context *smu);
195
196int smu_v11_0_get_current_power_limit(struct smu_context *smu,
197 uint32_t *power_limit);
198
199int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n);
200
201int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu);
202
203int smu_v11_0_enable_thermal_alert(struct smu_context *smu);
204
205int smu_v11_0_disable_thermal_alert(struct smu_context *smu);
206
207int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);
208
209int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
210
211int
212smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
213 struct pp_display_clock_request
214 *clock_req);
215
216uint32_t
217smu_v11_0_get_fan_control_mode(struct smu_context *smu);
218
219int
220smu_v11_0_set_fan_control_mode(struct smu_context *smu,
221 uint32_t mode);
222
223int smu_v11_0_set_fan_speed_percent(struct smu_context *smu,
224 uint32_t speed);
225
226int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
227 uint32_t pstate);
228
229int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable);
230
231int smu_v11_0_register_irq_handler(struct smu_context *smu);
232
233int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu);
234
235int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
236 struct pp_smu_nv_clock_table *max_clocks);
237
238bool smu_v11_0_baco_is_support(struct smu_context *smu);
239
240enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu);
241
242int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
243
244int smu_v11_0_baco_enter(struct smu_context *smu);
245int smu_v11_0_baco_exit(struct smu_context *smu);
246
247int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
248 enum smu_v11_0_baco_seq baco_seq);
249
250int smu_v11_0_mode1_reset(struct smu_context *smu);
251
252int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
253 uint32_t *min, uint32_t *max);
254
255int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
256 uint32_t min, uint32_t max);
257
258int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
259 enum smu_clk_type clk_type,
260 uint32_t min,
261 uint32_t max);
262
263int smu_v11_0_set_performance_level(struct smu_context *smu,
264 enum amd_dpm_forced_level level);
265
266int smu_v11_0_set_power_source(struct smu_context *smu,
267 enum smu_power_src_type power_src);
268
269int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
270 enum smu_clk_type clk_type,
271 uint16_t level,
272 uint32_t *value);
273
274int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
275 enum smu_clk_type clk_type,
276 uint32_t *value);
277
278int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
279 enum smu_clk_type clk_type,
280 struct smu_11_0_dpm_table *single_dpm_table);
281
282int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
283 enum smu_clk_type clk_type,
284 uint32_t *min_value,
285 uint32_t *max_value);
286
287int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu);
288
289uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu);
290
291int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu);
292
293uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu);
294
295int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
296 bool enablement);
297
298int smu_v11_0_deep_sleep_control(struct smu_context *smu,
299 bool enablement);
300
301void smu_v11_0_interrupt_work(struct smu_context *smu);
302
303int smu_v11_0_set_light_sbr(struct smu_context *smu, bool enable);
304
305#endif
306#endif