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1/*
2 * Timberdale FPGA GPIO driver
3 * Copyright (c) 2009 Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19/* Supports:
20 * Timberdale FPGA GPIO
21 */
22
23#include <linux/module.h>
24#include <linux/gpio.h>
25#include <linux/platform_device.h>
26#include <linux/irq.h>
27#include <linux/io.h>
28#include <linux/timb_gpio.h>
29#include <linux/interrupt.h>
30#include <linux/slab.h>
31
32#define DRIVER_NAME "timb-gpio"
33
34#define TGPIOVAL 0x00
35#define TGPIODIR 0x04
36#define TGPIO_IER 0x08
37#define TGPIO_ISR 0x0c
38#define TGPIO_IPR 0x10
39#define TGPIO_ICR 0x14
40#define TGPIO_FLR 0x18
41#define TGPIO_LVR 0x1c
42#define TGPIO_VER 0x20
43#define TGPIO_BFLR 0x24
44
45struct timbgpio {
46 void __iomem *membase;
47 spinlock_t lock; /* mutual exclusion */
48 struct gpio_chip gpio;
49 int irq_base;
50 unsigned long last_ier;
51};
52
53static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
54 unsigned offset, bool enabled)
55{
56 struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
57 u32 reg;
58
59 spin_lock(&tgpio->lock);
60 reg = ioread32(tgpio->membase + offset);
61
62 if (enabled)
63 reg |= (1 << index);
64 else
65 reg &= ~(1 << index);
66
67 iowrite32(reg, tgpio->membase + offset);
68 spin_unlock(&tgpio->lock);
69
70 return 0;
71}
72
73static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
74{
75 return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
76}
77
78static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
79{
80 struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
81 u32 value;
82
83 value = ioread32(tgpio->membase + TGPIOVAL);
84 return (value & (1 << nr)) ? 1 : 0;
85}
86
87static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
88 unsigned nr, int val)
89{
90 return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
91}
92
93static void timbgpio_gpio_set(struct gpio_chip *gpio,
94 unsigned nr, int val)
95{
96 timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
97}
98
99static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
100{
101 struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
102
103 if (tgpio->irq_base <= 0)
104 return -EINVAL;
105
106 return tgpio->irq_base + offset;
107}
108
109/*
110 * GPIO IRQ
111 */
112static void timbgpio_irq_disable(struct irq_data *d)
113{
114 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
115 int offset = d->irq - tgpio->irq_base;
116 unsigned long flags;
117
118 spin_lock_irqsave(&tgpio->lock, flags);
119 tgpio->last_ier &= ~(1UL << offset);
120 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
121 spin_unlock_irqrestore(&tgpio->lock, flags);
122}
123
124static void timbgpio_irq_enable(struct irq_data *d)
125{
126 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
127 int offset = d->irq - tgpio->irq_base;
128 unsigned long flags;
129
130 spin_lock_irqsave(&tgpio->lock, flags);
131 tgpio->last_ier |= 1UL << offset;
132 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
133 spin_unlock_irqrestore(&tgpio->lock, flags);
134}
135
136static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
137{
138 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
139 int offset = d->irq - tgpio->irq_base;
140 unsigned long flags;
141 u32 lvr, flr, bflr = 0;
142 u32 ver;
143 int ret = 0;
144
145 if (offset < 0 || offset > tgpio->gpio.ngpio)
146 return -EINVAL;
147
148 ver = ioread32(tgpio->membase + TGPIO_VER);
149
150 spin_lock_irqsave(&tgpio->lock, flags);
151
152 lvr = ioread32(tgpio->membase + TGPIO_LVR);
153 flr = ioread32(tgpio->membase + TGPIO_FLR);
154 if (ver > 2)
155 bflr = ioread32(tgpio->membase + TGPIO_BFLR);
156
157 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
158 bflr &= ~(1 << offset);
159 flr &= ~(1 << offset);
160 if (trigger & IRQ_TYPE_LEVEL_HIGH)
161 lvr |= 1 << offset;
162 else
163 lvr &= ~(1 << offset);
164 }
165
166 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
167 if (ver < 3) {
168 ret = -EINVAL;
169 goto out;
170 } else {
171 flr |= 1 << offset;
172 bflr |= 1 << offset;
173 }
174 } else {
175 bflr &= ~(1 << offset);
176 flr |= 1 << offset;
177 if (trigger & IRQ_TYPE_EDGE_FALLING)
178 lvr &= ~(1 << offset);
179 else
180 lvr |= 1 << offset;
181 }
182
183 iowrite32(lvr, tgpio->membase + TGPIO_LVR);
184 iowrite32(flr, tgpio->membase + TGPIO_FLR);
185 if (ver > 2)
186 iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
187
188 iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
189
190out:
191 spin_unlock_irqrestore(&tgpio->lock, flags);
192 return ret;
193}
194
195static void timbgpio_irq(unsigned int irq, struct irq_desc *desc)
196{
197 struct timbgpio *tgpio = irq_get_handler_data(irq);
198 unsigned long ipr;
199 int offset;
200
201 desc->irq_data.chip->irq_ack(irq_get_irq_data(irq));
202 ipr = ioread32(tgpio->membase + TGPIO_IPR);
203 iowrite32(ipr, tgpio->membase + TGPIO_ICR);
204
205 /*
206 * Some versions of the hardware trash the IER register if more than
207 * one interrupt is received simultaneously.
208 */
209 iowrite32(0, tgpio->membase + TGPIO_IER);
210
211 for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
212 generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
213
214 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
215}
216
217static struct irq_chip timbgpio_irqchip = {
218 .name = "GPIO",
219 .irq_enable = timbgpio_irq_enable,
220 .irq_disable = timbgpio_irq_disable,
221 .irq_set_type = timbgpio_irq_type,
222};
223
224static int timbgpio_probe(struct platform_device *pdev)
225{
226 int err, i;
227 struct gpio_chip *gc;
228 struct timbgpio *tgpio;
229 struct resource *iomem;
230 struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
231 int irq = platform_get_irq(pdev, 0);
232
233 if (!pdata || pdata->nr_pins > 32) {
234 err = -EINVAL;
235 goto err_mem;
236 }
237
238 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
239 if (!iomem) {
240 err = -EINVAL;
241 goto err_mem;
242 }
243
244 tgpio = kzalloc(sizeof(*tgpio), GFP_KERNEL);
245 if (!tgpio) {
246 err = -EINVAL;
247 goto err_mem;
248 }
249 tgpio->irq_base = pdata->irq_base;
250
251 spin_lock_init(&tgpio->lock);
252
253 if (!request_mem_region(iomem->start, resource_size(iomem),
254 DRIVER_NAME)) {
255 err = -EBUSY;
256 goto err_request;
257 }
258
259 tgpio->membase = ioremap(iomem->start, resource_size(iomem));
260 if (!tgpio->membase) {
261 err = -ENOMEM;
262 goto err_ioremap;
263 }
264
265 gc = &tgpio->gpio;
266
267 gc->label = dev_name(&pdev->dev);
268 gc->owner = THIS_MODULE;
269 gc->dev = &pdev->dev;
270 gc->direction_input = timbgpio_gpio_direction_input;
271 gc->get = timbgpio_gpio_get;
272 gc->direction_output = timbgpio_gpio_direction_output;
273 gc->set = timbgpio_gpio_set;
274 gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
275 gc->dbg_show = NULL;
276 gc->base = pdata->gpio_base;
277 gc->ngpio = pdata->nr_pins;
278 gc->can_sleep = false;
279
280 err = gpiochip_add(gc);
281 if (err)
282 goto err_chipadd;
283
284 platform_set_drvdata(pdev, tgpio);
285
286 /* make sure to disable interrupts */
287 iowrite32(0x0, tgpio->membase + TGPIO_IER);
288
289 if (irq < 0 || tgpio->irq_base <= 0)
290 return 0;
291
292 for (i = 0; i < pdata->nr_pins; i++) {
293 irq_set_chip_and_handler(tgpio->irq_base + i,
294 &timbgpio_irqchip, handle_simple_irq);
295 irq_set_chip_data(tgpio->irq_base + i, tgpio);
296#ifdef CONFIG_ARM
297 set_irq_flags(tgpio->irq_base + i, IRQF_VALID | IRQF_PROBE);
298#endif
299 }
300
301 irq_set_handler_data(irq, tgpio);
302 irq_set_chained_handler(irq, timbgpio_irq);
303
304 return 0;
305
306err_chipadd:
307 iounmap(tgpio->membase);
308err_ioremap:
309 release_mem_region(iomem->start, resource_size(iomem));
310err_request:
311 kfree(tgpio);
312err_mem:
313 printk(KERN_ERR DRIVER_NAME": Failed to register GPIOs: %d\n", err);
314
315 return err;
316}
317
318static int timbgpio_remove(struct platform_device *pdev)
319{
320 int err;
321 struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
322 struct timbgpio *tgpio = platform_get_drvdata(pdev);
323 struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
324 int irq = platform_get_irq(pdev, 0);
325
326 if (irq >= 0 && tgpio->irq_base > 0) {
327 int i;
328 for (i = 0; i < pdata->nr_pins; i++) {
329 irq_set_chip(tgpio->irq_base + i, NULL);
330 irq_set_chip_data(tgpio->irq_base + i, NULL);
331 }
332
333 irq_set_handler(irq, NULL);
334 irq_set_handler_data(irq, NULL);
335 }
336
337 err = gpiochip_remove(&tgpio->gpio);
338 if (err)
339 printk(KERN_ERR DRIVER_NAME": failed to remove gpio_chip\n");
340
341 iounmap(tgpio->membase);
342 release_mem_region(iomem->start, resource_size(iomem));
343 kfree(tgpio);
344
345 return 0;
346}
347
348static struct platform_driver timbgpio_platform_driver = {
349 .driver = {
350 .name = DRIVER_NAME,
351 .owner = THIS_MODULE,
352 },
353 .probe = timbgpio_probe,
354 .remove = timbgpio_remove,
355};
356
357/*--------------------------------------------------------------------------*/
358
359module_platform_driver(timbgpio_platform_driver);
360
361MODULE_DESCRIPTION("Timberdale GPIO driver");
362MODULE_LICENSE("GPL v2");
363MODULE_AUTHOR("Mocean Laboratories");
364MODULE_ALIAS("platform:"DRIVER_NAME);
365
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Timberdale FPGA GPIO driver
4 * Author: Mocean Laboratories
5 * Copyright (c) 2009 Intel Corporation
6 */
7
8/* Supports:
9 * Timberdale FPGA GPIO
10 */
11
12#include <linux/init.h>
13#include <linux/gpio/driver.h>
14#include <linux/platform_device.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <linux/timb_gpio.h>
18#include <linux/interrupt.h>
19#include <linux/slab.h>
20
21#define DRIVER_NAME "timb-gpio"
22
23#define TGPIOVAL 0x00
24#define TGPIODIR 0x04
25#define TGPIO_IER 0x08
26#define TGPIO_ISR 0x0c
27#define TGPIO_IPR 0x10
28#define TGPIO_ICR 0x14
29#define TGPIO_FLR 0x18
30#define TGPIO_LVR 0x1c
31#define TGPIO_VER 0x20
32#define TGPIO_BFLR 0x24
33
34struct timbgpio {
35 void __iomem *membase;
36 spinlock_t lock; /* mutual exclusion */
37 struct gpio_chip gpio;
38 int irq_base;
39 unsigned long last_ier;
40};
41
42static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
43 unsigned offset, bool enabled)
44{
45 struct timbgpio *tgpio = gpiochip_get_data(gpio);
46 u32 reg;
47
48 spin_lock(&tgpio->lock);
49 reg = ioread32(tgpio->membase + offset);
50
51 if (enabled)
52 reg |= (1 << index);
53 else
54 reg &= ~(1 << index);
55
56 iowrite32(reg, tgpio->membase + offset);
57 spin_unlock(&tgpio->lock);
58
59 return 0;
60}
61
62static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
63{
64 return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
65}
66
67static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
68{
69 struct timbgpio *tgpio = gpiochip_get_data(gpio);
70 u32 value;
71
72 value = ioread32(tgpio->membase + TGPIOVAL);
73 return (value & (1 << nr)) ? 1 : 0;
74}
75
76static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
77 unsigned nr, int val)
78{
79 return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
80}
81
82static void timbgpio_gpio_set(struct gpio_chip *gpio,
83 unsigned nr, int val)
84{
85 timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
86}
87
88static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
89{
90 struct timbgpio *tgpio = gpiochip_get_data(gpio);
91
92 if (tgpio->irq_base <= 0)
93 return -EINVAL;
94
95 return tgpio->irq_base + offset;
96}
97
98/*
99 * GPIO IRQ
100 */
101static void timbgpio_irq_disable(struct irq_data *d)
102{
103 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
104 int offset = d->irq - tgpio->irq_base;
105 unsigned long flags;
106
107 spin_lock_irqsave(&tgpio->lock, flags);
108 tgpio->last_ier &= ~(1UL << offset);
109 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
110 spin_unlock_irqrestore(&tgpio->lock, flags);
111}
112
113static void timbgpio_irq_enable(struct irq_data *d)
114{
115 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
116 int offset = d->irq - tgpio->irq_base;
117 unsigned long flags;
118
119 spin_lock_irqsave(&tgpio->lock, flags);
120 tgpio->last_ier |= 1UL << offset;
121 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
122 spin_unlock_irqrestore(&tgpio->lock, flags);
123}
124
125static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
126{
127 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
128 int offset = d->irq - tgpio->irq_base;
129 unsigned long flags;
130 u32 lvr, flr, bflr = 0;
131 u32 ver;
132 int ret = 0;
133
134 if (offset < 0 || offset > tgpio->gpio.ngpio)
135 return -EINVAL;
136
137 ver = ioread32(tgpio->membase + TGPIO_VER);
138
139 spin_lock_irqsave(&tgpio->lock, flags);
140
141 lvr = ioread32(tgpio->membase + TGPIO_LVR);
142 flr = ioread32(tgpio->membase + TGPIO_FLR);
143 if (ver > 2)
144 bflr = ioread32(tgpio->membase + TGPIO_BFLR);
145
146 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
147 bflr &= ~(1 << offset);
148 flr &= ~(1 << offset);
149 if (trigger & IRQ_TYPE_LEVEL_HIGH)
150 lvr |= 1 << offset;
151 else
152 lvr &= ~(1 << offset);
153 }
154
155 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
156 if (ver < 3) {
157 ret = -EINVAL;
158 goto out;
159 } else {
160 flr |= 1 << offset;
161 bflr |= 1 << offset;
162 }
163 } else {
164 bflr &= ~(1 << offset);
165 flr |= 1 << offset;
166 if (trigger & IRQ_TYPE_EDGE_FALLING)
167 lvr &= ~(1 << offset);
168 else
169 lvr |= 1 << offset;
170 }
171
172 iowrite32(lvr, tgpio->membase + TGPIO_LVR);
173 iowrite32(flr, tgpio->membase + TGPIO_FLR);
174 if (ver > 2)
175 iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
176
177 iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
178
179out:
180 spin_unlock_irqrestore(&tgpio->lock, flags);
181 return ret;
182}
183
184static void timbgpio_irq(struct irq_desc *desc)
185{
186 struct timbgpio *tgpio = irq_desc_get_handler_data(desc);
187 struct irq_data *data = irq_desc_get_irq_data(desc);
188 unsigned long ipr;
189 int offset;
190
191 data->chip->irq_ack(data);
192 ipr = ioread32(tgpio->membase + TGPIO_IPR);
193 iowrite32(ipr, tgpio->membase + TGPIO_ICR);
194
195 /*
196 * Some versions of the hardware trash the IER register if more than
197 * one interrupt is received simultaneously.
198 */
199 iowrite32(0, tgpio->membase + TGPIO_IER);
200
201 for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
202 generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
203
204 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
205}
206
207static struct irq_chip timbgpio_irqchip = {
208 .name = "GPIO",
209 .irq_enable = timbgpio_irq_enable,
210 .irq_disable = timbgpio_irq_disable,
211 .irq_set_type = timbgpio_irq_type,
212};
213
214static int timbgpio_probe(struct platform_device *pdev)
215{
216 int err, i;
217 struct device *dev = &pdev->dev;
218 struct gpio_chip *gc;
219 struct timbgpio *tgpio;
220 struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
221 int irq = platform_get_irq(pdev, 0);
222
223 if (!pdata || pdata->nr_pins > 32) {
224 dev_err(dev, "Invalid platform data\n");
225 return -EINVAL;
226 }
227
228 tgpio = devm_kzalloc(dev, sizeof(*tgpio), GFP_KERNEL);
229 if (!tgpio)
230 return -EINVAL;
231
232 tgpio->irq_base = pdata->irq_base;
233
234 spin_lock_init(&tgpio->lock);
235
236 tgpio->membase = devm_platform_ioremap_resource(pdev, 0);
237 if (IS_ERR(tgpio->membase))
238 return PTR_ERR(tgpio->membase);
239
240 gc = &tgpio->gpio;
241
242 gc->label = dev_name(&pdev->dev);
243 gc->owner = THIS_MODULE;
244 gc->parent = &pdev->dev;
245 gc->direction_input = timbgpio_gpio_direction_input;
246 gc->get = timbgpio_gpio_get;
247 gc->direction_output = timbgpio_gpio_direction_output;
248 gc->set = timbgpio_gpio_set;
249 gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
250 gc->dbg_show = NULL;
251 gc->base = pdata->gpio_base;
252 gc->ngpio = pdata->nr_pins;
253 gc->can_sleep = false;
254
255 err = devm_gpiochip_add_data(&pdev->dev, gc, tgpio);
256 if (err)
257 return err;
258
259 platform_set_drvdata(pdev, tgpio);
260
261 /* make sure to disable interrupts */
262 iowrite32(0x0, tgpio->membase + TGPIO_IER);
263
264 if (irq < 0 || tgpio->irq_base <= 0)
265 return 0;
266
267 for (i = 0; i < pdata->nr_pins; i++) {
268 irq_set_chip_and_handler(tgpio->irq_base + i,
269 &timbgpio_irqchip, handle_simple_irq);
270 irq_set_chip_data(tgpio->irq_base + i, tgpio);
271 irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST | IRQ_NOPROBE);
272 }
273
274 irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio);
275
276 return 0;
277}
278
279static struct platform_driver timbgpio_platform_driver = {
280 .driver = {
281 .name = DRIVER_NAME,
282 .suppress_bind_attrs = true,
283 },
284 .probe = timbgpio_probe,
285};
286
287/*--------------------------------------------------------------------------*/
288
289builtin_platform_driver(timbgpio_platform_driver);