Loading...
Note: File does not exist in v3.15.
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2016,2017 IBM Corporation.
4 */
5
6#define pr_fmt(fmt) "xive: " fmt
7
8#include <linux/types.h>
9#include <linux/threads.h>
10#include <linux/kernel.h>
11#include <linux/irq.h>
12#include <linux/debugfs.h>
13#include <linux/smp.h>
14#include <linux/interrupt.h>
15#include <linux/seq_file.h>
16#include <linux/init.h>
17#include <linux/cpu.h>
18#include <linux/of.h>
19#include <linux/slab.h>
20#include <linux/spinlock.h>
21#include <linux/msi.h>
22#include <linux/vmalloc.h>
23
24#include <asm/debugfs.h>
25#include <asm/prom.h>
26#include <asm/io.h>
27#include <asm/smp.h>
28#include <asm/machdep.h>
29#include <asm/irq.h>
30#include <asm/errno.h>
31#include <asm/xive.h>
32#include <asm/xive-regs.h>
33#include <asm/xmon.h>
34
35#include "xive-internal.h"
36
37#undef DEBUG_FLUSH
38#undef DEBUG_ALL
39
40#ifdef DEBUG_ALL
41#define DBG_VERBOSE(fmt, ...) pr_devel("cpu %d - " fmt, \
42 smp_processor_id(), ## __VA_ARGS__)
43#else
44#define DBG_VERBOSE(fmt...) do { } while(0)
45#endif
46
47bool __xive_enabled;
48EXPORT_SYMBOL_GPL(__xive_enabled);
49bool xive_cmdline_disabled;
50
51/* We use only one priority for now */
52static u8 xive_irq_priority;
53
54/* TIMA exported to KVM */
55void __iomem *xive_tima;
56EXPORT_SYMBOL_GPL(xive_tima);
57u32 xive_tima_offset;
58
59/* Backend ops */
60static const struct xive_ops *xive_ops;
61
62/* Our global interrupt domain */
63static struct irq_domain *xive_irq_domain;
64
65#ifdef CONFIG_SMP
66/* The IPIs use the same logical irq number when on the same chip */
67static struct xive_ipi_desc {
68 unsigned int irq;
69 char name[16];
70 atomic_t started;
71} *xive_ipis;
72
73/*
74 * Use early_cpu_to_node() for hot-plugged CPUs
75 */
76static unsigned int xive_ipi_cpu_to_irq(unsigned int cpu)
77{
78 return xive_ipis[early_cpu_to_node(cpu)].irq;
79}
80#endif
81
82/* Xive state for each CPU */
83static DEFINE_PER_CPU(struct xive_cpu *, xive_cpu);
84
85/* An invalid CPU target */
86#define XIVE_INVALID_TARGET (-1)
87
88/*
89 * Read the next entry in a queue, return its content if it's valid
90 * or 0 if there is no new entry.
91 *
92 * The queue pointer is moved forward unless "just_peek" is set
93 */
94static u32 xive_read_eq(struct xive_q *q, bool just_peek)
95{
96 u32 cur;
97
98 if (!q->qpage)
99 return 0;
100 cur = be32_to_cpup(q->qpage + q->idx);
101
102 /* Check valid bit (31) vs current toggle polarity */
103 if ((cur >> 31) == q->toggle)
104 return 0;
105
106 /* If consuming from the queue ... */
107 if (!just_peek) {
108 /* Next entry */
109 q->idx = (q->idx + 1) & q->msk;
110
111 /* Wrap around: flip valid toggle */
112 if (q->idx == 0)
113 q->toggle ^= 1;
114 }
115 /* Mask out the valid bit (31) */
116 return cur & 0x7fffffff;
117}
118
119/*
120 * Scans all the queue that may have interrupts in them
121 * (based on "pending_prio") in priority order until an
122 * interrupt is found or all the queues are empty.
123 *
124 * Then updates the CPPR (Current Processor Priority
125 * Register) based on the most favored interrupt found
126 * (0xff if none) and return what was found (0 if none).
127 *
128 * If just_peek is set, return the most favored pending
129 * interrupt if any but don't update the queue pointers.
130 *
131 * Note: This function can operate generically on any number
132 * of queues (up to 8). The current implementation of the XIVE
133 * driver only uses a single queue however.
134 *
135 * Note2: This will also "flush" "the pending_count" of a queue
136 * into the "count" when that queue is observed to be empty.
137 * This is used to keep track of the amount of interrupts
138 * targetting a queue. When an interrupt is moved away from
139 * a queue, we only decrement that queue count once the queue
140 * has been observed empty to avoid races.
141 */
142static u32 xive_scan_interrupts(struct xive_cpu *xc, bool just_peek)
143{
144 u32 irq = 0;
145 u8 prio = 0;
146
147 /* Find highest pending priority */
148 while (xc->pending_prio != 0) {
149 struct xive_q *q;
150
151 prio = ffs(xc->pending_prio) - 1;
152 DBG_VERBOSE("scan_irq: trying prio %d\n", prio);
153
154 /* Try to fetch */
155 irq = xive_read_eq(&xc->queue[prio], just_peek);
156
157 /* Found something ? That's it */
158 if (irq) {
159 if (just_peek || irq_to_desc(irq))
160 break;
161 /*
162 * We should never get here; if we do then we must
163 * have failed to synchronize the interrupt properly
164 * when shutting it down.
165 */
166 pr_crit("xive: got interrupt %d without descriptor, dropping\n",
167 irq);
168 WARN_ON(1);
169 continue;
170 }
171
172 /* Clear pending bits */
173 xc->pending_prio &= ~(1 << prio);
174
175 /*
176 * Check if the queue count needs adjusting due to
177 * interrupts being moved away. See description of
178 * xive_dec_target_count()
179 */
180 q = &xc->queue[prio];
181 if (atomic_read(&q->pending_count)) {
182 int p = atomic_xchg(&q->pending_count, 0);
183 if (p) {
184 WARN_ON(p > atomic_read(&q->count));
185 atomic_sub(p, &q->count);
186 }
187 }
188 }
189
190 /* If nothing was found, set CPPR to 0xff */
191 if (irq == 0)
192 prio = 0xff;
193
194 /* Update HW CPPR to match if necessary */
195 if (prio != xc->cppr) {
196 DBG_VERBOSE("scan_irq: adjusting CPPR to %d\n", prio);
197 xc->cppr = prio;
198 out_8(xive_tima + xive_tima_offset + TM_CPPR, prio);
199 }
200
201 return irq;
202}
203
204/*
205 * This is used to perform the magic loads from an ESB
206 * described in xive-regs.h
207 */
208static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
209{
210 u64 val;
211
212 if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
213 offset |= XIVE_ESB_LD_ST_MO;
214
215 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
216 val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);
217 else
218 val = in_be64(xd->eoi_mmio + offset);
219
220 return (u8)val;
221}
222
223static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data)
224{
225 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
226 xive_ops->esb_rw(xd->hw_irq, offset, data, 1);
227 else
228 out_be64(xd->eoi_mmio + offset, data);
229}
230
231#ifdef CONFIG_XMON
232static notrace void xive_dump_eq(const char *name, struct xive_q *q)
233{
234 u32 i0, i1, idx;
235
236 if (!q->qpage)
237 return;
238 idx = q->idx;
239 i0 = be32_to_cpup(q->qpage + idx);
240 idx = (idx + 1) & q->msk;
241 i1 = be32_to_cpup(q->qpage + idx);
242 xmon_printf("%s idx=%d T=%d %08x %08x ...", name,
243 q->idx, q->toggle, i0, i1);
244}
245
246notrace void xmon_xive_do_dump(int cpu)
247{
248 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
249
250 xmon_printf("CPU %d:", cpu);
251 if (xc) {
252 xmon_printf("pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr);
253
254#ifdef CONFIG_SMP
255 {
256 u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET);
257
258 xmon_printf("IPI=0x%08x PQ=%c%c ", xc->hw_ipi,
259 val & XIVE_ESB_VAL_P ? 'P' : '-',
260 val & XIVE_ESB_VAL_Q ? 'Q' : '-');
261 }
262#endif
263 xive_dump_eq("EQ", &xc->queue[xive_irq_priority]);
264 }
265 xmon_printf("\n");
266}
267
268static struct irq_data *xive_get_irq_data(u32 hw_irq)
269{
270 unsigned int irq = irq_find_mapping(xive_irq_domain, hw_irq);
271
272 return irq ? irq_get_irq_data(irq) : NULL;
273}
274
275int xmon_xive_get_irq_config(u32 hw_irq, struct irq_data *d)
276{
277 int rc;
278 u32 target;
279 u8 prio;
280 u32 lirq;
281
282 rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq);
283 if (rc) {
284 xmon_printf("IRQ 0x%08x : no config rc=%d\n", hw_irq, rc);
285 return rc;
286 }
287
288 xmon_printf("IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ",
289 hw_irq, target, prio, lirq);
290
291 if (!d)
292 d = xive_get_irq_data(hw_irq);
293
294 if (d) {
295 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
296 u64 val = xive_esb_read(xd, XIVE_ESB_GET);
297
298 xmon_printf("flags=%c%c%c PQ=%c%c",
299 xd->flags & XIVE_IRQ_FLAG_STORE_EOI ? 'S' : ' ',
300 xd->flags & XIVE_IRQ_FLAG_LSI ? 'L' : ' ',
301 xd->flags & XIVE_IRQ_FLAG_H_INT_ESB ? 'H' : ' ',
302 val & XIVE_ESB_VAL_P ? 'P' : '-',
303 val & XIVE_ESB_VAL_Q ? 'Q' : '-');
304 }
305
306 xmon_printf("\n");
307 return 0;
308}
309
310void xmon_xive_get_irq_all(void)
311{
312 unsigned int i;
313 struct irq_desc *desc;
314
315 for_each_irq_desc(i, desc) {
316 struct irq_data *d = irq_desc_get_irq_data(desc);
317 unsigned int hwirq = (unsigned int)irqd_to_hwirq(d);
318
319 if (d->domain == xive_irq_domain)
320 xmon_xive_get_irq_config(hwirq, d);
321 }
322}
323
324#endif /* CONFIG_XMON */
325
326static unsigned int xive_get_irq(void)
327{
328 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
329 u32 irq;
330
331 /*
332 * This can be called either as a result of a HW interrupt or
333 * as a "replay" because EOI decided there was still something
334 * in one of the queues.
335 *
336 * First we perform an ACK cycle in order to update our mask
337 * of pending priorities. This will also have the effect of
338 * updating the CPPR to the most favored pending interrupts.
339 *
340 * In the future, if we have a way to differentiate a first
341 * entry (on HW interrupt) from a replay triggered by EOI,
342 * we could skip this on replays unless we soft-mask tells us
343 * that a new HW interrupt occurred.
344 */
345 xive_ops->update_pending(xc);
346
347 DBG_VERBOSE("get_irq: pending=%02x\n", xc->pending_prio);
348
349 /* Scan our queue(s) for interrupts */
350 irq = xive_scan_interrupts(xc, false);
351
352 DBG_VERBOSE("get_irq: got irq 0x%x, new pending=0x%02x\n",
353 irq, xc->pending_prio);
354
355 /* Return pending interrupt if any */
356 if (irq == XIVE_BAD_IRQ)
357 return 0;
358 return irq;
359}
360
361/*
362 * After EOI'ing an interrupt, we need to re-check the queue
363 * to see if another interrupt is pending since multiple
364 * interrupts can coalesce into a single notification to the
365 * CPU.
366 *
367 * If we find that there is indeed more in there, we call
368 * force_external_irq_replay() to make Linux synthetize an
369 * external interrupt on the next call to local_irq_restore().
370 */
371static void xive_do_queue_eoi(struct xive_cpu *xc)
372{
373 if (xive_scan_interrupts(xc, true) != 0) {
374 DBG_VERBOSE("eoi: pending=0x%02x\n", xc->pending_prio);
375 force_external_irq_replay();
376 }
377}
378
379/*
380 * EOI an interrupt at the source. There are several methods
381 * to do this depending on the HW version and source type
382 */
383static void xive_do_source_eoi(struct xive_irq_data *xd)
384{
385 u8 eoi_val;
386
387 xd->stale_p = false;
388
389 /* If the XIVE supports the new "store EOI facility, use it */
390 if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI) {
391 xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0);
392 return;
393 }
394
395 /*
396 * For LSIs, we use the "EOI cycle" special load rather than
397 * PQ bits, as they are automatically re-triggered in HW when
398 * still pending.
399 */
400 if (xd->flags & XIVE_IRQ_FLAG_LSI) {
401 xive_esb_read(xd, XIVE_ESB_LOAD_EOI);
402 return;
403 }
404
405 /*
406 * Otherwise, we use the special MMIO that does a clear of
407 * both P and Q and returns the old Q. This allows us to then
408 * do a re-trigger if Q was set rather than synthesizing an
409 * interrupt in software
410 */
411 eoi_val = xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
412 DBG_VERBOSE("eoi_val=%x\n", eoi_val);
413
414 /* Re-trigger if needed */
415 if ((eoi_val & XIVE_ESB_VAL_Q) && xd->trig_mmio)
416 out_be64(xd->trig_mmio, 0);
417}
418
419/* irq_chip eoi callback, called with irq descriptor lock held */
420static void xive_irq_eoi(struct irq_data *d)
421{
422 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
423 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
424
425 DBG_VERBOSE("eoi_irq: irq=%d [0x%lx] pending=%02x\n",
426 d->irq, irqd_to_hwirq(d), xc->pending_prio);
427
428 /*
429 * EOI the source if it hasn't been disabled and hasn't
430 * been passed-through to a KVM guest
431 */
432 if (!irqd_irq_disabled(d) && !irqd_is_forwarded_to_vcpu(d) &&
433 !(xd->flags & XIVE_IRQ_FLAG_NO_EOI))
434 xive_do_source_eoi(xd);
435 else
436 xd->stale_p = true;
437
438 /*
439 * Clear saved_p to indicate that it's no longer occupying
440 * a queue slot on the target queue
441 */
442 xd->saved_p = false;
443
444 /* Check for more work in the queue */
445 xive_do_queue_eoi(xc);
446}
447
448/*
449 * Helper used to mask and unmask an interrupt source.
450 */
451static void xive_do_source_set_mask(struct xive_irq_data *xd,
452 bool mask)
453{
454 u64 val;
455
456 /*
457 * If the interrupt had P set, it may be in a queue.
458 *
459 * We need to make sure we don't re-enable it until it
460 * has been fetched from that queue and EOId. We keep
461 * a copy of that P state and use it to restore the
462 * ESB accordingly on unmask.
463 */
464 if (mask) {
465 val = xive_esb_read(xd, XIVE_ESB_SET_PQ_01);
466 if (!xd->stale_p && !!(val & XIVE_ESB_VAL_P))
467 xd->saved_p = true;
468 xd->stale_p = false;
469 } else if (xd->saved_p) {
470 xive_esb_read(xd, XIVE_ESB_SET_PQ_10);
471 xd->saved_p = false;
472 } else {
473 xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
474 xd->stale_p = false;
475 }
476}
477
478/*
479 * Try to chose "cpu" as a new interrupt target. Increments
480 * the queue accounting for that target if it's not already
481 * full.
482 */
483static bool xive_try_pick_target(int cpu)
484{
485 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
486 struct xive_q *q = &xc->queue[xive_irq_priority];
487 int max;
488
489 /*
490 * Calculate max number of interrupts in that queue.
491 *
492 * We leave a gap of 1 just in case...
493 */
494 max = (q->msk + 1) - 1;
495 return !!atomic_add_unless(&q->count, 1, max);
496}
497
498/*
499 * Un-account an interrupt for a target CPU. We don't directly
500 * decrement q->count since the interrupt might still be present
501 * in the queue.
502 *
503 * Instead increment a separate counter "pending_count" which
504 * will be substracted from "count" later when that CPU observes
505 * the queue to be empty.
506 */
507static void xive_dec_target_count(int cpu)
508{
509 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
510 struct xive_q *q = &xc->queue[xive_irq_priority];
511
512 if (WARN_ON(cpu < 0 || !xc)) {
513 pr_err("%s: cpu=%d xc=%p\n", __func__, cpu, xc);
514 return;
515 }
516
517 /*
518 * We increment the "pending count" which will be used
519 * to decrement the target queue count whenever it's next
520 * processed and found empty. This ensure that we don't
521 * decrement while we still have the interrupt there
522 * occupying a slot.
523 */
524 atomic_inc(&q->pending_count);
525}
526
527/* Find a tentative CPU target in a CPU mask */
528static int xive_find_target_in_mask(const struct cpumask *mask,
529 unsigned int fuzz)
530{
531 int cpu, first, num, i;
532
533 /* Pick up a starting point CPU in the mask based on fuzz */
534 num = min_t(int, cpumask_weight(mask), nr_cpu_ids);
535 first = fuzz % num;
536
537 /* Locate it */
538 cpu = cpumask_first(mask);
539 for (i = 0; i < first && cpu < nr_cpu_ids; i++)
540 cpu = cpumask_next(cpu, mask);
541
542 /* Sanity check */
543 if (WARN_ON(cpu >= nr_cpu_ids))
544 cpu = cpumask_first(cpu_online_mask);
545
546 /* Remember first one to handle wrap-around */
547 first = cpu;
548
549 /*
550 * Now go through the entire mask until we find a valid
551 * target.
552 */
553 do {
554 /*
555 * We re-check online as the fallback case passes us
556 * an untested affinity mask
557 */
558 if (cpu_online(cpu) && xive_try_pick_target(cpu))
559 return cpu;
560 cpu = cpumask_next(cpu, mask);
561 /* Wrap around */
562 if (cpu >= nr_cpu_ids)
563 cpu = cpumask_first(mask);
564 } while (cpu != first);
565
566 return -1;
567}
568
569/*
570 * Pick a target CPU for an interrupt. This is done at
571 * startup or if the affinity is changed in a way that
572 * invalidates the current target.
573 */
574static int xive_pick_irq_target(struct irq_data *d,
575 const struct cpumask *affinity)
576{
577 static unsigned int fuzz;
578 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
579 cpumask_var_t mask;
580 int cpu = -1;
581
582 /*
583 * If we have chip IDs, first we try to build a mask of
584 * CPUs matching the CPU and find a target in there
585 */
586 if (xd->src_chip != XIVE_INVALID_CHIP_ID &&
587 zalloc_cpumask_var(&mask, GFP_ATOMIC)) {
588 /* Build a mask of matching chip IDs */
589 for_each_cpu_and(cpu, affinity, cpu_online_mask) {
590 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
591 if (xc->chip_id == xd->src_chip)
592 cpumask_set_cpu(cpu, mask);
593 }
594 /* Try to find a target */
595 if (cpumask_empty(mask))
596 cpu = -1;
597 else
598 cpu = xive_find_target_in_mask(mask, fuzz++);
599 free_cpumask_var(mask);
600 if (cpu >= 0)
601 return cpu;
602 fuzz--;
603 }
604
605 /* No chip IDs, fallback to using the affinity mask */
606 return xive_find_target_in_mask(affinity, fuzz++);
607}
608
609static unsigned int xive_irq_startup(struct irq_data *d)
610{
611 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
612 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
613 int target, rc;
614
615 xd->saved_p = false;
616 xd->stale_p = false;
617 pr_devel("xive_irq_startup: irq %d [0x%x] data @%p\n",
618 d->irq, hw_irq, d);
619
620#ifdef CONFIG_PCI_MSI
621 /*
622 * The generic MSI code returns with the interrupt disabled on the
623 * card, using the MSI mask bits. Firmware doesn't appear to unmask
624 * at that level, so we do it here by hand.
625 */
626 if (irq_data_get_msi_desc(d))
627 pci_msi_unmask_irq(d);
628#endif
629
630 /* Pick a target */
631 target = xive_pick_irq_target(d, irq_data_get_affinity_mask(d));
632 if (target == XIVE_INVALID_TARGET) {
633 /* Try again breaking affinity */
634 target = xive_pick_irq_target(d, cpu_online_mask);
635 if (target == XIVE_INVALID_TARGET)
636 return -ENXIO;
637 pr_warn("irq %d started with broken affinity\n", d->irq);
638 }
639
640 /* Sanity check */
641 if (WARN_ON(target == XIVE_INVALID_TARGET ||
642 target >= nr_cpu_ids))
643 target = smp_processor_id();
644
645 xd->target = target;
646
647 /*
648 * Configure the logical number to be the Linux IRQ number
649 * and set the target queue
650 */
651 rc = xive_ops->configure_irq(hw_irq,
652 get_hard_smp_processor_id(target),
653 xive_irq_priority, d->irq);
654 if (rc)
655 return rc;
656
657 /* Unmask the ESB */
658 xive_do_source_set_mask(xd, false);
659
660 return 0;
661}
662
663/* called with irq descriptor lock held */
664static void xive_irq_shutdown(struct irq_data *d)
665{
666 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
667 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
668
669 pr_devel("xive_irq_shutdown: irq %d [0x%x] data @%p\n",
670 d->irq, hw_irq, d);
671
672 if (WARN_ON(xd->target == XIVE_INVALID_TARGET))
673 return;
674
675 /* Mask the interrupt at the source */
676 xive_do_source_set_mask(xd, true);
677
678 /*
679 * Mask the interrupt in HW in the IVT/EAS and set the number
680 * to be the "bad" IRQ number
681 */
682 xive_ops->configure_irq(hw_irq,
683 get_hard_smp_processor_id(xd->target),
684 0xff, XIVE_BAD_IRQ);
685
686 xive_dec_target_count(xd->target);
687 xd->target = XIVE_INVALID_TARGET;
688}
689
690static void xive_irq_unmask(struct irq_data *d)
691{
692 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
693
694 pr_devel("xive_irq_unmask: irq %d data @%p\n", d->irq, xd);
695
696 xive_do_source_set_mask(xd, false);
697}
698
699static void xive_irq_mask(struct irq_data *d)
700{
701 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
702
703 pr_devel("xive_irq_mask: irq %d data @%p\n", d->irq, xd);
704
705 xive_do_source_set_mask(xd, true);
706}
707
708static int xive_irq_set_affinity(struct irq_data *d,
709 const struct cpumask *cpumask,
710 bool force)
711{
712 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
713 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
714 u32 target, old_target;
715 int rc = 0;
716
717 pr_devel("xive_irq_set_affinity: irq %d\n", d->irq);
718
719 /* Is this valid ? */
720 if (cpumask_any_and(cpumask, cpu_online_mask) >= nr_cpu_ids)
721 return -EINVAL;
722
723 /* Don't do anything if the interrupt isn't started */
724 if (!irqd_is_started(d))
725 return IRQ_SET_MASK_OK;
726
727 /*
728 * If existing target is already in the new mask, and is
729 * online then do nothing.
730 */
731 if (xd->target != XIVE_INVALID_TARGET &&
732 cpu_online(xd->target) &&
733 cpumask_test_cpu(xd->target, cpumask))
734 return IRQ_SET_MASK_OK;
735
736 /* Pick a new target */
737 target = xive_pick_irq_target(d, cpumask);
738
739 /* No target found */
740 if (target == XIVE_INVALID_TARGET)
741 return -ENXIO;
742
743 /* Sanity check */
744 if (WARN_ON(target >= nr_cpu_ids))
745 target = smp_processor_id();
746
747 old_target = xd->target;
748
749 /*
750 * Only configure the irq if it's not currently passed-through to
751 * a KVM guest
752 */
753 if (!irqd_is_forwarded_to_vcpu(d))
754 rc = xive_ops->configure_irq(hw_irq,
755 get_hard_smp_processor_id(target),
756 xive_irq_priority, d->irq);
757 if (rc < 0) {
758 pr_err("Error %d reconfiguring irq %d\n", rc, d->irq);
759 return rc;
760 }
761
762 pr_devel(" target: 0x%x\n", target);
763 xd->target = target;
764
765 /* Give up previous target */
766 if (old_target != XIVE_INVALID_TARGET)
767 xive_dec_target_count(old_target);
768
769 return IRQ_SET_MASK_OK;
770}
771
772static int xive_irq_set_type(struct irq_data *d, unsigned int flow_type)
773{
774 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
775
776 /*
777 * We only support these. This has really no effect other than setting
778 * the corresponding descriptor bits mind you but those will in turn
779 * affect the resend function when re-enabling an edge interrupt.
780 *
781 * Set set the default to edge as explained in map().
782 */
783 if (flow_type == IRQ_TYPE_DEFAULT || flow_type == IRQ_TYPE_NONE)
784 flow_type = IRQ_TYPE_EDGE_RISING;
785
786 if (flow_type != IRQ_TYPE_EDGE_RISING &&
787 flow_type != IRQ_TYPE_LEVEL_LOW)
788 return -EINVAL;
789
790 irqd_set_trigger_type(d, flow_type);
791
792 /*
793 * Double check it matches what the FW thinks
794 *
795 * NOTE: We don't know yet if the PAPR interface will provide
796 * the LSI vs MSI information apart from the device-tree so
797 * this check might have to move into an optional backend call
798 * that is specific to the native backend
799 */
800 if ((flow_type == IRQ_TYPE_LEVEL_LOW) !=
801 !!(xd->flags & XIVE_IRQ_FLAG_LSI)) {
802 pr_warn("Interrupt %d (HW 0x%x) type mismatch, Linux says %s, FW says %s\n",
803 d->irq, (u32)irqd_to_hwirq(d),
804 (flow_type == IRQ_TYPE_LEVEL_LOW) ? "Level" : "Edge",
805 (xd->flags & XIVE_IRQ_FLAG_LSI) ? "Level" : "Edge");
806 }
807
808 return IRQ_SET_MASK_OK_NOCOPY;
809}
810
811static int xive_irq_retrigger(struct irq_data *d)
812{
813 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
814
815 /* This should be only for MSIs */
816 if (WARN_ON(xd->flags & XIVE_IRQ_FLAG_LSI))
817 return 0;
818
819 /*
820 * To perform a retrigger, we first set the PQ bits to
821 * 11, then perform an EOI.
822 */
823 xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
824 xive_do_source_eoi(xd);
825
826 return 1;
827}
828
829/*
830 * Caller holds the irq descriptor lock, so this won't be called
831 * concurrently with xive_get_irqchip_state on the same interrupt.
832 */
833static int xive_irq_set_vcpu_affinity(struct irq_data *d, void *state)
834{
835 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
836 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
837 int rc;
838 u8 pq;
839
840 /*
841 * This is called by KVM with state non-NULL for enabling
842 * pass-through or NULL for disabling it
843 */
844 if (state) {
845 irqd_set_forwarded_to_vcpu(d);
846
847 /* Set it to PQ=10 state to prevent further sends */
848 pq = xive_esb_read(xd, XIVE_ESB_SET_PQ_10);
849 if (!xd->stale_p) {
850 xd->saved_p = !!(pq & XIVE_ESB_VAL_P);
851 xd->stale_p = !xd->saved_p;
852 }
853
854 /* No target ? nothing to do */
855 if (xd->target == XIVE_INVALID_TARGET) {
856 /*
857 * An untargetted interrupt should have been
858 * also masked at the source
859 */
860 WARN_ON(xd->saved_p);
861
862 return 0;
863 }
864
865 /*
866 * If P was set, adjust state to PQ=11 to indicate
867 * that a resend is needed for the interrupt to reach
868 * the guest. Also remember the value of P.
869 *
870 * This also tells us that it's in flight to a host queue
871 * or has already been fetched but hasn't been EOIed yet
872 * by the host. This it's potentially using up a host
873 * queue slot. This is important to know because as long
874 * as this is the case, we must not hard-unmask it when
875 * "returning" that interrupt to the host.
876 *
877 * This saved_p is cleared by the host EOI, when we know
878 * for sure the queue slot is no longer in use.
879 */
880 if (xd->saved_p) {
881 xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
882
883 /*
884 * Sync the XIVE source HW to ensure the interrupt
885 * has gone through the EAS before we change its
886 * target to the guest. That should guarantee us
887 * that we *will* eventually get an EOI for it on
888 * the host. Otherwise there would be a small window
889 * for P to be seen here but the interrupt going
890 * to the guest queue.
891 */
892 if (xive_ops->sync_source)
893 xive_ops->sync_source(hw_irq);
894 }
895 } else {
896 irqd_clr_forwarded_to_vcpu(d);
897
898 /* No host target ? hard mask and return */
899 if (xd->target == XIVE_INVALID_TARGET) {
900 xive_do_source_set_mask(xd, true);
901 return 0;
902 }
903
904 /*
905 * Sync the XIVE source HW to ensure the interrupt
906 * has gone through the EAS before we change its
907 * target to the host.
908 */
909 if (xive_ops->sync_source)
910 xive_ops->sync_source(hw_irq);
911
912 /*
913 * By convention we are called with the interrupt in
914 * a PQ=10 or PQ=11 state, ie, it won't fire and will
915 * have latched in Q whether there's a pending HW
916 * interrupt or not.
917 *
918 * First reconfigure the target.
919 */
920 rc = xive_ops->configure_irq(hw_irq,
921 get_hard_smp_processor_id(xd->target),
922 xive_irq_priority, d->irq);
923 if (rc)
924 return rc;
925
926 /*
927 * Then if saved_p is not set, effectively re-enable the
928 * interrupt with an EOI. If it is set, we know there is
929 * still a message in a host queue somewhere that will be
930 * EOId eventually.
931 *
932 * Note: We don't check irqd_irq_disabled(). Effectively,
933 * we *will* let the irq get through even if masked if the
934 * HW is still firing it in order to deal with the whole
935 * saved_p business properly. If the interrupt triggers
936 * while masked, the generic code will re-mask it anyway.
937 */
938 if (!xd->saved_p)
939 xive_do_source_eoi(xd);
940
941 }
942 return 0;
943}
944
945/* Called with irq descriptor lock held. */
946static int xive_get_irqchip_state(struct irq_data *data,
947 enum irqchip_irq_state which, bool *state)
948{
949 struct xive_irq_data *xd = irq_data_get_irq_handler_data(data);
950 u8 pq;
951
952 switch (which) {
953 case IRQCHIP_STATE_ACTIVE:
954 pq = xive_esb_read(xd, XIVE_ESB_GET);
955
956 /*
957 * The esb value being all 1's means we couldn't get
958 * the PQ state of the interrupt through mmio. It may
959 * happen, for example when querying a PHB interrupt
960 * while the PHB is in an error state. We consider the
961 * interrupt to be inactive in that case.
962 */
963 *state = (pq != XIVE_ESB_INVALID) && !xd->stale_p &&
964 (xd->saved_p || (!!(pq & XIVE_ESB_VAL_P) &&
965 !irqd_irq_disabled(data)));
966 return 0;
967 default:
968 return -EINVAL;
969 }
970}
971
972static struct irq_chip xive_irq_chip = {
973 .name = "XIVE-IRQ",
974 .irq_startup = xive_irq_startup,
975 .irq_shutdown = xive_irq_shutdown,
976 .irq_eoi = xive_irq_eoi,
977 .irq_mask = xive_irq_mask,
978 .irq_unmask = xive_irq_unmask,
979 .irq_set_affinity = xive_irq_set_affinity,
980 .irq_set_type = xive_irq_set_type,
981 .irq_retrigger = xive_irq_retrigger,
982 .irq_set_vcpu_affinity = xive_irq_set_vcpu_affinity,
983 .irq_get_irqchip_state = xive_get_irqchip_state,
984};
985
986bool is_xive_irq(struct irq_chip *chip)
987{
988 return chip == &xive_irq_chip;
989}
990EXPORT_SYMBOL_GPL(is_xive_irq);
991
992void xive_cleanup_irq_data(struct xive_irq_data *xd)
993{
994 if (xd->eoi_mmio) {
995 iounmap(xd->eoi_mmio);
996 if (xd->eoi_mmio == xd->trig_mmio)
997 xd->trig_mmio = NULL;
998 xd->eoi_mmio = NULL;
999 }
1000 if (xd->trig_mmio) {
1001 iounmap(xd->trig_mmio);
1002 xd->trig_mmio = NULL;
1003 }
1004}
1005EXPORT_SYMBOL_GPL(xive_cleanup_irq_data);
1006
1007static int xive_irq_alloc_data(unsigned int virq, irq_hw_number_t hw)
1008{
1009 struct xive_irq_data *xd;
1010 int rc;
1011
1012 xd = kzalloc(sizeof(struct xive_irq_data), GFP_KERNEL);
1013 if (!xd)
1014 return -ENOMEM;
1015 rc = xive_ops->populate_irq_data(hw, xd);
1016 if (rc) {
1017 kfree(xd);
1018 return rc;
1019 }
1020 xd->target = XIVE_INVALID_TARGET;
1021 irq_set_handler_data(virq, xd);
1022
1023 /*
1024 * Turn OFF by default the interrupt being mapped. A side
1025 * effect of this check is the mapping the ESB page of the
1026 * interrupt in the Linux address space. This prevents page
1027 * fault issues in the crash handler which masks all
1028 * interrupts.
1029 */
1030 xive_esb_read(xd, XIVE_ESB_SET_PQ_01);
1031
1032 return 0;
1033}
1034
1035static void xive_irq_free_data(unsigned int virq)
1036{
1037 struct xive_irq_data *xd = irq_get_handler_data(virq);
1038
1039 if (!xd)
1040 return;
1041 irq_set_handler_data(virq, NULL);
1042 xive_cleanup_irq_data(xd);
1043 kfree(xd);
1044}
1045
1046#ifdef CONFIG_SMP
1047
1048static void xive_cause_ipi(int cpu)
1049{
1050 struct xive_cpu *xc;
1051 struct xive_irq_data *xd;
1052
1053 xc = per_cpu(xive_cpu, cpu);
1054
1055 DBG_VERBOSE("IPI CPU %d -> %d (HW IRQ 0x%x)\n",
1056 smp_processor_id(), cpu, xc->hw_ipi);
1057
1058 xd = &xc->ipi_data;
1059 if (WARN_ON(!xd->trig_mmio))
1060 return;
1061 out_be64(xd->trig_mmio, 0);
1062}
1063
1064static irqreturn_t xive_muxed_ipi_action(int irq, void *dev_id)
1065{
1066 return smp_ipi_demux();
1067}
1068
1069static void xive_ipi_eoi(struct irq_data *d)
1070{
1071 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1072
1073 /* Handle possible race with unplug and drop stale IPIs */
1074 if (!xc)
1075 return;
1076
1077 DBG_VERBOSE("IPI eoi: irq=%d [0x%lx] (HW IRQ 0x%x) pending=%02x\n",
1078 d->irq, irqd_to_hwirq(d), xc->hw_ipi, xc->pending_prio);
1079
1080 xive_do_source_eoi(&xc->ipi_data);
1081 xive_do_queue_eoi(xc);
1082}
1083
1084static void xive_ipi_do_nothing(struct irq_data *d)
1085{
1086 /*
1087 * Nothing to do, we never mask/unmask IPIs, but the callback
1088 * has to exist for the struct irq_chip.
1089 */
1090}
1091
1092static struct irq_chip xive_ipi_chip = {
1093 .name = "XIVE-IPI",
1094 .irq_eoi = xive_ipi_eoi,
1095 .irq_mask = xive_ipi_do_nothing,
1096 .irq_unmask = xive_ipi_do_nothing,
1097};
1098
1099/*
1100 * IPIs are marked per-cpu. We use separate HW interrupts under the
1101 * hood but associated with the same "linux" interrupt
1102 */
1103struct xive_ipi_alloc_info {
1104 irq_hw_number_t hwirq;
1105};
1106
1107static int xive_ipi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1108 unsigned int nr_irqs, void *arg)
1109{
1110 struct xive_ipi_alloc_info *info = arg;
1111 int i;
1112
1113 for (i = 0; i < nr_irqs; i++) {
1114 irq_domain_set_info(domain, virq + i, info->hwirq + i, &xive_ipi_chip,
1115 domain->host_data, handle_percpu_irq,
1116 NULL, NULL);
1117 }
1118 return 0;
1119}
1120
1121static const struct irq_domain_ops xive_ipi_irq_domain_ops = {
1122 .alloc = xive_ipi_irq_domain_alloc,
1123};
1124
1125static int __init xive_init_ipis(void)
1126{
1127 struct fwnode_handle *fwnode;
1128 struct irq_domain *ipi_domain;
1129 unsigned int node;
1130 int ret = -ENOMEM;
1131
1132 fwnode = irq_domain_alloc_named_fwnode("XIVE-IPI");
1133 if (!fwnode)
1134 goto out;
1135
1136 ipi_domain = irq_domain_create_linear(fwnode, nr_node_ids,
1137 &xive_ipi_irq_domain_ops, NULL);
1138 if (!ipi_domain)
1139 goto out_free_fwnode;
1140
1141 xive_ipis = kcalloc(nr_node_ids, sizeof(*xive_ipis), GFP_KERNEL | __GFP_NOFAIL);
1142 if (!xive_ipis)
1143 goto out_free_domain;
1144
1145 for_each_node(node) {
1146 struct xive_ipi_desc *xid = &xive_ipis[node];
1147 struct xive_ipi_alloc_info info = { node };
1148
1149 /*
1150 * Map one IPI interrupt per node for all cpus of that node.
1151 * Since the HW interrupt number doesn't have any meaning,
1152 * simply use the node number.
1153 */
1154 ret = irq_domain_alloc_irqs(ipi_domain, 1, node, &info);
1155 if (ret < 0)
1156 goto out_free_xive_ipis;
1157 xid->irq = ret;
1158
1159 snprintf(xid->name, sizeof(xid->name), "IPI-%d", node);
1160 }
1161
1162 return ret;
1163
1164out_free_xive_ipis:
1165 kfree(xive_ipis);
1166out_free_domain:
1167 irq_domain_remove(ipi_domain);
1168out_free_fwnode:
1169 irq_domain_free_fwnode(fwnode);
1170out:
1171 return ret;
1172}
1173
1174static int xive_request_ipi(unsigned int cpu)
1175{
1176 struct xive_ipi_desc *xid = &xive_ipis[early_cpu_to_node(cpu)];
1177 int ret;
1178
1179 if (atomic_inc_return(&xid->started) > 1)
1180 return 0;
1181
1182 ret = request_irq(xid->irq, xive_muxed_ipi_action,
1183 IRQF_PERCPU | IRQF_NO_THREAD,
1184 xid->name, NULL);
1185
1186 WARN(ret < 0, "Failed to request IPI %d: %d\n", xid->irq, ret);
1187 return ret;
1188}
1189
1190static int xive_setup_cpu_ipi(unsigned int cpu)
1191{
1192 unsigned int xive_ipi_irq = xive_ipi_cpu_to_irq(cpu);
1193 struct xive_cpu *xc;
1194 int rc;
1195
1196 pr_debug("Setting up IPI for CPU %d\n", cpu);
1197
1198 xc = per_cpu(xive_cpu, cpu);
1199
1200 /* Check if we are already setup */
1201 if (xc->hw_ipi != XIVE_BAD_IRQ)
1202 return 0;
1203
1204 /* Register the IPI */
1205 xive_request_ipi(cpu);
1206
1207 /* Grab an IPI from the backend, this will populate xc->hw_ipi */
1208 if (xive_ops->get_ipi(cpu, xc))
1209 return -EIO;
1210
1211 /*
1212 * Populate the IRQ data in the xive_cpu structure and
1213 * configure the HW / enable the IPIs.
1214 */
1215 rc = xive_ops->populate_irq_data(xc->hw_ipi, &xc->ipi_data);
1216 if (rc) {
1217 pr_err("Failed to populate IPI data on CPU %d\n", cpu);
1218 return -EIO;
1219 }
1220 rc = xive_ops->configure_irq(xc->hw_ipi,
1221 get_hard_smp_processor_id(cpu),
1222 xive_irq_priority, xive_ipi_irq);
1223 if (rc) {
1224 pr_err("Failed to map IPI CPU %d\n", cpu);
1225 return -EIO;
1226 }
1227 pr_devel("CPU %d HW IPI %x, virq %d, trig_mmio=%p\n", cpu,
1228 xc->hw_ipi, xive_ipi_irq, xc->ipi_data.trig_mmio);
1229
1230 /* Unmask it */
1231 xive_do_source_set_mask(&xc->ipi_data, false);
1232
1233 return 0;
1234}
1235
1236static void xive_cleanup_cpu_ipi(unsigned int cpu, struct xive_cpu *xc)
1237{
1238 unsigned int xive_ipi_irq = xive_ipi_cpu_to_irq(cpu);
1239
1240 /* Disable the IPI and free the IRQ data */
1241
1242 /* Already cleaned up ? */
1243 if (xc->hw_ipi == XIVE_BAD_IRQ)
1244 return;
1245
1246 /* TODO: clear IPI mapping */
1247
1248 /* Mask the IPI */
1249 xive_do_source_set_mask(&xc->ipi_data, true);
1250
1251 /*
1252 * Note: We don't call xive_cleanup_irq_data() to free
1253 * the mappings as this is called from an IPI on kexec
1254 * which is not a safe environment to call iounmap()
1255 */
1256
1257 /* Deconfigure/mask in the backend */
1258 xive_ops->configure_irq(xc->hw_ipi, hard_smp_processor_id(),
1259 0xff, xive_ipi_irq);
1260
1261 /* Free the IPIs in the backend */
1262 xive_ops->put_ipi(cpu, xc);
1263}
1264
1265void __init xive_smp_probe(void)
1266{
1267 smp_ops->cause_ipi = xive_cause_ipi;
1268
1269 /* Register the IPI */
1270 xive_init_ipis();
1271
1272 /* Allocate and setup IPI for the boot CPU */
1273 xive_setup_cpu_ipi(smp_processor_id());
1274}
1275
1276#endif /* CONFIG_SMP */
1277
1278static int xive_irq_domain_map(struct irq_domain *h, unsigned int virq,
1279 irq_hw_number_t hw)
1280{
1281 int rc;
1282
1283 /*
1284 * Mark interrupts as edge sensitive by default so that resend
1285 * actually works. Will fix that up below if needed.
1286 */
1287 irq_clear_status_flags(virq, IRQ_LEVEL);
1288
1289 rc = xive_irq_alloc_data(virq, hw);
1290 if (rc)
1291 return rc;
1292
1293 irq_set_chip_and_handler(virq, &xive_irq_chip, handle_fasteoi_irq);
1294
1295 return 0;
1296}
1297
1298static void xive_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
1299{
1300 xive_irq_free_data(virq);
1301}
1302
1303static int xive_irq_domain_xlate(struct irq_domain *h, struct device_node *ct,
1304 const u32 *intspec, unsigned int intsize,
1305 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1306
1307{
1308 *out_hwirq = intspec[0];
1309
1310 /*
1311 * If intsize is at least 2, we look for the type in the second cell,
1312 * we assume the LSB indicates a level interrupt.
1313 */
1314 if (intsize > 1) {
1315 if (intspec[1] & 1)
1316 *out_flags = IRQ_TYPE_LEVEL_LOW;
1317 else
1318 *out_flags = IRQ_TYPE_EDGE_RISING;
1319 } else
1320 *out_flags = IRQ_TYPE_LEVEL_LOW;
1321
1322 return 0;
1323}
1324
1325static int xive_irq_domain_match(struct irq_domain *h, struct device_node *node,
1326 enum irq_domain_bus_token bus_token)
1327{
1328 return xive_ops->match(node);
1329}
1330
1331#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
1332static const char * const esb_names[] = { "RESET", "OFF", "PENDING", "QUEUED" };
1333
1334static const struct {
1335 u64 mask;
1336 char *name;
1337} xive_irq_flags[] = {
1338 { XIVE_IRQ_FLAG_STORE_EOI, "STORE_EOI" },
1339 { XIVE_IRQ_FLAG_LSI, "LSI" },
1340 { XIVE_IRQ_FLAG_H_INT_ESB, "H_INT_ESB" },
1341 { XIVE_IRQ_FLAG_NO_EOI, "NO_EOI" },
1342};
1343
1344static void xive_irq_domain_debug_show(struct seq_file *m, struct irq_domain *d,
1345 struct irq_data *irqd, int ind)
1346{
1347 struct xive_irq_data *xd;
1348 u64 val;
1349 int i;
1350
1351 /* No IRQ domain level information. To be done */
1352 if (!irqd)
1353 return;
1354
1355 if (!is_xive_irq(irq_data_get_irq_chip(irqd)))
1356 return;
1357
1358 seq_printf(m, "%*sXIVE:\n", ind, "");
1359 ind++;
1360
1361 xd = irq_data_get_irq_handler_data(irqd);
1362 if (!xd) {
1363 seq_printf(m, "%*snot assigned\n", ind, "");
1364 return;
1365 }
1366
1367 val = xive_esb_read(xd, XIVE_ESB_GET);
1368 seq_printf(m, "%*sESB: %s\n", ind, "", esb_names[val & 0x3]);
1369 seq_printf(m, "%*sPstate: %s %s\n", ind, "", xd->stale_p ? "stale" : "",
1370 xd->saved_p ? "saved" : "");
1371 seq_printf(m, "%*sTarget: %d\n", ind, "", xd->target);
1372 seq_printf(m, "%*sChip: %d\n", ind, "", xd->src_chip);
1373 seq_printf(m, "%*sTrigger: 0x%016llx\n", ind, "", xd->trig_page);
1374 seq_printf(m, "%*sEOI: 0x%016llx\n", ind, "", xd->eoi_page);
1375 seq_printf(m, "%*sFlags: 0x%llx\n", ind, "", xd->flags);
1376 for (i = 0; i < ARRAY_SIZE(xive_irq_flags); i++) {
1377 if (xd->flags & xive_irq_flags[i].mask)
1378 seq_printf(m, "%*s%s\n", ind + 12, "", xive_irq_flags[i].name);
1379 }
1380}
1381#endif
1382
1383static const struct irq_domain_ops xive_irq_domain_ops = {
1384 .match = xive_irq_domain_match,
1385 .map = xive_irq_domain_map,
1386 .unmap = xive_irq_domain_unmap,
1387 .xlate = xive_irq_domain_xlate,
1388#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
1389 .debug_show = xive_irq_domain_debug_show,
1390#endif
1391};
1392
1393static void __init xive_init_host(struct device_node *np)
1394{
1395 xive_irq_domain = irq_domain_add_nomap(np, XIVE_MAX_IRQ,
1396 &xive_irq_domain_ops, NULL);
1397 if (WARN_ON(xive_irq_domain == NULL))
1398 return;
1399 irq_set_default_host(xive_irq_domain);
1400}
1401
1402static void xive_cleanup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)
1403{
1404 if (xc->queue[xive_irq_priority].qpage)
1405 xive_ops->cleanup_queue(cpu, xc, xive_irq_priority);
1406}
1407
1408static int xive_setup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)
1409{
1410 int rc = 0;
1411
1412 /* We setup 1 queues for now with a 64k page */
1413 if (!xc->queue[xive_irq_priority].qpage)
1414 rc = xive_ops->setup_queue(cpu, xc, xive_irq_priority);
1415
1416 return rc;
1417}
1418
1419static int xive_prepare_cpu(unsigned int cpu)
1420{
1421 struct xive_cpu *xc;
1422
1423 xc = per_cpu(xive_cpu, cpu);
1424 if (!xc) {
1425 xc = kzalloc_node(sizeof(struct xive_cpu),
1426 GFP_KERNEL, cpu_to_node(cpu));
1427 if (!xc)
1428 return -ENOMEM;
1429 xc->hw_ipi = XIVE_BAD_IRQ;
1430 xc->chip_id = XIVE_INVALID_CHIP_ID;
1431 if (xive_ops->prepare_cpu)
1432 xive_ops->prepare_cpu(cpu, xc);
1433
1434 per_cpu(xive_cpu, cpu) = xc;
1435 }
1436
1437 /* Setup EQs if not already */
1438 return xive_setup_cpu_queues(cpu, xc);
1439}
1440
1441static void xive_setup_cpu(void)
1442{
1443 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1444
1445 /* The backend might have additional things to do */
1446 if (xive_ops->setup_cpu)
1447 xive_ops->setup_cpu(smp_processor_id(), xc);
1448
1449 /* Set CPPR to 0xff to enable flow of interrupts */
1450 xc->cppr = 0xff;
1451 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);
1452}
1453
1454#ifdef CONFIG_SMP
1455void xive_smp_setup_cpu(void)
1456{
1457 pr_devel("SMP setup CPU %d\n", smp_processor_id());
1458
1459 /* This will have already been done on the boot CPU */
1460 if (smp_processor_id() != boot_cpuid)
1461 xive_setup_cpu();
1462
1463}
1464
1465int xive_smp_prepare_cpu(unsigned int cpu)
1466{
1467 int rc;
1468
1469 /* Allocate per-CPU data and queues */
1470 rc = xive_prepare_cpu(cpu);
1471 if (rc)
1472 return rc;
1473
1474 /* Allocate and setup IPI for the new CPU */
1475 return xive_setup_cpu_ipi(cpu);
1476}
1477
1478#ifdef CONFIG_HOTPLUG_CPU
1479static void xive_flush_cpu_queue(unsigned int cpu, struct xive_cpu *xc)
1480{
1481 u32 irq;
1482
1483 /* We assume local irqs are disabled */
1484 WARN_ON(!irqs_disabled());
1485
1486 /* Check what's already in the CPU queue */
1487 while ((irq = xive_scan_interrupts(xc, false)) != 0) {
1488 /*
1489 * We need to re-route that interrupt to its new destination.
1490 * First get and lock the descriptor
1491 */
1492 struct irq_desc *desc = irq_to_desc(irq);
1493 struct irq_data *d = irq_desc_get_irq_data(desc);
1494 struct xive_irq_data *xd;
1495
1496 /*
1497 * Ignore anything that isn't a XIVE irq and ignore
1498 * IPIs, so can just be dropped.
1499 */
1500 if (d->domain != xive_irq_domain)
1501 continue;
1502
1503 /*
1504 * The IRQ should have already been re-routed, it's just a
1505 * stale in the old queue, so re-trigger it in order to make
1506 * it reach is new destination.
1507 */
1508#ifdef DEBUG_FLUSH
1509 pr_info("CPU %d: Got irq %d while offline, re-sending...\n",
1510 cpu, irq);
1511#endif
1512 raw_spin_lock(&desc->lock);
1513 xd = irq_desc_get_handler_data(desc);
1514
1515 /*
1516 * Clear saved_p to indicate that it's no longer pending
1517 */
1518 xd->saved_p = false;
1519
1520 /*
1521 * For LSIs, we EOI, this will cause a resend if it's
1522 * still asserted. Otherwise do an MSI retrigger.
1523 */
1524 if (xd->flags & XIVE_IRQ_FLAG_LSI)
1525 xive_do_source_eoi(xd);
1526 else
1527 xive_irq_retrigger(d);
1528
1529 raw_spin_unlock(&desc->lock);
1530 }
1531}
1532
1533void xive_smp_disable_cpu(void)
1534{
1535 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1536 unsigned int cpu = smp_processor_id();
1537
1538 /* Migrate interrupts away from the CPU */
1539 irq_migrate_all_off_this_cpu();
1540
1541 /* Set CPPR to 0 to disable flow of interrupts */
1542 xc->cppr = 0;
1543 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1544
1545 /* Flush everything still in the queue */
1546 xive_flush_cpu_queue(cpu, xc);
1547
1548 /* Re-enable CPPR */
1549 xc->cppr = 0xff;
1550 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);
1551}
1552
1553void xive_flush_interrupt(void)
1554{
1555 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1556 unsigned int cpu = smp_processor_id();
1557
1558 /* Called if an interrupt occurs while the CPU is hot unplugged */
1559 xive_flush_cpu_queue(cpu, xc);
1560}
1561
1562#endif /* CONFIG_HOTPLUG_CPU */
1563
1564#endif /* CONFIG_SMP */
1565
1566void xive_teardown_cpu(void)
1567{
1568 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1569 unsigned int cpu = smp_processor_id();
1570
1571 /* Set CPPR to 0 to disable flow of interrupts */
1572 xc->cppr = 0;
1573 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1574
1575 if (xive_ops->teardown_cpu)
1576 xive_ops->teardown_cpu(cpu, xc);
1577
1578#ifdef CONFIG_SMP
1579 /* Get rid of IPI */
1580 xive_cleanup_cpu_ipi(cpu, xc);
1581#endif
1582
1583 /* Disable and free the queues */
1584 xive_cleanup_cpu_queues(cpu, xc);
1585}
1586
1587void xive_shutdown(void)
1588{
1589 xive_ops->shutdown();
1590}
1591
1592bool __init xive_core_init(struct device_node *np, const struct xive_ops *ops,
1593 void __iomem *area, u32 offset, u8 max_prio)
1594{
1595 xive_tima = area;
1596 xive_tima_offset = offset;
1597 xive_ops = ops;
1598 xive_irq_priority = max_prio;
1599
1600 ppc_md.get_irq = xive_get_irq;
1601 __xive_enabled = true;
1602
1603 pr_devel("Initializing host..\n");
1604 xive_init_host(np);
1605
1606 pr_devel("Initializing boot CPU..\n");
1607
1608 /* Allocate per-CPU data and queues */
1609 xive_prepare_cpu(smp_processor_id());
1610
1611 /* Get ready for interrupts */
1612 xive_setup_cpu();
1613
1614 pr_info("Interrupt handling initialized with %s backend\n",
1615 xive_ops->name);
1616 pr_info("Using priority %d for all interrupts\n", max_prio);
1617
1618 return true;
1619}
1620
1621__be32 *xive_queue_page_alloc(unsigned int cpu, u32 queue_shift)
1622{
1623 unsigned int alloc_order;
1624 struct page *pages;
1625 __be32 *qpage;
1626
1627 alloc_order = xive_alloc_order(queue_shift);
1628 pages = alloc_pages_node(cpu_to_node(cpu), GFP_KERNEL, alloc_order);
1629 if (!pages)
1630 return ERR_PTR(-ENOMEM);
1631 qpage = (__be32 *)page_address(pages);
1632 memset(qpage, 0, 1 << queue_shift);
1633
1634 return qpage;
1635}
1636
1637static int __init xive_off(char *arg)
1638{
1639 xive_cmdline_disabled = true;
1640 return 0;
1641}
1642__setup("xive=off", xive_off);
1643
1644static void xive_debug_show_cpu(struct seq_file *m, int cpu)
1645{
1646 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
1647
1648 seq_printf(m, "CPU %d:", cpu);
1649 if (xc) {
1650 seq_printf(m, "pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr);
1651
1652#ifdef CONFIG_SMP
1653 {
1654 u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET);
1655
1656 seq_printf(m, "IPI=0x%08x PQ=%c%c ", xc->hw_ipi,
1657 val & XIVE_ESB_VAL_P ? 'P' : '-',
1658 val & XIVE_ESB_VAL_Q ? 'Q' : '-');
1659 }
1660#endif
1661 {
1662 struct xive_q *q = &xc->queue[xive_irq_priority];
1663 u32 i0, i1, idx;
1664
1665 if (q->qpage) {
1666 idx = q->idx;
1667 i0 = be32_to_cpup(q->qpage + idx);
1668 idx = (idx + 1) & q->msk;
1669 i1 = be32_to_cpup(q->qpage + idx);
1670 seq_printf(m, "EQ idx=%d T=%d %08x %08x ...",
1671 q->idx, q->toggle, i0, i1);
1672 }
1673 }
1674 }
1675 seq_puts(m, "\n");
1676}
1677
1678static void xive_debug_show_irq(struct seq_file *m, struct irq_data *d)
1679{
1680 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
1681 int rc;
1682 u32 target;
1683 u8 prio;
1684 u32 lirq;
1685 struct xive_irq_data *xd;
1686 u64 val;
1687
1688 rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq);
1689 if (rc) {
1690 seq_printf(m, "IRQ 0x%08x : no config rc=%d\n", hw_irq, rc);
1691 return;
1692 }
1693
1694 seq_printf(m, "IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ",
1695 hw_irq, target, prio, lirq);
1696
1697 xd = irq_data_get_irq_handler_data(d);
1698 val = xive_esb_read(xd, XIVE_ESB_GET);
1699 seq_printf(m, "flags=%c%c%c PQ=%c%c",
1700 xd->flags & XIVE_IRQ_FLAG_STORE_EOI ? 'S' : ' ',
1701 xd->flags & XIVE_IRQ_FLAG_LSI ? 'L' : ' ',
1702 xd->flags & XIVE_IRQ_FLAG_H_INT_ESB ? 'H' : ' ',
1703 val & XIVE_ESB_VAL_P ? 'P' : '-',
1704 val & XIVE_ESB_VAL_Q ? 'Q' : '-');
1705 seq_puts(m, "\n");
1706}
1707
1708static int xive_core_debug_show(struct seq_file *m, void *private)
1709{
1710 unsigned int i;
1711 struct irq_desc *desc;
1712 int cpu;
1713
1714 if (xive_ops->debug_show)
1715 xive_ops->debug_show(m, private);
1716
1717 for_each_possible_cpu(cpu)
1718 xive_debug_show_cpu(m, cpu);
1719
1720 for_each_irq_desc(i, desc) {
1721 struct irq_data *d = irq_desc_get_irq_data(desc);
1722
1723 if (d->domain == xive_irq_domain)
1724 xive_debug_show_irq(m, d);
1725 }
1726 return 0;
1727}
1728DEFINE_SHOW_ATTRIBUTE(xive_core_debug);
1729
1730int xive_core_debug_init(void)
1731{
1732 if (xive_enabled())
1733 debugfs_create_file("xive", 0400, powerpc_debugfs_root,
1734 NULL, &xive_core_debug_fops);
1735 return 0;
1736}