1/*
 2 *	Routines to identify additional cpu features that are scattered in
 3 *	cpuid space.
 4 */
 5#include <linux/cpu.h>
 6
 7#include <asm/pat.h>
 
 8#include <asm/processor.h>
 9
10#include <asm/apic.h>
11
12struct cpuid_bit {
13	u16 feature;
14	u8 reg;
15	u8 bit;
16	u32 level;
17	u32 sub_leaf;
18};
19
20enum cpuid_regs {
21	CR_EAX = 0,
22	CR_ECX,
23	CR_EDX,
24	CR_EBX
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
25};
26
27void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
28{
29	u32 max_level;
30	u32 regs[4];
31	const struct cpuid_bit *cb;
32
33	static const struct cpuid_bit cpuid_bits[] = {
34		{ X86_FEATURE_DTHERM,		CR_EAX, 0, 0x00000006, 0 },
35		{ X86_FEATURE_IDA,		CR_EAX, 1, 0x00000006, 0 },
36		{ X86_FEATURE_ARAT,		CR_EAX, 2, 0x00000006, 0 },
37		{ X86_FEATURE_PLN,		CR_EAX, 4, 0x00000006, 0 },
38		{ X86_FEATURE_PTS,		CR_EAX, 6, 0x00000006, 0 },
39		{ X86_FEATURE_APERFMPERF,	CR_ECX, 0, 0x00000006, 0 },
40		{ X86_FEATURE_EPB,		CR_ECX, 3, 0x00000006, 0 },
41		{ X86_FEATURE_XSAVEOPT,		CR_EAX,	0, 0x0000000d, 1 },
42		{ X86_FEATURE_HW_PSTATE,	CR_EDX, 7, 0x80000007, 0 },
43		{ X86_FEATURE_CPB,		CR_EDX, 9, 0x80000007, 0 },
44		{ X86_FEATURE_PROC_FEEDBACK,	CR_EDX,11, 0x80000007, 0 },
45		{ X86_FEATURE_NPT,		CR_EDX, 0, 0x8000000a, 0 },
46		{ X86_FEATURE_LBRV,		CR_EDX, 1, 0x8000000a, 0 },
47		{ X86_FEATURE_SVML,		CR_EDX, 2, 0x8000000a, 0 },
48		{ X86_FEATURE_NRIPS,		CR_EDX, 3, 0x8000000a, 0 },
49		{ X86_FEATURE_TSCRATEMSR,	CR_EDX, 4, 0x8000000a, 0 },
50		{ X86_FEATURE_VMCBCLEAN,	CR_EDX, 5, 0x8000000a, 0 },
51		{ X86_FEATURE_FLUSHBYASID,	CR_EDX, 6, 0x8000000a, 0 },
52		{ X86_FEATURE_DECODEASSISTS,	CR_EDX, 7, 0x8000000a, 0 },
53		{ X86_FEATURE_PAUSEFILTER,	CR_EDX,10, 0x8000000a, 0 },
54		{ X86_FEATURE_PFTHRESHOLD,	CR_EDX,12, 0x8000000a, 0 },
55		{ 0, 0, 0, 0, 0 }
56	};
57
58	for (cb = cpuid_bits; cb->feature; cb++) {
59
60		/* Verify that the level is valid */
61		max_level = cpuid_eax(cb->level & 0xffff0000);
62		if (max_level < cb->level ||
63		    max_level > (cb->level | 0xffff))
64			continue;
65
66		cpuid_count(cb->level, cb->sub_leaf, &regs[CR_EAX],
67			    &regs[CR_EBX], &regs[CR_ECX], &regs[CR_EDX]);
 
68
69		if (regs[cb->reg] & (1 << cb->bit))
70			set_cpu_cap(c, cb->feature);
71	}
72}

 1/*
 2 *	Routines to identify additional cpu features that are scattered in
 3 *	cpuid space.
 4 */
 5#include <linux/cpu.h>
 6
 7#include <asm/memtype.h>
 8#include <asm/apic.h>
 9#include <asm/processor.h>
10
11#include "cpu.h"
12
13struct cpuid_bit {
14	u16 feature;
15	u8 reg;
16	u8 bit;
17	u32 level;
18	u32 sub_leaf;
19};
20
21/*
22 * Please keep the leaf sorted by cpuid_bit.level for faster search.
23 * X86_FEATURE_MBA is supported by both Intel and AMD. But the CPUID
24 * levels are different and there is a separate entry for each.
25 */
26static const struct cpuid_bit cpuid_bits[] = {
27	{ X86_FEATURE_APERFMPERF,       CPUID_ECX,  0, 0x00000006, 0 },
28	{ X86_FEATURE_EPB,		CPUID_ECX,  3, 0x00000006, 0 },
29	{ X86_FEATURE_CQM_LLC,		CPUID_EDX,  1, 0x0000000f, 0 },
30	{ X86_FEATURE_CQM_OCCUP_LLC,	CPUID_EDX,  0, 0x0000000f, 1 },
31	{ X86_FEATURE_CQM_MBM_TOTAL,	CPUID_EDX,  1, 0x0000000f, 1 },
32	{ X86_FEATURE_CQM_MBM_LOCAL,	CPUID_EDX,  2, 0x0000000f, 1 },
33	{ X86_FEATURE_CAT_L3,		CPUID_EBX,  1, 0x00000010, 0 },
34	{ X86_FEATURE_CAT_L2,		CPUID_EBX,  2, 0x00000010, 0 },
35	{ X86_FEATURE_CDP_L3,		CPUID_ECX,  2, 0x00000010, 1 },
36	{ X86_FEATURE_CDP_L2,		CPUID_ECX,  2, 0x00000010, 2 },
37	{ X86_FEATURE_MBA,		CPUID_EBX,  3, 0x00000010, 0 },
38	{ X86_FEATURE_PER_THREAD_MBA,	CPUID_ECX,  0, 0x00000010, 3 },
39	{ X86_FEATURE_SGX1,		CPUID_EAX,  0, 0x00000012, 0 },
40	{ X86_FEATURE_SGX2,		CPUID_EAX,  1, 0x00000012, 0 },
41	{ X86_FEATURE_HW_PSTATE,	CPUID_EDX,  7, 0x80000007, 0 },
42	{ X86_FEATURE_CPB,		CPUID_EDX,  9, 0x80000007, 0 },
43	{ X86_FEATURE_PROC_FEEDBACK,    CPUID_EDX, 11, 0x80000007, 0 },
44	{ X86_FEATURE_MBA,		CPUID_EBX,  6, 0x80000008, 0 },
45	{ 0, 0, 0, 0, 0 }
46};
47
48void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
49{
50	u32 max_level;
51	u32 regs[4];
52	const struct cpuid_bit *cb;
53
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
54	for (cb = cpuid_bits; cb->feature; cb++) {
55
56		/* Verify that the level is valid */
57		max_level = cpuid_eax(cb->level & 0xffff0000);
58		if (max_level < cb->level ||
59		    max_level > (cb->level | 0xffff))
60			continue;
61
62		cpuid_count(cb->level, cb->sub_leaf, &regs[CPUID_EAX],
63			    &regs[CPUID_EBX], &regs[CPUID_ECX],
64			    &regs[CPUID_EDX]);
65
66		if (regs[cb->reg] & (1 << cb->bit))
67			set_cpu_cap(c, cb->feature);
68	}
69}