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1/*
2 * linux/arch/arm/mach-omap1/clock.h
3 *
4 * Copyright (C) 2004 - 2005, 2009 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
14#define __ARCH_ARM_MACH_OMAP1_CLOCK_H
15
16#include <linux/clk.h>
17#include <linux/list.h>
18
19#include <linux/clkdev.h>
20
21struct module;
22struct clk;
23
24struct omap_clk {
25 u16 cpu;
26 struct clk_lookup lk;
27};
28
29#define CLK(dev, con, ck, cp) \
30 { \
31 .cpu = cp, \
32 .lk = { \
33 .dev_id = dev, \
34 .con_id = con, \
35 .clk = ck, \
36 }, \
37 }
38
39/* Platform flags for the clkdev-OMAP integration code */
40#define CK_310 (1 << 0)
41#define CK_7XX (1 << 1) /* 7xx, 850 */
42#define CK_1510 (1 << 2)
43#define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */
44#define CK_1710 (1 << 4) /* 1710 extra for rate selection */
45
46
47/* Temporary, needed during the common clock framework conversion */
48#define __clk_get_name(clk) (clk->name)
49#define __clk_get_parent(clk) (clk->parent)
50#define __clk_get_rate(clk) (clk->rate)
51
52/**
53 * struct clkops - some clock function pointers
54 * @enable: fn ptr that enables the current clock in hardware
55 * @disable: fn ptr that enables the current clock in hardware
56 * @find_idlest: function returning the IDLEST register for the clock's IP blk
57 * @find_companion: function returning the "companion" clk reg for the clock
58 * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
59 * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
60 *
61 * A "companion" clk is an accompanying clock to the one being queried
62 * that must be enabled for the IP module connected to the clock to
63 * become accessible by the hardware. Neither @find_idlest nor
64 * @find_companion should be needed; that information is IP
65 * block-specific; the hwmod code has been created to handle this, but
66 * until hwmod data is ready and drivers have been converted to use PM
67 * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
68 * @find_companion must, unfortunately, remain.
69 */
70struct clkops {
71 int (*enable)(struct clk *);
72 void (*disable)(struct clk *);
73 void (*find_idlest)(struct clk *, void __iomem **,
74 u8 *, u8 *);
75 void (*find_companion)(struct clk *, void __iomem **,
76 u8 *);
77 void (*allow_idle)(struct clk *);
78 void (*deny_idle)(struct clk *);
79};
80
81/*
82 * struct clk.flags possibilities
83 *
84 * XXX document the rest of the clock flags here
85 *
86 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
87 * bits share the same register. This flag allows the
88 * omap4_dpllmx*() code to determine which GATE_CTRL bit field
89 * should be used. This is a temporary solution - a better approach
90 * would be to associate clock type-specific data with the clock,
91 * similar to the struct dpll_data approach.
92 */
93#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
94#define CLOCK_IDLE_CONTROL (1 << 1)
95#define CLOCK_NO_IDLE_PARENT (1 << 2)
96#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
97#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
98#define CLOCK_CLKOUTX2 (1 << 5)
99
100/**
101 * struct clk - OMAP struct clk
102 * @node: list_head connecting this clock into the full clock list
103 * @ops: struct clkops * for this clock
104 * @name: the name of the clock in the hardware (used in hwmod data and debug)
105 * @parent: pointer to this clock's parent struct clk
106 * @children: list_head connecting to the child clks' @sibling list_heads
107 * @sibling: list_head connecting this clk to its parent clk's @children
108 * @rate: current clock rate
109 * @enable_reg: register to write to enable the clock (see @enable_bit)
110 * @recalc: fn ptr that returns the clock's current rate
111 * @set_rate: fn ptr that can change the clock's current rate
112 * @round_rate: fn ptr that can round the clock's current rate
113 * @init: fn ptr to do clock-specific initialization
114 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
115 * @usecount: number of users that have requested this clock to be enabled
116 * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
117 * @flags: see "struct clk.flags possibilities" above
118 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
119 * @src_offset: bitshift for source selection bitfield (OMAP1 only)
120 *
121 * XXX @rate_offset, @src_offset should probably be removed and OMAP1
122 * clock code converted to use clksel.
123 *
124 * XXX @usecount is poorly named. It should be "enable_count" or
125 * something similar. "users" in the description refers to kernel
126 * code (core code or drivers) that have called clk_enable() and not
127 * yet called clk_disable(); the usecount of parent clocks is also
128 * incremented by the clock code when clk_enable() is called on child
129 * clocks and decremented by the clock code when clk_disable() is
130 * called on child clocks.
131 *
132 * XXX @clkdm, @usecount, @children, @sibling should be marked for
133 * internal use only.
134 *
135 * @children and @sibling are used to optimize parent-to-child clock
136 * tree traversals. (child-to-parent traversals use @parent.)
137 *
138 * XXX The notion of the clock's current rate probably needs to be
139 * separated from the clock's target rate.
140 */
141struct clk {
142 struct list_head node;
143 const struct clkops *ops;
144 const char *name;
145 struct clk *parent;
146 struct list_head children;
147 struct list_head sibling; /* node for children */
148 unsigned long rate;
149 void __iomem *enable_reg;
150 unsigned long (*recalc)(struct clk *);
151 int (*set_rate)(struct clk *, unsigned long);
152 long (*round_rate)(struct clk *, unsigned long);
153 void (*init)(struct clk *);
154 u8 enable_bit;
155 s8 usecount;
156 u8 fixed_div;
157 u8 flags;
158 u8 rate_offset;
159 u8 src_offset;
160#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
161 struct dentry *dent; /* For visible tree hierarchy */
162#endif
163};
164
165struct clk_functions {
166 int (*clk_enable)(struct clk *clk);
167 void (*clk_disable)(struct clk *clk);
168 long (*clk_round_rate)(struct clk *clk, unsigned long rate);
169 int (*clk_set_rate)(struct clk *clk, unsigned long rate);
170 int (*clk_set_parent)(struct clk *clk, struct clk *parent);
171 void (*clk_allow_idle)(struct clk *clk);
172 void (*clk_deny_idle)(struct clk *clk);
173 void (*clk_disable_unused)(struct clk *clk);
174};
175
176extern int mpurate;
177
178extern int clk_init(struct clk_functions *custom_clocks);
179extern void clk_preinit(struct clk *clk);
180extern int clk_register(struct clk *clk);
181extern void clk_reparent(struct clk *child, struct clk *parent);
182extern void clk_unregister(struct clk *clk);
183extern void propagate_rate(struct clk *clk);
184extern void recalculate_root_clocks(void);
185extern unsigned long followparent_recalc(struct clk *clk);
186extern void clk_enable_init_clocks(void);
187unsigned long omap_fixed_divisor_recalc(struct clk *clk);
188extern struct clk *omap_clk_get_by_name(const char *name);
189extern int omap_clk_enable_autoidle_all(void);
190extern int omap_clk_disable_autoidle_all(void);
191
192extern const struct clkops clkops_null;
193
194extern struct clk dummy_ck;
195
196int omap1_clk_init(void);
197void omap1_clk_late_init(void);
198extern int omap1_clk_enable(struct clk *clk);
199extern void omap1_clk_disable(struct clk *clk);
200extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
201extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate);
202extern unsigned long omap1_ckctl_recalc(struct clk *clk);
203extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
204extern unsigned long omap1_sossi_recalc(struct clk *clk);
205extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
206extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate);
207extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate);
208extern unsigned long omap1_uart_recalc(struct clk *clk);
209extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate);
210extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate);
211extern void omap1_init_ext_clk(struct clk *clk);
212extern int omap1_select_table_rate(struct clk *clk, unsigned long rate);
213extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate);
214extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
215extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
216extern unsigned long omap1_watchdog_recalc(struct clk *clk);
217
218#ifdef CONFIG_OMAP_RESET_CLOCKS
219extern void omap1_clk_disable_unused(struct clk *clk);
220#else
221#define omap1_clk_disable_unused NULL
222#endif
223
224struct uart_clk {
225 struct clk clk;
226 unsigned long sysc_addr;
227};
228
229/* Provide a method for preventing idling some ARM IDLECT clocks */
230struct arm_idlect1_clk {
231 struct clk clk;
232 unsigned long no_idle_count;
233 __u8 idlect_shift;
234};
235
236/* ARM_CKCTL bit shifts */
237#define CKCTL_PERDIV_OFFSET 0
238#define CKCTL_LCDDIV_OFFSET 2
239#define CKCTL_ARMDIV_OFFSET 4
240#define CKCTL_DSPDIV_OFFSET 6
241#define CKCTL_TCDIV_OFFSET 8
242#define CKCTL_DSPMMUDIV_OFFSET 10
243/*#define ARM_TIMXO 12*/
244#define EN_DSPCK 13
245/*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
246/* DSP_CKCTL bit shifts */
247#define CKCTL_DSPPERDIV_OFFSET 0
248
249/* ARM_IDLECT2 bit shifts */
250#define EN_WDTCK 0
251#define EN_XORPCK 1
252#define EN_PERCK 2
253#define EN_LCDCK 3
254#define EN_LBCK 4 /* Not on 1610/1710 */
255/*#define EN_HSABCK 5*/
256#define EN_APICK 6
257#define EN_TIMCK 7
258#define DMACK_REQ 8
259#define EN_GPIOCK 9 /* Not on 1610/1710 */
260/*#define EN_LBFREECK 10*/
261#define EN_CKOUT_ARM 11
262
263/* ARM_IDLECT3 bit shifts */
264#define EN_OCPI_CK 0
265#define EN_TC1_CK 2
266#define EN_TC2_CK 4
267
268/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
269#define EN_DSPTIMCK 5
270
271/* Various register defines for clock controls scattered around OMAP chip */
272#define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */
273#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
274#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
275#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
276#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
277#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
278#define COM_CLK_DIV_CTRL_SEL 0xfffe0878
279#define SOFT_REQ_REG 0xfffe0834
280#define SOFT_REQ_REG2 0xfffe0880
281
282extern __u32 arm_idlect1_mask;
283extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
284
285extern const struct clkops clkops_dspck;
286extern const struct clkops clkops_dummy;
287extern const struct clkops clkops_uart_16xx;
288extern const struct clkops clkops_generic;
289
290/* used for passing SoC type to omap1_{select,round_to}_table_rate() */
291extern u32 cpu_mask;
292
293#endif
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/mach-omap1/clock.h
4 *
5 * Copyright (C) 2004 - 2005, 2009 Nokia corporation
6 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 */
9
10#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
11#define __ARCH_ARM_MACH_OMAP1_CLOCK_H
12
13#include <linux/clk.h>
14#include <linux/list.h>
15
16#include <linux/clkdev.h>
17
18struct module;
19struct clk;
20
21struct omap_clk {
22 u16 cpu;
23 struct clk_lookup lk;
24};
25
26#define CLK(dev, con, ck, cp) \
27 { \
28 .cpu = cp, \
29 .lk = { \
30 .dev_id = dev, \
31 .con_id = con, \
32 .clk = ck, \
33 }, \
34 }
35
36/* Platform flags for the clkdev-OMAP integration code */
37#define CK_310 (1 << 0)
38#define CK_7XX (1 << 1) /* 7xx, 850 */
39#define CK_1510 (1 << 2)
40#define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */
41#define CK_1710 (1 << 4) /* 1710 extra for rate selection */
42
43
44/* Temporary, needed during the common clock framework conversion */
45#define __clk_get_name(clk) (clk->name)
46#define __clk_get_parent(clk) (clk->parent)
47#define __clk_get_rate(clk) (clk->rate)
48
49/**
50 * struct clkops - some clock function pointers
51 * @enable: fn ptr that enables the current clock in hardware
52 * @disable: fn ptr that enables the current clock in hardware
53 * @find_idlest: function returning the IDLEST register for the clock's IP blk
54 * @find_companion: function returning the "companion" clk reg for the clock
55 * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
56 * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
57 *
58 * A "companion" clk is an accompanying clock to the one being queried
59 * that must be enabled for the IP module connected to the clock to
60 * become accessible by the hardware. Neither @find_idlest nor
61 * @find_companion should be needed; that information is IP
62 * block-specific; the hwmod code has been created to handle this, but
63 * until hwmod data is ready and drivers have been converted to use PM
64 * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
65 * @find_companion must, unfortunately, remain.
66 */
67struct clkops {
68 int (*enable)(struct clk *);
69 void (*disable)(struct clk *);
70 void (*find_idlest)(struct clk *, void __iomem **,
71 u8 *, u8 *);
72 void (*find_companion)(struct clk *, void __iomem **,
73 u8 *);
74 void (*allow_idle)(struct clk *);
75 void (*deny_idle)(struct clk *);
76};
77
78/*
79 * struct clk.flags possibilities
80 *
81 * XXX document the rest of the clock flags here
82 *
83 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
84 * bits share the same register. This flag allows the
85 * omap4_dpllmx*() code to determine which GATE_CTRL bit field
86 * should be used. This is a temporary solution - a better approach
87 * would be to associate clock type-specific data with the clock,
88 * similar to the struct dpll_data approach.
89 */
90#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
91#define CLOCK_IDLE_CONTROL (1 << 1)
92#define CLOCK_NO_IDLE_PARENT (1 << 2)
93#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
94#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
95#define CLOCK_CLKOUTX2 (1 << 5)
96
97/**
98 * struct clk - OMAP struct clk
99 * @node: list_head connecting this clock into the full clock list
100 * @ops: struct clkops * for this clock
101 * @name: the name of the clock in the hardware (used in hwmod data and debug)
102 * @parent: pointer to this clock's parent struct clk
103 * @children: list_head connecting to the child clks' @sibling list_heads
104 * @sibling: list_head connecting this clk to its parent clk's @children
105 * @rate: current clock rate
106 * @enable_reg: register to write to enable the clock (see @enable_bit)
107 * @recalc: fn ptr that returns the clock's current rate
108 * @set_rate: fn ptr that can change the clock's current rate
109 * @round_rate: fn ptr that can round the clock's current rate
110 * @init: fn ptr to do clock-specific initialization
111 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
112 * @usecount: number of users that have requested this clock to be enabled
113 * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
114 * @flags: see "struct clk.flags possibilities" above
115 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
116 * @src_offset: bitshift for source selection bitfield (OMAP1 only)
117 *
118 * XXX @rate_offset, @src_offset should probably be removed and OMAP1
119 * clock code converted to use clksel.
120 *
121 * XXX @usecount is poorly named. It should be "enable_count" or
122 * something similar. "users" in the description refers to kernel
123 * code (core code or drivers) that have called clk_enable() and not
124 * yet called clk_disable(); the usecount of parent clocks is also
125 * incremented by the clock code when clk_enable() is called on child
126 * clocks and decremented by the clock code when clk_disable() is
127 * called on child clocks.
128 *
129 * XXX @clkdm, @usecount, @children, @sibling should be marked for
130 * internal use only.
131 *
132 * @children and @sibling are used to optimize parent-to-child clock
133 * tree traversals. (child-to-parent traversals use @parent.)
134 *
135 * XXX The notion of the clock's current rate probably needs to be
136 * separated from the clock's target rate.
137 */
138struct clk {
139 struct list_head node;
140 const struct clkops *ops;
141 const char *name;
142 struct clk *parent;
143 struct list_head children;
144 struct list_head sibling; /* node for children */
145 unsigned long rate;
146 void __iomem *enable_reg;
147 unsigned long (*recalc)(struct clk *);
148 int (*set_rate)(struct clk *, unsigned long);
149 long (*round_rate)(struct clk *, unsigned long);
150 void (*init)(struct clk *);
151 u8 enable_bit;
152 s8 usecount;
153 u8 fixed_div;
154 u8 flags;
155 u8 rate_offset;
156 u8 src_offset;
157#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
158 struct dentry *dent; /* For visible tree hierarchy */
159#endif
160};
161
162struct clk_functions {
163 int (*clk_enable)(struct clk *clk);
164 void (*clk_disable)(struct clk *clk);
165 long (*clk_round_rate)(struct clk *clk, unsigned long rate);
166 int (*clk_set_rate)(struct clk *clk, unsigned long rate);
167 int (*clk_set_parent)(struct clk *clk, struct clk *parent);
168 void (*clk_allow_idle)(struct clk *clk);
169 void (*clk_deny_idle)(struct clk *clk);
170 void (*clk_disable_unused)(struct clk *clk);
171};
172
173extern int clk_init(struct clk_functions *custom_clocks);
174extern void clk_preinit(struct clk *clk);
175extern int clk_register(struct clk *clk);
176extern void clk_reparent(struct clk *child, struct clk *parent);
177extern void clk_unregister(struct clk *clk);
178extern void propagate_rate(struct clk *clk);
179extern void recalculate_root_clocks(void);
180extern unsigned long followparent_recalc(struct clk *clk);
181extern void clk_enable_init_clocks(void);
182unsigned long omap_fixed_divisor_recalc(struct clk *clk);
183extern struct clk *omap_clk_get_by_name(const char *name);
184extern int omap_clk_enable_autoidle_all(void);
185extern int omap_clk_disable_autoidle_all(void);
186
187extern const struct clkops clkops_null;
188
189extern struct clk dummy_ck;
190
191int omap1_clk_init(void);
192void omap1_clk_late_init(void);
193extern int omap1_clk_enable(struct clk *clk);
194extern void omap1_clk_disable(struct clk *clk);
195extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
196extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate);
197extern unsigned long omap1_ckctl_recalc(struct clk *clk);
198extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
199extern unsigned long omap1_sossi_recalc(struct clk *clk);
200extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
201extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate);
202extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate);
203extern unsigned long omap1_uart_recalc(struct clk *clk);
204extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate);
205extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate);
206extern void omap1_init_ext_clk(struct clk *clk);
207extern int omap1_select_table_rate(struct clk *clk, unsigned long rate);
208extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate);
209extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
210extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
211extern unsigned long omap1_watchdog_recalc(struct clk *clk);
212
213#ifdef CONFIG_OMAP_RESET_CLOCKS
214extern void omap1_clk_disable_unused(struct clk *clk);
215#else
216#define omap1_clk_disable_unused NULL
217#endif
218
219struct uart_clk {
220 struct clk clk;
221 unsigned long sysc_addr;
222};
223
224/* Provide a method for preventing idling some ARM IDLECT clocks */
225struct arm_idlect1_clk {
226 struct clk clk;
227 unsigned long no_idle_count;
228 __u8 idlect_shift;
229};
230
231/* ARM_CKCTL bit shifts */
232#define CKCTL_PERDIV_OFFSET 0
233#define CKCTL_LCDDIV_OFFSET 2
234#define CKCTL_ARMDIV_OFFSET 4
235#define CKCTL_DSPDIV_OFFSET 6
236#define CKCTL_TCDIV_OFFSET 8
237#define CKCTL_DSPMMUDIV_OFFSET 10
238/*#define ARM_TIMXO 12*/
239#define EN_DSPCK 13
240/*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
241/* DSP_CKCTL bit shifts */
242#define CKCTL_DSPPERDIV_OFFSET 0
243
244/* ARM_IDLECT2 bit shifts */
245#define EN_WDTCK 0
246#define EN_XORPCK 1
247#define EN_PERCK 2
248#define EN_LCDCK 3
249#define EN_LBCK 4 /* Not on 1610/1710 */
250/*#define EN_HSABCK 5*/
251#define EN_APICK 6
252#define EN_TIMCK 7
253#define DMACK_REQ 8
254#define EN_GPIOCK 9 /* Not on 1610/1710 */
255/*#define EN_LBFREECK 10*/
256#define EN_CKOUT_ARM 11
257
258/* ARM_IDLECT3 bit shifts */
259#define EN_OCPI_CK 0
260#define EN_TC1_CK 2
261#define EN_TC2_CK 4
262
263/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
264#define EN_DSPTIMCK 5
265
266/* Various register defines for clock controls scattered around OMAP chip */
267#define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */
268#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
269#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
270#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
271#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
272#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
273#define COM_CLK_DIV_CTRL_SEL 0xfffe0878
274#define SOFT_REQ_REG 0xfffe0834
275#define SOFT_REQ_REG2 0xfffe0880
276
277extern __u32 arm_idlect1_mask;
278extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
279
280extern const struct clkops clkops_dspck;
281extern const struct clkops clkops_dummy;
282extern const struct clkops clkops_uart_16xx;
283extern const struct clkops clkops_generic;
284
285/* used for passing SoC type to omap1_{select,round_to}_table_rate() */
286extern u32 cpu_mask;
287
288#endif