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1/*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/signal.h>
34#include <linux/jiffies.h>
35#include <linux/timer.h>
36#include <linux/pci.h>
37#include <linux/interrupt.h>
38#include <linux/time.h>
39#include <linux/slab.h>
40
41#include "../pci.h"
42#include "pciehp.h"
43
44static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
45{
46 return ctrl->pcie->port;
47}
48
49static irqreturn_t pcie_isr(int irq, void *dev_id);
50static void start_int_poll_timer(struct controller *ctrl, int sec);
51
52/* This is the interrupt polling timeout function. */
53static void int_poll_timeout(unsigned long data)
54{
55 struct controller *ctrl = (struct controller *)data;
56
57 /* Poll for interrupt events. regs == NULL => polling */
58 pcie_isr(0, ctrl);
59
60 init_timer(&ctrl->poll_timer);
61 if (!pciehp_poll_time)
62 pciehp_poll_time = 2; /* default polling interval is 2 sec */
63
64 start_int_poll_timer(ctrl, pciehp_poll_time);
65}
66
67/* This function starts the interrupt polling timer. */
68static void start_int_poll_timer(struct controller *ctrl, int sec)
69{
70 /* Clamp to sane value */
71 if ((sec <= 0) || (sec > 60))
72 sec = 2;
73
74 ctrl->poll_timer.function = &int_poll_timeout;
75 ctrl->poll_timer.data = (unsigned long)ctrl;
76 ctrl->poll_timer.expires = jiffies + sec * HZ;
77 add_timer(&ctrl->poll_timer);
78}
79
80static inline int pciehp_request_irq(struct controller *ctrl)
81{
82 int retval, irq = ctrl->pcie->irq;
83
84 /* Install interrupt polling timer. Start with 10 sec delay */
85 if (pciehp_poll_mode) {
86 init_timer(&ctrl->poll_timer);
87 start_int_poll_timer(ctrl, 10);
88 return 0;
89 }
90
91 /* Installs the interrupt handler */
92 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
93 if (retval)
94 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
95 irq);
96 return retval;
97}
98
99static inline void pciehp_free_irq(struct controller *ctrl)
100{
101 if (pciehp_poll_mode)
102 del_timer_sync(&ctrl->poll_timer);
103 else
104 free_irq(ctrl->pcie->irq, ctrl);
105}
106
107static int pcie_poll_cmd(struct controller *ctrl)
108{
109 struct pci_dev *pdev = ctrl_dev(ctrl);
110 u16 slot_status;
111 int timeout = 1000;
112
113 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
114 if (slot_status & PCI_EXP_SLTSTA_CC) {
115 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
116 PCI_EXP_SLTSTA_CC);
117 return 1;
118 }
119 while (timeout > 0) {
120 msleep(10);
121 timeout -= 10;
122 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
123 if (slot_status & PCI_EXP_SLTSTA_CC) {
124 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
125 PCI_EXP_SLTSTA_CC);
126 return 1;
127 }
128 }
129 return 0; /* timeout */
130}
131
132static void pcie_wait_cmd(struct controller *ctrl, int poll)
133{
134 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
135 unsigned long timeout = msecs_to_jiffies(msecs);
136 int rc;
137
138 if (poll)
139 rc = pcie_poll_cmd(ctrl);
140 else
141 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
142 if (!rc)
143 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
144}
145
146/**
147 * pcie_write_cmd - Issue controller command
148 * @ctrl: controller to which the command is issued
149 * @cmd: command value written to slot control register
150 * @mask: bitmask of slot control register to be modified
151 */
152static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
153{
154 struct pci_dev *pdev = ctrl_dev(ctrl);
155 u16 slot_status;
156 u16 slot_ctrl;
157
158 mutex_lock(&ctrl->ctrl_lock);
159
160 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
161 if (slot_status & PCI_EXP_SLTSTA_CC) {
162 if (!ctrl->no_cmd_complete) {
163 /*
164 * After 1 sec and CMD_COMPLETED still not set, just
165 * proceed forward to issue the next command according
166 * to spec. Just print out the error message.
167 */
168 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
169 } else if (!NO_CMD_CMPL(ctrl)) {
170 /*
171 * This controller seems to notify of command completed
172 * event even though it supports none of power
173 * controller, attention led, power led and EMI.
174 */
175 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
176 "wait for command completed event.\n");
177 ctrl->no_cmd_complete = 0;
178 } else {
179 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
180 "the controller is broken.\n");
181 }
182 }
183
184 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
185 slot_ctrl &= ~mask;
186 slot_ctrl |= (cmd & mask);
187 ctrl->cmd_busy = 1;
188 smp_mb();
189 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
190
191 /*
192 * Wait for command completion.
193 */
194 if (!ctrl->no_cmd_complete) {
195 int poll = 0;
196 /*
197 * if hotplug interrupt is not enabled or command
198 * completed interrupt is not enabled, we need to poll
199 * command completed event.
200 */
201 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
202 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
203 poll = 1;
204 pcie_wait_cmd(ctrl, poll);
205 }
206 mutex_unlock(&ctrl->ctrl_lock);
207}
208
209bool pciehp_check_link_active(struct controller *ctrl)
210{
211 struct pci_dev *pdev = ctrl_dev(ctrl);
212 u16 lnk_status;
213 bool ret;
214
215 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
216 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
217
218 if (ret)
219 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
220
221 return ret;
222}
223
224static void __pcie_wait_link_active(struct controller *ctrl, bool active)
225{
226 int timeout = 1000;
227
228 if (pciehp_check_link_active(ctrl) == active)
229 return;
230 while (timeout > 0) {
231 msleep(10);
232 timeout -= 10;
233 if (pciehp_check_link_active(ctrl) == active)
234 return;
235 }
236 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
237 active ? "set" : "cleared");
238}
239
240static void pcie_wait_link_active(struct controller *ctrl)
241{
242 __pcie_wait_link_active(ctrl, true);
243}
244
245static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
246{
247 u32 l;
248 int count = 0;
249 int delay = 1000, step = 20;
250 bool found = false;
251
252 do {
253 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
254 count++;
255
256 if (found)
257 break;
258
259 msleep(step);
260 delay -= step;
261 } while (delay > 0);
262
263 if (count > 1 && pciehp_debug)
264 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
265 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
266 PCI_FUNC(devfn), count, step, l);
267
268 return found;
269}
270
271int pciehp_check_link_status(struct controller *ctrl)
272{
273 struct pci_dev *pdev = ctrl_dev(ctrl);
274 bool found;
275 u16 lnk_status;
276
277 /*
278 * Data Link Layer Link Active Reporting must be capable for
279 * hot-plug capable downstream port. But old controller might
280 * not implement it. In this case, we wait for 1000 ms.
281 */
282 if (ctrl->link_active_reporting)
283 pcie_wait_link_active(ctrl);
284 else
285 msleep(1000);
286
287 /* wait 100ms before read pci conf, and try in 1s */
288 msleep(100);
289 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
290 PCI_DEVFN(0, 0));
291
292 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
293 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
294 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
295 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
296 ctrl_err(ctrl, "Link Training Error occurs \n");
297 return -1;
298 }
299
300 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
301
302 if (!found)
303 return -1;
304
305 return 0;
306}
307
308static int __pciehp_link_set(struct controller *ctrl, bool enable)
309{
310 struct pci_dev *pdev = ctrl_dev(ctrl);
311 u16 lnk_ctrl;
312
313 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
314
315 if (enable)
316 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
317 else
318 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
319
320 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
321 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
322 return 0;
323}
324
325static int pciehp_link_enable(struct controller *ctrl)
326{
327 return __pciehp_link_set(ctrl, true);
328}
329
330void pciehp_get_attention_status(struct slot *slot, u8 *status)
331{
332 struct controller *ctrl = slot->ctrl;
333 struct pci_dev *pdev = ctrl_dev(ctrl);
334 u16 slot_ctrl;
335
336 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
337 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
338 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
339
340 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
341 case PCI_EXP_SLTCTL_ATTN_IND_ON:
342 *status = 1; /* On */
343 break;
344 case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
345 *status = 2; /* Blink */
346 break;
347 case PCI_EXP_SLTCTL_ATTN_IND_OFF:
348 *status = 0; /* Off */
349 break;
350 default:
351 *status = 0xFF;
352 break;
353 }
354}
355
356void pciehp_get_power_status(struct slot *slot, u8 *status)
357{
358 struct controller *ctrl = slot->ctrl;
359 struct pci_dev *pdev = ctrl_dev(ctrl);
360 u16 slot_ctrl;
361
362 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
363 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
364 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
365
366 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
367 case PCI_EXP_SLTCTL_PWR_ON:
368 *status = 1; /* On */
369 break;
370 case PCI_EXP_SLTCTL_PWR_OFF:
371 *status = 0; /* Off */
372 break;
373 default:
374 *status = 0xFF;
375 break;
376 }
377}
378
379void pciehp_get_latch_status(struct slot *slot, u8 *status)
380{
381 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
382 u16 slot_status;
383
384 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
385 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
386}
387
388void pciehp_get_adapter_status(struct slot *slot, u8 *status)
389{
390 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
391 u16 slot_status;
392
393 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
394 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
395}
396
397int pciehp_query_power_fault(struct slot *slot)
398{
399 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
400 u16 slot_status;
401
402 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
403 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
404}
405
406void pciehp_set_attention_status(struct slot *slot, u8 value)
407{
408 struct controller *ctrl = slot->ctrl;
409 u16 slot_cmd;
410
411 if (!ATTN_LED(ctrl))
412 return;
413
414 switch (value) {
415 case 0 : /* turn off */
416 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
417 break;
418 case 1: /* turn on */
419 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
420 break;
421 case 2: /* turn blink */
422 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
423 break;
424 default:
425 return;
426 }
427 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
428 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
429 pcie_write_cmd(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
430}
431
432void pciehp_green_led_on(struct slot *slot)
433{
434 struct controller *ctrl = slot->ctrl;
435
436 if (!PWR_LED(ctrl))
437 return;
438
439 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, PCI_EXP_SLTCTL_PIC);
440 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
441 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
442 PCI_EXP_SLTCTL_PWR_IND_ON);
443}
444
445void pciehp_green_led_off(struct slot *slot)
446{
447 struct controller *ctrl = slot->ctrl;
448
449 if (!PWR_LED(ctrl))
450 return;
451
452 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, PCI_EXP_SLTCTL_PIC);
453 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
454 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
455 PCI_EXP_SLTCTL_PWR_IND_OFF);
456}
457
458void pciehp_green_led_blink(struct slot *slot)
459{
460 struct controller *ctrl = slot->ctrl;
461
462 if (!PWR_LED(ctrl))
463 return;
464
465 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, PCI_EXP_SLTCTL_PIC);
466 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
467 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
468 PCI_EXP_SLTCTL_PWR_IND_BLINK);
469}
470
471int pciehp_power_on_slot(struct slot * slot)
472{
473 struct controller *ctrl = slot->ctrl;
474 struct pci_dev *pdev = ctrl_dev(ctrl);
475 u16 slot_status;
476 int retval;
477
478 /* Clear sticky power-fault bit from previous power failures */
479 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
480 if (slot_status & PCI_EXP_SLTSTA_PFD)
481 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
482 PCI_EXP_SLTSTA_PFD);
483 ctrl->power_fault_detected = 0;
484
485 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
486 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
487 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
488 PCI_EXP_SLTCTL_PWR_ON);
489
490 retval = pciehp_link_enable(ctrl);
491 if (retval)
492 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
493
494 return retval;
495}
496
497void pciehp_power_off_slot(struct slot * slot)
498{
499 struct controller *ctrl = slot->ctrl;
500
501 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
502 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
503 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
504 PCI_EXP_SLTCTL_PWR_OFF);
505}
506
507static irqreturn_t pcie_isr(int irq, void *dev_id)
508{
509 struct controller *ctrl = (struct controller *)dev_id;
510 struct pci_dev *pdev = ctrl_dev(ctrl);
511 struct slot *slot = ctrl->slot;
512 u16 detected, intr_loc;
513
514 /*
515 * In order to guarantee that all interrupt events are
516 * serviced, we need to re-inspect Slot Status register after
517 * clearing what is presumed to be the last pending interrupt.
518 */
519 intr_loc = 0;
520 do {
521 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected);
522
523 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
524 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
525 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
526 detected &= ~intr_loc;
527 intr_loc |= detected;
528 if (!intr_loc)
529 return IRQ_NONE;
530 if (detected)
531 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
532 intr_loc);
533 } while (detected);
534
535 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
536
537 /* Check Command Complete Interrupt Pending */
538 if (intr_loc & PCI_EXP_SLTSTA_CC) {
539 ctrl->cmd_busy = 0;
540 smp_mb();
541 wake_up(&ctrl->queue);
542 }
543
544 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
545 return IRQ_HANDLED;
546
547 /* Check MRL Sensor Changed */
548 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
549 pciehp_handle_switch_change(slot);
550
551 /* Check Attention Button Pressed */
552 if (intr_loc & PCI_EXP_SLTSTA_ABP)
553 pciehp_handle_attention_button(slot);
554
555 /* Check Presence Detect Changed */
556 if (intr_loc & PCI_EXP_SLTSTA_PDC)
557 pciehp_handle_presence_change(slot);
558
559 /* Check Power Fault Detected */
560 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
561 ctrl->power_fault_detected = 1;
562 pciehp_handle_power_fault(slot);
563 }
564
565 if (intr_loc & PCI_EXP_SLTSTA_DLLSC)
566 pciehp_handle_linkstate_change(slot);
567
568 return IRQ_HANDLED;
569}
570
571void pcie_enable_notification(struct controller *ctrl)
572{
573 u16 cmd, mask;
574
575 /*
576 * TBD: Power fault detected software notification support.
577 *
578 * Power fault detected software notification is not enabled
579 * now, because it caused power fault detected interrupt storm
580 * on some machines. On those machines, power fault detected
581 * bit in the slot status register was set again immediately
582 * when it is cleared in the interrupt service routine, and
583 * next power fault detected interrupt was notified again.
584 */
585
586 /*
587 * Always enable link events: thus link-up and link-down shall
588 * always be treated as hotplug and unplug respectively. Enable
589 * presence detect only if Attention Button is not present.
590 */
591 cmd = PCI_EXP_SLTCTL_DLLSCE;
592 if (ATTN_BUTTN(ctrl))
593 cmd |= PCI_EXP_SLTCTL_ABPE;
594 else
595 cmd |= PCI_EXP_SLTCTL_PDCE;
596 if (MRL_SENS(ctrl))
597 cmd |= PCI_EXP_SLTCTL_MRLSCE;
598 if (!pciehp_poll_mode)
599 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
600
601 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
602 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
603 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
604 PCI_EXP_SLTCTL_DLLSCE);
605
606 pcie_write_cmd(ctrl, cmd, mask);
607}
608
609static void pcie_disable_notification(struct controller *ctrl)
610{
611 u16 mask;
612
613 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
614 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
615 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
616 PCI_EXP_SLTCTL_DLLSCE);
617 pcie_write_cmd(ctrl, 0, mask);
618}
619
620/*
621 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
622 * bus reset of the bridge, but at the same time we want to ensure that it is
623 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
624 * disable link state notification and presence detection change notification
625 * momentarily, if we see that they could interfere. Also, clear any spurious
626 * events after.
627 */
628int pciehp_reset_slot(struct slot *slot, int probe)
629{
630 struct controller *ctrl = slot->ctrl;
631 struct pci_dev *pdev = ctrl_dev(ctrl);
632 u16 stat_mask = 0, ctrl_mask = 0;
633
634 if (probe)
635 return 0;
636
637 if (!ATTN_BUTTN(ctrl)) {
638 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
639 stat_mask |= PCI_EXP_SLTSTA_PDC;
640 }
641 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
642 stat_mask |= PCI_EXP_SLTSTA_DLLSC;
643
644 pcie_write_cmd(ctrl, 0, ctrl_mask);
645 if (pciehp_poll_mode)
646 del_timer_sync(&ctrl->poll_timer);
647
648 pci_reset_bridge_secondary_bus(ctrl->pcie->port);
649
650 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
651 pcie_write_cmd(ctrl, ctrl_mask, ctrl_mask);
652 if (pciehp_poll_mode)
653 int_poll_timeout(ctrl->poll_timer.data);
654
655 return 0;
656}
657
658int pcie_init_notification(struct controller *ctrl)
659{
660 if (pciehp_request_irq(ctrl))
661 return -1;
662 pcie_enable_notification(ctrl);
663 ctrl->notification_enabled = 1;
664 return 0;
665}
666
667static void pcie_shutdown_notification(struct controller *ctrl)
668{
669 if (ctrl->notification_enabled) {
670 pcie_disable_notification(ctrl);
671 pciehp_free_irq(ctrl);
672 ctrl->notification_enabled = 0;
673 }
674}
675
676static int pcie_init_slot(struct controller *ctrl)
677{
678 struct slot *slot;
679
680 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
681 if (!slot)
682 return -ENOMEM;
683
684 slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
685 if (!slot->wq)
686 goto abort;
687
688 slot->ctrl = ctrl;
689 mutex_init(&slot->lock);
690 mutex_init(&slot->hotplug_lock);
691 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
692 ctrl->slot = slot;
693 return 0;
694abort:
695 kfree(slot);
696 return -ENOMEM;
697}
698
699static void pcie_cleanup_slot(struct controller *ctrl)
700{
701 struct slot *slot = ctrl->slot;
702 cancel_delayed_work(&slot->work);
703 destroy_workqueue(slot->wq);
704 kfree(slot);
705}
706
707static inline void dbg_ctrl(struct controller *ctrl)
708{
709 int i;
710 u16 reg16;
711 struct pci_dev *pdev = ctrl->pcie->port;
712
713 if (!pciehp_debug)
714 return;
715
716 ctrl_info(ctrl, "Hotplug Controller:\n");
717 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
718 pci_name(pdev), pdev->irq);
719 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
720 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
721 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
722 pdev->subsystem_device);
723 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
724 pdev->subsystem_vendor);
725 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
726 pci_pcie_cap(pdev));
727 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
728 if (!pci_resource_len(pdev, i))
729 continue;
730 ctrl_info(ctrl, " PCI resource [%d] : %pR\n",
731 i, &pdev->resource[i]);
732 }
733 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
734 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
735 ctrl_info(ctrl, " Attention Button : %3s\n",
736 ATTN_BUTTN(ctrl) ? "yes" : "no");
737 ctrl_info(ctrl, " Power Controller : %3s\n",
738 POWER_CTRL(ctrl) ? "yes" : "no");
739 ctrl_info(ctrl, " MRL Sensor : %3s\n",
740 MRL_SENS(ctrl) ? "yes" : "no");
741 ctrl_info(ctrl, " Attention Indicator : %3s\n",
742 ATTN_LED(ctrl) ? "yes" : "no");
743 ctrl_info(ctrl, " Power Indicator : %3s\n",
744 PWR_LED(ctrl) ? "yes" : "no");
745 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
746 HP_SUPR_RM(ctrl) ? "yes" : "no");
747 ctrl_info(ctrl, " EMI Present : %3s\n",
748 EMI(ctrl) ? "yes" : "no");
749 ctrl_info(ctrl, " Command Completed : %3s\n",
750 NO_CMD_CMPL(ctrl) ? "no" : "yes");
751 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
752 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
753 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
754 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
755}
756
757#define FLAG(x,y) (((x) & (y)) ? '+' : '-')
758
759struct controller *pcie_init(struct pcie_device *dev)
760{
761 struct controller *ctrl;
762 u32 slot_cap, link_cap;
763 struct pci_dev *pdev = dev->port;
764
765 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
766 if (!ctrl) {
767 dev_err(&dev->device, "%s: Out of memory\n", __func__);
768 goto abort;
769 }
770 ctrl->pcie = dev;
771 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
772 ctrl->slot_cap = slot_cap;
773 mutex_init(&ctrl->ctrl_lock);
774 init_waitqueue_head(&ctrl->queue);
775 dbg_ctrl(ctrl);
776 /*
777 * Controller doesn't notify of command completion if the "No
778 * Command Completed Support" bit is set in Slot Capability
779 * register or the controller supports none of power
780 * controller, attention led, power led and EMI.
781 */
782 if (NO_CMD_CMPL(ctrl) ||
783 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
784 ctrl->no_cmd_complete = 1;
785
786 /* Check if Data Link Layer Link Active Reporting is implemented */
787 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
788 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
789 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
790 ctrl->link_active_reporting = 1;
791 }
792
793 /* Clear all remaining event bits in Slot Status register */
794 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
795 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
796 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
797 PCI_EXP_SLTSTA_CC);
798
799 /* Disable software notification */
800 pcie_disable_notification(ctrl);
801
802 ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n",
803 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
804 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
805 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
806 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
807 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
808 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
809 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
810 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
811 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
812
813 if (pcie_init_slot(ctrl))
814 goto abort_ctrl;
815
816 return ctrl;
817
818abort_ctrl:
819 kfree(ctrl);
820abort:
821 return NULL;
822}
823
824void pciehp_release_ctrl(struct controller *ctrl)
825{
826 pcie_shutdown_notification(ctrl);
827 pcie_cleanup_slot(ctrl);
828 kfree(ctrl);
829}
1/*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/signal.h>
34#include <linux/jiffies.h>
35#include <linux/timer.h>
36#include <linux/pci.h>
37#include <linux/interrupt.h>
38#include <linux/time.h>
39#include <linux/slab.h>
40
41#include "../pci.h"
42#include "pciehp.h"
43
44static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
45{
46 return ctrl->pcie->port;
47}
48
49static irqreturn_t pcie_isr(int irq, void *dev_id);
50static void start_int_poll_timer(struct controller *ctrl, int sec);
51
52/* This is the interrupt polling timeout function. */
53static void int_poll_timeout(unsigned long data)
54{
55 struct controller *ctrl = (struct controller *)data;
56
57 /* Poll for interrupt events. regs == NULL => polling */
58 pcie_isr(0, ctrl);
59
60 init_timer(&ctrl->poll_timer);
61 if (!pciehp_poll_time)
62 pciehp_poll_time = 2; /* default polling interval is 2 sec */
63
64 start_int_poll_timer(ctrl, pciehp_poll_time);
65}
66
67/* This function starts the interrupt polling timer. */
68static void start_int_poll_timer(struct controller *ctrl, int sec)
69{
70 /* Clamp to sane value */
71 if ((sec <= 0) || (sec > 60))
72 sec = 2;
73
74 ctrl->poll_timer.function = &int_poll_timeout;
75 ctrl->poll_timer.data = (unsigned long)ctrl;
76 ctrl->poll_timer.expires = jiffies + sec * HZ;
77 add_timer(&ctrl->poll_timer);
78}
79
80static inline int pciehp_request_irq(struct controller *ctrl)
81{
82 int retval, irq = ctrl->pcie->irq;
83
84 /* Install interrupt polling timer. Start with 10 sec delay */
85 if (pciehp_poll_mode) {
86 init_timer(&ctrl->poll_timer);
87 start_int_poll_timer(ctrl, 10);
88 return 0;
89 }
90
91 /* Installs the interrupt handler */
92 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
93 if (retval)
94 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
95 irq);
96 return retval;
97}
98
99static inline void pciehp_free_irq(struct controller *ctrl)
100{
101 if (pciehp_poll_mode)
102 del_timer_sync(&ctrl->poll_timer);
103 else
104 free_irq(ctrl->pcie->irq, ctrl);
105}
106
107static int pcie_poll_cmd(struct controller *ctrl, int timeout)
108{
109 struct pci_dev *pdev = ctrl_dev(ctrl);
110 u16 slot_status;
111
112 while (true) {
113 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
114 if (slot_status == (u16) ~0) {
115 ctrl_info(ctrl, "%s: no response from device\n",
116 __func__);
117 return 0;
118 }
119
120 if (slot_status & PCI_EXP_SLTSTA_CC) {
121 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
122 PCI_EXP_SLTSTA_CC);
123 return 1;
124 }
125 if (timeout < 0)
126 break;
127 msleep(10);
128 timeout -= 10;
129 }
130 return 0; /* timeout */
131}
132
133static void pcie_wait_cmd(struct controller *ctrl)
134{
135 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
136 unsigned long duration = msecs_to_jiffies(msecs);
137 unsigned long cmd_timeout = ctrl->cmd_started + duration;
138 unsigned long now, timeout;
139 int rc;
140
141 /*
142 * If the controller does not generate notifications for command
143 * completions, we never need to wait between writes.
144 */
145 if (NO_CMD_CMPL(ctrl))
146 return;
147
148 if (!ctrl->cmd_busy)
149 return;
150
151 /*
152 * Even if the command has already timed out, we want to call
153 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
154 */
155 now = jiffies;
156 if (time_before_eq(cmd_timeout, now))
157 timeout = 1;
158 else
159 timeout = cmd_timeout - now;
160
161 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
162 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
163 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
164 else
165 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
166
167 /*
168 * Controllers with errata like Intel CF118 don't generate
169 * completion notifications unless the power/indicator/interlock
170 * control bits are changed. On such controllers, we'll emit this
171 * timeout message when we wait for completion of commands that
172 * don't change those bits, e.g., commands that merely enable
173 * interrupts.
174 */
175 if (!rc)
176 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
177 ctrl->slot_ctrl,
178 jiffies_to_msecs(jiffies - ctrl->cmd_started));
179}
180
181static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
182 u16 mask, bool wait)
183{
184 struct pci_dev *pdev = ctrl_dev(ctrl);
185 u16 slot_ctrl;
186
187 mutex_lock(&ctrl->ctrl_lock);
188
189 /*
190 * Always wait for any previous command that might still be in progress
191 */
192 pcie_wait_cmd(ctrl);
193
194 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
195 if (slot_ctrl == (u16) ~0) {
196 ctrl_info(ctrl, "%s: no response from device\n", __func__);
197 goto out;
198 }
199
200 slot_ctrl &= ~mask;
201 slot_ctrl |= (cmd & mask);
202 ctrl->cmd_busy = 1;
203 smp_mb();
204 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
205 ctrl->cmd_started = jiffies;
206 ctrl->slot_ctrl = slot_ctrl;
207
208 /*
209 * Optionally wait for the hardware to be ready for a new command,
210 * indicating completion of the above issued command.
211 */
212 if (wait)
213 pcie_wait_cmd(ctrl);
214
215out:
216 mutex_unlock(&ctrl->ctrl_lock);
217}
218
219/**
220 * pcie_write_cmd - Issue controller command
221 * @ctrl: controller to which the command is issued
222 * @cmd: command value written to slot control register
223 * @mask: bitmask of slot control register to be modified
224 */
225static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
226{
227 pcie_do_write_cmd(ctrl, cmd, mask, true);
228}
229
230/* Same as above without waiting for the hardware to latch */
231static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
232{
233 pcie_do_write_cmd(ctrl, cmd, mask, false);
234}
235
236bool pciehp_check_link_active(struct controller *ctrl)
237{
238 struct pci_dev *pdev = ctrl_dev(ctrl);
239 u16 lnk_status;
240 bool ret;
241
242 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
243 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
244
245 if (ret)
246 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
247
248 return ret;
249}
250
251static void __pcie_wait_link_active(struct controller *ctrl, bool active)
252{
253 int timeout = 1000;
254
255 if (pciehp_check_link_active(ctrl) == active)
256 return;
257 while (timeout > 0) {
258 msleep(10);
259 timeout -= 10;
260 if (pciehp_check_link_active(ctrl) == active)
261 return;
262 }
263 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
264 active ? "set" : "cleared");
265}
266
267static void pcie_wait_link_active(struct controller *ctrl)
268{
269 __pcie_wait_link_active(ctrl, true);
270}
271
272static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
273{
274 u32 l;
275 int count = 0;
276 int delay = 1000, step = 20;
277 bool found = false;
278
279 do {
280 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
281 count++;
282
283 if (found)
284 break;
285
286 msleep(step);
287 delay -= step;
288 } while (delay > 0);
289
290 if (count > 1 && pciehp_debug)
291 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
292 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
293 PCI_FUNC(devfn), count, step, l);
294
295 return found;
296}
297
298int pciehp_check_link_status(struct controller *ctrl)
299{
300 struct pci_dev *pdev = ctrl_dev(ctrl);
301 bool found;
302 u16 lnk_status;
303
304 /*
305 * Data Link Layer Link Active Reporting must be capable for
306 * hot-plug capable downstream port. But old controller might
307 * not implement it. In this case, we wait for 1000 ms.
308 */
309 if (ctrl->link_active_reporting)
310 pcie_wait_link_active(ctrl);
311 else
312 msleep(1000);
313
314 /* wait 100ms before read pci conf, and try in 1s */
315 msleep(100);
316 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
317 PCI_DEVFN(0, 0));
318
319 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
320 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
321 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
322 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
323 ctrl_err(ctrl, "link training error: status %#06x\n",
324 lnk_status);
325 return -1;
326 }
327
328 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
329
330 if (!found)
331 return -1;
332
333 return 0;
334}
335
336static int __pciehp_link_set(struct controller *ctrl, bool enable)
337{
338 struct pci_dev *pdev = ctrl_dev(ctrl);
339 u16 lnk_ctrl;
340
341 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
342
343 if (enable)
344 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
345 else
346 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
347
348 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
349 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
350 return 0;
351}
352
353static int pciehp_link_enable(struct controller *ctrl)
354{
355 return __pciehp_link_set(ctrl, true);
356}
357
358void pciehp_get_attention_status(struct slot *slot, u8 *status)
359{
360 struct controller *ctrl = slot->ctrl;
361 struct pci_dev *pdev = ctrl_dev(ctrl);
362 u16 slot_ctrl;
363
364 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
365 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
366 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
367
368 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
369 case PCI_EXP_SLTCTL_ATTN_IND_ON:
370 *status = 1; /* On */
371 break;
372 case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
373 *status = 2; /* Blink */
374 break;
375 case PCI_EXP_SLTCTL_ATTN_IND_OFF:
376 *status = 0; /* Off */
377 break;
378 default:
379 *status = 0xFF;
380 break;
381 }
382}
383
384void pciehp_get_power_status(struct slot *slot, u8 *status)
385{
386 struct controller *ctrl = slot->ctrl;
387 struct pci_dev *pdev = ctrl_dev(ctrl);
388 u16 slot_ctrl;
389
390 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
391 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
392 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
393
394 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
395 case PCI_EXP_SLTCTL_PWR_ON:
396 *status = 1; /* On */
397 break;
398 case PCI_EXP_SLTCTL_PWR_OFF:
399 *status = 0; /* Off */
400 break;
401 default:
402 *status = 0xFF;
403 break;
404 }
405}
406
407void pciehp_get_latch_status(struct slot *slot, u8 *status)
408{
409 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
410 u16 slot_status;
411
412 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
413 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
414}
415
416void pciehp_get_adapter_status(struct slot *slot, u8 *status)
417{
418 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
419 u16 slot_status;
420
421 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
422 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
423}
424
425int pciehp_query_power_fault(struct slot *slot)
426{
427 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
428 u16 slot_status;
429
430 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
431 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
432}
433
434void pciehp_set_attention_status(struct slot *slot, u8 value)
435{
436 struct controller *ctrl = slot->ctrl;
437 u16 slot_cmd;
438
439 if (!ATTN_LED(ctrl))
440 return;
441
442 switch (value) {
443 case 0: /* turn off */
444 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
445 break;
446 case 1: /* turn on */
447 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
448 break;
449 case 2: /* turn blink */
450 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
451 break;
452 default:
453 return;
454 }
455 pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
456 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
457 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
458}
459
460void pciehp_green_led_on(struct slot *slot)
461{
462 struct controller *ctrl = slot->ctrl;
463
464 if (!PWR_LED(ctrl))
465 return;
466
467 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
468 PCI_EXP_SLTCTL_PIC);
469 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
470 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
471 PCI_EXP_SLTCTL_PWR_IND_ON);
472}
473
474void pciehp_green_led_off(struct slot *slot)
475{
476 struct controller *ctrl = slot->ctrl;
477
478 if (!PWR_LED(ctrl))
479 return;
480
481 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
482 PCI_EXP_SLTCTL_PIC);
483 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
484 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
485 PCI_EXP_SLTCTL_PWR_IND_OFF);
486}
487
488void pciehp_green_led_blink(struct slot *slot)
489{
490 struct controller *ctrl = slot->ctrl;
491
492 if (!PWR_LED(ctrl))
493 return;
494
495 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
496 PCI_EXP_SLTCTL_PIC);
497 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
498 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
499 PCI_EXP_SLTCTL_PWR_IND_BLINK);
500}
501
502int pciehp_power_on_slot(struct slot *slot)
503{
504 struct controller *ctrl = slot->ctrl;
505 struct pci_dev *pdev = ctrl_dev(ctrl);
506 u16 slot_status;
507 int retval;
508
509 /* Clear sticky power-fault bit from previous power failures */
510 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
511 if (slot_status & PCI_EXP_SLTSTA_PFD)
512 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
513 PCI_EXP_SLTSTA_PFD);
514 ctrl->power_fault_detected = 0;
515
516 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
517 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
518 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
519 PCI_EXP_SLTCTL_PWR_ON);
520
521 retval = pciehp_link_enable(ctrl);
522 if (retval)
523 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
524
525 return retval;
526}
527
528void pciehp_power_off_slot(struct slot *slot)
529{
530 struct controller *ctrl = slot->ctrl;
531
532 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
533 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
534 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
535 PCI_EXP_SLTCTL_PWR_OFF);
536}
537
538static irqreturn_t pcie_isr(int irq, void *dev_id)
539{
540 struct controller *ctrl = (struct controller *)dev_id;
541 struct pci_dev *pdev = ctrl_dev(ctrl);
542 struct pci_bus *subordinate = pdev->subordinate;
543 struct pci_dev *dev;
544 struct slot *slot = ctrl->slot;
545 u16 detected, intr_loc;
546 u8 present;
547 bool link;
548
549 /*
550 * In order to guarantee that all interrupt events are
551 * serviced, we need to re-inspect Slot Status register after
552 * clearing what is presumed to be the last pending interrupt.
553 */
554 intr_loc = 0;
555 do {
556 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected);
557 if (detected == (u16) ~0) {
558 ctrl_info(ctrl, "%s: no response from device\n",
559 __func__);
560 return IRQ_HANDLED;
561 }
562
563 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
564 PCI_EXP_SLTSTA_PDC |
565 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
566 detected &= ~intr_loc;
567 intr_loc |= detected;
568 if (!intr_loc)
569 return IRQ_NONE;
570 if (detected)
571 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
572 intr_loc);
573 } while (detected);
574
575 ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", intr_loc);
576
577 /* Check Command Complete Interrupt Pending */
578 if (intr_loc & PCI_EXP_SLTSTA_CC) {
579 ctrl->cmd_busy = 0;
580 smp_mb();
581 wake_up(&ctrl->queue);
582 }
583
584 if (subordinate) {
585 list_for_each_entry(dev, &subordinate->devices, bus_list) {
586 if (dev->ignore_hotplug) {
587 ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n",
588 intr_loc, pci_name(dev));
589 return IRQ_HANDLED;
590 }
591 }
592 }
593
594 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
595 return IRQ_HANDLED;
596
597 /* Check Attention Button Pressed */
598 if (intr_loc & PCI_EXP_SLTSTA_ABP) {
599 ctrl_info(ctrl, "Button pressed on Slot(%s)\n",
600 slot_name(slot));
601 pciehp_queue_interrupt_event(slot, INT_BUTTON_PRESS);
602 }
603
604 /* Check Presence Detect Changed */
605 if (intr_loc & PCI_EXP_SLTSTA_PDC) {
606 pciehp_get_adapter_status(slot, &present);
607 ctrl_info(ctrl, "Card %spresent on Slot(%s)\n",
608 present ? "" : "not ", slot_name(slot));
609 pciehp_queue_interrupt_event(slot, present ? INT_PRESENCE_ON :
610 INT_PRESENCE_OFF);
611 }
612
613 /* Check Power Fault Detected */
614 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
615 ctrl->power_fault_detected = 1;
616 ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(slot));
617 pciehp_queue_interrupt_event(slot, INT_POWER_FAULT);
618 }
619
620 if (intr_loc & PCI_EXP_SLTSTA_DLLSC) {
621 link = pciehp_check_link_active(ctrl);
622 ctrl_info(ctrl, "slot(%s): Link %s event\n",
623 slot_name(slot), link ? "Up" : "Down");
624 pciehp_queue_interrupt_event(slot, link ? INT_LINK_UP :
625 INT_LINK_DOWN);
626 }
627
628 return IRQ_HANDLED;
629}
630
631void pcie_enable_notification(struct controller *ctrl)
632{
633 u16 cmd, mask;
634
635 /*
636 * TBD: Power fault detected software notification support.
637 *
638 * Power fault detected software notification is not enabled
639 * now, because it caused power fault detected interrupt storm
640 * on some machines. On those machines, power fault detected
641 * bit in the slot status register was set again immediately
642 * when it is cleared in the interrupt service routine, and
643 * next power fault detected interrupt was notified again.
644 */
645
646 /*
647 * Always enable link events: thus link-up and link-down shall
648 * always be treated as hotplug and unplug respectively. Enable
649 * presence detect only if Attention Button is not present.
650 */
651 cmd = PCI_EXP_SLTCTL_DLLSCE;
652 if (ATTN_BUTTN(ctrl))
653 cmd |= PCI_EXP_SLTCTL_ABPE;
654 else
655 cmd |= PCI_EXP_SLTCTL_PDCE;
656 if (!pciehp_poll_mode)
657 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
658
659 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
660 PCI_EXP_SLTCTL_PFDE |
661 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
662 PCI_EXP_SLTCTL_DLLSCE);
663
664 pcie_write_cmd_nowait(ctrl, cmd, mask);
665 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
666 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
667}
668
669static void pcie_disable_notification(struct controller *ctrl)
670{
671 u16 mask;
672
673 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
674 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
675 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
676 PCI_EXP_SLTCTL_DLLSCE);
677 pcie_write_cmd(ctrl, 0, mask);
678 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
679 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
680}
681
682/*
683 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
684 * bus reset of the bridge, but at the same time we want to ensure that it is
685 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
686 * disable link state notification and presence detection change notification
687 * momentarily, if we see that they could interfere. Also, clear any spurious
688 * events after.
689 */
690int pciehp_reset_slot(struct slot *slot, int probe)
691{
692 struct controller *ctrl = slot->ctrl;
693 struct pci_dev *pdev = ctrl_dev(ctrl);
694 u16 stat_mask = 0, ctrl_mask = 0;
695
696 if (probe)
697 return 0;
698
699 if (!ATTN_BUTTN(ctrl)) {
700 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
701 stat_mask |= PCI_EXP_SLTSTA_PDC;
702 }
703 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
704 stat_mask |= PCI_EXP_SLTSTA_DLLSC;
705
706 pcie_write_cmd(ctrl, 0, ctrl_mask);
707 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
708 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
709 if (pciehp_poll_mode)
710 del_timer_sync(&ctrl->poll_timer);
711
712 pci_reset_bridge_secondary_bus(ctrl->pcie->port);
713
714 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
715 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
716 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
717 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
718 if (pciehp_poll_mode)
719 int_poll_timeout(ctrl->poll_timer.data);
720
721 return 0;
722}
723
724int pcie_init_notification(struct controller *ctrl)
725{
726 if (pciehp_request_irq(ctrl))
727 return -1;
728 pcie_enable_notification(ctrl);
729 ctrl->notification_enabled = 1;
730 return 0;
731}
732
733static void pcie_shutdown_notification(struct controller *ctrl)
734{
735 if (ctrl->notification_enabled) {
736 pcie_disable_notification(ctrl);
737 pciehp_free_irq(ctrl);
738 ctrl->notification_enabled = 0;
739 }
740}
741
742static int pcie_init_slot(struct controller *ctrl)
743{
744 struct slot *slot;
745
746 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
747 if (!slot)
748 return -ENOMEM;
749
750 slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
751 if (!slot->wq)
752 goto abort;
753
754 slot->ctrl = ctrl;
755 mutex_init(&slot->lock);
756 mutex_init(&slot->hotplug_lock);
757 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
758 ctrl->slot = slot;
759 return 0;
760abort:
761 kfree(slot);
762 return -ENOMEM;
763}
764
765static void pcie_cleanup_slot(struct controller *ctrl)
766{
767 struct slot *slot = ctrl->slot;
768 cancel_delayed_work(&slot->work);
769 destroy_workqueue(slot->wq);
770 kfree(slot);
771}
772
773static inline void dbg_ctrl(struct controller *ctrl)
774{
775 struct pci_dev *pdev = ctrl->pcie->port;
776 u16 reg16;
777
778 if (!pciehp_debug)
779 return;
780
781 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
782 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
783 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
784 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
785 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
786}
787
788#define FLAG(x, y) (((x) & (y)) ? '+' : '-')
789
790struct controller *pcie_init(struct pcie_device *dev)
791{
792 struct controller *ctrl;
793 u32 slot_cap, link_cap;
794 struct pci_dev *pdev = dev->port;
795
796 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
797 if (!ctrl) {
798 dev_err(&dev->device, "%s: Out of memory\n", __func__);
799 goto abort;
800 }
801 ctrl->pcie = dev;
802 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
803 ctrl->slot_cap = slot_cap;
804 mutex_init(&ctrl->ctrl_lock);
805 init_waitqueue_head(&ctrl->queue);
806 dbg_ctrl(ctrl);
807
808 /* Check if Data Link Layer Link Active Reporting is implemented */
809 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
810 if (link_cap & PCI_EXP_LNKCAP_DLLLARC)
811 ctrl->link_active_reporting = 1;
812
813 /* Clear all remaining event bits in Slot Status register */
814 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
815 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
816 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
817 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
818
819 ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c\n",
820 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
821 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
822 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
823 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
824 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
825 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
826 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
827 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
828 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
829 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
830 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
831
832 if (pcie_init_slot(ctrl))
833 goto abort_ctrl;
834
835 return ctrl;
836
837abort_ctrl:
838 kfree(ctrl);
839abort:
840 return NULL;
841}
842
843void pciehp_release_ctrl(struct controller *ctrl)
844{
845 pcie_shutdown_notification(ctrl);
846 pcie_cleanup_slot(ctrl);
847 kfree(ctrl);
848}