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1/*
2 * FarSync WAN driver for Linux (2.6.x kernel version)
3 *
4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
5 *
6 * Copyright (C) 2001-2004 FarSite Communications Ltd.
7 * www.farsite.co.uk
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 *
14 * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk>
15 * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk>
16 */
17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/version.h>
23#include <linux/pci.h>
24#include <linux/sched.h>
25#include <linux/slab.h>
26#include <linux/ioport.h>
27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <linux/if.h>
30#include <linux/hdlc.h>
31#include <asm/io.h>
32#include <asm/uaccess.h>
33
34#include "farsync.h"
35
36/*
37 * Module info
38 */
39MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>");
40MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
41MODULE_LICENSE("GPL");
42
43/* Driver configuration and global parameters
44 * ==========================================
45 */
46
47/* Number of ports (per card) and cards supported
48 */
49#define FST_MAX_PORTS 4
50#define FST_MAX_CARDS 32
51
52/* Default parameters for the link
53 */
54#define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is
55 * useful */
56#define FST_TXQ_DEPTH 16 /* This one is for the buffering
57 * of frames on the way down to the card
58 * so that we can keep the card busy
59 * and maximise throughput
60 */
61#define FST_HIGH_WATER_MARK 12 /* Point at which we flow control
62 * network layer */
63#define FST_LOW_WATER_MARK 8 /* Point at which we remove flow
64 * control from network layer */
65#define FST_MAX_MTU 8000 /* Huge but possible */
66#define FST_DEF_MTU 1500 /* Common sane value */
67
68#define FST_TX_TIMEOUT (2*HZ)
69
70#ifdef ARPHRD_RAWHDLC
71#define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */
72#else
73#define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */
74#endif
75
76/*
77 * Modules parameters and associated variables
78 */
79static int fst_txq_low = FST_LOW_WATER_MARK;
80static int fst_txq_high = FST_HIGH_WATER_MARK;
81static int fst_max_reads = 7;
82static int fst_excluded_cards = 0;
83static int fst_excluded_list[FST_MAX_CARDS];
84
85module_param(fst_txq_low, int, 0);
86module_param(fst_txq_high, int, 0);
87module_param(fst_max_reads, int, 0);
88module_param(fst_excluded_cards, int, 0);
89module_param_array(fst_excluded_list, int, NULL, 0);
90
91/* Card shared memory layout
92 * =========================
93 */
94#pragma pack(1)
95
96/* This information is derived in part from the FarSite FarSync Smc.h
97 * file. Unfortunately various name clashes and the non-portability of the
98 * bit field declarations in that file have meant that I have chosen to
99 * recreate the information here.
100 *
101 * The SMC (Shared Memory Configuration) has a version number that is
102 * incremented every time there is a significant change. This number can
103 * be used to check that we have not got out of step with the firmware
104 * contained in the .CDE files.
105 */
106#define SMC_VERSION 24
107
108#define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */
109
110#define SMC_BASE 0x00002000L /* Base offset of the shared memory window main
111 * configuration structure */
112#define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA
113 * buffers */
114
115#define LEN_TX_BUFFER 8192 /* Size of packet buffers */
116#define LEN_RX_BUFFER 8192
117
118#define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */
119#define LEN_SMALL_RX_BUFFER 256
120
121#define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */
122#define NUM_RX_BUFFER 8
123
124/* Interrupt retry time in milliseconds */
125#define INT_RETRY_TIME 2
126
127/* The Am186CH/CC processors support a SmartDMA mode using circular pools
128 * of buffer descriptors. The structure is almost identical to that used
129 * in the LANCE Ethernet controllers. Details available as PDF from the
130 * AMD web site: http://www.amd.com/products/epd/processors/\
131 * 2.16bitcont/3.am186cxfa/a21914/21914.pdf
132 */
133struct txdesc { /* Transmit descriptor */
134 volatile u16 ladr; /* Low order address of packet. This is a
135 * linear address in the Am186 memory space
136 */
137 volatile u8 hadr; /* High order address. Low 4 bits only, high 4
138 * bits must be zero
139 */
140 volatile u8 bits; /* Status and config */
141 volatile u16 bcnt; /* 2s complement of packet size in low 15 bits.
142 * Transmit terminal count interrupt enable in
143 * top bit.
144 */
145 u16 unused; /* Not used in Tx */
146};
147
148struct rxdesc { /* Receive descriptor */
149 volatile u16 ladr; /* Low order address of packet */
150 volatile u8 hadr; /* High order address */
151 volatile u8 bits; /* Status and config */
152 volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits.
153 * Receive terminal count interrupt enable in
154 * top bit.
155 */
156 volatile u16 mcnt; /* Message byte count (15 bits) */
157};
158
159/* Convert a length into the 15 bit 2's complement */
160/* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */
161/* Since we need to set the high bit to enable the completion interrupt this
162 * can be made a lot simpler
163 */
164#define cnv_bcnt(len) (-(len))
165
166/* Status and config bits for the above */
167#define DMA_OWN 0x80 /* SmartDMA owns the descriptor */
168#define TX_STP 0x02 /* Tx: start of packet */
169#define TX_ENP 0x01 /* Tx: end of packet */
170#define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */
171#define RX_FRAM 0x20 /* Rx: framing error */
172#define RX_OFLO 0x10 /* Rx: overflow error */
173#define RX_CRC 0x08 /* Rx: CRC error */
174#define RX_HBUF 0x04 /* Rx: buffer error */
175#define RX_STP 0x02 /* Rx: start of packet */
176#define RX_ENP 0x01 /* Rx: end of packet */
177
178/* Interrupts from the card are caused by various events which are presented
179 * in a circular buffer as several events may be processed on one physical int
180 */
181#define MAX_CIRBUFF 32
182
183struct cirbuff {
184 u8 rdindex; /* read, then increment and wrap */
185 u8 wrindex; /* write, then increment and wrap */
186 u8 evntbuff[MAX_CIRBUFF];
187};
188
189/* Interrupt event codes.
190 * Where appropriate the two low order bits indicate the port number
191 */
192#define CTLA_CHG 0x18 /* Control signal changed */
193#define CTLB_CHG 0x19
194#define CTLC_CHG 0x1A
195#define CTLD_CHG 0x1B
196
197#define INIT_CPLT 0x20 /* Initialisation complete */
198#define INIT_FAIL 0x21 /* Initialisation failed */
199
200#define ABTA_SENT 0x24 /* Abort sent */
201#define ABTB_SENT 0x25
202#define ABTC_SENT 0x26
203#define ABTD_SENT 0x27
204
205#define TXA_UNDF 0x28 /* Transmission underflow */
206#define TXB_UNDF 0x29
207#define TXC_UNDF 0x2A
208#define TXD_UNDF 0x2B
209
210#define F56_INT 0x2C
211#define M32_INT 0x2D
212
213#define TE1_ALMA 0x30
214
215/* Port physical configuration. See farsync.h for field values */
216struct port_cfg {
217 u16 lineInterface; /* Physical interface type */
218 u8 x25op; /* Unused at present */
219 u8 internalClock; /* 1 => internal clock, 0 => external */
220 u8 transparentMode; /* 1 => on, 0 => off */
221 u8 invertClock; /* 0 => normal, 1 => inverted */
222 u8 padBytes[6]; /* Padding */
223 u32 lineSpeed; /* Speed in bps */
224};
225
226/* TE1 port physical configuration */
227struct su_config {
228 u32 dataRate;
229 u8 clocking;
230 u8 framing;
231 u8 structure;
232 u8 interface;
233 u8 coding;
234 u8 lineBuildOut;
235 u8 equalizer;
236 u8 transparentMode;
237 u8 loopMode;
238 u8 range;
239 u8 txBufferMode;
240 u8 rxBufferMode;
241 u8 startingSlot;
242 u8 losThreshold;
243 u8 enableIdleCode;
244 u8 idleCode;
245 u8 spare[44];
246};
247
248/* TE1 Status */
249struct su_status {
250 u32 receiveBufferDelay;
251 u32 framingErrorCount;
252 u32 codeViolationCount;
253 u32 crcErrorCount;
254 u32 lineAttenuation;
255 u8 portStarted;
256 u8 lossOfSignal;
257 u8 receiveRemoteAlarm;
258 u8 alarmIndicationSignal;
259 u8 spare[40];
260};
261
262/* Finally sling all the above together into the shared memory structure.
263 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been
264 * evolving under NT for some time so I guess we're stuck with it.
265 * The structure starts at offset SMC_BASE.
266 * See farsync.h for some field values.
267 */
268struct fst_shared {
269 /* DMA descriptor rings */
270 struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER];
271 struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER];
272
273 /* Obsolete small buffers */
274 u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER];
275 u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER];
276
277 u8 taskStatus; /* 0x00 => initialising, 0x01 => running,
278 * 0xFF => halted
279 */
280
281 u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt,
282 * set to 0xEE by host to acknowledge interrupt
283 */
284
285 u16 smcVersion; /* Must match SMC_VERSION */
286
287 u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major
288 * version, RR = revision and BB = build
289 */
290
291 u16 txa_done; /* Obsolete completion flags */
292 u16 rxa_done;
293 u16 txb_done;
294 u16 rxb_done;
295 u16 txc_done;
296 u16 rxc_done;
297 u16 txd_done;
298 u16 rxd_done;
299
300 u16 mailbox[4]; /* Diagnostics mailbox. Not used */
301
302 struct cirbuff interruptEvent; /* interrupt causes */
303
304 u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */
305 u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */
306
307 struct port_cfg portConfig[FST_MAX_PORTS];
308
309 u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */
310
311 u16 cableStatus; /* lsb: 0=> present, 1=> absent */
312
313 u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */
314 u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */
315
316 u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */
317 u16 cardMailbox[4]; /* Not used */
318
319 /* Number of times the card thinks the host has
320 * missed an interrupt by not acknowledging
321 * within 2mS (I guess NT has problems)
322 */
323 u32 interruptRetryCount;
324
325 /* Driver private data used as an ID. We'll not
326 * use this as I'd rather keep such things
327 * in main memory rather than on the PCI bus
328 */
329 u32 portHandle[FST_MAX_PORTS];
330
331 /* Count of Tx underflows for stats */
332 u32 transmitBufferUnderflow[FST_MAX_PORTS];
333
334 /* Debounced V.24 control input status */
335 u32 v24DebouncedSts[FST_MAX_PORTS];
336
337 /* Adapter debounce timers. Don't touch */
338 u32 ctsTimer[FST_MAX_PORTS];
339 u32 ctsTimerRun[FST_MAX_PORTS];
340 u32 dcdTimer[FST_MAX_PORTS];
341 u32 dcdTimerRun[FST_MAX_PORTS];
342
343 u32 numberOfPorts; /* Number of ports detected at startup */
344
345 u16 _reserved[64];
346
347 u16 cardMode; /* Bit-mask to enable features:
348 * Bit 0: 1 enables LED identify mode
349 */
350
351 u16 portScheduleOffset;
352
353 struct su_config suConfig; /* TE1 Bits */
354 struct su_status suStatus;
355
356 u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of
357 * the structure and marks the end of shared
358 * memory. Adapter code initializes it as
359 * END_SIG.
360 */
361};
362
363/* endOfSmcSignature value */
364#define END_SIG 0x12345678
365
366/* Mailbox values. (portMailbox) */
367#define NOP 0 /* No operation */
368#define ACK 1 /* Positive acknowledgement to PC driver */
369#define NAK 2 /* Negative acknowledgement to PC driver */
370#define STARTPORT 3 /* Start an HDLC port */
371#define STOPPORT 4 /* Stop an HDLC port */
372#define ABORTTX 5 /* Abort the transmitter for a port */
373#define SETV24O 6 /* Set V24 outputs */
374
375/* PLX Chip Register Offsets */
376#define CNTRL_9052 0x50 /* Control Register */
377#define CNTRL_9054 0x6c /* Control Register */
378
379#define INTCSR_9052 0x4c /* Interrupt control/status register */
380#define INTCSR_9054 0x68 /* Interrupt control/status register */
381
382/* 9054 DMA Registers */
383/*
384 * Note that we will be using DMA Channel 0 for copying rx data
385 * and Channel 1 for copying tx data
386 */
387#define DMAMODE0 0x80
388#define DMAPADR0 0x84
389#define DMALADR0 0x88
390#define DMASIZ0 0x8c
391#define DMADPR0 0x90
392#define DMAMODE1 0x94
393#define DMAPADR1 0x98
394#define DMALADR1 0x9c
395#define DMASIZ1 0xa0
396#define DMADPR1 0xa4
397#define DMACSR0 0xa8
398#define DMACSR1 0xa9
399#define DMAARB 0xac
400#define DMATHR 0xb0
401#define DMADAC0 0xb4
402#define DMADAC1 0xb8
403#define DMAMARBR 0xac
404
405#define FST_MIN_DMA_LEN 64
406#define FST_RX_DMA_INT 0x01
407#define FST_TX_DMA_INT 0x02
408#define FST_CARD_INT 0x04
409
410/* Larger buffers are positioned in memory at offset BFM_BASE */
411struct buf_window {
412 u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER];
413 u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER];
414};
415
416/* Calculate offset of a buffer object within the shared memory window */
417#define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X))
418
419#pragma pack()
420
421/* Device driver private information
422 * =================================
423 */
424/* Per port (line or channel) information
425 */
426struct fst_port_info {
427 struct net_device *dev; /* Device struct - must be first */
428 struct fst_card_info *card; /* Card we're associated with */
429 int index; /* Port index on the card */
430 int hwif; /* Line hardware (lineInterface copy) */
431 int run; /* Port is running */
432 int mode; /* Normal or FarSync raw */
433 int rxpos; /* Next Rx buffer to use */
434 int txpos; /* Next Tx buffer to use */
435 int txipos; /* Next Tx buffer to check for free */
436 int start; /* Indication of start/stop to network */
437 /*
438 * A sixteen entry transmit queue
439 */
440 int txqs; /* index to get next buffer to tx */
441 int txqe; /* index to queue next packet */
442 struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */
443 int rxqdepth;
444};
445
446/* Per card information
447 */
448struct fst_card_info {
449 char __iomem *mem; /* Card memory mapped to kernel space */
450 char __iomem *ctlmem; /* Control memory for PCI cards */
451 unsigned int phys_mem; /* Physical memory window address */
452 unsigned int phys_ctlmem; /* Physical control memory address */
453 unsigned int irq; /* Interrupt request line number */
454 unsigned int nports; /* Number of serial ports */
455 unsigned int type; /* Type index of card */
456 unsigned int state; /* State of card */
457 spinlock_t card_lock; /* Lock for SMP access */
458 unsigned short pci_conf; /* PCI card config in I/O space */
459 /* Per port info */
460 struct fst_port_info ports[FST_MAX_PORTS];
461 struct pci_dev *device; /* Information about the pci device */
462 int card_no; /* Inst of the card on the system */
463 int family; /* TxP or TxU */
464 int dmarx_in_progress;
465 int dmatx_in_progress;
466 unsigned long int_count;
467 unsigned long int_time_ave;
468 void *rx_dma_handle_host;
469 dma_addr_t rx_dma_handle_card;
470 void *tx_dma_handle_host;
471 dma_addr_t tx_dma_handle_card;
472 struct sk_buff *dma_skb_rx;
473 struct fst_port_info *dma_port_rx;
474 struct fst_port_info *dma_port_tx;
475 int dma_len_rx;
476 int dma_len_tx;
477 int dma_txpos;
478 int dma_rxpos;
479};
480
481/* Convert an HDLC device pointer into a port info pointer and similar */
482#define dev_to_port(D) (dev_to_hdlc(D)->priv)
483#define port_to_dev(P) ((P)->dev)
484
485
486/*
487 * Shared memory window access macros
488 *
489 * We have a nice memory based structure above, which could be directly
490 * mapped on i386 but might not work on other architectures unless we use
491 * the readb,w,l and writeb,w,l macros. Unfortunately these macros take
492 * physical offsets so we have to convert. The only saving grace is that
493 * this should all collapse back to a simple indirection eventually.
494 */
495#define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X))
496
497#define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E))
498#define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E))
499#define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E))
500
501#define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E))
502#define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E))
503#define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E))
504
505/*
506 * Debug support
507 */
508#if FST_DEBUG
509
510static int fst_debug_mask = { FST_DEBUG };
511
512/* Most common debug activity is to print something if the corresponding bit
513 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to
514 * support variable numbers of macro parameters. The inverted if prevents us
515 * eating someone else's else clause.
516 */
517#define dbg(F, fmt, args...) \
518do { \
519 if (fst_debug_mask & (F)) \
520 printk(KERN_DEBUG pr_fmt(fmt), ##args); \
521} while (0)
522#else
523#define dbg(F, fmt, args...) \
524do { \
525 if (0) \
526 printk(KERN_DEBUG pr_fmt(fmt), ##args); \
527} while (0)
528#endif
529
530/*
531 * PCI ID lookup table
532 */
533static DEFINE_PCI_DEVICE_TABLE(fst_pci_dev_id) = {
534 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID,
535 PCI_ANY_ID, 0, 0, FST_TYPE_T2P},
536
537 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID,
538 PCI_ANY_ID, 0, 0, FST_TYPE_T4P},
539
540 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID,
541 PCI_ANY_ID, 0, 0, FST_TYPE_T1U},
542
543 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID,
544 PCI_ANY_ID, 0, 0, FST_TYPE_T2U},
545
546 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID,
547 PCI_ANY_ID, 0, 0, FST_TYPE_T4U},
548
549 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID,
550 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
551
552 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID,
553 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
554 {0,} /* End */
555};
556
557MODULE_DEVICE_TABLE(pci, fst_pci_dev_id);
558
559/*
560 * Device Driver Work Queues
561 *
562 * So that we don't spend too much time processing events in the
563 * Interrupt Service routine, we will declare a work queue per Card
564 * and make the ISR schedule a task in the queue for later execution.
565 * In the 2.4 Kernel we used to use the immediate queue for BH's
566 * Now that they are gone, tasklets seem to be much better than work
567 * queues.
568 */
569
570static void do_bottom_half_tx(struct fst_card_info *card);
571static void do_bottom_half_rx(struct fst_card_info *card);
572static void fst_process_tx_work_q(unsigned long work_q);
573static void fst_process_int_work_q(unsigned long work_q);
574
575static DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q, 0);
576static DECLARE_TASKLET(fst_int_task, fst_process_int_work_q, 0);
577
578static struct fst_card_info *fst_card_array[FST_MAX_CARDS];
579static spinlock_t fst_work_q_lock;
580static u64 fst_work_txq;
581static u64 fst_work_intq;
582
583static void
584fst_q_work_item(u64 * queue, int card_index)
585{
586 unsigned long flags;
587 u64 mask;
588
589 /*
590 * Grab the queue exclusively
591 */
592 spin_lock_irqsave(&fst_work_q_lock, flags);
593
594 /*
595 * Making an entry in the queue is simply a matter of setting
596 * a bit for the card indicating that there is work to do in the
597 * bottom half for the card. Note the limitation of 64 cards.
598 * That ought to be enough
599 */
600 mask = (u64)1 << card_index;
601 *queue |= mask;
602 spin_unlock_irqrestore(&fst_work_q_lock, flags);
603}
604
605static void
606fst_process_tx_work_q(unsigned long /*void **/work_q)
607{
608 unsigned long flags;
609 u64 work_txq;
610 int i;
611
612 /*
613 * Grab the queue exclusively
614 */
615 dbg(DBG_TX, "fst_process_tx_work_q\n");
616 spin_lock_irqsave(&fst_work_q_lock, flags);
617 work_txq = fst_work_txq;
618 fst_work_txq = 0;
619 spin_unlock_irqrestore(&fst_work_q_lock, flags);
620
621 /*
622 * Call the bottom half for each card with work waiting
623 */
624 for (i = 0; i < FST_MAX_CARDS; i++) {
625 if (work_txq & 0x01) {
626 if (fst_card_array[i] != NULL) {
627 dbg(DBG_TX, "Calling tx bh for card %d\n", i);
628 do_bottom_half_tx(fst_card_array[i]);
629 }
630 }
631 work_txq = work_txq >> 1;
632 }
633}
634
635static void
636fst_process_int_work_q(unsigned long /*void **/work_q)
637{
638 unsigned long flags;
639 u64 work_intq;
640 int i;
641
642 /*
643 * Grab the queue exclusively
644 */
645 dbg(DBG_INTR, "fst_process_int_work_q\n");
646 spin_lock_irqsave(&fst_work_q_lock, flags);
647 work_intq = fst_work_intq;
648 fst_work_intq = 0;
649 spin_unlock_irqrestore(&fst_work_q_lock, flags);
650
651 /*
652 * Call the bottom half for each card with work waiting
653 */
654 for (i = 0; i < FST_MAX_CARDS; i++) {
655 if (work_intq & 0x01) {
656 if (fst_card_array[i] != NULL) {
657 dbg(DBG_INTR,
658 "Calling rx & tx bh for card %d\n", i);
659 do_bottom_half_rx(fst_card_array[i]);
660 do_bottom_half_tx(fst_card_array[i]);
661 }
662 }
663 work_intq = work_intq >> 1;
664 }
665}
666
667/* Card control functions
668 * ======================
669 */
670/* Place the processor in reset state
671 *
672 * Used to be a simple write to card control space but a glitch in the latest
673 * AMD Am186CH processor means that we now have to do it by asserting and de-
674 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register
675 * at offset 9052_CNTRL. Note the updates for the TXU.
676 */
677static inline void
678fst_cpureset(struct fst_card_info *card)
679{
680 unsigned char interrupt_line_register;
681 unsigned long j = jiffies + 1;
682 unsigned int regval;
683
684 if (card->family == FST_FAMILY_TXU) {
685 if (pci_read_config_byte
686 (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) {
687 dbg(DBG_ASS,
688 "Error in reading interrupt line register\n");
689 }
690 /*
691 * Assert PLX software reset and Am186 hardware reset
692 * and then deassert the PLX software reset but 186 still in reset
693 */
694 outw(0x440f, card->pci_conf + CNTRL_9054 + 2);
695 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
696 /*
697 * We are delaying here to allow the 9054 to reset itself
698 */
699 j = jiffies + 1;
700 while (jiffies < j)
701 /* Do nothing */ ;
702 outw(0x240f, card->pci_conf + CNTRL_9054 + 2);
703 /*
704 * We are delaying here to allow the 9054 to reload its eeprom
705 */
706 j = jiffies + 1;
707 while (jiffies < j)
708 /* Do nothing */ ;
709 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
710
711 if (pci_write_config_byte
712 (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) {
713 dbg(DBG_ASS,
714 "Error in writing interrupt line register\n");
715 }
716
717 } else {
718 regval = inl(card->pci_conf + CNTRL_9052);
719
720 outl(regval | 0x40000000, card->pci_conf + CNTRL_9052);
721 outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052);
722 }
723}
724
725/* Release the processor from reset
726 */
727static inline void
728fst_cpurelease(struct fst_card_info *card)
729{
730 if (card->family == FST_FAMILY_TXU) {
731 /*
732 * Force posted writes to complete
733 */
734 (void) readb(card->mem);
735
736 /*
737 * Release LRESET DO = 1
738 * Then release Local Hold, DO = 1
739 */
740 outw(0x040e, card->pci_conf + CNTRL_9054 + 2);
741 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
742 } else {
743 (void) readb(card->ctlmem);
744 }
745}
746
747/* Clear the cards interrupt flag
748 */
749static inline void
750fst_clear_intr(struct fst_card_info *card)
751{
752 if (card->family == FST_FAMILY_TXU) {
753 (void) readb(card->ctlmem);
754 } else {
755 /* Poke the appropriate PLX chip register (same as enabling interrupts)
756 */
757 outw(0x0543, card->pci_conf + INTCSR_9052);
758 }
759}
760
761/* Enable card interrupts
762 */
763static inline void
764fst_enable_intr(struct fst_card_info *card)
765{
766 if (card->family == FST_FAMILY_TXU) {
767 outl(0x0f0c0900, card->pci_conf + INTCSR_9054);
768 } else {
769 outw(0x0543, card->pci_conf + INTCSR_9052);
770 }
771}
772
773/* Disable card interrupts
774 */
775static inline void
776fst_disable_intr(struct fst_card_info *card)
777{
778 if (card->family == FST_FAMILY_TXU) {
779 outl(0x00000000, card->pci_conf + INTCSR_9054);
780 } else {
781 outw(0x0000, card->pci_conf + INTCSR_9052);
782 }
783}
784
785/* Process the result of trying to pass a received frame up the stack
786 */
787static void
788fst_process_rx_status(int rx_status, char *name)
789{
790 switch (rx_status) {
791 case NET_RX_SUCCESS:
792 {
793 /*
794 * Nothing to do here
795 */
796 break;
797 }
798 case NET_RX_DROP:
799 {
800 dbg(DBG_ASS, "%s: Received packet dropped\n", name);
801 break;
802 }
803 }
804}
805
806/* Initilaise DMA for PLX 9054
807 */
808static inline void
809fst_init_dma(struct fst_card_info *card)
810{
811 /*
812 * This is only required for the PLX 9054
813 */
814 if (card->family == FST_FAMILY_TXU) {
815 pci_set_master(card->device);
816 outl(0x00020441, card->pci_conf + DMAMODE0);
817 outl(0x00020441, card->pci_conf + DMAMODE1);
818 outl(0x0, card->pci_conf + DMATHR);
819 }
820}
821
822/* Tx dma complete interrupt
823 */
824static void
825fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
826 int len, int txpos)
827{
828 struct net_device *dev = port_to_dev(port);
829
830 /*
831 * Everything is now set, just tell the card to go
832 */
833 dbg(DBG_TX, "fst_tx_dma_complete\n");
834 FST_WRB(card, txDescrRing[port->index][txpos].bits,
835 DMA_OWN | TX_STP | TX_ENP);
836 dev->stats.tx_packets++;
837 dev->stats.tx_bytes += len;
838 dev->trans_start = jiffies;
839}
840
841/*
842 * Mark it for our own raw sockets interface
843 */
844static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev)
845{
846 skb->dev = dev;
847 skb_reset_mac_header(skb);
848 skb->pkt_type = PACKET_HOST;
849 return htons(ETH_P_CUST);
850}
851
852/* Rx dma complete interrupt
853 */
854static void
855fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
856 int len, struct sk_buff *skb, int rxp)
857{
858 struct net_device *dev = port_to_dev(port);
859 int pi;
860 int rx_status;
861
862 dbg(DBG_TX, "fst_rx_dma_complete\n");
863 pi = port->index;
864 memcpy(skb_put(skb, len), card->rx_dma_handle_host, len);
865
866 /* Reset buffer descriptor */
867 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
868
869 /* Update stats */
870 dev->stats.rx_packets++;
871 dev->stats.rx_bytes += len;
872
873 /* Push upstream */
874 dbg(DBG_RX, "Pushing the frame up the stack\n");
875 if (port->mode == FST_RAW)
876 skb->protocol = farsync_type_trans(skb, dev);
877 else
878 skb->protocol = hdlc_type_trans(skb, dev);
879 rx_status = netif_rx(skb);
880 fst_process_rx_status(rx_status, port_to_dev(port)->name);
881 if (rx_status == NET_RX_DROP)
882 dev->stats.rx_dropped++;
883}
884
885/*
886 * Receive a frame through the DMA
887 */
888static inline void
889fst_rx_dma(struct fst_card_info *card, dma_addr_t skb,
890 dma_addr_t mem, int len)
891{
892 /*
893 * This routine will setup the DMA and start it
894 */
895
896 dbg(DBG_RX, "In fst_rx_dma %lx %lx %d\n",
897 (unsigned long) skb, (unsigned long) mem, len);
898 if (card->dmarx_in_progress) {
899 dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n");
900 }
901
902 outl(skb, card->pci_conf + DMAPADR0); /* Copy to here */
903 outl(mem, card->pci_conf + DMALADR0); /* from here */
904 outl(len, card->pci_conf + DMASIZ0); /* for this length */
905 outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */
906
907 /*
908 * We use the dmarx_in_progress flag to flag the channel as busy
909 */
910 card->dmarx_in_progress = 1;
911 outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */
912}
913
914/*
915 * Send a frame through the DMA
916 */
917static inline void
918fst_tx_dma(struct fst_card_info *card, unsigned char *skb,
919 unsigned char *mem, int len)
920{
921 /*
922 * This routine will setup the DMA and start it.
923 */
924
925 dbg(DBG_TX, "In fst_tx_dma %p %p %d\n", skb, mem, len);
926 if (card->dmatx_in_progress) {
927 dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n");
928 }
929
930 outl((unsigned long) skb, card->pci_conf + DMAPADR1); /* Copy from here */
931 outl((unsigned long) mem, card->pci_conf + DMALADR1); /* to here */
932 outl(len, card->pci_conf + DMASIZ1); /* for this length */
933 outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */
934
935 /*
936 * We use the dmatx_in_progress to flag the channel as busy
937 */
938 card->dmatx_in_progress = 1;
939 outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */
940}
941
942/* Issue a Mailbox command for a port.
943 * Note we issue them on a fire and forget basis, not expecting to see an
944 * error and not waiting for completion.
945 */
946static void
947fst_issue_cmd(struct fst_port_info *port, unsigned short cmd)
948{
949 struct fst_card_info *card;
950 unsigned short mbval;
951 unsigned long flags;
952 int safety;
953
954 card = port->card;
955 spin_lock_irqsave(&card->card_lock, flags);
956 mbval = FST_RDW(card, portMailbox[port->index][0]);
957
958 safety = 0;
959 /* Wait for any previous command to complete */
960 while (mbval > NAK) {
961 spin_unlock_irqrestore(&card->card_lock, flags);
962 schedule_timeout_uninterruptible(1);
963 spin_lock_irqsave(&card->card_lock, flags);
964
965 if (++safety > 2000) {
966 pr_err("Mailbox safety timeout\n");
967 break;
968 }
969
970 mbval = FST_RDW(card, portMailbox[port->index][0]);
971 }
972 if (safety > 0) {
973 dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety);
974 }
975 if (mbval == NAK) {
976 dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n");
977 }
978
979 FST_WRW(card, portMailbox[port->index][0], cmd);
980
981 if (cmd == ABORTTX || cmd == STARTPORT) {
982 port->txpos = 0;
983 port->txipos = 0;
984 port->start = 0;
985 }
986
987 spin_unlock_irqrestore(&card->card_lock, flags);
988}
989
990/* Port output signals control
991 */
992static inline void
993fst_op_raise(struct fst_port_info *port, unsigned int outputs)
994{
995 outputs |= FST_RDL(port->card, v24OpSts[port->index]);
996 FST_WRL(port->card, v24OpSts[port->index], outputs);
997
998 if (port->run)
999 fst_issue_cmd(port, SETV24O);
1000}
1001
1002static inline void
1003fst_op_lower(struct fst_port_info *port, unsigned int outputs)
1004{
1005 outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]);
1006 FST_WRL(port->card, v24OpSts[port->index], outputs);
1007
1008 if (port->run)
1009 fst_issue_cmd(port, SETV24O);
1010}
1011
1012/*
1013 * Setup port Rx buffers
1014 */
1015static void
1016fst_rx_config(struct fst_port_info *port)
1017{
1018 int i;
1019 int pi;
1020 unsigned int offset;
1021 unsigned long flags;
1022 struct fst_card_info *card;
1023
1024 pi = port->index;
1025 card = port->card;
1026 spin_lock_irqsave(&card->card_lock, flags);
1027 for (i = 0; i < NUM_RX_BUFFER; i++) {
1028 offset = BUF_OFFSET(rxBuffer[pi][i][0]);
1029
1030 FST_WRW(card, rxDescrRing[pi][i].ladr, (u16) offset);
1031 FST_WRB(card, rxDescrRing[pi][i].hadr, (u8) (offset >> 16));
1032 FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER));
1033 FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER);
1034 FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN);
1035 }
1036 port->rxpos = 0;
1037 spin_unlock_irqrestore(&card->card_lock, flags);
1038}
1039
1040/*
1041 * Setup port Tx buffers
1042 */
1043static void
1044fst_tx_config(struct fst_port_info *port)
1045{
1046 int i;
1047 int pi;
1048 unsigned int offset;
1049 unsigned long flags;
1050 struct fst_card_info *card;
1051
1052 pi = port->index;
1053 card = port->card;
1054 spin_lock_irqsave(&card->card_lock, flags);
1055 for (i = 0; i < NUM_TX_BUFFER; i++) {
1056 offset = BUF_OFFSET(txBuffer[pi][i][0]);
1057
1058 FST_WRW(card, txDescrRing[pi][i].ladr, (u16) offset);
1059 FST_WRB(card, txDescrRing[pi][i].hadr, (u8) (offset >> 16));
1060 FST_WRW(card, txDescrRing[pi][i].bcnt, 0);
1061 FST_WRB(card, txDescrRing[pi][i].bits, 0);
1062 }
1063 port->txpos = 0;
1064 port->txipos = 0;
1065 port->start = 0;
1066 spin_unlock_irqrestore(&card->card_lock, flags);
1067}
1068
1069/* TE1 Alarm change interrupt event
1070 */
1071static void
1072fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port)
1073{
1074 u8 los;
1075 u8 rra;
1076 u8 ais;
1077
1078 los = FST_RDB(card, suStatus.lossOfSignal);
1079 rra = FST_RDB(card, suStatus.receiveRemoteAlarm);
1080 ais = FST_RDB(card, suStatus.alarmIndicationSignal);
1081
1082 if (los) {
1083 /*
1084 * Lost the link
1085 */
1086 if (netif_carrier_ok(port_to_dev(port))) {
1087 dbg(DBG_INTR, "Net carrier off\n");
1088 netif_carrier_off(port_to_dev(port));
1089 }
1090 } else {
1091 /*
1092 * Link available
1093 */
1094 if (!netif_carrier_ok(port_to_dev(port))) {
1095 dbg(DBG_INTR, "Net carrier on\n");
1096 netif_carrier_on(port_to_dev(port));
1097 }
1098 }
1099
1100 if (los)
1101 dbg(DBG_INTR, "Assert LOS Alarm\n");
1102 else
1103 dbg(DBG_INTR, "De-assert LOS Alarm\n");
1104 if (rra)
1105 dbg(DBG_INTR, "Assert RRA Alarm\n");
1106 else
1107 dbg(DBG_INTR, "De-assert RRA Alarm\n");
1108
1109 if (ais)
1110 dbg(DBG_INTR, "Assert AIS Alarm\n");
1111 else
1112 dbg(DBG_INTR, "De-assert AIS Alarm\n");
1113}
1114
1115/* Control signal change interrupt event
1116 */
1117static void
1118fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port)
1119{
1120 int signals;
1121
1122 signals = FST_RDL(card, v24DebouncedSts[port->index]);
1123
1124 if (signals & (((port->hwif == X21) || (port->hwif == X21D))
1125 ? IPSTS_INDICATE : IPSTS_DCD)) {
1126 if (!netif_carrier_ok(port_to_dev(port))) {
1127 dbg(DBG_INTR, "DCD active\n");
1128 netif_carrier_on(port_to_dev(port));
1129 }
1130 } else {
1131 if (netif_carrier_ok(port_to_dev(port))) {
1132 dbg(DBG_INTR, "DCD lost\n");
1133 netif_carrier_off(port_to_dev(port));
1134 }
1135 }
1136}
1137
1138/* Log Rx Errors
1139 */
1140static void
1141fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1142 unsigned char dmabits, int rxp, unsigned short len)
1143{
1144 struct net_device *dev = port_to_dev(port);
1145
1146 /*
1147 * Increment the appropriate error counter
1148 */
1149 dev->stats.rx_errors++;
1150 if (dmabits & RX_OFLO) {
1151 dev->stats.rx_fifo_errors++;
1152 dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n",
1153 card->card_no, port->index, rxp);
1154 }
1155 if (dmabits & RX_CRC) {
1156 dev->stats.rx_crc_errors++;
1157 dbg(DBG_ASS, "Rx crc error on card %d port %d\n",
1158 card->card_no, port->index);
1159 }
1160 if (dmabits & RX_FRAM) {
1161 dev->stats.rx_frame_errors++;
1162 dbg(DBG_ASS, "Rx frame error on card %d port %d\n",
1163 card->card_no, port->index);
1164 }
1165 if (dmabits == (RX_STP | RX_ENP)) {
1166 dev->stats.rx_length_errors++;
1167 dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n",
1168 len, card->card_no, port->index);
1169 }
1170}
1171
1172/* Rx Error Recovery
1173 */
1174static void
1175fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1176 unsigned char dmabits, int rxp, unsigned short len)
1177{
1178 int i;
1179 int pi;
1180
1181 pi = port->index;
1182 /*
1183 * Discard buffer descriptors until we see the start of the
1184 * next frame. Note that for long frames this could be in
1185 * a subsequent interrupt.
1186 */
1187 i = 0;
1188 while ((dmabits & (DMA_OWN | RX_STP)) == 0) {
1189 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1190 rxp = (rxp+1) % NUM_RX_BUFFER;
1191 if (++i > NUM_RX_BUFFER) {
1192 dbg(DBG_ASS, "intr_rx: Discarding more bufs"
1193 " than we have\n");
1194 break;
1195 }
1196 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1197 dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits);
1198 }
1199 dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i);
1200
1201 /* Discard the terminal buffer */
1202 if (!(dmabits & DMA_OWN)) {
1203 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1204 rxp = (rxp+1) % NUM_RX_BUFFER;
1205 }
1206 port->rxpos = rxp;
1207 return;
1208
1209}
1210
1211/* Rx complete interrupt
1212 */
1213static void
1214fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port)
1215{
1216 unsigned char dmabits;
1217 int pi;
1218 int rxp;
1219 int rx_status;
1220 unsigned short len;
1221 struct sk_buff *skb;
1222 struct net_device *dev = port_to_dev(port);
1223
1224 /* Check we have a buffer to process */
1225 pi = port->index;
1226 rxp = port->rxpos;
1227 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1228 if (dmabits & DMA_OWN) {
1229 dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n",
1230 pi, rxp);
1231 return;
1232 }
1233 if (card->dmarx_in_progress) {
1234 return;
1235 }
1236
1237 /* Get buffer length */
1238 len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt);
1239 /* Discard the CRC */
1240 len -= 2;
1241 if (len == 0) {
1242 /*
1243 * This seems to happen on the TE1 interface sometimes
1244 * so throw the frame away and log the event.
1245 */
1246 pr_err("Frame received with 0 length. Card %d Port %d\n",
1247 card->card_no, port->index);
1248 /* Return descriptor to card */
1249 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1250
1251 rxp = (rxp+1) % NUM_RX_BUFFER;
1252 port->rxpos = rxp;
1253 return;
1254 }
1255
1256 /* Check buffer length and for other errors. We insist on one packet
1257 * in one buffer. This simplifies things greatly and since we've
1258 * allocated 8K it shouldn't be a real world limitation
1259 */
1260 dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len);
1261 if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) {
1262 fst_log_rx_error(card, port, dmabits, rxp, len);
1263 fst_recover_rx_error(card, port, dmabits, rxp, len);
1264 return;
1265 }
1266
1267 /* Allocate SKB */
1268 if ((skb = dev_alloc_skb(len)) == NULL) {
1269 dbg(DBG_RX, "intr_rx: can't allocate buffer\n");
1270
1271 dev->stats.rx_dropped++;
1272
1273 /* Return descriptor to card */
1274 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1275
1276 rxp = (rxp+1) % NUM_RX_BUFFER;
1277 port->rxpos = rxp;
1278 return;
1279 }
1280
1281 /*
1282 * We know the length we need to receive, len.
1283 * It's not worth using the DMA for reads of less than
1284 * FST_MIN_DMA_LEN
1285 */
1286
1287 if ((len < FST_MIN_DMA_LEN) || (card->family == FST_FAMILY_TXP)) {
1288 memcpy_fromio(skb_put(skb, len),
1289 card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]),
1290 len);
1291
1292 /* Reset buffer descriptor */
1293 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1294
1295 /* Update stats */
1296 dev->stats.rx_packets++;
1297 dev->stats.rx_bytes += len;
1298
1299 /* Push upstream */
1300 dbg(DBG_RX, "Pushing frame up the stack\n");
1301 if (port->mode == FST_RAW)
1302 skb->protocol = farsync_type_trans(skb, dev);
1303 else
1304 skb->protocol = hdlc_type_trans(skb, dev);
1305 rx_status = netif_rx(skb);
1306 fst_process_rx_status(rx_status, port_to_dev(port)->name);
1307 if (rx_status == NET_RX_DROP)
1308 dev->stats.rx_dropped++;
1309 } else {
1310 card->dma_skb_rx = skb;
1311 card->dma_port_rx = port;
1312 card->dma_len_rx = len;
1313 card->dma_rxpos = rxp;
1314 fst_rx_dma(card, card->rx_dma_handle_card,
1315 BUF_OFFSET(rxBuffer[pi][rxp][0]), len);
1316 }
1317 if (rxp != port->rxpos) {
1318 dbg(DBG_ASS, "About to increment rxpos by more than 1\n");
1319 dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos);
1320 }
1321 rxp = (rxp+1) % NUM_RX_BUFFER;
1322 port->rxpos = rxp;
1323}
1324
1325/*
1326 * The bottom halfs to the ISR
1327 *
1328 */
1329
1330static void
1331do_bottom_half_tx(struct fst_card_info *card)
1332{
1333 struct fst_port_info *port;
1334 int pi;
1335 int txq_length;
1336 struct sk_buff *skb;
1337 unsigned long flags;
1338 struct net_device *dev;
1339
1340 /*
1341 * Find a free buffer for the transmit
1342 * Step through each port on this card
1343 */
1344
1345 dbg(DBG_TX, "do_bottom_half_tx\n");
1346 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1347 if (!port->run)
1348 continue;
1349
1350 dev = port_to_dev(port);
1351 while (!(FST_RDB(card, txDescrRing[pi][port->txpos].bits) &
1352 DMA_OWN) &&
1353 !(card->dmatx_in_progress)) {
1354 /*
1355 * There doesn't seem to be a txdone event per-se
1356 * We seem to have to deduce it, by checking the DMA_OWN
1357 * bit on the next buffer we think we can use
1358 */
1359 spin_lock_irqsave(&card->card_lock, flags);
1360 if ((txq_length = port->txqe - port->txqs) < 0) {
1361 /*
1362 * This is the case where one has wrapped and the
1363 * maths gives us a negative number
1364 */
1365 txq_length = txq_length + FST_TXQ_DEPTH;
1366 }
1367 spin_unlock_irqrestore(&card->card_lock, flags);
1368 if (txq_length > 0) {
1369 /*
1370 * There is something to send
1371 */
1372 spin_lock_irqsave(&card->card_lock, flags);
1373 skb = port->txq[port->txqs];
1374 port->txqs++;
1375 if (port->txqs == FST_TXQ_DEPTH) {
1376 port->txqs = 0;
1377 }
1378 spin_unlock_irqrestore(&card->card_lock, flags);
1379 /*
1380 * copy the data and set the required indicators on the
1381 * card.
1382 */
1383 FST_WRW(card, txDescrRing[pi][port->txpos].bcnt,
1384 cnv_bcnt(skb->len));
1385 if ((skb->len < FST_MIN_DMA_LEN) ||
1386 (card->family == FST_FAMILY_TXP)) {
1387 /* Enqueue the packet with normal io */
1388 memcpy_toio(card->mem +
1389 BUF_OFFSET(txBuffer[pi]
1390 [port->
1391 txpos][0]),
1392 skb->data, skb->len);
1393 FST_WRB(card,
1394 txDescrRing[pi][port->txpos].
1395 bits,
1396 DMA_OWN | TX_STP | TX_ENP);
1397 dev->stats.tx_packets++;
1398 dev->stats.tx_bytes += skb->len;
1399 dev->trans_start = jiffies;
1400 } else {
1401 /* Or do it through dma */
1402 memcpy(card->tx_dma_handle_host,
1403 skb->data, skb->len);
1404 card->dma_port_tx = port;
1405 card->dma_len_tx = skb->len;
1406 card->dma_txpos = port->txpos;
1407 fst_tx_dma(card,
1408 (char *) card->
1409 tx_dma_handle_card,
1410 (char *)
1411 BUF_OFFSET(txBuffer[pi]
1412 [port->txpos][0]),
1413 skb->len);
1414 }
1415 if (++port->txpos >= NUM_TX_BUFFER)
1416 port->txpos = 0;
1417 /*
1418 * If we have flow control on, can we now release it?
1419 */
1420 if (port->start) {
1421 if (txq_length < fst_txq_low) {
1422 netif_wake_queue(port_to_dev
1423 (port));
1424 port->start = 0;
1425 }
1426 }
1427 dev_kfree_skb(skb);
1428 } else {
1429 /*
1430 * Nothing to send so break out of the while loop
1431 */
1432 break;
1433 }
1434 }
1435 }
1436}
1437
1438static void
1439do_bottom_half_rx(struct fst_card_info *card)
1440{
1441 struct fst_port_info *port;
1442 int pi;
1443 int rx_count = 0;
1444
1445 /* Check for rx completions on all ports on this card */
1446 dbg(DBG_RX, "do_bottom_half_rx\n");
1447 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1448 if (!port->run)
1449 continue;
1450
1451 while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits)
1452 & DMA_OWN) && !(card->dmarx_in_progress)) {
1453 if (rx_count > fst_max_reads) {
1454 /*
1455 * Don't spend forever in receive processing
1456 * Schedule another event
1457 */
1458 fst_q_work_item(&fst_work_intq, card->card_no);
1459 tasklet_schedule(&fst_int_task);
1460 break; /* Leave the loop */
1461 }
1462 fst_intr_rx(card, port);
1463 rx_count++;
1464 }
1465 }
1466}
1467
1468/*
1469 * The interrupt service routine
1470 * Dev_id is our fst_card_info pointer
1471 */
1472static irqreturn_t
1473fst_intr(int dummy, void *dev_id)
1474{
1475 struct fst_card_info *card = dev_id;
1476 struct fst_port_info *port;
1477 int rdidx; /* Event buffer indices */
1478 int wridx;
1479 int event; /* Actual event for processing */
1480 unsigned int dma_intcsr = 0;
1481 unsigned int do_card_interrupt;
1482 unsigned int int_retry_count;
1483
1484 /*
1485 * Check to see if the interrupt was for this card
1486 * return if not
1487 * Note that the call to clear the interrupt is important
1488 */
1489 dbg(DBG_INTR, "intr: %d %p\n", card->irq, card);
1490 if (card->state != FST_RUNNING) {
1491 pr_err("Interrupt received for card %d in a non running state (%d)\n",
1492 card->card_no, card->state);
1493
1494 /*
1495 * It is possible to really be running, i.e. we have re-loaded
1496 * a running card
1497 * Clear and reprime the interrupt source
1498 */
1499 fst_clear_intr(card);
1500 return IRQ_HANDLED;
1501 }
1502
1503 /* Clear and reprime the interrupt source */
1504 fst_clear_intr(card);
1505
1506 /*
1507 * Is the interrupt for this card (handshake == 1)
1508 */
1509 do_card_interrupt = 0;
1510 if (FST_RDB(card, interruptHandshake) == 1) {
1511 do_card_interrupt += FST_CARD_INT;
1512 /* Set the software acknowledge */
1513 FST_WRB(card, interruptHandshake, 0xEE);
1514 }
1515 if (card->family == FST_FAMILY_TXU) {
1516 /*
1517 * Is it a DMA Interrupt
1518 */
1519 dma_intcsr = inl(card->pci_conf + INTCSR_9054);
1520 if (dma_intcsr & 0x00200000) {
1521 /*
1522 * DMA Channel 0 (Rx transfer complete)
1523 */
1524 dbg(DBG_RX, "DMA Rx xfer complete\n");
1525 outb(0x8, card->pci_conf + DMACSR0);
1526 fst_rx_dma_complete(card, card->dma_port_rx,
1527 card->dma_len_rx, card->dma_skb_rx,
1528 card->dma_rxpos);
1529 card->dmarx_in_progress = 0;
1530 do_card_interrupt += FST_RX_DMA_INT;
1531 }
1532 if (dma_intcsr & 0x00400000) {
1533 /*
1534 * DMA Channel 1 (Tx transfer complete)
1535 */
1536 dbg(DBG_TX, "DMA Tx xfer complete\n");
1537 outb(0x8, card->pci_conf + DMACSR1);
1538 fst_tx_dma_complete(card, card->dma_port_tx,
1539 card->dma_len_tx, card->dma_txpos);
1540 card->dmatx_in_progress = 0;
1541 do_card_interrupt += FST_TX_DMA_INT;
1542 }
1543 }
1544
1545 /*
1546 * Have we been missing Interrupts
1547 */
1548 int_retry_count = FST_RDL(card, interruptRetryCount);
1549 if (int_retry_count) {
1550 dbg(DBG_ASS, "Card %d int_retry_count is %d\n",
1551 card->card_no, int_retry_count);
1552 FST_WRL(card, interruptRetryCount, 0);
1553 }
1554
1555 if (!do_card_interrupt) {
1556 return IRQ_HANDLED;
1557 }
1558
1559 /* Scehdule the bottom half of the ISR */
1560 fst_q_work_item(&fst_work_intq, card->card_no);
1561 tasklet_schedule(&fst_int_task);
1562
1563 /* Drain the event queue */
1564 rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f;
1565 wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f;
1566 while (rdidx != wridx) {
1567 event = FST_RDB(card, interruptEvent.evntbuff[rdidx]);
1568 port = &card->ports[event & 0x03];
1569
1570 dbg(DBG_INTR, "Processing Interrupt event: %x\n", event);
1571
1572 switch (event) {
1573 case TE1_ALMA:
1574 dbg(DBG_INTR, "TE1 Alarm intr\n");
1575 if (port->run)
1576 fst_intr_te1_alarm(card, port);
1577 break;
1578
1579 case CTLA_CHG:
1580 case CTLB_CHG:
1581 case CTLC_CHG:
1582 case CTLD_CHG:
1583 if (port->run)
1584 fst_intr_ctlchg(card, port);
1585 break;
1586
1587 case ABTA_SENT:
1588 case ABTB_SENT:
1589 case ABTC_SENT:
1590 case ABTD_SENT:
1591 dbg(DBG_TX, "Abort complete port %d\n", port->index);
1592 break;
1593
1594 case TXA_UNDF:
1595 case TXB_UNDF:
1596 case TXC_UNDF:
1597 case TXD_UNDF:
1598 /* Difficult to see how we'd get this given that we
1599 * always load up the entire packet for DMA.
1600 */
1601 dbg(DBG_TX, "Tx underflow port %d\n", port->index);
1602 port_to_dev(port)->stats.tx_errors++;
1603 port_to_dev(port)->stats.tx_fifo_errors++;
1604 dbg(DBG_ASS, "Tx underflow on card %d port %d\n",
1605 card->card_no, port->index);
1606 break;
1607
1608 case INIT_CPLT:
1609 dbg(DBG_INIT, "Card init OK intr\n");
1610 break;
1611
1612 case INIT_FAIL:
1613 dbg(DBG_INIT, "Card init FAILED intr\n");
1614 card->state = FST_IFAILED;
1615 break;
1616
1617 default:
1618 pr_err("intr: unknown card event %d. ignored\n", event);
1619 break;
1620 }
1621
1622 /* Bump and wrap the index */
1623 if (++rdidx >= MAX_CIRBUFF)
1624 rdidx = 0;
1625 }
1626 FST_WRB(card, interruptEvent.rdindex, rdidx);
1627 return IRQ_HANDLED;
1628}
1629
1630/* Check that the shared memory configuration is one that we can handle
1631 * and that some basic parameters are correct
1632 */
1633static void
1634check_started_ok(struct fst_card_info *card)
1635{
1636 int i;
1637
1638 /* Check structure version and end marker */
1639 if (FST_RDW(card, smcVersion) != SMC_VERSION) {
1640 pr_err("Bad shared memory version %d expected %d\n",
1641 FST_RDW(card, smcVersion), SMC_VERSION);
1642 card->state = FST_BADVERSION;
1643 return;
1644 }
1645 if (FST_RDL(card, endOfSmcSignature) != END_SIG) {
1646 pr_err("Missing shared memory signature\n");
1647 card->state = FST_BADVERSION;
1648 return;
1649 }
1650 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */
1651 if ((i = FST_RDB(card, taskStatus)) == 0x01) {
1652 card->state = FST_RUNNING;
1653 } else if (i == 0xFF) {
1654 pr_err("Firmware initialisation failed. Card halted\n");
1655 card->state = FST_HALTED;
1656 return;
1657 } else if (i != 0x00) {
1658 pr_err("Unknown firmware status 0x%x\n", i);
1659 card->state = FST_HALTED;
1660 return;
1661 }
1662
1663 /* Finally check the number of ports reported by firmware against the
1664 * number we assumed at card detection. Should never happen with
1665 * existing firmware etc so we just report it for the moment.
1666 */
1667 if (FST_RDL(card, numberOfPorts) != card->nports) {
1668 pr_warn("Port count mismatch on card %d. Firmware thinks %d we say %d\n",
1669 card->card_no,
1670 FST_RDL(card, numberOfPorts), card->nports);
1671 }
1672}
1673
1674static int
1675set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port,
1676 struct fstioc_info *info)
1677{
1678 int err;
1679 unsigned char my_framing;
1680
1681 /* Set things according to the user set valid flags
1682 * Several of the old options have been invalidated/replaced by the
1683 * generic hdlc package.
1684 */
1685 err = 0;
1686 if (info->valid & FSTVAL_PROTO) {
1687 if (info->proto == FST_RAW)
1688 port->mode = FST_RAW;
1689 else
1690 port->mode = FST_GEN_HDLC;
1691 }
1692
1693 if (info->valid & FSTVAL_CABLE)
1694 err = -EINVAL;
1695
1696 if (info->valid & FSTVAL_SPEED)
1697 err = -EINVAL;
1698
1699 if (info->valid & FSTVAL_PHASE)
1700 FST_WRB(card, portConfig[port->index].invertClock,
1701 info->invertClock);
1702 if (info->valid & FSTVAL_MODE)
1703 FST_WRW(card, cardMode, info->cardMode);
1704 if (info->valid & FSTVAL_TE1) {
1705 FST_WRL(card, suConfig.dataRate, info->lineSpeed);
1706 FST_WRB(card, suConfig.clocking, info->clockSource);
1707 my_framing = FRAMING_E1;
1708 if (info->framing == E1)
1709 my_framing = FRAMING_E1;
1710 if (info->framing == T1)
1711 my_framing = FRAMING_T1;
1712 if (info->framing == J1)
1713 my_framing = FRAMING_J1;
1714 FST_WRB(card, suConfig.framing, my_framing);
1715 FST_WRB(card, suConfig.structure, info->structure);
1716 FST_WRB(card, suConfig.interface, info->interface);
1717 FST_WRB(card, suConfig.coding, info->coding);
1718 FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut);
1719 FST_WRB(card, suConfig.equalizer, info->equalizer);
1720 FST_WRB(card, suConfig.transparentMode, info->transparentMode);
1721 FST_WRB(card, suConfig.loopMode, info->loopMode);
1722 FST_WRB(card, suConfig.range, info->range);
1723 FST_WRB(card, suConfig.txBufferMode, info->txBufferMode);
1724 FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode);
1725 FST_WRB(card, suConfig.startingSlot, info->startingSlot);
1726 FST_WRB(card, suConfig.losThreshold, info->losThreshold);
1727 if (info->idleCode)
1728 FST_WRB(card, suConfig.enableIdleCode, 1);
1729 else
1730 FST_WRB(card, suConfig.enableIdleCode, 0);
1731 FST_WRB(card, suConfig.idleCode, info->idleCode);
1732#if FST_DEBUG
1733 if (info->valid & FSTVAL_TE1) {
1734 printk("Setting TE1 data\n");
1735 printk("Line Speed = %d\n", info->lineSpeed);
1736 printk("Start slot = %d\n", info->startingSlot);
1737 printk("Clock source = %d\n", info->clockSource);
1738 printk("Framing = %d\n", my_framing);
1739 printk("Structure = %d\n", info->structure);
1740 printk("interface = %d\n", info->interface);
1741 printk("Coding = %d\n", info->coding);
1742 printk("Line build out = %d\n", info->lineBuildOut);
1743 printk("Equaliser = %d\n", info->equalizer);
1744 printk("Transparent mode = %d\n",
1745 info->transparentMode);
1746 printk("Loop mode = %d\n", info->loopMode);
1747 printk("Range = %d\n", info->range);
1748 printk("Tx Buffer mode = %d\n", info->txBufferMode);
1749 printk("Rx Buffer mode = %d\n", info->rxBufferMode);
1750 printk("LOS Threshold = %d\n", info->losThreshold);
1751 printk("Idle Code = %d\n", info->idleCode);
1752 }
1753#endif
1754 }
1755#if FST_DEBUG
1756 if (info->valid & FSTVAL_DEBUG) {
1757 fst_debug_mask = info->debug;
1758 }
1759#endif
1760
1761 return err;
1762}
1763
1764static void
1765gather_conf_info(struct fst_card_info *card, struct fst_port_info *port,
1766 struct fstioc_info *info)
1767{
1768 int i;
1769
1770 memset(info, 0, sizeof (struct fstioc_info));
1771
1772 i = port->index;
1773 info->kernelVersion = LINUX_VERSION_CODE;
1774 info->nports = card->nports;
1775 info->type = card->type;
1776 info->state = card->state;
1777 info->proto = FST_GEN_HDLC;
1778 info->index = i;
1779#if FST_DEBUG
1780 info->debug = fst_debug_mask;
1781#endif
1782
1783 /* Only mark information as valid if card is running.
1784 * Copy the data anyway in case it is useful for diagnostics
1785 */
1786 info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD)
1787#if FST_DEBUG
1788 | FSTVAL_DEBUG
1789#endif
1790 ;
1791
1792 info->lineInterface = FST_RDW(card, portConfig[i].lineInterface);
1793 info->internalClock = FST_RDB(card, portConfig[i].internalClock);
1794 info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed);
1795 info->invertClock = FST_RDB(card, portConfig[i].invertClock);
1796 info->v24IpSts = FST_RDL(card, v24IpSts[i]);
1797 info->v24OpSts = FST_RDL(card, v24OpSts[i]);
1798 info->clockStatus = FST_RDW(card, clockStatus[i]);
1799 info->cableStatus = FST_RDW(card, cableStatus);
1800 info->cardMode = FST_RDW(card, cardMode);
1801 info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion);
1802
1803 /*
1804 * The T2U can report cable presence for both A or B
1805 * in bits 0 and 1 of cableStatus. See which port we are and
1806 * do the mapping.
1807 */
1808 if (card->family == FST_FAMILY_TXU) {
1809 if (port->index == 0) {
1810 /*
1811 * Port A
1812 */
1813 info->cableStatus = info->cableStatus & 1;
1814 } else {
1815 /*
1816 * Port B
1817 */
1818 info->cableStatus = info->cableStatus >> 1;
1819 info->cableStatus = info->cableStatus & 1;
1820 }
1821 }
1822 /*
1823 * Some additional bits if we are TE1
1824 */
1825 if (card->type == FST_TYPE_TE1) {
1826 info->lineSpeed = FST_RDL(card, suConfig.dataRate);
1827 info->clockSource = FST_RDB(card, suConfig.clocking);
1828 info->framing = FST_RDB(card, suConfig.framing);
1829 info->structure = FST_RDB(card, suConfig.structure);
1830 info->interface = FST_RDB(card, suConfig.interface);
1831 info->coding = FST_RDB(card, suConfig.coding);
1832 info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut);
1833 info->equalizer = FST_RDB(card, suConfig.equalizer);
1834 info->loopMode = FST_RDB(card, suConfig.loopMode);
1835 info->range = FST_RDB(card, suConfig.range);
1836 info->txBufferMode = FST_RDB(card, suConfig.txBufferMode);
1837 info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode);
1838 info->startingSlot = FST_RDB(card, suConfig.startingSlot);
1839 info->losThreshold = FST_RDB(card, suConfig.losThreshold);
1840 if (FST_RDB(card, suConfig.enableIdleCode))
1841 info->idleCode = FST_RDB(card, suConfig.idleCode);
1842 else
1843 info->idleCode = 0;
1844 info->receiveBufferDelay =
1845 FST_RDL(card, suStatus.receiveBufferDelay);
1846 info->framingErrorCount =
1847 FST_RDL(card, suStatus.framingErrorCount);
1848 info->codeViolationCount =
1849 FST_RDL(card, suStatus.codeViolationCount);
1850 info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount);
1851 info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation);
1852 info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal);
1853 info->receiveRemoteAlarm =
1854 FST_RDB(card, suStatus.receiveRemoteAlarm);
1855 info->alarmIndicationSignal =
1856 FST_RDB(card, suStatus.alarmIndicationSignal);
1857 }
1858}
1859
1860static int
1861fst_set_iface(struct fst_card_info *card, struct fst_port_info *port,
1862 struct ifreq *ifr)
1863{
1864 sync_serial_settings sync;
1865 int i;
1866
1867 if (ifr->ifr_settings.size != sizeof (sync)) {
1868 return -ENOMEM;
1869 }
1870
1871 if (copy_from_user
1872 (&sync, ifr->ifr_settings.ifs_ifsu.sync, sizeof (sync))) {
1873 return -EFAULT;
1874 }
1875
1876 if (sync.loopback)
1877 return -EINVAL;
1878
1879 i = port->index;
1880
1881 switch (ifr->ifr_settings.type) {
1882 case IF_IFACE_V35:
1883 FST_WRW(card, portConfig[i].lineInterface, V35);
1884 port->hwif = V35;
1885 break;
1886
1887 case IF_IFACE_V24:
1888 FST_WRW(card, portConfig[i].lineInterface, V24);
1889 port->hwif = V24;
1890 break;
1891
1892 case IF_IFACE_X21:
1893 FST_WRW(card, portConfig[i].lineInterface, X21);
1894 port->hwif = X21;
1895 break;
1896
1897 case IF_IFACE_X21D:
1898 FST_WRW(card, portConfig[i].lineInterface, X21D);
1899 port->hwif = X21D;
1900 break;
1901
1902 case IF_IFACE_T1:
1903 FST_WRW(card, portConfig[i].lineInterface, T1);
1904 port->hwif = T1;
1905 break;
1906
1907 case IF_IFACE_E1:
1908 FST_WRW(card, portConfig[i].lineInterface, E1);
1909 port->hwif = E1;
1910 break;
1911
1912 case IF_IFACE_SYNC_SERIAL:
1913 break;
1914
1915 default:
1916 return -EINVAL;
1917 }
1918
1919 switch (sync.clock_type) {
1920 case CLOCK_EXT:
1921 FST_WRB(card, portConfig[i].internalClock, EXTCLK);
1922 break;
1923
1924 case CLOCK_INT:
1925 FST_WRB(card, portConfig[i].internalClock, INTCLK);
1926 break;
1927
1928 default:
1929 return -EINVAL;
1930 }
1931 FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate);
1932 return 0;
1933}
1934
1935static int
1936fst_get_iface(struct fst_card_info *card, struct fst_port_info *port,
1937 struct ifreq *ifr)
1938{
1939 sync_serial_settings sync;
1940 int i;
1941
1942 /* First check what line type is set, we'll default to reporting X.21
1943 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be
1944 * changed
1945 */
1946 switch (port->hwif) {
1947 case E1:
1948 ifr->ifr_settings.type = IF_IFACE_E1;
1949 break;
1950 case T1:
1951 ifr->ifr_settings.type = IF_IFACE_T1;
1952 break;
1953 case V35:
1954 ifr->ifr_settings.type = IF_IFACE_V35;
1955 break;
1956 case V24:
1957 ifr->ifr_settings.type = IF_IFACE_V24;
1958 break;
1959 case X21D:
1960 ifr->ifr_settings.type = IF_IFACE_X21D;
1961 break;
1962 case X21:
1963 default:
1964 ifr->ifr_settings.type = IF_IFACE_X21;
1965 break;
1966 }
1967 if (ifr->ifr_settings.size == 0) {
1968 return 0; /* only type requested */
1969 }
1970 if (ifr->ifr_settings.size < sizeof (sync)) {
1971 return -ENOMEM;
1972 }
1973
1974 i = port->index;
1975 memset(&sync, 0, sizeof(sync));
1976 sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed);
1977 /* Lucky card and linux use same encoding here */
1978 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) ==
1979 INTCLK ? CLOCK_INT : CLOCK_EXT;
1980 sync.loopback = 0;
1981
1982 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &sync, sizeof (sync))) {
1983 return -EFAULT;
1984 }
1985
1986 ifr->ifr_settings.size = sizeof (sync);
1987 return 0;
1988}
1989
1990static int
1991fst_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1992{
1993 struct fst_card_info *card;
1994 struct fst_port_info *port;
1995 struct fstioc_write wrthdr;
1996 struct fstioc_info info;
1997 unsigned long flags;
1998 void *buf;
1999
2000 dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, ifr->ifr_data);
2001
2002 port = dev_to_port(dev);
2003 card = port->card;
2004
2005 if (!capable(CAP_NET_ADMIN))
2006 return -EPERM;
2007
2008 switch (cmd) {
2009 case FSTCPURESET:
2010 fst_cpureset(card);
2011 card->state = FST_RESET;
2012 return 0;
2013
2014 case FSTCPURELEASE:
2015 fst_cpurelease(card);
2016 card->state = FST_STARTING;
2017 return 0;
2018
2019 case FSTWRITE: /* Code write (download) */
2020
2021 /* First copy in the header with the length and offset of data
2022 * to write
2023 */
2024 if (ifr->ifr_data == NULL) {
2025 return -EINVAL;
2026 }
2027 if (copy_from_user(&wrthdr, ifr->ifr_data,
2028 sizeof (struct fstioc_write))) {
2029 return -EFAULT;
2030 }
2031
2032 /* Sanity check the parameters. We don't support partial writes
2033 * when going over the top
2034 */
2035 if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE ||
2036 wrthdr.size + wrthdr.offset > FST_MEMSIZE) {
2037 return -ENXIO;
2038 }
2039
2040 /* Now copy the data to the card. */
2041
2042 buf = memdup_user(ifr->ifr_data + sizeof(struct fstioc_write),
2043 wrthdr.size);
2044 if (IS_ERR(buf))
2045 return PTR_ERR(buf);
2046
2047 memcpy_toio(card->mem + wrthdr.offset, buf, wrthdr.size);
2048 kfree(buf);
2049
2050 /* Writes to the memory of a card in the reset state constitute
2051 * a download
2052 */
2053 if (card->state == FST_RESET) {
2054 card->state = FST_DOWNLOAD;
2055 }
2056 return 0;
2057
2058 case FSTGETCONF:
2059
2060 /* If card has just been started check the shared memory config
2061 * version and marker
2062 */
2063 if (card->state == FST_STARTING) {
2064 check_started_ok(card);
2065
2066 /* If everything checked out enable card interrupts */
2067 if (card->state == FST_RUNNING) {
2068 spin_lock_irqsave(&card->card_lock, flags);
2069 fst_enable_intr(card);
2070 FST_WRB(card, interruptHandshake, 0xEE);
2071 spin_unlock_irqrestore(&card->card_lock, flags);
2072 }
2073 }
2074
2075 if (ifr->ifr_data == NULL) {
2076 return -EINVAL;
2077 }
2078
2079 gather_conf_info(card, port, &info);
2080
2081 if (copy_to_user(ifr->ifr_data, &info, sizeof (info))) {
2082 return -EFAULT;
2083 }
2084 return 0;
2085
2086 case FSTSETCONF:
2087
2088 /*
2089 * Most of the settings have been moved to the generic ioctls
2090 * this just covers debug and board ident now
2091 */
2092
2093 if (card->state != FST_RUNNING) {
2094 pr_err("Attempt to configure card %d in non-running state (%d)\n",
2095 card->card_no, card->state);
2096 return -EIO;
2097 }
2098 if (copy_from_user(&info, ifr->ifr_data, sizeof (info))) {
2099 return -EFAULT;
2100 }
2101
2102 return set_conf_from_info(card, port, &info);
2103
2104 case SIOCWANDEV:
2105 switch (ifr->ifr_settings.type) {
2106 case IF_GET_IFACE:
2107 return fst_get_iface(card, port, ifr);
2108
2109 case IF_IFACE_SYNC_SERIAL:
2110 case IF_IFACE_V35:
2111 case IF_IFACE_V24:
2112 case IF_IFACE_X21:
2113 case IF_IFACE_X21D:
2114 case IF_IFACE_T1:
2115 case IF_IFACE_E1:
2116 return fst_set_iface(card, port, ifr);
2117
2118 case IF_PROTO_RAW:
2119 port->mode = FST_RAW;
2120 return 0;
2121
2122 case IF_GET_PROTO:
2123 if (port->mode == FST_RAW) {
2124 ifr->ifr_settings.type = IF_PROTO_RAW;
2125 return 0;
2126 }
2127 return hdlc_ioctl(dev, ifr, cmd);
2128
2129 default:
2130 port->mode = FST_GEN_HDLC;
2131 dbg(DBG_IOCTL, "Passing this type to hdlc %x\n",
2132 ifr->ifr_settings.type);
2133 return hdlc_ioctl(dev, ifr, cmd);
2134 }
2135
2136 default:
2137 /* Not one of ours. Pass through to HDLC package */
2138 return hdlc_ioctl(dev, ifr, cmd);
2139 }
2140}
2141
2142static void
2143fst_openport(struct fst_port_info *port)
2144{
2145 int signals;
2146 int txq_length;
2147
2148 /* Only init things if card is actually running. This allows open to
2149 * succeed for downloads etc.
2150 */
2151 if (port->card->state == FST_RUNNING) {
2152 if (port->run) {
2153 dbg(DBG_OPEN, "open: found port already running\n");
2154
2155 fst_issue_cmd(port, STOPPORT);
2156 port->run = 0;
2157 }
2158
2159 fst_rx_config(port);
2160 fst_tx_config(port);
2161 fst_op_raise(port, OPSTS_RTS | OPSTS_DTR);
2162
2163 fst_issue_cmd(port, STARTPORT);
2164 port->run = 1;
2165
2166 signals = FST_RDL(port->card, v24DebouncedSts[port->index]);
2167 if (signals & (((port->hwif == X21) || (port->hwif == X21D))
2168 ? IPSTS_INDICATE : IPSTS_DCD))
2169 netif_carrier_on(port_to_dev(port));
2170 else
2171 netif_carrier_off(port_to_dev(port));
2172
2173 txq_length = port->txqe - port->txqs;
2174 port->txqe = 0;
2175 port->txqs = 0;
2176 }
2177
2178}
2179
2180static void
2181fst_closeport(struct fst_port_info *port)
2182{
2183 if (port->card->state == FST_RUNNING) {
2184 if (port->run) {
2185 port->run = 0;
2186 fst_op_lower(port, OPSTS_RTS | OPSTS_DTR);
2187
2188 fst_issue_cmd(port, STOPPORT);
2189 } else {
2190 dbg(DBG_OPEN, "close: port not running\n");
2191 }
2192 }
2193}
2194
2195static int
2196fst_open(struct net_device *dev)
2197{
2198 int err;
2199 struct fst_port_info *port;
2200
2201 port = dev_to_port(dev);
2202 if (!try_module_get(THIS_MODULE))
2203 return -EBUSY;
2204
2205 if (port->mode != FST_RAW) {
2206 err = hdlc_open(dev);
2207 if (err) {
2208 module_put(THIS_MODULE);
2209 return err;
2210 }
2211 }
2212
2213 fst_openport(port);
2214 netif_wake_queue(dev);
2215 return 0;
2216}
2217
2218static int
2219fst_close(struct net_device *dev)
2220{
2221 struct fst_port_info *port;
2222 struct fst_card_info *card;
2223 unsigned char tx_dma_done;
2224 unsigned char rx_dma_done;
2225
2226 port = dev_to_port(dev);
2227 card = port->card;
2228
2229 tx_dma_done = inb(card->pci_conf + DMACSR1);
2230 rx_dma_done = inb(card->pci_conf + DMACSR0);
2231 dbg(DBG_OPEN,
2232 "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n",
2233 card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress,
2234 rx_dma_done);
2235
2236 netif_stop_queue(dev);
2237 fst_closeport(dev_to_port(dev));
2238 if (port->mode != FST_RAW) {
2239 hdlc_close(dev);
2240 }
2241 module_put(THIS_MODULE);
2242 return 0;
2243}
2244
2245static int
2246fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity)
2247{
2248 /*
2249 * Setting currently fixed in FarSync card so we check and forget
2250 */
2251 if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT)
2252 return -EINVAL;
2253 return 0;
2254}
2255
2256static void
2257fst_tx_timeout(struct net_device *dev)
2258{
2259 struct fst_port_info *port;
2260 struct fst_card_info *card;
2261
2262 port = dev_to_port(dev);
2263 card = port->card;
2264 dev->stats.tx_errors++;
2265 dev->stats.tx_aborted_errors++;
2266 dbg(DBG_ASS, "Tx timeout card %d port %d\n",
2267 card->card_no, port->index);
2268 fst_issue_cmd(port, ABORTTX);
2269
2270 dev->trans_start = jiffies;
2271 netif_wake_queue(dev);
2272 port->start = 0;
2273}
2274
2275static netdev_tx_t
2276fst_start_xmit(struct sk_buff *skb, struct net_device *dev)
2277{
2278 struct fst_card_info *card;
2279 struct fst_port_info *port;
2280 unsigned long flags;
2281 int txq_length;
2282
2283 port = dev_to_port(dev);
2284 card = port->card;
2285 dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len);
2286
2287 /* Drop packet with error if we don't have carrier */
2288 if (!netif_carrier_ok(dev)) {
2289 dev_kfree_skb(skb);
2290 dev->stats.tx_errors++;
2291 dev->stats.tx_carrier_errors++;
2292 dbg(DBG_ASS,
2293 "Tried to transmit but no carrier on card %d port %d\n",
2294 card->card_no, port->index);
2295 return NETDEV_TX_OK;
2296 }
2297
2298 /* Drop it if it's too big! MTU failure ? */
2299 if (skb->len > LEN_TX_BUFFER) {
2300 dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len,
2301 LEN_TX_BUFFER);
2302 dev_kfree_skb(skb);
2303 dev->stats.tx_errors++;
2304 return NETDEV_TX_OK;
2305 }
2306
2307 /*
2308 * We are always going to queue the packet
2309 * so that the bottom half is the only place we tx from
2310 * Check there is room in the port txq
2311 */
2312 spin_lock_irqsave(&card->card_lock, flags);
2313 if ((txq_length = port->txqe - port->txqs) < 0) {
2314 /*
2315 * This is the case where the next free has wrapped but the
2316 * last used hasn't
2317 */
2318 txq_length = txq_length + FST_TXQ_DEPTH;
2319 }
2320 spin_unlock_irqrestore(&card->card_lock, flags);
2321 if (txq_length > fst_txq_high) {
2322 /*
2323 * We have got enough buffers in the pipeline. Ask the network
2324 * layer to stop sending frames down
2325 */
2326 netif_stop_queue(dev);
2327 port->start = 1; /* I'm using this to signal stop sent up */
2328 }
2329
2330 if (txq_length == FST_TXQ_DEPTH - 1) {
2331 /*
2332 * This shouldn't have happened but such is life
2333 */
2334 dev_kfree_skb(skb);
2335 dev->stats.tx_errors++;
2336 dbg(DBG_ASS, "Tx queue overflow card %d port %d\n",
2337 card->card_no, port->index);
2338 return NETDEV_TX_OK;
2339 }
2340
2341 /*
2342 * queue the buffer
2343 */
2344 spin_lock_irqsave(&card->card_lock, flags);
2345 port->txq[port->txqe] = skb;
2346 port->txqe++;
2347 if (port->txqe == FST_TXQ_DEPTH)
2348 port->txqe = 0;
2349 spin_unlock_irqrestore(&card->card_lock, flags);
2350
2351 /* Scehdule the bottom half which now does transmit processing */
2352 fst_q_work_item(&fst_work_txq, card->card_no);
2353 tasklet_schedule(&fst_tx_task);
2354
2355 return NETDEV_TX_OK;
2356}
2357
2358/*
2359 * Card setup having checked hardware resources.
2360 * Should be pretty bizarre if we get an error here (kernel memory
2361 * exhaustion is one possibility). If we do see a problem we report it
2362 * via a printk and leave the corresponding interface and all that follow
2363 * disabled.
2364 */
2365static char *type_strings[] = {
2366 "no hardware", /* Should never be seen */
2367 "FarSync T2P",
2368 "FarSync T4P",
2369 "FarSync T1U",
2370 "FarSync T2U",
2371 "FarSync T4U",
2372 "FarSync TE1"
2373};
2374
2375static void
2376fst_init_card(struct fst_card_info *card)
2377{
2378 int i;
2379 int err;
2380
2381 /* We're working on a number of ports based on the card ID. If the
2382 * firmware detects something different later (should never happen)
2383 * we'll have to revise it in some way then.
2384 */
2385 for (i = 0; i < card->nports; i++) {
2386 err = register_hdlc_device(card->ports[i].dev);
2387 if (err < 0) {
2388 int j;
2389 pr_err("Cannot register HDLC device for port %d (errno %d)\n",
2390 i, -err);
2391 for (j = i; j < card->nports; j++) {
2392 free_netdev(card->ports[j].dev);
2393 card->ports[j].dev = NULL;
2394 }
2395 card->nports = i;
2396 break;
2397 }
2398 }
2399
2400 pr_info("%s-%s: %s IRQ%d, %d ports\n",
2401 port_to_dev(&card->ports[0])->name,
2402 port_to_dev(&card->ports[card->nports - 1])->name,
2403 type_strings[card->type], card->irq, card->nports);
2404}
2405
2406static const struct net_device_ops fst_ops = {
2407 .ndo_open = fst_open,
2408 .ndo_stop = fst_close,
2409 .ndo_change_mtu = hdlc_change_mtu,
2410 .ndo_start_xmit = hdlc_start_xmit,
2411 .ndo_do_ioctl = fst_ioctl,
2412 .ndo_tx_timeout = fst_tx_timeout,
2413};
2414
2415/*
2416 * Initialise card when detected.
2417 * Returns 0 to indicate success, or errno otherwise.
2418 */
2419static int
2420fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2421{
2422 static int no_of_cards_added = 0;
2423 struct fst_card_info *card;
2424 int err = 0;
2425 int i;
2426
2427 printk_once(KERN_INFO
2428 pr_fmt("FarSync WAN driver " FST_USER_VERSION
2429 " (c) 2001-2004 FarSite Communications Ltd.\n"));
2430#if FST_DEBUG
2431 dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask);
2432#endif
2433 /*
2434 * We are going to be clever and allow certain cards not to be
2435 * configured. An exclude list can be provided in /etc/modules.conf
2436 */
2437 if (fst_excluded_cards != 0) {
2438 /*
2439 * There are cards to exclude
2440 *
2441 */
2442 for (i = 0; i < fst_excluded_cards; i++) {
2443 if ((pdev->devfn) >> 3 == fst_excluded_list[i]) {
2444 pr_info("FarSync PCI device %d not assigned\n",
2445 (pdev->devfn) >> 3);
2446 return -EBUSY;
2447 }
2448 }
2449 }
2450
2451 /* Allocate driver private data */
2452 card = kzalloc(sizeof(struct fst_card_info), GFP_KERNEL);
2453 if (card == NULL)
2454 return -ENOMEM;
2455
2456 /* Try to enable the device */
2457 if ((err = pci_enable_device(pdev)) != 0) {
2458 pr_err("Failed to enable card. Err %d\n", -err);
2459 kfree(card);
2460 return err;
2461 }
2462
2463 if ((err = pci_request_regions(pdev, "FarSync")) !=0) {
2464 pr_err("Failed to allocate regions. Err %d\n", -err);
2465 pci_disable_device(pdev);
2466 kfree(card);
2467 return err;
2468 }
2469
2470 /* Get virtual addresses of memory regions */
2471 card->pci_conf = pci_resource_start(pdev, 1);
2472 card->phys_mem = pci_resource_start(pdev, 2);
2473 card->phys_ctlmem = pci_resource_start(pdev, 3);
2474 if ((card->mem = ioremap(card->phys_mem, FST_MEMSIZE)) == NULL) {
2475 pr_err("Physical memory remap failed\n");
2476 pci_release_regions(pdev);
2477 pci_disable_device(pdev);
2478 kfree(card);
2479 return -ENODEV;
2480 }
2481 if ((card->ctlmem = ioremap(card->phys_ctlmem, 0x10)) == NULL) {
2482 pr_err("Control memory remap failed\n");
2483 pci_release_regions(pdev);
2484 pci_disable_device(pdev);
2485 iounmap(card->mem);
2486 kfree(card);
2487 return -ENODEV;
2488 }
2489 dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem);
2490
2491 /* Register the interrupt handler */
2492 if (request_irq(pdev->irq, fst_intr, IRQF_SHARED, FST_DEV_NAME, card)) {
2493 pr_err("Unable to register interrupt %d\n", card->irq);
2494 pci_release_regions(pdev);
2495 pci_disable_device(pdev);
2496 iounmap(card->ctlmem);
2497 iounmap(card->mem);
2498 kfree(card);
2499 return -ENODEV;
2500 }
2501
2502 /* Record info we need */
2503 card->irq = pdev->irq;
2504 card->type = ent->driver_data;
2505 card->family = ((ent->driver_data == FST_TYPE_T2P) ||
2506 (ent->driver_data == FST_TYPE_T4P))
2507 ? FST_FAMILY_TXP : FST_FAMILY_TXU;
2508 if ((ent->driver_data == FST_TYPE_T1U) ||
2509 (ent->driver_data == FST_TYPE_TE1))
2510 card->nports = 1;
2511 else
2512 card->nports = ((ent->driver_data == FST_TYPE_T2P) ||
2513 (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4;
2514
2515 card->state = FST_UNINIT;
2516 spin_lock_init ( &card->card_lock );
2517
2518 for ( i = 0 ; i < card->nports ; i++ ) {
2519 struct net_device *dev = alloc_hdlcdev(&card->ports[i]);
2520 hdlc_device *hdlc;
2521 if (!dev) {
2522 while (i--)
2523 free_netdev(card->ports[i].dev);
2524 pr_err("FarSync: out of memory\n");
2525 free_irq(card->irq, card);
2526 pci_release_regions(pdev);
2527 pci_disable_device(pdev);
2528 iounmap(card->ctlmem);
2529 iounmap(card->mem);
2530 kfree(card);
2531 return -ENODEV;
2532 }
2533 card->ports[i].dev = dev;
2534 card->ports[i].card = card;
2535 card->ports[i].index = i;
2536 card->ports[i].run = 0;
2537
2538 hdlc = dev_to_hdlc(dev);
2539
2540 /* Fill in the net device info */
2541 /* Since this is a PCI setup this is purely
2542 * informational. Give them the buffer addresses
2543 * and basic card I/O.
2544 */
2545 dev->mem_start = card->phys_mem
2546 + BUF_OFFSET ( txBuffer[i][0][0]);
2547 dev->mem_end = card->phys_mem
2548 + BUF_OFFSET ( txBuffer[i][NUM_TX_BUFFER][0]);
2549 dev->base_addr = card->pci_conf;
2550 dev->irq = card->irq;
2551
2552 dev->netdev_ops = &fst_ops;
2553 dev->tx_queue_len = FST_TX_QUEUE_LEN;
2554 dev->watchdog_timeo = FST_TX_TIMEOUT;
2555 hdlc->attach = fst_attach;
2556 hdlc->xmit = fst_start_xmit;
2557 }
2558
2559 card->device = pdev;
2560
2561 dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type,
2562 card->nports, card->irq);
2563 dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n",
2564 card->pci_conf, card->phys_mem, card->phys_ctlmem);
2565
2566 /* Reset the card's processor */
2567 fst_cpureset(card);
2568 card->state = FST_RESET;
2569
2570 /* Initialise DMA (if required) */
2571 fst_init_dma(card);
2572
2573 /* Record driver data for later use */
2574 pci_set_drvdata(pdev, card);
2575
2576 /* Remainder of card setup */
2577 fst_card_array[no_of_cards_added] = card;
2578 card->card_no = no_of_cards_added++; /* Record instance and bump it */
2579 fst_init_card(card);
2580 if (card->family == FST_FAMILY_TXU) {
2581 /*
2582 * Allocate a dma buffer for transmit and receives
2583 */
2584 card->rx_dma_handle_host =
2585 pci_alloc_consistent(card->device, FST_MAX_MTU,
2586 &card->rx_dma_handle_card);
2587 if (card->rx_dma_handle_host == NULL) {
2588 pr_err("Could not allocate rx dma buffer\n");
2589 fst_disable_intr(card);
2590 pci_release_regions(pdev);
2591 pci_disable_device(pdev);
2592 iounmap(card->ctlmem);
2593 iounmap(card->mem);
2594 kfree(card);
2595 return -ENOMEM;
2596 }
2597 card->tx_dma_handle_host =
2598 pci_alloc_consistent(card->device, FST_MAX_MTU,
2599 &card->tx_dma_handle_card);
2600 if (card->tx_dma_handle_host == NULL) {
2601 pr_err("Could not allocate tx dma buffer\n");
2602 fst_disable_intr(card);
2603 pci_release_regions(pdev);
2604 pci_disable_device(pdev);
2605 iounmap(card->ctlmem);
2606 iounmap(card->mem);
2607 kfree(card);
2608 return -ENOMEM;
2609 }
2610 }
2611 return 0; /* Success */
2612}
2613
2614/*
2615 * Cleanup and close down a card
2616 */
2617static void
2618fst_remove_one(struct pci_dev *pdev)
2619{
2620 struct fst_card_info *card;
2621 int i;
2622
2623 card = pci_get_drvdata(pdev);
2624
2625 for (i = 0; i < card->nports; i++) {
2626 struct net_device *dev = port_to_dev(&card->ports[i]);
2627 unregister_hdlc_device(dev);
2628 }
2629
2630 fst_disable_intr(card);
2631 free_irq(card->irq, card);
2632
2633 iounmap(card->ctlmem);
2634 iounmap(card->mem);
2635 pci_release_regions(pdev);
2636 if (card->family == FST_FAMILY_TXU) {
2637 /*
2638 * Free dma buffers
2639 */
2640 pci_free_consistent(card->device, FST_MAX_MTU,
2641 card->rx_dma_handle_host,
2642 card->rx_dma_handle_card);
2643 pci_free_consistent(card->device, FST_MAX_MTU,
2644 card->tx_dma_handle_host,
2645 card->tx_dma_handle_card);
2646 }
2647 fst_card_array[card->card_no] = NULL;
2648}
2649
2650static struct pci_driver fst_driver = {
2651 .name = FST_NAME,
2652 .id_table = fst_pci_dev_id,
2653 .probe = fst_add_one,
2654 .remove = fst_remove_one,
2655 .suspend = NULL,
2656 .resume = NULL,
2657};
2658
2659static int __init
2660fst_init(void)
2661{
2662 int i;
2663
2664 for (i = 0; i < FST_MAX_CARDS; i++)
2665 fst_card_array[i] = NULL;
2666 spin_lock_init(&fst_work_q_lock);
2667 return pci_register_driver(&fst_driver);
2668}
2669
2670static void __exit
2671fst_cleanup_module(void)
2672{
2673 pr_info("FarSync WAN driver unloading\n");
2674 pci_unregister_driver(&fst_driver);
2675}
2676
2677module_init(fst_init);
2678module_exit(fst_cleanup_module);
1/*
2 * FarSync WAN driver for Linux (2.6.x kernel version)
3 *
4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
5 *
6 * Copyright (C) 2001-2004 FarSite Communications Ltd.
7 * www.farsite.co.uk
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 *
14 * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk>
15 * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk>
16 */
17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/version.h>
23#include <linux/pci.h>
24#include <linux/sched.h>
25#include <linux/slab.h>
26#include <linux/ioport.h>
27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <linux/delay.h>
30#include <linux/if.h>
31#include <linux/hdlc.h>
32#include <asm/io.h>
33#include <asm/uaccess.h>
34
35#include "farsync.h"
36
37/*
38 * Module info
39 */
40MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>");
41MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
42MODULE_LICENSE("GPL");
43
44/* Driver configuration and global parameters
45 * ==========================================
46 */
47
48/* Number of ports (per card) and cards supported
49 */
50#define FST_MAX_PORTS 4
51#define FST_MAX_CARDS 32
52
53/* Default parameters for the link
54 */
55#define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is
56 * useful */
57#define FST_TXQ_DEPTH 16 /* This one is for the buffering
58 * of frames on the way down to the card
59 * so that we can keep the card busy
60 * and maximise throughput
61 */
62#define FST_HIGH_WATER_MARK 12 /* Point at which we flow control
63 * network layer */
64#define FST_LOW_WATER_MARK 8 /* Point at which we remove flow
65 * control from network layer */
66#define FST_MAX_MTU 8000 /* Huge but possible */
67#define FST_DEF_MTU 1500 /* Common sane value */
68
69#define FST_TX_TIMEOUT (2*HZ)
70
71#ifdef ARPHRD_RAWHDLC
72#define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */
73#else
74#define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */
75#endif
76
77/*
78 * Modules parameters and associated variables
79 */
80static int fst_txq_low = FST_LOW_WATER_MARK;
81static int fst_txq_high = FST_HIGH_WATER_MARK;
82static int fst_max_reads = 7;
83static int fst_excluded_cards = 0;
84static int fst_excluded_list[FST_MAX_CARDS];
85
86module_param(fst_txq_low, int, 0);
87module_param(fst_txq_high, int, 0);
88module_param(fst_max_reads, int, 0);
89module_param(fst_excluded_cards, int, 0);
90module_param_array(fst_excluded_list, int, NULL, 0);
91
92/* Card shared memory layout
93 * =========================
94 */
95#pragma pack(1)
96
97/* This information is derived in part from the FarSite FarSync Smc.h
98 * file. Unfortunately various name clashes and the non-portability of the
99 * bit field declarations in that file have meant that I have chosen to
100 * recreate the information here.
101 *
102 * The SMC (Shared Memory Configuration) has a version number that is
103 * incremented every time there is a significant change. This number can
104 * be used to check that we have not got out of step with the firmware
105 * contained in the .CDE files.
106 */
107#define SMC_VERSION 24
108
109#define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */
110
111#define SMC_BASE 0x00002000L /* Base offset of the shared memory window main
112 * configuration structure */
113#define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA
114 * buffers */
115
116#define LEN_TX_BUFFER 8192 /* Size of packet buffers */
117#define LEN_RX_BUFFER 8192
118
119#define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */
120#define LEN_SMALL_RX_BUFFER 256
121
122#define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */
123#define NUM_RX_BUFFER 8
124
125/* Interrupt retry time in milliseconds */
126#define INT_RETRY_TIME 2
127
128/* The Am186CH/CC processors support a SmartDMA mode using circular pools
129 * of buffer descriptors. The structure is almost identical to that used
130 * in the LANCE Ethernet controllers. Details available as PDF from the
131 * AMD web site: http://www.amd.com/products/epd/processors/\
132 * 2.16bitcont/3.am186cxfa/a21914/21914.pdf
133 */
134struct txdesc { /* Transmit descriptor */
135 volatile u16 ladr; /* Low order address of packet. This is a
136 * linear address in the Am186 memory space
137 */
138 volatile u8 hadr; /* High order address. Low 4 bits only, high 4
139 * bits must be zero
140 */
141 volatile u8 bits; /* Status and config */
142 volatile u16 bcnt; /* 2s complement of packet size in low 15 bits.
143 * Transmit terminal count interrupt enable in
144 * top bit.
145 */
146 u16 unused; /* Not used in Tx */
147};
148
149struct rxdesc { /* Receive descriptor */
150 volatile u16 ladr; /* Low order address of packet */
151 volatile u8 hadr; /* High order address */
152 volatile u8 bits; /* Status and config */
153 volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits.
154 * Receive terminal count interrupt enable in
155 * top bit.
156 */
157 volatile u16 mcnt; /* Message byte count (15 bits) */
158};
159
160/* Convert a length into the 15 bit 2's complement */
161/* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */
162/* Since we need to set the high bit to enable the completion interrupt this
163 * can be made a lot simpler
164 */
165#define cnv_bcnt(len) (-(len))
166
167/* Status and config bits for the above */
168#define DMA_OWN 0x80 /* SmartDMA owns the descriptor */
169#define TX_STP 0x02 /* Tx: start of packet */
170#define TX_ENP 0x01 /* Tx: end of packet */
171#define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */
172#define RX_FRAM 0x20 /* Rx: framing error */
173#define RX_OFLO 0x10 /* Rx: overflow error */
174#define RX_CRC 0x08 /* Rx: CRC error */
175#define RX_HBUF 0x04 /* Rx: buffer error */
176#define RX_STP 0x02 /* Rx: start of packet */
177#define RX_ENP 0x01 /* Rx: end of packet */
178
179/* Interrupts from the card are caused by various events which are presented
180 * in a circular buffer as several events may be processed on one physical int
181 */
182#define MAX_CIRBUFF 32
183
184struct cirbuff {
185 u8 rdindex; /* read, then increment and wrap */
186 u8 wrindex; /* write, then increment and wrap */
187 u8 evntbuff[MAX_CIRBUFF];
188};
189
190/* Interrupt event codes.
191 * Where appropriate the two low order bits indicate the port number
192 */
193#define CTLA_CHG 0x18 /* Control signal changed */
194#define CTLB_CHG 0x19
195#define CTLC_CHG 0x1A
196#define CTLD_CHG 0x1B
197
198#define INIT_CPLT 0x20 /* Initialisation complete */
199#define INIT_FAIL 0x21 /* Initialisation failed */
200
201#define ABTA_SENT 0x24 /* Abort sent */
202#define ABTB_SENT 0x25
203#define ABTC_SENT 0x26
204#define ABTD_SENT 0x27
205
206#define TXA_UNDF 0x28 /* Transmission underflow */
207#define TXB_UNDF 0x29
208#define TXC_UNDF 0x2A
209#define TXD_UNDF 0x2B
210
211#define F56_INT 0x2C
212#define M32_INT 0x2D
213
214#define TE1_ALMA 0x30
215
216/* Port physical configuration. See farsync.h for field values */
217struct port_cfg {
218 u16 lineInterface; /* Physical interface type */
219 u8 x25op; /* Unused at present */
220 u8 internalClock; /* 1 => internal clock, 0 => external */
221 u8 transparentMode; /* 1 => on, 0 => off */
222 u8 invertClock; /* 0 => normal, 1 => inverted */
223 u8 padBytes[6]; /* Padding */
224 u32 lineSpeed; /* Speed in bps */
225};
226
227/* TE1 port physical configuration */
228struct su_config {
229 u32 dataRate;
230 u8 clocking;
231 u8 framing;
232 u8 structure;
233 u8 interface;
234 u8 coding;
235 u8 lineBuildOut;
236 u8 equalizer;
237 u8 transparentMode;
238 u8 loopMode;
239 u8 range;
240 u8 txBufferMode;
241 u8 rxBufferMode;
242 u8 startingSlot;
243 u8 losThreshold;
244 u8 enableIdleCode;
245 u8 idleCode;
246 u8 spare[44];
247};
248
249/* TE1 Status */
250struct su_status {
251 u32 receiveBufferDelay;
252 u32 framingErrorCount;
253 u32 codeViolationCount;
254 u32 crcErrorCount;
255 u32 lineAttenuation;
256 u8 portStarted;
257 u8 lossOfSignal;
258 u8 receiveRemoteAlarm;
259 u8 alarmIndicationSignal;
260 u8 spare[40];
261};
262
263/* Finally sling all the above together into the shared memory structure.
264 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been
265 * evolving under NT for some time so I guess we're stuck with it.
266 * The structure starts at offset SMC_BASE.
267 * See farsync.h for some field values.
268 */
269struct fst_shared {
270 /* DMA descriptor rings */
271 struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER];
272 struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER];
273
274 /* Obsolete small buffers */
275 u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER];
276 u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER];
277
278 u8 taskStatus; /* 0x00 => initialising, 0x01 => running,
279 * 0xFF => halted
280 */
281
282 u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt,
283 * set to 0xEE by host to acknowledge interrupt
284 */
285
286 u16 smcVersion; /* Must match SMC_VERSION */
287
288 u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major
289 * version, RR = revision and BB = build
290 */
291
292 u16 txa_done; /* Obsolete completion flags */
293 u16 rxa_done;
294 u16 txb_done;
295 u16 rxb_done;
296 u16 txc_done;
297 u16 rxc_done;
298 u16 txd_done;
299 u16 rxd_done;
300
301 u16 mailbox[4]; /* Diagnostics mailbox. Not used */
302
303 struct cirbuff interruptEvent; /* interrupt causes */
304
305 u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */
306 u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */
307
308 struct port_cfg portConfig[FST_MAX_PORTS];
309
310 u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */
311
312 u16 cableStatus; /* lsb: 0=> present, 1=> absent */
313
314 u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */
315 u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */
316
317 u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */
318 u16 cardMailbox[4]; /* Not used */
319
320 /* Number of times the card thinks the host has
321 * missed an interrupt by not acknowledging
322 * within 2mS (I guess NT has problems)
323 */
324 u32 interruptRetryCount;
325
326 /* Driver private data used as an ID. We'll not
327 * use this as I'd rather keep such things
328 * in main memory rather than on the PCI bus
329 */
330 u32 portHandle[FST_MAX_PORTS];
331
332 /* Count of Tx underflows for stats */
333 u32 transmitBufferUnderflow[FST_MAX_PORTS];
334
335 /* Debounced V.24 control input status */
336 u32 v24DebouncedSts[FST_MAX_PORTS];
337
338 /* Adapter debounce timers. Don't touch */
339 u32 ctsTimer[FST_MAX_PORTS];
340 u32 ctsTimerRun[FST_MAX_PORTS];
341 u32 dcdTimer[FST_MAX_PORTS];
342 u32 dcdTimerRun[FST_MAX_PORTS];
343
344 u32 numberOfPorts; /* Number of ports detected at startup */
345
346 u16 _reserved[64];
347
348 u16 cardMode; /* Bit-mask to enable features:
349 * Bit 0: 1 enables LED identify mode
350 */
351
352 u16 portScheduleOffset;
353
354 struct su_config suConfig; /* TE1 Bits */
355 struct su_status suStatus;
356
357 u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of
358 * the structure and marks the end of shared
359 * memory. Adapter code initializes it as
360 * END_SIG.
361 */
362};
363
364/* endOfSmcSignature value */
365#define END_SIG 0x12345678
366
367/* Mailbox values. (portMailbox) */
368#define NOP 0 /* No operation */
369#define ACK 1 /* Positive acknowledgement to PC driver */
370#define NAK 2 /* Negative acknowledgement to PC driver */
371#define STARTPORT 3 /* Start an HDLC port */
372#define STOPPORT 4 /* Stop an HDLC port */
373#define ABORTTX 5 /* Abort the transmitter for a port */
374#define SETV24O 6 /* Set V24 outputs */
375
376/* PLX Chip Register Offsets */
377#define CNTRL_9052 0x50 /* Control Register */
378#define CNTRL_9054 0x6c /* Control Register */
379
380#define INTCSR_9052 0x4c /* Interrupt control/status register */
381#define INTCSR_9054 0x68 /* Interrupt control/status register */
382
383/* 9054 DMA Registers */
384/*
385 * Note that we will be using DMA Channel 0 for copying rx data
386 * and Channel 1 for copying tx data
387 */
388#define DMAMODE0 0x80
389#define DMAPADR0 0x84
390#define DMALADR0 0x88
391#define DMASIZ0 0x8c
392#define DMADPR0 0x90
393#define DMAMODE1 0x94
394#define DMAPADR1 0x98
395#define DMALADR1 0x9c
396#define DMASIZ1 0xa0
397#define DMADPR1 0xa4
398#define DMACSR0 0xa8
399#define DMACSR1 0xa9
400#define DMAARB 0xac
401#define DMATHR 0xb0
402#define DMADAC0 0xb4
403#define DMADAC1 0xb8
404#define DMAMARBR 0xac
405
406#define FST_MIN_DMA_LEN 64
407#define FST_RX_DMA_INT 0x01
408#define FST_TX_DMA_INT 0x02
409#define FST_CARD_INT 0x04
410
411/* Larger buffers are positioned in memory at offset BFM_BASE */
412struct buf_window {
413 u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER];
414 u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER];
415};
416
417/* Calculate offset of a buffer object within the shared memory window */
418#define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X))
419
420#pragma pack()
421
422/* Device driver private information
423 * =================================
424 */
425/* Per port (line or channel) information
426 */
427struct fst_port_info {
428 struct net_device *dev; /* Device struct - must be first */
429 struct fst_card_info *card; /* Card we're associated with */
430 int index; /* Port index on the card */
431 int hwif; /* Line hardware (lineInterface copy) */
432 int run; /* Port is running */
433 int mode; /* Normal or FarSync raw */
434 int rxpos; /* Next Rx buffer to use */
435 int txpos; /* Next Tx buffer to use */
436 int txipos; /* Next Tx buffer to check for free */
437 int start; /* Indication of start/stop to network */
438 /*
439 * A sixteen entry transmit queue
440 */
441 int txqs; /* index to get next buffer to tx */
442 int txqe; /* index to queue next packet */
443 struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */
444 int rxqdepth;
445};
446
447/* Per card information
448 */
449struct fst_card_info {
450 char __iomem *mem; /* Card memory mapped to kernel space */
451 char __iomem *ctlmem; /* Control memory for PCI cards */
452 unsigned int phys_mem; /* Physical memory window address */
453 unsigned int phys_ctlmem; /* Physical control memory address */
454 unsigned int irq; /* Interrupt request line number */
455 unsigned int nports; /* Number of serial ports */
456 unsigned int type; /* Type index of card */
457 unsigned int state; /* State of card */
458 spinlock_t card_lock; /* Lock for SMP access */
459 unsigned short pci_conf; /* PCI card config in I/O space */
460 /* Per port info */
461 struct fst_port_info ports[FST_MAX_PORTS];
462 struct pci_dev *device; /* Information about the pci device */
463 int card_no; /* Inst of the card on the system */
464 int family; /* TxP or TxU */
465 int dmarx_in_progress;
466 int dmatx_in_progress;
467 unsigned long int_count;
468 unsigned long int_time_ave;
469 void *rx_dma_handle_host;
470 dma_addr_t rx_dma_handle_card;
471 void *tx_dma_handle_host;
472 dma_addr_t tx_dma_handle_card;
473 struct sk_buff *dma_skb_rx;
474 struct fst_port_info *dma_port_rx;
475 struct fst_port_info *dma_port_tx;
476 int dma_len_rx;
477 int dma_len_tx;
478 int dma_txpos;
479 int dma_rxpos;
480};
481
482/* Convert an HDLC device pointer into a port info pointer and similar */
483#define dev_to_port(D) (dev_to_hdlc(D)->priv)
484#define port_to_dev(P) ((P)->dev)
485
486
487/*
488 * Shared memory window access macros
489 *
490 * We have a nice memory based structure above, which could be directly
491 * mapped on i386 but might not work on other architectures unless we use
492 * the readb,w,l and writeb,w,l macros. Unfortunately these macros take
493 * physical offsets so we have to convert. The only saving grace is that
494 * this should all collapse back to a simple indirection eventually.
495 */
496#define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X))
497
498#define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E))
499#define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E))
500#define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E))
501
502#define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E))
503#define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E))
504#define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E))
505
506/*
507 * Debug support
508 */
509#if FST_DEBUG
510
511static int fst_debug_mask = { FST_DEBUG };
512
513/* Most common debug activity is to print something if the corresponding bit
514 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to
515 * support variable numbers of macro parameters. The inverted if prevents us
516 * eating someone else's else clause.
517 */
518#define dbg(F, fmt, args...) \
519do { \
520 if (fst_debug_mask & (F)) \
521 printk(KERN_DEBUG pr_fmt(fmt), ##args); \
522} while (0)
523#else
524#define dbg(F, fmt, args...) \
525do { \
526 if (0) \
527 printk(KERN_DEBUG pr_fmt(fmt), ##args); \
528} while (0)
529#endif
530
531/*
532 * PCI ID lookup table
533 */
534static const struct pci_device_id fst_pci_dev_id[] = {
535 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID,
536 PCI_ANY_ID, 0, 0, FST_TYPE_T2P},
537
538 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID,
539 PCI_ANY_ID, 0, 0, FST_TYPE_T4P},
540
541 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID,
542 PCI_ANY_ID, 0, 0, FST_TYPE_T1U},
543
544 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID,
545 PCI_ANY_ID, 0, 0, FST_TYPE_T2U},
546
547 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID,
548 PCI_ANY_ID, 0, 0, FST_TYPE_T4U},
549
550 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID,
551 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
552
553 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID,
554 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
555 {0,} /* End */
556};
557
558MODULE_DEVICE_TABLE(pci, fst_pci_dev_id);
559
560/*
561 * Device Driver Work Queues
562 *
563 * So that we don't spend too much time processing events in the
564 * Interrupt Service routine, we will declare a work queue per Card
565 * and make the ISR schedule a task in the queue for later execution.
566 * In the 2.4 Kernel we used to use the immediate queue for BH's
567 * Now that they are gone, tasklets seem to be much better than work
568 * queues.
569 */
570
571static void do_bottom_half_tx(struct fst_card_info *card);
572static void do_bottom_half_rx(struct fst_card_info *card);
573static void fst_process_tx_work_q(unsigned long work_q);
574static void fst_process_int_work_q(unsigned long work_q);
575
576static DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q, 0);
577static DECLARE_TASKLET(fst_int_task, fst_process_int_work_q, 0);
578
579static struct fst_card_info *fst_card_array[FST_MAX_CARDS];
580static spinlock_t fst_work_q_lock;
581static u64 fst_work_txq;
582static u64 fst_work_intq;
583
584static void
585fst_q_work_item(u64 * queue, int card_index)
586{
587 unsigned long flags;
588 u64 mask;
589
590 /*
591 * Grab the queue exclusively
592 */
593 spin_lock_irqsave(&fst_work_q_lock, flags);
594
595 /*
596 * Making an entry in the queue is simply a matter of setting
597 * a bit for the card indicating that there is work to do in the
598 * bottom half for the card. Note the limitation of 64 cards.
599 * That ought to be enough
600 */
601 mask = (u64)1 << card_index;
602 *queue |= mask;
603 spin_unlock_irqrestore(&fst_work_q_lock, flags);
604}
605
606static void
607fst_process_tx_work_q(unsigned long /*void **/work_q)
608{
609 unsigned long flags;
610 u64 work_txq;
611 int i;
612
613 /*
614 * Grab the queue exclusively
615 */
616 dbg(DBG_TX, "fst_process_tx_work_q\n");
617 spin_lock_irqsave(&fst_work_q_lock, flags);
618 work_txq = fst_work_txq;
619 fst_work_txq = 0;
620 spin_unlock_irqrestore(&fst_work_q_lock, flags);
621
622 /*
623 * Call the bottom half for each card with work waiting
624 */
625 for (i = 0; i < FST_MAX_CARDS; i++) {
626 if (work_txq & 0x01) {
627 if (fst_card_array[i] != NULL) {
628 dbg(DBG_TX, "Calling tx bh for card %d\n", i);
629 do_bottom_half_tx(fst_card_array[i]);
630 }
631 }
632 work_txq = work_txq >> 1;
633 }
634}
635
636static void
637fst_process_int_work_q(unsigned long /*void **/work_q)
638{
639 unsigned long flags;
640 u64 work_intq;
641 int i;
642
643 /*
644 * Grab the queue exclusively
645 */
646 dbg(DBG_INTR, "fst_process_int_work_q\n");
647 spin_lock_irqsave(&fst_work_q_lock, flags);
648 work_intq = fst_work_intq;
649 fst_work_intq = 0;
650 spin_unlock_irqrestore(&fst_work_q_lock, flags);
651
652 /*
653 * Call the bottom half for each card with work waiting
654 */
655 for (i = 0; i < FST_MAX_CARDS; i++) {
656 if (work_intq & 0x01) {
657 if (fst_card_array[i] != NULL) {
658 dbg(DBG_INTR,
659 "Calling rx & tx bh for card %d\n", i);
660 do_bottom_half_rx(fst_card_array[i]);
661 do_bottom_half_tx(fst_card_array[i]);
662 }
663 }
664 work_intq = work_intq >> 1;
665 }
666}
667
668/* Card control functions
669 * ======================
670 */
671/* Place the processor in reset state
672 *
673 * Used to be a simple write to card control space but a glitch in the latest
674 * AMD Am186CH processor means that we now have to do it by asserting and de-
675 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register
676 * at offset 9052_CNTRL. Note the updates for the TXU.
677 */
678static inline void
679fst_cpureset(struct fst_card_info *card)
680{
681 unsigned char interrupt_line_register;
682 unsigned int regval;
683
684 if (card->family == FST_FAMILY_TXU) {
685 if (pci_read_config_byte
686 (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) {
687 dbg(DBG_ASS,
688 "Error in reading interrupt line register\n");
689 }
690 /*
691 * Assert PLX software reset and Am186 hardware reset
692 * and then deassert the PLX software reset but 186 still in reset
693 */
694 outw(0x440f, card->pci_conf + CNTRL_9054 + 2);
695 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
696 /*
697 * We are delaying here to allow the 9054 to reset itself
698 */
699 usleep_range(10, 20);
700 outw(0x240f, card->pci_conf + CNTRL_9054 + 2);
701 /*
702 * We are delaying here to allow the 9054 to reload its eeprom
703 */
704 usleep_range(10, 20);
705 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
706
707 if (pci_write_config_byte
708 (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) {
709 dbg(DBG_ASS,
710 "Error in writing interrupt line register\n");
711 }
712
713 } else {
714 regval = inl(card->pci_conf + CNTRL_9052);
715
716 outl(regval | 0x40000000, card->pci_conf + CNTRL_9052);
717 outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052);
718 }
719}
720
721/* Release the processor from reset
722 */
723static inline void
724fst_cpurelease(struct fst_card_info *card)
725{
726 if (card->family == FST_FAMILY_TXU) {
727 /*
728 * Force posted writes to complete
729 */
730 (void) readb(card->mem);
731
732 /*
733 * Release LRESET DO = 1
734 * Then release Local Hold, DO = 1
735 */
736 outw(0x040e, card->pci_conf + CNTRL_9054 + 2);
737 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
738 } else {
739 (void) readb(card->ctlmem);
740 }
741}
742
743/* Clear the cards interrupt flag
744 */
745static inline void
746fst_clear_intr(struct fst_card_info *card)
747{
748 if (card->family == FST_FAMILY_TXU) {
749 (void) readb(card->ctlmem);
750 } else {
751 /* Poke the appropriate PLX chip register (same as enabling interrupts)
752 */
753 outw(0x0543, card->pci_conf + INTCSR_9052);
754 }
755}
756
757/* Enable card interrupts
758 */
759static inline void
760fst_enable_intr(struct fst_card_info *card)
761{
762 if (card->family == FST_FAMILY_TXU) {
763 outl(0x0f0c0900, card->pci_conf + INTCSR_9054);
764 } else {
765 outw(0x0543, card->pci_conf + INTCSR_9052);
766 }
767}
768
769/* Disable card interrupts
770 */
771static inline void
772fst_disable_intr(struct fst_card_info *card)
773{
774 if (card->family == FST_FAMILY_TXU) {
775 outl(0x00000000, card->pci_conf + INTCSR_9054);
776 } else {
777 outw(0x0000, card->pci_conf + INTCSR_9052);
778 }
779}
780
781/* Process the result of trying to pass a received frame up the stack
782 */
783static void
784fst_process_rx_status(int rx_status, char *name)
785{
786 switch (rx_status) {
787 case NET_RX_SUCCESS:
788 {
789 /*
790 * Nothing to do here
791 */
792 break;
793 }
794 case NET_RX_DROP:
795 {
796 dbg(DBG_ASS, "%s: Received packet dropped\n", name);
797 break;
798 }
799 }
800}
801
802/* Initilaise DMA for PLX 9054
803 */
804static inline void
805fst_init_dma(struct fst_card_info *card)
806{
807 /*
808 * This is only required for the PLX 9054
809 */
810 if (card->family == FST_FAMILY_TXU) {
811 pci_set_master(card->device);
812 outl(0x00020441, card->pci_conf + DMAMODE0);
813 outl(0x00020441, card->pci_conf + DMAMODE1);
814 outl(0x0, card->pci_conf + DMATHR);
815 }
816}
817
818/* Tx dma complete interrupt
819 */
820static void
821fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
822 int len, int txpos)
823{
824 struct net_device *dev = port_to_dev(port);
825
826 /*
827 * Everything is now set, just tell the card to go
828 */
829 dbg(DBG_TX, "fst_tx_dma_complete\n");
830 FST_WRB(card, txDescrRing[port->index][txpos].bits,
831 DMA_OWN | TX_STP | TX_ENP);
832 dev->stats.tx_packets++;
833 dev->stats.tx_bytes += len;
834 dev->trans_start = jiffies;
835}
836
837/*
838 * Mark it for our own raw sockets interface
839 */
840static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev)
841{
842 skb->dev = dev;
843 skb_reset_mac_header(skb);
844 skb->pkt_type = PACKET_HOST;
845 return htons(ETH_P_CUST);
846}
847
848/* Rx dma complete interrupt
849 */
850static void
851fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
852 int len, struct sk_buff *skb, int rxp)
853{
854 struct net_device *dev = port_to_dev(port);
855 int pi;
856 int rx_status;
857
858 dbg(DBG_TX, "fst_rx_dma_complete\n");
859 pi = port->index;
860 memcpy(skb_put(skb, len), card->rx_dma_handle_host, len);
861
862 /* Reset buffer descriptor */
863 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
864
865 /* Update stats */
866 dev->stats.rx_packets++;
867 dev->stats.rx_bytes += len;
868
869 /* Push upstream */
870 dbg(DBG_RX, "Pushing the frame up the stack\n");
871 if (port->mode == FST_RAW)
872 skb->protocol = farsync_type_trans(skb, dev);
873 else
874 skb->protocol = hdlc_type_trans(skb, dev);
875 rx_status = netif_rx(skb);
876 fst_process_rx_status(rx_status, port_to_dev(port)->name);
877 if (rx_status == NET_RX_DROP)
878 dev->stats.rx_dropped++;
879}
880
881/*
882 * Receive a frame through the DMA
883 */
884static inline void
885fst_rx_dma(struct fst_card_info *card, dma_addr_t dma, u32 mem, int len)
886{
887 /*
888 * This routine will setup the DMA and start it
889 */
890
891 dbg(DBG_RX, "In fst_rx_dma %x %x %d\n", (u32)dma, mem, len);
892 if (card->dmarx_in_progress) {
893 dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n");
894 }
895
896 outl(dma, card->pci_conf + DMAPADR0); /* Copy to here */
897 outl(mem, card->pci_conf + DMALADR0); /* from here */
898 outl(len, card->pci_conf + DMASIZ0); /* for this length */
899 outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */
900
901 /*
902 * We use the dmarx_in_progress flag to flag the channel as busy
903 */
904 card->dmarx_in_progress = 1;
905 outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */
906}
907
908/*
909 * Send a frame through the DMA
910 */
911static inline void
912fst_tx_dma(struct fst_card_info *card, dma_addr_t dma, u32 mem, int len)
913{
914 /*
915 * This routine will setup the DMA and start it.
916 */
917
918 dbg(DBG_TX, "In fst_tx_dma %x %x %d\n", (u32)dma, mem, len);
919 if (card->dmatx_in_progress) {
920 dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n");
921 }
922
923 outl(dma, card->pci_conf + DMAPADR1); /* Copy from here */
924 outl(mem, card->pci_conf + DMALADR1); /* to here */
925 outl(len, card->pci_conf + DMASIZ1); /* for this length */
926 outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */
927
928 /*
929 * We use the dmatx_in_progress to flag the channel as busy
930 */
931 card->dmatx_in_progress = 1;
932 outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */
933}
934
935/* Issue a Mailbox command for a port.
936 * Note we issue them on a fire and forget basis, not expecting to see an
937 * error and not waiting for completion.
938 */
939static void
940fst_issue_cmd(struct fst_port_info *port, unsigned short cmd)
941{
942 struct fst_card_info *card;
943 unsigned short mbval;
944 unsigned long flags;
945 int safety;
946
947 card = port->card;
948 spin_lock_irqsave(&card->card_lock, flags);
949 mbval = FST_RDW(card, portMailbox[port->index][0]);
950
951 safety = 0;
952 /* Wait for any previous command to complete */
953 while (mbval > NAK) {
954 spin_unlock_irqrestore(&card->card_lock, flags);
955 schedule_timeout_uninterruptible(1);
956 spin_lock_irqsave(&card->card_lock, flags);
957
958 if (++safety > 2000) {
959 pr_err("Mailbox safety timeout\n");
960 break;
961 }
962
963 mbval = FST_RDW(card, portMailbox[port->index][0]);
964 }
965 if (safety > 0) {
966 dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety);
967 }
968 if (mbval == NAK) {
969 dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n");
970 }
971
972 FST_WRW(card, portMailbox[port->index][0], cmd);
973
974 if (cmd == ABORTTX || cmd == STARTPORT) {
975 port->txpos = 0;
976 port->txipos = 0;
977 port->start = 0;
978 }
979
980 spin_unlock_irqrestore(&card->card_lock, flags);
981}
982
983/* Port output signals control
984 */
985static inline void
986fst_op_raise(struct fst_port_info *port, unsigned int outputs)
987{
988 outputs |= FST_RDL(port->card, v24OpSts[port->index]);
989 FST_WRL(port->card, v24OpSts[port->index], outputs);
990
991 if (port->run)
992 fst_issue_cmd(port, SETV24O);
993}
994
995static inline void
996fst_op_lower(struct fst_port_info *port, unsigned int outputs)
997{
998 outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]);
999 FST_WRL(port->card, v24OpSts[port->index], outputs);
1000
1001 if (port->run)
1002 fst_issue_cmd(port, SETV24O);
1003}
1004
1005/*
1006 * Setup port Rx buffers
1007 */
1008static void
1009fst_rx_config(struct fst_port_info *port)
1010{
1011 int i;
1012 int pi;
1013 unsigned int offset;
1014 unsigned long flags;
1015 struct fst_card_info *card;
1016
1017 pi = port->index;
1018 card = port->card;
1019 spin_lock_irqsave(&card->card_lock, flags);
1020 for (i = 0; i < NUM_RX_BUFFER; i++) {
1021 offset = BUF_OFFSET(rxBuffer[pi][i][0]);
1022
1023 FST_WRW(card, rxDescrRing[pi][i].ladr, (u16) offset);
1024 FST_WRB(card, rxDescrRing[pi][i].hadr, (u8) (offset >> 16));
1025 FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER));
1026 FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER);
1027 FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN);
1028 }
1029 port->rxpos = 0;
1030 spin_unlock_irqrestore(&card->card_lock, flags);
1031}
1032
1033/*
1034 * Setup port Tx buffers
1035 */
1036static void
1037fst_tx_config(struct fst_port_info *port)
1038{
1039 int i;
1040 int pi;
1041 unsigned int offset;
1042 unsigned long flags;
1043 struct fst_card_info *card;
1044
1045 pi = port->index;
1046 card = port->card;
1047 spin_lock_irqsave(&card->card_lock, flags);
1048 for (i = 0; i < NUM_TX_BUFFER; i++) {
1049 offset = BUF_OFFSET(txBuffer[pi][i][0]);
1050
1051 FST_WRW(card, txDescrRing[pi][i].ladr, (u16) offset);
1052 FST_WRB(card, txDescrRing[pi][i].hadr, (u8) (offset >> 16));
1053 FST_WRW(card, txDescrRing[pi][i].bcnt, 0);
1054 FST_WRB(card, txDescrRing[pi][i].bits, 0);
1055 }
1056 port->txpos = 0;
1057 port->txipos = 0;
1058 port->start = 0;
1059 spin_unlock_irqrestore(&card->card_lock, flags);
1060}
1061
1062/* TE1 Alarm change interrupt event
1063 */
1064static void
1065fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port)
1066{
1067 u8 los;
1068 u8 rra;
1069 u8 ais;
1070
1071 los = FST_RDB(card, suStatus.lossOfSignal);
1072 rra = FST_RDB(card, suStatus.receiveRemoteAlarm);
1073 ais = FST_RDB(card, suStatus.alarmIndicationSignal);
1074
1075 if (los) {
1076 /*
1077 * Lost the link
1078 */
1079 if (netif_carrier_ok(port_to_dev(port))) {
1080 dbg(DBG_INTR, "Net carrier off\n");
1081 netif_carrier_off(port_to_dev(port));
1082 }
1083 } else {
1084 /*
1085 * Link available
1086 */
1087 if (!netif_carrier_ok(port_to_dev(port))) {
1088 dbg(DBG_INTR, "Net carrier on\n");
1089 netif_carrier_on(port_to_dev(port));
1090 }
1091 }
1092
1093 if (los)
1094 dbg(DBG_INTR, "Assert LOS Alarm\n");
1095 else
1096 dbg(DBG_INTR, "De-assert LOS Alarm\n");
1097 if (rra)
1098 dbg(DBG_INTR, "Assert RRA Alarm\n");
1099 else
1100 dbg(DBG_INTR, "De-assert RRA Alarm\n");
1101
1102 if (ais)
1103 dbg(DBG_INTR, "Assert AIS Alarm\n");
1104 else
1105 dbg(DBG_INTR, "De-assert AIS Alarm\n");
1106}
1107
1108/* Control signal change interrupt event
1109 */
1110static void
1111fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port)
1112{
1113 int signals;
1114
1115 signals = FST_RDL(card, v24DebouncedSts[port->index]);
1116
1117 if (signals & (((port->hwif == X21) || (port->hwif == X21D))
1118 ? IPSTS_INDICATE : IPSTS_DCD)) {
1119 if (!netif_carrier_ok(port_to_dev(port))) {
1120 dbg(DBG_INTR, "DCD active\n");
1121 netif_carrier_on(port_to_dev(port));
1122 }
1123 } else {
1124 if (netif_carrier_ok(port_to_dev(port))) {
1125 dbg(DBG_INTR, "DCD lost\n");
1126 netif_carrier_off(port_to_dev(port));
1127 }
1128 }
1129}
1130
1131/* Log Rx Errors
1132 */
1133static void
1134fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1135 unsigned char dmabits, int rxp, unsigned short len)
1136{
1137 struct net_device *dev = port_to_dev(port);
1138
1139 /*
1140 * Increment the appropriate error counter
1141 */
1142 dev->stats.rx_errors++;
1143 if (dmabits & RX_OFLO) {
1144 dev->stats.rx_fifo_errors++;
1145 dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n",
1146 card->card_no, port->index, rxp);
1147 }
1148 if (dmabits & RX_CRC) {
1149 dev->stats.rx_crc_errors++;
1150 dbg(DBG_ASS, "Rx crc error on card %d port %d\n",
1151 card->card_no, port->index);
1152 }
1153 if (dmabits & RX_FRAM) {
1154 dev->stats.rx_frame_errors++;
1155 dbg(DBG_ASS, "Rx frame error on card %d port %d\n",
1156 card->card_no, port->index);
1157 }
1158 if (dmabits == (RX_STP | RX_ENP)) {
1159 dev->stats.rx_length_errors++;
1160 dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n",
1161 len, card->card_no, port->index);
1162 }
1163}
1164
1165/* Rx Error Recovery
1166 */
1167static void
1168fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1169 unsigned char dmabits, int rxp, unsigned short len)
1170{
1171 int i;
1172 int pi;
1173
1174 pi = port->index;
1175 /*
1176 * Discard buffer descriptors until we see the start of the
1177 * next frame. Note that for long frames this could be in
1178 * a subsequent interrupt.
1179 */
1180 i = 0;
1181 while ((dmabits & (DMA_OWN | RX_STP)) == 0) {
1182 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1183 rxp = (rxp+1) % NUM_RX_BUFFER;
1184 if (++i > NUM_RX_BUFFER) {
1185 dbg(DBG_ASS, "intr_rx: Discarding more bufs"
1186 " than we have\n");
1187 break;
1188 }
1189 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1190 dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits);
1191 }
1192 dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i);
1193
1194 /* Discard the terminal buffer */
1195 if (!(dmabits & DMA_OWN)) {
1196 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1197 rxp = (rxp+1) % NUM_RX_BUFFER;
1198 }
1199 port->rxpos = rxp;
1200 return;
1201
1202}
1203
1204/* Rx complete interrupt
1205 */
1206static void
1207fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port)
1208{
1209 unsigned char dmabits;
1210 int pi;
1211 int rxp;
1212 int rx_status;
1213 unsigned short len;
1214 struct sk_buff *skb;
1215 struct net_device *dev = port_to_dev(port);
1216
1217 /* Check we have a buffer to process */
1218 pi = port->index;
1219 rxp = port->rxpos;
1220 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1221 if (dmabits & DMA_OWN) {
1222 dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n",
1223 pi, rxp);
1224 return;
1225 }
1226 if (card->dmarx_in_progress) {
1227 return;
1228 }
1229
1230 /* Get buffer length */
1231 len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt);
1232 /* Discard the CRC */
1233 len -= 2;
1234 if (len == 0) {
1235 /*
1236 * This seems to happen on the TE1 interface sometimes
1237 * so throw the frame away and log the event.
1238 */
1239 pr_err("Frame received with 0 length. Card %d Port %d\n",
1240 card->card_no, port->index);
1241 /* Return descriptor to card */
1242 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1243
1244 rxp = (rxp+1) % NUM_RX_BUFFER;
1245 port->rxpos = rxp;
1246 return;
1247 }
1248
1249 /* Check buffer length and for other errors. We insist on one packet
1250 * in one buffer. This simplifies things greatly and since we've
1251 * allocated 8K it shouldn't be a real world limitation
1252 */
1253 dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len);
1254 if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) {
1255 fst_log_rx_error(card, port, dmabits, rxp, len);
1256 fst_recover_rx_error(card, port, dmabits, rxp, len);
1257 return;
1258 }
1259
1260 /* Allocate SKB */
1261 if ((skb = dev_alloc_skb(len)) == NULL) {
1262 dbg(DBG_RX, "intr_rx: can't allocate buffer\n");
1263
1264 dev->stats.rx_dropped++;
1265
1266 /* Return descriptor to card */
1267 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1268
1269 rxp = (rxp+1) % NUM_RX_BUFFER;
1270 port->rxpos = rxp;
1271 return;
1272 }
1273
1274 /*
1275 * We know the length we need to receive, len.
1276 * It's not worth using the DMA for reads of less than
1277 * FST_MIN_DMA_LEN
1278 */
1279
1280 if ((len < FST_MIN_DMA_LEN) || (card->family == FST_FAMILY_TXP)) {
1281 memcpy_fromio(skb_put(skb, len),
1282 card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]),
1283 len);
1284
1285 /* Reset buffer descriptor */
1286 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1287
1288 /* Update stats */
1289 dev->stats.rx_packets++;
1290 dev->stats.rx_bytes += len;
1291
1292 /* Push upstream */
1293 dbg(DBG_RX, "Pushing frame up the stack\n");
1294 if (port->mode == FST_RAW)
1295 skb->protocol = farsync_type_trans(skb, dev);
1296 else
1297 skb->protocol = hdlc_type_trans(skb, dev);
1298 rx_status = netif_rx(skb);
1299 fst_process_rx_status(rx_status, port_to_dev(port)->name);
1300 if (rx_status == NET_RX_DROP)
1301 dev->stats.rx_dropped++;
1302 } else {
1303 card->dma_skb_rx = skb;
1304 card->dma_port_rx = port;
1305 card->dma_len_rx = len;
1306 card->dma_rxpos = rxp;
1307 fst_rx_dma(card, card->rx_dma_handle_card,
1308 BUF_OFFSET(rxBuffer[pi][rxp][0]), len);
1309 }
1310 if (rxp != port->rxpos) {
1311 dbg(DBG_ASS, "About to increment rxpos by more than 1\n");
1312 dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos);
1313 }
1314 rxp = (rxp+1) % NUM_RX_BUFFER;
1315 port->rxpos = rxp;
1316}
1317
1318/*
1319 * The bottom halfs to the ISR
1320 *
1321 */
1322
1323static void
1324do_bottom_half_tx(struct fst_card_info *card)
1325{
1326 struct fst_port_info *port;
1327 int pi;
1328 int txq_length;
1329 struct sk_buff *skb;
1330 unsigned long flags;
1331 struct net_device *dev;
1332
1333 /*
1334 * Find a free buffer for the transmit
1335 * Step through each port on this card
1336 */
1337
1338 dbg(DBG_TX, "do_bottom_half_tx\n");
1339 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1340 if (!port->run)
1341 continue;
1342
1343 dev = port_to_dev(port);
1344 while (!(FST_RDB(card, txDescrRing[pi][port->txpos].bits) &
1345 DMA_OWN) &&
1346 !(card->dmatx_in_progress)) {
1347 /*
1348 * There doesn't seem to be a txdone event per-se
1349 * We seem to have to deduce it, by checking the DMA_OWN
1350 * bit on the next buffer we think we can use
1351 */
1352 spin_lock_irqsave(&card->card_lock, flags);
1353 if ((txq_length = port->txqe - port->txqs) < 0) {
1354 /*
1355 * This is the case where one has wrapped and the
1356 * maths gives us a negative number
1357 */
1358 txq_length = txq_length + FST_TXQ_DEPTH;
1359 }
1360 spin_unlock_irqrestore(&card->card_lock, flags);
1361 if (txq_length > 0) {
1362 /*
1363 * There is something to send
1364 */
1365 spin_lock_irqsave(&card->card_lock, flags);
1366 skb = port->txq[port->txqs];
1367 port->txqs++;
1368 if (port->txqs == FST_TXQ_DEPTH) {
1369 port->txqs = 0;
1370 }
1371 spin_unlock_irqrestore(&card->card_lock, flags);
1372 /*
1373 * copy the data and set the required indicators on the
1374 * card.
1375 */
1376 FST_WRW(card, txDescrRing[pi][port->txpos].bcnt,
1377 cnv_bcnt(skb->len));
1378 if ((skb->len < FST_MIN_DMA_LEN) ||
1379 (card->family == FST_FAMILY_TXP)) {
1380 /* Enqueue the packet with normal io */
1381 memcpy_toio(card->mem +
1382 BUF_OFFSET(txBuffer[pi]
1383 [port->
1384 txpos][0]),
1385 skb->data, skb->len);
1386 FST_WRB(card,
1387 txDescrRing[pi][port->txpos].
1388 bits,
1389 DMA_OWN | TX_STP | TX_ENP);
1390 dev->stats.tx_packets++;
1391 dev->stats.tx_bytes += skb->len;
1392 dev->trans_start = jiffies;
1393 } else {
1394 /* Or do it through dma */
1395 memcpy(card->tx_dma_handle_host,
1396 skb->data, skb->len);
1397 card->dma_port_tx = port;
1398 card->dma_len_tx = skb->len;
1399 card->dma_txpos = port->txpos;
1400 fst_tx_dma(card,
1401 card->tx_dma_handle_card,
1402 BUF_OFFSET(txBuffer[pi]
1403 [port->txpos][0]),
1404 skb->len);
1405 }
1406 if (++port->txpos >= NUM_TX_BUFFER)
1407 port->txpos = 0;
1408 /*
1409 * If we have flow control on, can we now release it?
1410 */
1411 if (port->start) {
1412 if (txq_length < fst_txq_low) {
1413 netif_wake_queue(port_to_dev
1414 (port));
1415 port->start = 0;
1416 }
1417 }
1418 dev_kfree_skb(skb);
1419 } else {
1420 /*
1421 * Nothing to send so break out of the while loop
1422 */
1423 break;
1424 }
1425 }
1426 }
1427}
1428
1429static void
1430do_bottom_half_rx(struct fst_card_info *card)
1431{
1432 struct fst_port_info *port;
1433 int pi;
1434 int rx_count = 0;
1435
1436 /* Check for rx completions on all ports on this card */
1437 dbg(DBG_RX, "do_bottom_half_rx\n");
1438 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1439 if (!port->run)
1440 continue;
1441
1442 while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits)
1443 & DMA_OWN) && !(card->dmarx_in_progress)) {
1444 if (rx_count > fst_max_reads) {
1445 /*
1446 * Don't spend forever in receive processing
1447 * Schedule another event
1448 */
1449 fst_q_work_item(&fst_work_intq, card->card_no);
1450 tasklet_schedule(&fst_int_task);
1451 break; /* Leave the loop */
1452 }
1453 fst_intr_rx(card, port);
1454 rx_count++;
1455 }
1456 }
1457}
1458
1459/*
1460 * The interrupt service routine
1461 * Dev_id is our fst_card_info pointer
1462 */
1463static irqreturn_t
1464fst_intr(int dummy, void *dev_id)
1465{
1466 struct fst_card_info *card = dev_id;
1467 struct fst_port_info *port;
1468 int rdidx; /* Event buffer indices */
1469 int wridx;
1470 int event; /* Actual event for processing */
1471 unsigned int dma_intcsr = 0;
1472 unsigned int do_card_interrupt;
1473 unsigned int int_retry_count;
1474
1475 /*
1476 * Check to see if the interrupt was for this card
1477 * return if not
1478 * Note that the call to clear the interrupt is important
1479 */
1480 dbg(DBG_INTR, "intr: %d %p\n", card->irq, card);
1481 if (card->state != FST_RUNNING) {
1482 pr_err("Interrupt received for card %d in a non running state (%d)\n",
1483 card->card_no, card->state);
1484
1485 /*
1486 * It is possible to really be running, i.e. we have re-loaded
1487 * a running card
1488 * Clear and reprime the interrupt source
1489 */
1490 fst_clear_intr(card);
1491 return IRQ_HANDLED;
1492 }
1493
1494 /* Clear and reprime the interrupt source */
1495 fst_clear_intr(card);
1496
1497 /*
1498 * Is the interrupt for this card (handshake == 1)
1499 */
1500 do_card_interrupt = 0;
1501 if (FST_RDB(card, interruptHandshake) == 1) {
1502 do_card_interrupt += FST_CARD_INT;
1503 /* Set the software acknowledge */
1504 FST_WRB(card, interruptHandshake, 0xEE);
1505 }
1506 if (card->family == FST_FAMILY_TXU) {
1507 /*
1508 * Is it a DMA Interrupt
1509 */
1510 dma_intcsr = inl(card->pci_conf + INTCSR_9054);
1511 if (dma_intcsr & 0x00200000) {
1512 /*
1513 * DMA Channel 0 (Rx transfer complete)
1514 */
1515 dbg(DBG_RX, "DMA Rx xfer complete\n");
1516 outb(0x8, card->pci_conf + DMACSR0);
1517 fst_rx_dma_complete(card, card->dma_port_rx,
1518 card->dma_len_rx, card->dma_skb_rx,
1519 card->dma_rxpos);
1520 card->dmarx_in_progress = 0;
1521 do_card_interrupt += FST_RX_DMA_INT;
1522 }
1523 if (dma_intcsr & 0x00400000) {
1524 /*
1525 * DMA Channel 1 (Tx transfer complete)
1526 */
1527 dbg(DBG_TX, "DMA Tx xfer complete\n");
1528 outb(0x8, card->pci_conf + DMACSR1);
1529 fst_tx_dma_complete(card, card->dma_port_tx,
1530 card->dma_len_tx, card->dma_txpos);
1531 card->dmatx_in_progress = 0;
1532 do_card_interrupt += FST_TX_DMA_INT;
1533 }
1534 }
1535
1536 /*
1537 * Have we been missing Interrupts
1538 */
1539 int_retry_count = FST_RDL(card, interruptRetryCount);
1540 if (int_retry_count) {
1541 dbg(DBG_ASS, "Card %d int_retry_count is %d\n",
1542 card->card_no, int_retry_count);
1543 FST_WRL(card, interruptRetryCount, 0);
1544 }
1545
1546 if (!do_card_interrupt) {
1547 return IRQ_HANDLED;
1548 }
1549
1550 /* Scehdule the bottom half of the ISR */
1551 fst_q_work_item(&fst_work_intq, card->card_no);
1552 tasklet_schedule(&fst_int_task);
1553
1554 /* Drain the event queue */
1555 rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f;
1556 wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f;
1557 while (rdidx != wridx) {
1558 event = FST_RDB(card, interruptEvent.evntbuff[rdidx]);
1559 port = &card->ports[event & 0x03];
1560
1561 dbg(DBG_INTR, "Processing Interrupt event: %x\n", event);
1562
1563 switch (event) {
1564 case TE1_ALMA:
1565 dbg(DBG_INTR, "TE1 Alarm intr\n");
1566 if (port->run)
1567 fst_intr_te1_alarm(card, port);
1568 break;
1569
1570 case CTLA_CHG:
1571 case CTLB_CHG:
1572 case CTLC_CHG:
1573 case CTLD_CHG:
1574 if (port->run)
1575 fst_intr_ctlchg(card, port);
1576 break;
1577
1578 case ABTA_SENT:
1579 case ABTB_SENT:
1580 case ABTC_SENT:
1581 case ABTD_SENT:
1582 dbg(DBG_TX, "Abort complete port %d\n", port->index);
1583 break;
1584
1585 case TXA_UNDF:
1586 case TXB_UNDF:
1587 case TXC_UNDF:
1588 case TXD_UNDF:
1589 /* Difficult to see how we'd get this given that we
1590 * always load up the entire packet for DMA.
1591 */
1592 dbg(DBG_TX, "Tx underflow port %d\n", port->index);
1593 port_to_dev(port)->stats.tx_errors++;
1594 port_to_dev(port)->stats.tx_fifo_errors++;
1595 dbg(DBG_ASS, "Tx underflow on card %d port %d\n",
1596 card->card_no, port->index);
1597 break;
1598
1599 case INIT_CPLT:
1600 dbg(DBG_INIT, "Card init OK intr\n");
1601 break;
1602
1603 case INIT_FAIL:
1604 dbg(DBG_INIT, "Card init FAILED intr\n");
1605 card->state = FST_IFAILED;
1606 break;
1607
1608 default:
1609 pr_err("intr: unknown card event %d. ignored\n", event);
1610 break;
1611 }
1612
1613 /* Bump and wrap the index */
1614 if (++rdidx >= MAX_CIRBUFF)
1615 rdidx = 0;
1616 }
1617 FST_WRB(card, interruptEvent.rdindex, rdidx);
1618 return IRQ_HANDLED;
1619}
1620
1621/* Check that the shared memory configuration is one that we can handle
1622 * and that some basic parameters are correct
1623 */
1624static void
1625check_started_ok(struct fst_card_info *card)
1626{
1627 int i;
1628
1629 /* Check structure version and end marker */
1630 if (FST_RDW(card, smcVersion) != SMC_VERSION) {
1631 pr_err("Bad shared memory version %d expected %d\n",
1632 FST_RDW(card, smcVersion), SMC_VERSION);
1633 card->state = FST_BADVERSION;
1634 return;
1635 }
1636 if (FST_RDL(card, endOfSmcSignature) != END_SIG) {
1637 pr_err("Missing shared memory signature\n");
1638 card->state = FST_BADVERSION;
1639 return;
1640 }
1641 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */
1642 if ((i = FST_RDB(card, taskStatus)) == 0x01) {
1643 card->state = FST_RUNNING;
1644 } else if (i == 0xFF) {
1645 pr_err("Firmware initialisation failed. Card halted\n");
1646 card->state = FST_HALTED;
1647 return;
1648 } else if (i != 0x00) {
1649 pr_err("Unknown firmware status 0x%x\n", i);
1650 card->state = FST_HALTED;
1651 return;
1652 }
1653
1654 /* Finally check the number of ports reported by firmware against the
1655 * number we assumed at card detection. Should never happen with
1656 * existing firmware etc so we just report it for the moment.
1657 */
1658 if (FST_RDL(card, numberOfPorts) != card->nports) {
1659 pr_warn("Port count mismatch on card %d. Firmware thinks %d we say %d\n",
1660 card->card_no,
1661 FST_RDL(card, numberOfPorts), card->nports);
1662 }
1663}
1664
1665static int
1666set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port,
1667 struct fstioc_info *info)
1668{
1669 int err;
1670 unsigned char my_framing;
1671
1672 /* Set things according to the user set valid flags
1673 * Several of the old options have been invalidated/replaced by the
1674 * generic hdlc package.
1675 */
1676 err = 0;
1677 if (info->valid & FSTVAL_PROTO) {
1678 if (info->proto == FST_RAW)
1679 port->mode = FST_RAW;
1680 else
1681 port->mode = FST_GEN_HDLC;
1682 }
1683
1684 if (info->valid & FSTVAL_CABLE)
1685 err = -EINVAL;
1686
1687 if (info->valid & FSTVAL_SPEED)
1688 err = -EINVAL;
1689
1690 if (info->valid & FSTVAL_PHASE)
1691 FST_WRB(card, portConfig[port->index].invertClock,
1692 info->invertClock);
1693 if (info->valid & FSTVAL_MODE)
1694 FST_WRW(card, cardMode, info->cardMode);
1695 if (info->valid & FSTVAL_TE1) {
1696 FST_WRL(card, suConfig.dataRate, info->lineSpeed);
1697 FST_WRB(card, suConfig.clocking, info->clockSource);
1698 my_framing = FRAMING_E1;
1699 if (info->framing == E1)
1700 my_framing = FRAMING_E1;
1701 if (info->framing == T1)
1702 my_framing = FRAMING_T1;
1703 if (info->framing == J1)
1704 my_framing = FRAMING_J1;
1705 FST_WRB(card, suConfig.framing, my_framing);
1706 FST_WRB(card, suConfig.structure, info->structure);
1707 FST_WRB(card, suConfig.interface, info->interface);
1708 FST_WRB(card, suConfig.coding, info->coding);
1709 FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut);
1710 FST_WRB(card, suConfig.equalizer, info->equalizer);
1711 FST_WRB(card, suConfig.transparentMode, info->transparentMode);
1712 FST_WRB(card, suConfig.loopMode, info->loopMode);
1713 FST_WRB(card, suConfig.range, info->range);
1714 FST_WRB(card, suConfig.txBufferMode, info->txBufferMode);
1715 FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode);
1716 FST_WRB(card, suConfig.startingSlot, info->startingSlot);
1717 FST_WRB(card, suConfig.losThreshold, info->losThreshold);
1718 if (info->idleCode)
1719 FST_WRB(card, suConfig.enableIdleCode, 1);
1720 else
1721 FST_WRB(card, suConfig.enableIdleCode, 0);
1722 FST_WRB(card, suConfig.idleCode, info->idleCode);
1723#if FST_DEBUG
1724 if (info->valid & FSTVAL_TE1) {
1725 printk("Setting TE1 data\n");
1726 printk("Line Speed = %d\n", info->lineSpeed);
1727 printk("Start slot = %d\n", info->startingSlot);
1728 printk("Clock source = %d\n", info->clockSource);
1729 printk("Framing = %d\n", my_framing);
1730 printk("Structure = %d\n", info->structure);
1731 printk("interface = %d\n", info->interface);
1732 printk("Coding = %d\n", info->coding);
1733 printk("Line build out = %d\n", info->lineBuildOut);
1734 printk("Equaliser = %d\n", info->equalizer);
1735 printk("Transparent mode = %d\n",
1736 info->transparentMode);
1737 printk("Loop mode = %d\n", info->loopMode);
1738 printk("Range = %d\n", info->range);
1739 printk("Tx Buffer mode = %d\n", info->txBufferMode);
1740 printk("Rx Buffer mode = %d\n", info->rxBufferMode);
1741 printk("LOS Threshold = %d\n", info->losThreshold);
1742 printk("Idle Code = %d\n", info->idleCode);
1743 }
1744#endif
1745 }
1746#if FST_DEBUG
1747 if (info->valid & FSTVAL_DEBUG) {
1748 fst_debug_mask = info->debug;
1749 }
1750#endif
1751
1752 return err;
1753}
1754
1755static void
1756gather_conf_info(struct fst_card_info *card, struct fst_port_info *port,
1757 struct fstioc_info *info)
1758{
1759 int i;
1760
1761 memset(info, 0, sizeof (struct fstioc_info));
1762
1763 i = port->index;
1764 info->kernelVersion = LINUX_VERSION_CODE;
1765 info->nports = card->nports;
1766 info->type = card->type;
1767 info->state = card->state;
1768 info->proto = FST_GEN_HDLC;
1769 info->index = i;
1770#if FST_DEBUG
1771 info->debug = fst_debug_mask;
1772#endif
1773
1774 /* Only mark information as valid if card is running.
1775 * Copy the data anyway in case it is useful for diagnostics
1776 */
1777 info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD)
1778#if FST_DEBUG
1779 | FSTVAL_DEBUG
1780#endif
1781 ;
1782
1783 info->lineInterface = FST_RDW(card, portConfig[i].lineInterface);
1784 info->internalClock = FST_RDB(card, portConfig[i].internalClock);
1785 info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed);
1786 info->invertClock = FST_RDB(card, portConfig[i].invertClock);
1787 info->v24IpSts = FST_RDL(card, v24IpSts[i]);
1788 info->v24OpSts = FST_RDL(card, v24OpSts[i]);
1789 info->clockStatus = FST_RDW(card, clockStatus[i]);
1790 info->cableStatus = FST_RDW(card, cableStatus);
1791 info->cardMode = FST_RDW(card, cardMode);
1792 info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion);
1793
1794 /*
1795 * The T2U can report cable presence for both A or B
1796 * in bits 0 and 1 of cableStatus. See which port we are and
1797 * do the mapping.
1798 */
1799 if (card->family == FST_FAMILY_TXU) {
1800 if (port->index == 0) {
1801 /*
1802 * Port A
1803 */
1804 info->cableStatus = info->cableStatus & 1;
1805 } else {
1806 /*
1807 * Port B
1808 */
1809 info->cableStatus = info->cableStatus >> 1;
1810 info->cableStatus = info->cableStatus & 1;
1811 }
1812 }
1813 /*
1814 * Some additional bits if we are TE1
1815 */
1816 if (card->type == FST_TYPE_TE1) {
1817 info->lineSpeed = FST_RDL(card, suConfig.dataRate);
1818 info->clockSource = FST_RDB(card, suConfig.clocking);
1819 info->framing = FST_RDB(card, suConfig.framing);
1820 info->structure = FST_RDB(card, suConfig.structure);
1821 info->interface = FST_RDB(card, suConfig.interface);
1822 info->coding = FST_RDB(card, suConfig.coding);
1823 info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut);
1824 info->equalizer = FST_RDB(card, suConfig.equalizer);
1825 info->loopMode = FST_RDB(card, suConfig.loopMode);
1826 info->range = FST_RDB(card, suConfig.range);
1827 info->txBufferMode = FST_RDB(card, suConfig.txBufferMode);
1828 info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode);
1829 info->startingSlot = FST_RDB(card, suConfig.startingSlot);
1830 info->losThreshold = FST_RDB(card, suConfig.losThreshold);
1831 if (FST_RDB(card, suConfig.enableIdleCode))
1832 info->idleCode = FST_RDB(card, suConfig.idleCode);
1833 else
1834 info->idleCode = 0;
1835 info->receiveBufferDelay =
1836 FST_RDL(card, suStatus.receiveBufferDelay);
1837 info->framingErrorCount =
1838 FST_RDL(card, suStatus.framingErrorCount);
1839 info->codeViolationCount =
1840 FST_RDL(card, suStatus.codeViolationCount);
1841 info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount);
1842 info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation);
1843 info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal);
1844 info->receiveRemoteAlarm =
1845 FST_RDB(card, suStatus.receiveRemoteAlarm);
1846 info->alarmIndicationSignal =
1847 FST_RDB(card, suStatus.alarmIndicationSignal);
1848 }
1849}
1850
1851static int
1852fst_set_iface(struct fst_card_info *card, struct fst_port_info *port,
1853 struct ifreq *ifr)
1854{
1855 sync_serial_settings sync;
1856 int i;
1857
1858 if (ifr->ifr_settings.size != sizeof (sync)) {
1859 return -ENOMEM;
1860 }
1861
1862 if (copy_from_user
1863 (&sync, ifr->ifr_settings.ifs_ifsu.sync, sizeof (sync))) {
1864 return -EFAULT;
1865 }
1866
1867 if (sync.loopback)
1868 return -EINVAL;
1869
1870 i = port->index;
1871
1872 switch (ifr->ifr_settings.type) {
1873 case IF_IFACE_V35:
1874 FST_WRW(card, portConfig[i].lineInterface, V35);
1875 port->hwif = V35;
1876 break;
1877
1878 case IF_IFACE_V24:
1879 FST_WRW(card, portConfig[i].lineInterface, V24);
1880 port->hwif = V24;
1881 break;
1882
1883 case IF_IFACE_X21:
1884 FST_WRW(card, portConfig[i].lineInterface, X21);
1885 port->hwif = X21;
1886 break;
1887
1888 case IF_IFACE_X21D:
1889 FST_WRW(card, portConfig[i].lineInterface, X21D);
1890 port->hwif = X21D;
1891 break;
1892
1893 case IF_IFACE_T1:
1894 FST_WRW(card, portConfig[i].lineInterface, T1);
1895 port->hwif = T1;
1896 break;
1897
1898 case IF_IFACE_E1:
1899 FST_WRW(card, portConfig[i].lineInterface, E1);
1900 port->hwif = E1;
1901 break;
1902
1903 case IF_IFACE_SYNC_SERIAL:
1904 break;
1905
1906 default:
1907 return -EINVAL;
1908 }
1909
1910 switch (sync.clock_type) {
1911 case CLOCK_EXT:
1912 FST_WRB(card, portConfig[i].internalClock, EXTCLK);
1913 break;
1914
1915 case CLOCK_INT:
1916 FST_WRB(card, portConfig[i].internalClock, INTCLK);
1917 break;
1918
1919 default:
1920 return -EINVAL;
1921 }
1922 FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate);
1923 return 0;
1924}
1925
1926static int
1927fst_get_iface(struct fst_card_info *card, struct fst_port_info *port,
1928 struct ifreq *ifr)
1929{
1930 sync_serial_settings sync;
1931 int i;
1932
1933 /* First check what line type is set, we'll default to reporting X.21
1934 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be
1935 * changed
1936 */
1937 switch (port->hwif) {
1938 case E1:
1939 ifr->ifr_settings.type = IF_IFACE_E1;
1940 break;
1941 case T1:
1942 ifr->ifr_settings.type = IF_IFACE_T1;
1943 break;
1944 case V35:
1945 ifr->ifr_settings.type = IF_IFACE_V35;
1946 break;
1947 case V24:
1948 ifr->ifr_settings.type = IF_IFACE_V24;
1949 break;
1950 case X21D:
1951 ifr->ifr_settings.type = IF_IFACE_X21D;
1952 break;
1953 case X21:
1954 default:
1955 ifr->ifr_settings.type = IF_IFACE_X21;
1956 break;
1957 }
1958 if (ifr->ifr_settings.size == 0) {
1959 return 0; /* only type requested */
1960 }
1961 if (ifr->ifr_settings.size < sizeof (sync)) {
1962 return -ENOMEM;
1963 }
1964
1965 i = port->index;
1966 memset(&sync, 0, sizeof(sync));
1967 sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed);
1968 /* Lucky card and linux use same encoding here */
1969 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) ==
1970 INTCLK ? CLOCK_INT : CLOCK_EXT;
1971 sync.loopback = 0;
1972
1973 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &sync, sizeof (sync))) {
1974 return -EFAULT;
1975 }
1976
1977 ifr->ifr_settings.size = sizeof (sync);
1978 return 0;
1979}
1980
1981static int
1982fst_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1983{
1984 struct fst_card_info *card;
1985 struct fst_port_info *port;
1986 struct fstioc_write wrthdr;
1987 struct fstioc_info info;
1988 unsigned long flags;
1989 void *buf;
1990
1991 dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, ifr->ifr_data);
1992
1993 port = dev_to_port(dev);
1994 card = port->card;
1995
1996 if (!capable(CAP_NET_ADMIN))
1997 return -EPERM;
1998
1999 switch (cmd) {
2000 case FSTCPURESET:
2001 fst_cpureset(card);
2002 card->state = FST_RESET;
2003 return 0;
2004
2005 case FSTCPURELEASE:
2006 fst_cpurelease(card);
2007 card->state = FST_STARTING;
2008 return 0;
2009
2010 case FSTWRITE: /* Code write (download) */
2011
2012 /* First copy in the header with the length and offset of data
2013 * to write
2014 */
2015 if (ifr->ifr_data == NULL) {
2016 return -EINVAL;
2017 }
2018 if (copy_from_user(&wrthdr, ifr->ifr_data,
2019 sizeof (struct fstioc_write))) {
2020 return -EFAULT;
2021 }
2022
2023 /* Sanity check the parameters. We don't support partial writes
2024 * when going over the top
2025 */
2026 if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE ||
2027 wrthdr.size + wrthdr.offset > FST_MEMSIZE) {
2028 return -ENXIO;
2029 }
2030
2031 /* Now copy the data to the card. */
2032
2033 buf = memdup_user(ifr->ifr_data + sizeof(struct fstioc_write),
2034 wrthdr.size);
2035 if (IS_ERR(buf))
2036 return PTR_ERR(buf);
2037
2038 memcpy_toio(card->mem + wrthdr.offset, buf, wrthdr.size);
2039 kfree(buf);
2040
2041 /* Writes to the memory of a card in the reset state constitute
2042 * a download
2043 */
2044 if (card->state == FST_RESET) {
2045 card->state = FST_DOWNLOAD;
2046 }
2047 return 0;
2048
2049 case FSTGETCONF:
2050
2051 /* If card has just been started check the shared memory config
2052 * version and marker
2053 */
2054 if (card->state == FST_STARTING) {
2055 check_started_ok(card);
2056
2057 /* If everything checked out enable card interrupts */
2058 if (card->state == FST_RUNNING) {
2059 spin_lock_irqsave(&card->card_lock, flags);
2060 fst_enable_intr(card);
2061 FST_WRB(card, interruptHandshake, 0xEE);
2062 spin_unlock_irqrestore(&card->card_lock, flags);
2063 }
2064 }
2065
2066 if (ifr->ifr_data == NULL) {
2067 return -EINVAL;
2068 }
2069
2070 gather_conf_info(card, port, &info);
2071
2072 if (copy_to_user(ifr->ifr_data, &info, sizeof (info))) {
2073 return -EFAULT;
2074 }
2075 return 0;
2076
2077 case FSTSETCONF:
2078
2079 /*
2080 * Most of the settings have been moved to the generic ioctls
2081 * this just covers debug and board ident now
2082 */
2083
2084 if (card->state != FST_RUNNING) {
2085 pr_err("Attempt to configure card %d in non-running state (%d)\n",
2086 card->card_no, card->state);
2087 return -EIO;
2088 }
2089 if (copy_from_user(&info, ifr->ifr_data, sizeof (info))) {
2090 return -EFAULT;
2091 }
2092
2093 return set_conf_from_info(card, port, &info);
2094
2095 case SIOCWANDEV:
2096 switch (ifr->ifr_settings.type) {
2097 case IF_GET_IFACE:
2098 return fst_get_iface(card, port, ifr);
2099
2100 case IF_IFACE_SYNC_SERIAL:
2101 case IF_IFACE_V35:
2102 case IF_IFACE_V24:
2103 case IF_IFACE_X21:
2104 case IF_IFACE_X21D:
2105 case IF_IFACE_T1:
2106 case IF_IFACE_E1:
2107 return fst_set_iface(card, port, ifr);
2108
2109 case IF_PROTO_RAW:
2110 port->mode = FST_RAW;
2111 return 0;
2112
2113 case IF_GET_PROTO:
2114 if (port->mode == FST_RAW) {
2115 ifr->ifr_settings.type = IF_PROTO_RAW;
2116 return 0;
2117 }
2118 return hdlc_ioctl(dev, ifr, cmd);
2119
2120 default:
2121 port->mode = FST_GEN_HDLC;
2122 dbg(DBG_IOCTL, "Passing this type to hdlc %x\n",
2123 ifr->ifr_settings.type);
2124 return hdlc_ioctl(dev, ifr, cmd);
2125 }
2126
2127 default:
2128 /* Not one of ours. Pass through to HDLC package */
2129 return hdlc_ioctl(dev, ifr, cmd);
2130 }
2131}
2132
2133static void
2134fst_openport(struct fst_port_info *port)
2135{
2136 int signals;
2137 int txq_length;
2138
2139 /* Only init things if card is actually running. This allows open to
2140 * succeed for downloads etc.
2141 */
2142 if (port->card->state == FST_RUNNING) {
2143 if (port->run) {
2144 dbg(DBG_OPEN, "open: found port already running\n");
2145
2146 fst_issue_cmd(port, STOPPORT);
2147 port->run = 0;
2148 }
2149
2150 fst_rx_config(port);
2151 fst_tx_config(port);
2152 fst_op_raise(port, OPSTS_RTS | OPSTS_DTR);
2153
2154 fst_issue_cmd(port, STARTPORT);
2155 port->run = 1;
2156
2157 signals = FST_RDL(port->card, v24DebouncedSts[port->index]);
2158 if (signals & (((port->hwif == X21) || (port->hwif == X21D))
2159 ? IPSTS_INDICATE : IPSTS_DCD))
2160 netif_carrier_on(port_to_dev(port));
2161 else
2162 netif_carrier_off(port_to_dev(port));
2163
2164 txq_length = port->txqe - port->txqs;
2165 port->txqe = 0;
2166 port->txqs = 0;
2167 }
2168
2169}
2170
2171static void
2172fst_closeport(struct fst_port_info *port)
2173{
2174 if (port->card->state == FST_RUNNING) {
2175 if (port->run) {
2176 port->run = 0;
2177 fst_op_lower(port, OPSTS_RTS | OPSTS_DTR);
2178
2179 fst_issue_cmd(port, STOPPORT);
2180 } else {
2181 dbg(DBG_OPEN, "close: port not running\n");
2182 }
2183 }
2184}
2185
2186static int
2187fst_open(struct net_device *dev)
2188{
2189 int err;
2190 struct fst_port_info *port;
2191
2192 port = dev_to_port(dev);
2193 if (!try_module_get(THIS_MODULE))
2194 return -EBUSY;
2195
2196 if (port->mode != FST_RAW) {
2197 err = hdlc_open(dev);
2198 if (err) {
2199 module_put(THIS_MODULE);
2200 return err;
2201 }
2202 }
2203
2204 fst_openport(port);
2205 netif_wake_queue(dev);
2206 return 0;
2207}
2208
2209static int
2210fst_close(struct net_device *dev)
2211{
2212 struct fst_port_info *port;
2213 struct fst_card_info *card;
2214 unsigned char tx_dma_done;
2215 unsigned char rx_dma_done;
2216
2217 port = dev_to_port(dev);
2218 card = port->card;
2219
2220 tx_dma_done = inb(card->pci_conf + DMACSR1);
2221 rx_dma_done = inb(card->pci_conf + DMACSR0);
2222 dbg(DBG_OPEN,
2223 "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n",
2224 card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress,
2225 rx_dma_done);
2226
2227 netif_stop_queue(dev);
2228 fst_closeport(dev_to_port(dev));
2229 if (port->mode != FST_RAW) {
2230 hdlc_close(dev);
2231 }
2232 module_put(THIS_MODULE);
2233 return 0;
2234}
2235
2236static int
2237fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity)
2238{
2239 /*
2240 * Setting currently fixed in FarSync card so we check and forget
2241 */
2242 if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT)
2243 return -EINVAL;
2244 return 0;
2245}
2246
2247static void
2248fst_tx_timeout(struct net_device *dev)
2249{
2250 struct fst_port_info *port;
2251 struct fst_card_info *card;
2252
2253 port = dev_to_port(dev);
2254 card = port->card;
2255 dev->stats.tx_errors++;
2256 dev->stats.tx_aborted_errors++;
2257 dbg(DBG_ASS, "Tx timeout card %d port %d\n",
2258 card->card_no, port->index);
2259 fst_issue_cmd(port, ABORTTX);
2260
2261 dev->trans_start = jiffies;
2262 netif_wake_queue(dev);
2263 port->start = 0;
2264}
2265
2266static netdev_tx_t
2267fst_start_xmit(struct sk_buff *skb, struct net_device *dev)
2268{
2269 struct fst_card_info *card;
2270 struct fst_port_info *port;
2271 unsigned long flags;
2272 int txq_length;
2273
2274 port = dev_to_port(dev);
2275 card = port->card;
2276 dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len);
2277
2278 /* Drop packet with error if we don't have carrier */
2279 if (!netif_carrier_ok(dev)) {
2280 dev_kfree_skb(skb);
2281 dev->stats.tx_errors++;
2282 dev->stats.tx_carrier_errors++;
2283 dbg(DBG_ASS,
2284 "Tried to transmit but no carrier on card %d port %d\n",
2285 card->card_no, port->index);
2286 return NETDEV_TX_OK;
2287 }
2288
2289 /* Drop it if it's too big! MTU failure ? */
2290 if (skb->len > LEN_TX_BUFFER) {
2291 dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len,
2292 LEN_TX_BUFFER);
2293 dev_kfree_skb(skb);
2294 dev->stats.tx_errors++;
2295 return NETDEV_TX_OK;
2296 }
2297
2298 /*
2299 * We are always going to queue the packet
2300 * so that the bottom half is the only place we tx from
2301 * Check there is room in the port txq
2302 */
2303 spin_lock_irqsave(&card->card_lock, flags);
2304 if ((txq_length = port->txqe - port->txqs) < 0) {
2305 /*
2306 * This is the case where the next free has wrapped but the
2307 * last used hasn't
2308 */
2309 txq_length = txq_length + FST_TXQ_DEPTH;
2310 }
2311 spin_unlock_irqrestore(&card->card_lock, flags);
2312 if (txq_length > fst_txq_high) {
2313 /*
2314 * We have got enough buffers in the pipeline. Ask the network
2315 * layer to stop sending frames down
2316 */
2317 netif_stop_queue(dev);
2318 port->start = 1; /* I'm using this to signal stop sent up */
2319 }
2320
2321 if (txq_length == FST_TXQ_DEPTH - 1) {
2322 /*
2323 * This shouldn't have happened but such is life
2324 */
2325 dev_kfree_skb(skb);
2326 dev->stats.tx_errors++;
2327 dbg(DBG_ASS, "Tx queue overflow card %d port %d\n",
2328 card->card_no, port->index);
2329 return NETDEV_TX_OK;
2330 }
2331
2332 /*
2333 * queue the buffer
2334 */
2335 spin_lock_irqsave(&card->card_lock, flags);
2336 port->txq[port->txqe] = skb;
2337 port->txqe++;
2338 if (port->txqe == FST_TXQ_DEPTH)
2339 port->txqe = 0;
2340 spin_unlock_irqrestore(&card->card_lock, flags);
2341
2342 /* Scehdule the bottom half which now does transmit processing */
2343 fst_q_work_item(&fst_work_txq, card->card_no);
2344 tasklet_schedule(&fst_tx_task);
2345
2346 return NETDEV_TX_OK;
2347}
2348
2349/*
2350 * Card setup having checked hardware resources.
2351 * Should be pretty bizarre if we get an error here (kernel memory
2352 * exhaustion is one possibility). If we do see a problem we report it
2353 * via a printk and leave the corresponding interface and all that follow
2354 * disabled.
2355 */
2356static char *type_strings[] = {
2357 "no hardware", /* Should never be seen */
2358 "FarSync T2P",
2359 "FarSync T4P",
2360 "FarSync T1U",
2361 "FarSync T2U",
2362 "FarSync T4U",
2363 "FarSync TE1"
2364};
2365
2366static int
2367fst_init_card(struct fst_card_info *card)
2368{
2369 int i;
2370 int err;
2371
2372 /* We're working on a number of ports based on the card ID. If the
2373 * firmware detects something different later (should never happen)
2374 * we'll have to revise it in some way then.
2375 */
2376 for (i = 0; i < card->nports; i++) {
2377 err = register_hdlc_device(card->ports[i].dev);
2378 if (err < 0) {
2379 pr_err("Cannot register HDLC device for port %d (errno %d)\n",
2380 i, -err);
2381 while (i--)
2382 unregister_hdlc_device(card->ports[i].dev);
2383 return err;
2384 }
2385 }
2386
2387 pr_info("%s-%s: %s IRQ%d, %d ports\n",
2388 port_to_dev(&card->ports[0])->name,
2389 port_to_dev(&card->ports[card->nports - 1])->name,
2390 type_strings[card->type], card->irq, card->nports);
2391 return 0;
2392}
2393
2394static const struct net_device_ops fst_ops = {
2395 .ndo_open = fst_open,
2396 .ndo_stop = fst_close,
2397 .ndo_change_mtu = hdlc_change_mtu,
2398 .ndo_start_xmit = hdlc_start_xmit,
2399 .ndo_do_ioctl = fst_ioctl,
2400 .ndo_tx_timeout = fst_tx_timeout,
2401};
2402
2403/*
2404 * Initialise card when detected.
2405 * Returns 0 to indicate success, or errno otherwise.
2406 */
2407static int
2408fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2409{
2410 static int no_of_cards_added = 0;
2411 struct fst_card_info *card;
2412 int err = 0;
2413 int i;
2414
2415 printk_once(KERN_INFO
2416 pr_fmt("FarSync WAN driver " FST_USER_VERSION
2417 " (c) 2001-2004 FarSite Communications Ltd.\n"));
2418#if FST_DEBUG
2419 dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask);
2420#endif
2421 /*
2422 * We are going to be clever and allow certain cards not to be
2423 * configured. An exclude list can be provided in /etc/modules.conf
2424 */
2425 if (fst_excluded_cards != 0) {
2426 /*
2427 * There are cards to exclude
2428 *
2429 */
2430 for (i = 0; i < fst_excluded_cards; i++) {
2431 if ((pdev->devfn) >> 3 == fst_excluded_list[i]) {
2432 pr_info("FarSync PCI device %d not assigned\n",
2433 (pdev->devfn) >> 3);
2434 return -EBUSY;
2435 }
2436 }
2437 }
2438
2439 /* Allocate driver private data */
2440 card = kzalloc(sizeof(struct fst_card_info), GFP_KERNEL);
2441 if (card == NULL)
2442 return -ENOMEM;
2443
2444 /* Try to enable the device */
2445 if ((err = pci_enable_device(pdev)) != 0) {
2446 pr_err("Failed to enable card. Err %d\n", -err);
2447 goto enable_fail;
2448 }
2449
2450 if ((err = pci_request_regions(pdev, "FarSync")) !=0) {
2451 pr_err("Failed to allocate regions. Err %d\n", -err);
2452 goto regions_fail;
2453 }
2454
2455 /* Get virtual addresses of memory regions */
2456 card->pci_conf = pci_resource_start(pdev, 1);
2457 card->phys_mem = pci_resource_start(pdev, 2);
2458 card->phys_ctlmem = pci_resource_start(pdev, 3);
2459 if ((card->mem = ioremap(card->phys_mem, FST_MEMSIZE)) == NULL) {
2460 pr_err("Physical memory remap failed\n");
2461 err = -ENODEV;
2462 goto ioremap_physmem_fail;
2463 }
2464 if ((card->ctlmem = ioremap(card->phys_ctlmem, 0x10)) == NULL) {
2465 pr_err("Control memory remap failed\n");
2466 err = -ENODEV;
2467 goto ioremap_ctlmem_fail;
2468 }
2469 dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem);
2470
2471 /* Register the interrupt handler */
2472 if (request_irq(pdev->irq, fst_intr, IRQF_SHARED, FST_DEV_NAME, card)) {
2473 pr_err("Unable to register interrupt %d\n", card->irq);
2474 err = -ENODEV;
2475 goto irq_fail;
2476 }
2477
2478 /* Record info we need */
2479 card->irq = pdev->irq;
2480 card->type = ent->driver_data;
2481 card->family = ((ent->driver_data == FST_TYPE_T2P) ||
2482 (ent->driver_data == FST_TYPE_T4P))
2483 ? FST_FAMILY_TXP : FST_FAMILY_TXU;
2484 if ((ent->driver_data == FST_TYPE_T1U) ||
2485 (ent->driver_data == FST_TYPE_TE1))
2486 card->nports = 1;
2487 else
2488 card->nports = ((ent->driver_data == FST_TYPE_T2P) ||
2489 (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4;
2490
2491 card->state = FST_UNINIT;
2492 spin_lock_init ( &card->card_lock );
2493
2494 for ( i = 0 ; i < card->nports ; i++ ) {
2495 struct net_device *dev = alloc_hdlcdev(&card->ports[i]);
2496 hdlc_device *hdlc;
2497 if (!dev) {
2498 while (i--)
2499 free_netdev(card->ports[i].dev);
2500 pr_err("FarSync: out of memory\n");
2501 err = -ENOMEM;
2502 goto hdlcdev_fail;
2503 }
2504 card->ports[i].dev = dev;
2505 card->ports[i].card = card;
2506 card->ports[i].index = i;
2507 card->ports[i].run = 0;
2508
2509 hdlc = dev_to_hdlc(dev);
2510
2511 /* Fill in the net device info */
2512 /* Since this is a PCI setup this is purely
2513 * informational. Give them the buffer addresses
2514 * and basic card I/O.
2515 */
2516 dev->mem_start = card->phys_mem
2517 + BUF_OFFSET ( txBuffer[i][0][0]);
2518 dev->mem_end = card->phys_mem
2519 + BUF_OFFSET ( txBuffer[i][NUM_TX_BUFFER - 1][LEN_RX_BUFFER - 1]);
2520 dev->base_addr = card->pci_conf;
2521 dev->irq = card->irq;
2522
2523 dev->netdev_ops = &fst_ops;
2524 dev->tx_queue_len = FST_TX_QUEUE_LEN;
2525 dev->watchdog_timeo = FST_TX_TIMEOUT;
2526 hdlc->attach = fst_attach;
2527 hdlc->xmit = fst_start_xmit;
2528 }
2529
2530 card->device = pdev;
2531
2532 dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type,
2533 card->nports, card->irq);
2534 dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n",
2535 card->pci_conf, card->phys_mem, card->phys_ctlmem);
2536
2537 /* Reset the card's processor */
2538 fst_cpureset(card);
2539 card->state = FST_RESET;
2540
2541 /* Initialise DMA (if required) */
2542 fst_init_dma(card);
2543
2544 /* Record driver data for later use */
2545 pci_set_drvdata(pdev, card);
2546
2547 /* Remainder of card setup */
2548 if (no_of_cards_added >= FST_MAX_CARDS) {
2549 pr_err("FarSync: too many cards\n");
2550 err = -ENOMEM;
2551 goto card_array_fail;
2552 }
2553 fst_card_array[no_of_cards_added] = card;
2554 card->card_no = no_of_cards_added++; /* Record instance and bump it */
2555 err = fst_init_card(card);
2556 if (err)
2557 goto init_card_fail;
2558 if (card->family == FST_FAMILY_TXU) {
2559 /*
2560 * Allocate a dma buffer for transmit and receives
2561 */
2562 card->rx_dma_handle_host =
2563 pci_alloc_consistent(card->device, FST_MAX_MTU,
2564 &card->rx_dma_handle_card);
2565 if (card->rx_dma_handle_host == NULL) {
2566 pr_err("Could not allocate rx dma buffer\n");
2567 err = -ENOMEM;
2568 goto rx_dma_fail;
2569 }
2570 card->tx_dma_handle_host =
2571 pci_alloc_consistent(card->device, FST_MAX_MTU,
2572 &card->tx_dma_handle_card);
2573 if (card->tx_dma_handle_host == NULL) {
2574 pr_err("Could not allocate tx dma buffer\n");
2575 err = -ENOMEM;
2576 goto tx_dma_fail;
2577 }
2578 }
2579 return 0; /* Success */
2580
2581tx_dma_fail:
2582 pci_free_consistent(card->device, FST_MAX_MTU,
2583 card->rx_dma_handle_host,
2584 card->rx_dma_handle_card);
2585rx_dma_fail:
2586 fst_disable_intr(card);
2587 for (i = 0 ; i < card->nports ; i++)
2588 unregister_hdlc_device(card->ports[i].dev);
2589init_card_fail:
2590 fst_card_array[card->card_no] = NULL;
2591card_array_fail:
2592 for (i = 0 ; i < card->nports ; i++)
2593 free_netdev(card->ports[i].dev);
2594hdlcdev_fail:
2595 free_irq(card->irq, card);
2596irq_fail:
2597 iounmap(card->ctlmem);
2598ioremap_ctlmem_fail:
2599 iounmap(card->mem);
2600ioremap_physmem_fail:
2601 pci_release_regions(pdev);
2602regions_fail:
2603 pci_disable_device(pdev);
2604enable_fail:
2605 kfree(card);
2606 return err;
2607}
2608
2609/*
2610 * Cleanup and close down a card
2611 */
2612static void
2613fst_remove_one(struct pci_dev *pdev)
2614{
2615 struct fst_card_info *card;
2616 int i;
2617
2618 card = pci_get_drvdata(pdev);
2619
2620 for (i = 0; i < card->nports; i++) {
2621 struct net_device *dev = port_to_dev(&card->ports[i]);
2622 unregister_hdlc_device(dev);
2623 }
2624
2625 fst_disable_intr(card);
2626 free_irq(card->irq, card);
2627
2628 iounmap(card->ctlmem);
2629 iounmap(card->mem);
2630 pci_release_regions(pdev);
2631 if (card->family == FST_FAMILY_TXU) {
2632 /*
2633 * Free dma buffers
2634 */
2635 pci_free_consistent(card->device, FST_MAX_MTU,
2636 card->rx_dma_handle_host,
2637 card->rx_dma_handle_card);
2638 pci_free_consistent(card->device, FST_MAX_MTU,
2639 card->tx_dma_handle_host,
2640 card->tx_dma_handle_card);
2641 }
2642 fst_card_array[card->card_no] = NULL;
2643}
2644
2645static struct pci_driver fst_driver = {
2646 .name = FST_NAME,
2647 .id_table = fst_pci_dev_id,
2648 .probe = fst_add_one,
2649 .remove = fst_remove_one,
2650 .suspend = NULL,
2651 .resume = NULL,
2652};
2653
2654static int __init
2655fst_init(void)
2656{
2657 int i;
2658
2659 for (i = 0; i < FST_MAX_CARDS; i++)
2660 fst_card_array[i] = NULL;
2661 spin_lock_init(&fst_work_q_lock);
2662 return pci_register_driver(&fst_driver);
2663}
2664
2665static void __exit
2666fst_cleanup_module(void)
2667{
2668 pr_info("FarSync WAN driver unloading\n");
2669 pci_unregister_driver(&fst_driver);
2670}
2671
2672module_init(fst_init);
2673module_exit(fst_cleanup_module);