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1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
17#include "selftest.h"
18#include <linux/in.h>
19#include <linux/jhash.h>
20#include <linux/wait.h>
21#include <linux/workqueue.h>
22
23/* Hardware control for EF10 architecture including 'Huntington'. */
24
25#define EFX_EF10_DRVGEN_EV 7
26enum {
27 EFX_EF10_TEST = 1,
28 EFX_EF10_REFILL,
29};
30
31/* The reserved RSS context value */
32#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
33
34/* The filter table(s) are managed by firmware and we have write-only
35 * access. When removing filters we must identify them to the
36 * firmware by a 64-bit handle, but this is too wide for Linux kernel
37 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
38 * be able to tell in advance whether a requested insertion will
39 * replace an existing filter. Therefore we maintain a software hash
40 * table, which should be at least as large as the hardware hash
41 * table.
42 *
43 * Huntington has a single 8K filter table shared between all filter
44 * types and both ports.
45 */
46#define HUNT_FILTER_TBL_ROWS 8192
47
48struct efx_ef10_filter_table {
49/* The RX match field masks supported by this fw & hw, in order of priority */
50 enum efx_filter_match_flags rx_match_flags[
51 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
52 unsigned int rx_match_count;
53
54 struct {
55 unsigned long spec; /* pointer to spec plus flag bits */
56/* BUSY flag indicates that an update is in progress. AUTO_OLD is
57 * used to mark and sweep MAC filters for the device address lists.
58 */
59#define EFX_EF10_FILTER_FLAG_BUSY 1UL
60#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
61#define EFX_EF10_FILTER_FLAGS 3UL
62 u64 handle; /* firmware handle */
63 } *entry;
64 wait_queue_head_t waitq;
65/* Shadow of net_device address lists, guarded by mac_lock */
66#define EFX_EF10_FILTER_DEV_UC_MAX 32
67#define EFX_EF10_FILTER_DEV_MC_MAX 256
68 struct {
69 u8 addr[ETH_ALEN];
70 u16 id;
71 } dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX],
72 dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
73 int dev_uc_count; /* negative for PROMISC */
74 int dev_mc_count; /* negative for PROMISC/ALLMULTI */
75};
76
77/* An arbitrary search limit for the software hash table */
78#define EFX_EF10_FILTER_SEARCH_LIMIT 200
79
80static void efx_ef10_rx_push_rss_config(struct efx_nic *efx);
81static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
82static void efx_ef10_filter_table_remove(struct efx_nic *efx);
83
84static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
85{
86 efx_dword_t reg;
87
88 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS);
89 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
90 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
91}
92
93static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
94{
95 return resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]);
96}
97
98static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
99{
100 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
101 struct efx_ef10_nic_data *nic_data = efx->nic_data;
102 size_t outlen;
103 int rc;
104
105 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
106
107 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
108 outbuf, sizeof(outbuf), &outlen);
109 if (rc)
110 return rc;
111 if (outlen < sizeof(outbuf)) {
112 netif_err(efx, drv, efx->net_dev,
113 "unable to read datapath firmware capabilities\n");
114 return -EIO;
115 }
116
117 nic_data->datapath_caps =
118 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
119
120 if (!(nic_data->datapath_caps &
121 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
122 netif_err(efx, drv, efx->net_dev,
123 "current firmware does not support TSO\n");
124 return -ENODEV;
125 }
126
127 if (!(nic_data->datapath_caps &
128 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
129 netif_err(efx, probe, efx->net_dev,
130 "current firmware does not support an RX prefix\n");
131 return -ENODEV;
132 }
133
134 return 0;
135}
136
137static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
138{
139 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
140 int rc;
141
142 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
143 outbuf, sizeof(outbuf), NULL);
144 if (rc)
145 return rc;
146 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
147 return rc > 0 ? rc : -ERANGE;
148}
149
150static int efx_ef10_get_mac_address(struct efx_nic *efx, u8 *mac_address)
151{
152 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
153 size_t outlen;
154 int rc;
155
156 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
157
158 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
159 outbuf, sizeof(outbuf), &outlen);
160 if (rc)
161 return rc;
162 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
163 return -EIO;
164
165 ether_addr_copy(mac_address,
166 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
167 return 0;
168}
169
170static int efx_ef10_probe(struct efx_nic *efx)
171{
172 struct efx_ef10_nic_data *nic_data;
173 int i, rc;
174
175 /* We can have one VI for each 8K region. However, until we
176 * use TX option descriptors we need two TX queues per channel.
177 */
178 efx->max_channels =
179 min_t(unsigned int,
180 EFX_MAX_CHANNELS,
181 resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]) /
182 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
183 BUG_ON(efx->max_channels == 0);
184
185 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
186 if (!nic_data)
187 return -ENOMEM;
188 efx->nic_data = nic_data;
189
190 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
191 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
192 if (rc)
193 goto fail1;
194
195 /* Get the MC's warm boot count. In case it's rebooting right
196 * now, be prepared to retry.
197 */
198 i = 0;
199 for (;;) {
200 rc = efx_ef10_get_warm_boot_count(efx);
201 if (rc >= 0)
202 break;
203 if (++i == 5)
204 goto fail2;
205 ssleep(1);
206 }
207 nic_data->warm_boot_count = rc;
208
209 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
210
211 /* In case we're recovering from a crash (kexec), we want to
212 * cancel any outstanding request by the previous user of this
213 * function. We send a special message using the least
214 * significant bits of the 'high' (doorbell) register.
215 */
216 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
217
218 rc = efx_mcdi_init(efx);
219 if (rc)
220 goto fail2;
221
222 /* Reset (most) configuration for this function */
223 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
224 if (rc)
225 goto fail3;
226
227 /* Enable event logging */
228 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
229 if (rc)
230 goto fail3;
231
232 rc = efx_ef10_init_datapath_caps(efx);
233 if (rc < 0)
234 goto fail3;
235
236 efx->rx_packet_len_offset =
237 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
238
239 rc = efx_mcdi_port_get_number(efx);
240 if (rc < 0)
241 goto fail3;
242 efx->port_num = rc;
243
244 rc = efx_ef10_get_mac_address(efx, efx->net_dev->perm_addr);
245 if (rc)
246 goto fail3;
247
248 rc = efx_ef10_get_sysclk_freq(efx);
249 if (rc < 0)
250 goto fail3;
251 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
252
253 /* Check whether firmware supports bug 35388 workaround */
254 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true);
255 if (rc == 0)
256 nic_data->workaround_35388 = true;
257 else if (rc != -ENOSYS && rc != -ENOENT)
258 goto fail3;
259 netif_dbg(efx, probe, efx->net_dev,
260 "workaround for bug 35388 is %sabled\n",
261 nic_data->workaround_35388 ? "en" : "dis");
262
263 rc = efx_mcdi_mon_probe(efx);
264 if (rc)
265 goto fail3;
266
267 efx_ptp_probe(efx, NULL);
268
269 return 0;
270
271fail3:
272 efx_mcdi_fini(efx);
273fail2:
274 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
275fail1:
276 kfree(nic_data);
277 efx->nic_data = NULL;
278 return rc;
279}
280
281static int efx_ef10_free_vis(struct efx_nic *efx)
282{
283 MCDI_DECLARE_BUF_OUT_OR_ERR(outbuf, 0);
284 size_t outlen;
285 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
286 outbuf, sizeof(outbuf), &outlen);
287
288 /* -EALREADY means nothing to free, so ignore */
289 if (rc == -EALREADY)
290 rc = 0;
291 if (rc)
292 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
293 rc);
294 return rc;
295}
296
297#ifdef EFX_USE_PIO
298
299static void efx_ef10_free_piobufs(struct efx_nic *efx)
300{
301 struct efx_ef10_nic_data *nic_data = efx->nic_data;
302 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
303 unsigned int i;
304 int rc;
305
306 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
307
308 for (i = 0; i < nic_data->n_piobufs; i++) {
309 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
310 nic_data->piobuf_handle[i]);
311 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
312 NULL, 0, NULL);
313 WARN_ON(rc);
314 }
315
316 nic_data->n_piobufs = 0;
317}
318
319static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
320{
321 struct efx_ef10_nic_data *nic_data = efx->nic_data;
322 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
323 unsigned int i;
324 size_t outlen;
325 int rc = 0;
326
327 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
328
329 for (i = 0; i < n; i++) {
330 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
331 outbuf, sizeof(outbuf), &outlen);
332 if (rc)
333 break;
334 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
335 rc = -EIO;
336 break;
337 }
338 nic_data->piobuf_handle[i] =
339 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
340 netif_dbg(efx, probe, efx->net_dev,
341 "allocated PIO buffer %u handle %x\n", i,
342 nic_data->piobuf_handle[i]);
343 }
344
345 nic_data->n_piobufs = i;
346 if (rc)
347 efx_ef10_free_piobufs(efx);
348 return rc;
349}
350
351static int efx_ef10_link_piobufs(struct efx_nic *efx)
352{
353 struct efx_ef10_nic_data *nic_data = efx->nic_data;
354 MCDI_DECLARE_BUF(inbuf,
355 max(MC_CMD_LINK_PIOBUF_IN_LEN,
356 MC_CMD_UNLINK_PIOBUF_IN_LEN));
357 struct efx_channel *channel;
358 struct efx_tx_queue *tx_queue;
359 unsigned int offset, index;
360 int rc;
361
362 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
363 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
364
365 /* Link a buffer to each VI in the write-combining mapping */
366 for (index = 0; index < nic_data->n_piobufs; ++index) {
367 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
368 nic_data->piobuf_handle[index]);
369 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
370 nic_data->pio_write_vi_base + index);
371 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
372 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
373 NULL, 0, NULL);
374 if (rc) {
375 netif_err(efx, drv, efx->net_dev,
376 "failed to link VI %u to PIO buffer %u (%d)\n",
377 nic_data->pio_write_vi_base + index, index,
378 rc);
379 goto fail;
380 }
381 netif_dbg(efx, probe, efx->net_dev,
382 "linked VI %u to PIO buffer %u\n",
383 nic_data->pio_write_vi_base + index, index);
384 }
385
386 /* Link a buffer to each TX queue */
387 efx_for_each_channel(channel, efx) {
388 efx_for_each_channel_tx_queue(tx_queue, channel) {
389 /* We assign the PIO buffers to queues in
390 * reverse order to allow for the following
391 * special case.
392 */
393 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
394 tx_queue->channel->channel - 1) *
395 efx_piobuf_size);
396 index = offset / ER_DZ_TX_PIOBUF_SIZE;
397 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
398
399 /* When the host page size is 4K, the first
400 * host page in the WC mapping may be within
401 * the same VI page as the last TX queue. We
402 * can only link one buffer to each VI.
403 */
404 if (tx_queue->queue == nic_data->pio_write_vi_base) {
405 BUG_ON(index != 0);
406 rc = 0;
407 } else {
408 MCDI_SET_DWORD(inbuf,
409 LINK_PIOBUF_IN_PIOBUF_HANDLE,
410 nic_data->piobuf_handle[index]);
411 MCDI_SET_DWORD(inbuf,
412 LINK_PIOBUF_IN_TXQ_INSTANCE,
413 tx_queue->queue);
414 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
415 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
416 NULL, 0, NULL);
417 }
418
419 if (rc) {
420 /* This is non-fatal; the TX path just
421 * won't use PIO for this queue
422 */
423 netif_err(efx, drv, efx->net_dev,
424 "failed to link VI %u to PIO buffer %u (%d)\n",
425 tx_queue->queue, index, rc);
426 tx_queue->piobuf = NULL;
427 } else {
428 tx_queue->piobuf =
429 nic_data->pio_write_base +
430 index * EFX_VI_PAGE_SIZE + offset;
431 tx_queue->piobuf_offset = offset;
432 netif_dbg(efx, probe, efx->net_dev,
433 "linked VI %u to PIO buffer %u offset %x addr %p\n",
434 tx_queue->queue, index,
435 tx_queue->piobuf_offset,
436 tx_queue->piobuf);
437 }
438 }
439 }
440
441 return 0;
442
443fail:
444 while (index--) {
445 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
446 nic_data->pio_write_vi_base + index);
447 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
448 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
449 NULL, 0, NULL);
450 }
451 return rc;
452}
453
454#else /* !EFX_USE_PIO */
455
456static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
457{
458 return n == 0 ? 0 : -ENOBUFS;
459}
460
461static int efx_ef10_link_piobufs(struct efx_nic *efx)
462{
463 return 0;
464}
465
466static void efx_ef10_free_piobufs(struct efx_nic *efx)
467{
468}
469
470#endif /* EFX_USE_PIO */
471
472static void efx_ef10_remove(struct efx_nic *efx)
473{
474 struct efx_ef10_nic_data *nic_data = efx->nic_data;
475 int rc;
476
477 efx_ptp_remove(efx);
478
479 efx_mcdi_mon_remove(efx);
480
481 efx_ef10_rx_free_indir_table(efx);
482
483 if (nic_data->wc_membase)
484 iounmap(nic_data->wc_membase);
485
486 rc = efx_ef10_free_vis(efx);
487 WARN_ON(rc != 0);
488
489 if (!nic_data->must_restore_piobufs)
490 efx_ef10_free_piobufs(efx);
491
492 efx_mcdi_fini(efx);
493 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
494 kfree(nic_data);
495}
496
497static int efx_ef10_alloc_vis(struct efx_nic *efx,
498 unsigned int min_vis, unsigned int max_vis)
499{
500 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
501 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
502 struct efx_ef10_nic_data *nic_data = efx->nic_data;
503 size_t outlen;
504 int rc;
505
506 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
507 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
508 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
509 outbuf, sizeof(outbuf), &outlen);
510 if (rc != 0)
511 return rc;
512
513 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
514 return -EIO;
515
516 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
517 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
518
519 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
520 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
521 return 0;
522}
523
524/* Note that the failure path of this function does not free
525 * resources, as this will be done by efx_ef10_remove().
526 */
527static int efx_ef10_dimension_resources(struct efx_nic *efx)
528{
529 struct efx_ef10_nic_data *nic_data = efx->nic_data;
530 unsigned int uc_mem_map_size, wc_mem_map_size;
531 unsigned int min_vis, pio_write_vi_base, max_vis;
532 void __iomem *membase;
533 int rc;
534
535 min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
536
537#ifdef EFX_USE_PIO
538 /* Try to allocate PIO buffers if wanted and if the full
539 * number of PIO buffers would be sufficient to allocate one
540 * copy-buffer per TX channel. Failure is non-fatal, as there
541 * are only a small number of PIO buffers shared between all
542 * functions of the controller.
543 */
544 if (efx_piobuf_size != 0 &&
545 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
546 efx->n_tx_channels) {
547 unsigned int n_piobufs =
548 DIV_ROUND_UP(efx->n_tx_channels,
549 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
550
551 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
552 if (rc)
553 netif_err(efx, probe, efx->net_dev,
554 "failed to allocate PIO buffers (%d)\n", rc);
555 else
556 netif_dbg(efx, probe, efx->net_dev,
557 "allocated %u PIO buffers\n", n_piobufs);
558 }
559#else
560 nic_data->n_piobufs = 0;
561#endif
562
563 /* PIO buffers should be mapped with write-combining enabled,
564 * and we want to make single UC and WC mappings rather than
565 * several of each (in fact that's the only option if host
566 * page size is >4K). So we may allocate some extra VIs just
567 * for writing PIO buffers through.
568 *
569 * The UC mapping contains (min_vis - 1) complete VIs and the
570 * first half of the next VI. Then the WC mapping begins with
571 * the second half of this last VI.
572 */
573 uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE +
574 ER_DZ_TX_PIOBUF);
575 if (nic_data->n_piobufs) {
576 /* pio_write_vi_base rounds down to give the number of complete
577 * VIs inside the UC mapping.
578 */
579 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
580 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
581 nic_data->n_piobufs) *
582 EFX_VI_PAGE_SIZE) -
583 uc_mem_map_size);
584 max_vis = pio_write_vi_base + nic_data->n_piobufs;
585 } else {
586 pio_write_vi_base = 0;
587 wc_mem_map_size = 0;
588 max_vis = min_vis;
589 }
590
591 /* In case the last attached driver failed to free VIs, do it now */
592 rc = efx_ef10_free_vis(efx);
593 if (rc != 0)
594 return rc;
595
596 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
597 if (rc != 0)
598 return rc;
599
600 /* If we didn't get enough VIs to map all the PIO buffers, free the
601 * PIO buffers
602 */
603 if (nic_data->n_piobufs &&
604 nic_data->n_allocated_vis <
605 pio_write_vi_base + nic_data->n_piobufs) {
606 netif_dbg(efx, probe, efx->net_dev,
607 "%u VIs are not sufficient to map %u PIO buffers\n",
608 nic_data->n_allocated_vis, nic_data->n_piobufs);
609 efx_ef10_free_piobufs(efx);
610 }
611
612 /* Shrink the original UC mapping of the memory BAR */
613 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
614 if (!membase) {
615 netif_err(efx, probe, efx->net_dev,
616 "could not shrink memory BAR to %x\n",
617 uc_mem_map_size);
618 return -ENOMEM;
619 }
620 iounmap(efx->membase);
621 efx->membase = membase;
622
623 /* Set up the WC mapping if needed */
624 if (wc_mem_map_size) {
625 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
626 uc_mem_map_size,
627 wc_mem_map_size);
628 if (!nic_data->wc_membase) {
629 netif_err(efx, probe, efx->net_dev,
630 "could not allocate WC mapping of size %x\n",
631 wc_mem_map_size);
632 return -ENOMEM;
633 }
634 nic_data->pio_write_vi_base = pio_write_vi_base;
635 nic_data->pio_write_base =
636 nic_data->wc_membase +
637 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
638 uc_mem_map_size);
639
640 rc = efx_ef10_link_piobufs(efx);
641 if (rc)
642 efx_ef10_free_piobufs(efx);
643 }
644
645 netif_dbg(efx, probe, efx->net_dev,
646 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
647 &efx->membase_phys, efx->membase, uc_mem_map_size,
648 nic_data->wc_membase, wc_mem_map_size);
649
650 return 0;
651}
652
653static int efx_ef10_init_nic(struct efx_nic *efx)
654{
655 struct efx_ef10_nic_data *nic_data = efx->nic_data;
656 int rc;
657
658 if (nic_data->must_check_datapath_caps) {
659 rc = efx_ef10_init_datapath_caps(efx);
660 if (rc)
661 return rc;
662 nic_data->must_check_datapath_caps = false;
663 }
664
665 if (nic_data->must_realloc_vis) {
666 /* We cannot let the number of VIs change now */
667 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
668 nic_data->n_allocated_vis);
669 if (rc)
670 return rc;
671 nic_data->must_realloc_vis = false;
672 }
673
674 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
675 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
676 if (rc == 0) {
677 rc = efx_ef10_link_piobufs(efx);
678 if (rc)
679 efx_ef10_free_piobufs(efx);
680 }
681
682 /* Log an error on failure, but this is non-fatal */
683 if (rc)
684 netif_err(efx, drv, efx->net_dev,
685 "failed to restore PIO buffers (%d)\n", rc);
686 nic_data->must_restore_piobufs = false;
687 }
688
689 efx_ef10_rx_push_rss_config(efx);
690 return 0;
691}
692
693static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
694{
695 struct efx_ef10_nic_data *nic_data = efx->nic_data;
696
697 /* All our allocations have been reset */
698 nic_data->must_realloc_vis = true;
699 nic_data->must_restore_filters = true;
700 nic_data->must_restore_piobufs = true;
701 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
702}
703
704static int efx_ef10_map_reset_flags(u32 *flags)
705{
706 enum {
707 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
708 ETH_RESET_SHARED_SHIFT),
709 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
710 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
711 ETH_RESET_PHY | ETH_RESET_MGMT) <<
712 ETH_RESET_SHARED_SHIFT)
713 };
714
715 /* We assume for now that our PCI function is permitted to
716 * reset everything.
717 */
718
719 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
720 *flags &= ~EF10_RESET_MC;
721 return RESET_TYPE_WORLD;
722 }
723
724 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
725 *flags &= ~EF10_RESET_PORT;
726 return RESET_TYPE_ALL;
727 }
728
729 /* no invisible reset implemented */
730
731 return -EINVAL;
732}
733
734static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
735{
736 int rc = efx_mcdi_reset(efx, reset_type);
737
738 /* If it was a port reset, trigger reallocation of MC resources.
739 * Note that on an MC reset nothing needs to be done now because we'll
740 * detect the MC reset later and handle it then.
741 * For an FLR, we never get an MC reset event, but the MC has reset all
742 * resources assigned to us, so we have to trigger reallocation now.
743 */
744 if ((reset_type == RESET_TYPE_ALL ||
745 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
746 efx_ef10_reset_mc_allocations(efx);
747 return rc;
748}
749
750#define EF10_DMA_STAT(ext_name, mcdi_name) \
751 [EF10_STAT_ ## ext_name] = \
752 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
753#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
754 [EF10_STAT_ ## int_name] = \
755 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
756#define EF10_OTHER_STAT(ext_name) \
757 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
758
759static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
760 EF10_DMA_STAT(tx_bytes, TX_BYTES),
761 EF10_DMA_STAT(tx_packets, TX_PKTS),
762 EF10_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
763 EF10_DMA_STAT(tx_control, TX_CONTROL_PKTS),
764 EF10_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
765 EF10_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
766 EF10_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
767 EF10_DMA_STAT(tx_lt64, TX_LT64_PKTS),
768 EF10_DMA_STAT(tx_64, TX_64_PKTS),
769 EF10_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
770 EF10_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
771 EF10_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
772 EF10_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
773 EF10_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
774 EF10_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
775 EF10_DMA_STAT(rx_bytes, RX_BYTES),
776 EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes, RX_BAD_BYTES),
777 EF10_OTHER_STAT(rx_good_bytes),
778 EF10_OTHER_STAT(rx_bad_bytes),
779 EF10_DMA_STAT(rx_packets, RX_PKTS),
780 EF10_DMA_STAT(rx_good, RX_GOOD_PKTS),
781 EF10_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
782 EF10_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
783 EF10_DMA_STAT(rx_control, RX_CONTROL_PKTS),
784 EF10_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
785 EF10_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
786 EF10_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
787 EF10_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
788 EF10_DMA_STAT(rx_64, RX_64_PKTS),
789 EF10_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
790 EF10_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
791 EF10_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
792 EF10_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
793 EF10_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
794 EF10_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
795 EF10_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
796 EF10_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
797 EF10_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
798 EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
799 EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
800 EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS),
801 EF10_DMA_STAT(rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
802 EF10_DMA_STAT(rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
803 EF10_DMA_STAT(rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
804 EF10_DMA_STAT(rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
805 EF10_DMA_STAT(rx_pm_trunc_qbb, PM_TRUNC_QBB),
806 EF10_DMA_STAT(rx_pm_discard_qbb, PM_DISCARD_QBB),
807 EF10_DMA_STAT(rx_pm_discard_mapping, PM_DISCARD_MAPPING),
808 EF10_DMA_STAT(rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
809 EF10_DMA_STAT(rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
810 EF10_DMA_STAT(rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
811 EF10_DMA_STAT(rx_dp_hlb_fetch, RXDP_EMERGENCY_FETCH_CONDITIONS),
812 EF10_DMA_STAT(rx_dp_hlb_wait, RXDP_EMERGENCY_WAIT_CONDITIONS),
813};
814
815#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) | \
816 (1ULL << EF10_STAT_tx_packets) | \
817 (1ULL << EF10_STAT_tx_pause) | \
818 (1ULL << EF10_STAT_tx_unicast) | \
819 (1ULL << EF10_STAT_tx_multicast) | \
820 (1ULL << EF10_STAT_tx_broadcast) | \
821 (1ULL << EF10_STAT_rx_bytes) | \
822 (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \
823 (1ULL << EF10_STAT_rx_good_bytes) | \
824 (1ULL << EF10_STAT_rx_bad_bytes) | \
825 (1ULL << EF10_STAT_rx_packets) | \
826 (1ULL << EF10_STAT_rx_good) | \
827 (1ULL << EF10_STAT_rx_bad) | \
828 (1ULL << EF10_STAT_rx_pause) | \
829 (1ULL << EF10_STAT_rx_control) | \
830 (1ULL << EF10_STAT_rx_unicast) | \
831 (1ULL << EF10_STAT_rx_multicast) | \
832 (1ULL << EF10_STAT_rx_broadcast) | \
833 (1ULL << EF10_STAT_rx_lt64) | \
834 (1ULL << EF10_STAT_rx_64) | \
835 (1ULL << EF10_STAT_rx_65_to_127) | \
836 (1ULL << EF10_STAT_rx_128_to_255) | \
837 (1ULL << EF10_STAT_rx_256_to_511) | \
838 (1ULL << EF10_STAT_rx_512_to_1023) | \
839 (1ULL << EF10_STAT_rx_1024_to_15xx) | \
840 (1ULL << EF10_STAT_rx_15xx_to_jumbo) | \
841 (1ULL << EF10_STAT_rx_gtjumbo) | \
842 (1ULL << EF10_STAT_rx_bad_gtjumbo) | \
843 (1ULL << EF10_STAT_rx_overflow) | \
844 (1ULL << EF10_STAT_rx_nodesc_drops))
845
846/* These statistics are only provided by the 10G MAC. For a 10G/40G
847 * switchable port we do not expose these because they might not
848 * include all the packets they should.
849 */
850#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) | \
851 (1ULL << EF10_STAT_tx_lt64) | \
852 (1ULL << EF10_STAT_tx_64) | \
853 (1ULL << EF10_STAT_tx_65_to_127) | \
854 (1ULL << EF10_STAT_tx_128_to_255) | \
855 (1ULL << EF10_STAT_tx_256_to_511) | \
856 (1ULL << EF10_STAT_tx_512_to_1023) | \
857 (1ULL << EF10_STAT_tx_1024_to_15xx) | \
858 (1ULL << EF10_STAT_tx_15xx_to_jumbo))
859
860/* These statistics are only provided by the 40G MAC. For a 10G/40G
861 * switchable port we do expose these because the errors will otherwise
862 * be silent.
863 */
864#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) | \
865 (1ULL << EF10_STAT_rx_length_error))
866
867/* These statistics are only provided if the firmware supports the
868 * capability PM_AND_RXDP_COUNTERS.
869 */
870#define HUNT_PM_AND_RXDP_STAT_MASK ( \
871 (1ULL << EF10_STAT_rx_pm_trunc_bb_overflow) | \
872 (1ULL << EF10_STAT_rx_pm_discard_bb_overflow) | \
873 (1ULL << EF10_STAT_rx_pm_trunc_vfifo_full) | \
874 (1ULL << EF10_STAT_rx_pm_discard_vfifo_full) | \
875 (1ULL << EF10_STAT_rx_pm_trunc_qbb) | \
876 (1ULL << EF10_STAT_rx_pm_discard_qbb) | \
877 (1ULL << EF10_STAT_rx_pm_discard_mapping) | \
878 (1ULL << EF10_STAT_rx_dp_q_disabled_packets) | \
879 (1ULL << EF10_STAT_rx_dp_di_dropped_packets) | \
880 (1ULL << EF10_STAT_rx_dp_streaming_packets) | \
881 (1ULL << EF10_STAT_rx_dp_hlb_fetch) | \
882 (1ULL << EF10_STAT_rx_dp_hlb_wait))
883
884static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
885{
886 u64 raw_mask = HUNT_COMMON_STAT_MASK;
887 u32 port_caps = efx_mcdi_phy_get_caps(efx);
888 struct efx_ef10_nic_data *nic_data = efx->nic_data;
889
890 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
891 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
892 else
893 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
894
895 if (nic_data->datapath_caps &
896 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
897 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
898
899 return raw_mask;
900}
901
902static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
903{
904 u64 raw_mask = efx_ef10_raw_stat_mask(efx);
905
906#if BITS_PER_LONG == 64
907 mask[0] = raw_mask;
908#else
909 mask[0] = raw_mask & 0xffffffff;
910 mask[1] = raw_mask >> 32;
911#endif
912}
913
914static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
915{
916 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
917
918 efx_ef10_get_stat_mask(efx, mask);
919 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
920 mask, names);
921}
922
923static int efx_ef10_try_update_nic_stats(struct efx_nic *efx)
924{
925 struct efx_ef10_nic_data *nic_data = efx->nic_data;
926 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
927 __le64 generation_start, generation_end;
928 u64 *stats = nic_data->stats;
929 __le64 *dma_stats;
930
931 efx_ef10_get_stat_mask(efx, mask);
932
933 dma_stats = efx->stats_buffer.addr;
934 nic_data = efx->nic_data;
935
936 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
937 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
938 return 0;
939 rmb();
940 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
941 stats, efx->stats_buffer.addr, false);
942 rmb();
943 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
944 if (generation_end != generation_start)
945 return -EAGAIN;
946
947 /* Update derived statistics */
948 efx_nic_fix_nodesc_drop_stat(efx, &stats[EF10_STAT_rx_nodesc_drops]);
949 stats[EF10_STAT_rx_good_bytes] =
950 stats[EF10_STAT_rx_bytes] -
951 stats[EF10_STAT_rx_bytes_minus_good_bytes];
952 efx_update_diff_stat(&stats[EF10_STAT_rx_bad_bytes],
953 stats[EF10_STAT_rx_bytes_minus_good_bytes]);
954
955 return 0;
956}
957
958
959static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats,
960 struct rtnl_link_stats64 *core_stats)
961{
962 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
963 struct efx_ef10_nic_data *nic_data = efx->nic_data;
964 u64 *stats = nic_data->stats;
965 size_t stats_count = 0, index;
966 int retry;
967
968 efx_ef10_get_stat_mask(efx, mask);
969
970 /* If we're unlucky enough to read statistics during the DMA, wait
971 * up to 10ms for it to finish (typically takes <500us)
972 */
973 for (retry = 0; retry < 100; ++retry) {
974 if (efx_ef10_try_update_nic_stats(efx) == 0)
975 break;
976 udelay(100);
977 }
978
979 if (full_stats) {
980 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
981 if (efx_ef10_stat_desc[index].name) {
982 *full_stats++ = stats[index];
983 ++stats_count;
984 }
985 }
986 }
987
988 if (core_stats) {
989 core_stats->rx_packets = stats[EF10_STAT_rx_packets];
990 core_stats->tx_packets = stats[EF10_STAT_tx_packets];
991 core_stats->rx_bytes = stats[EF10_STAT_rx_bytes];
992 core_stats->tx_bytes = stats[EF10_STAT_tx_bytes];
993 core_stats->rx_dropped = stats[EF10_STAT_rx_nodesc_drops];
994 core_stats->multicast = stats[EF10_STAT_rx_multicast];
995 core_stats->rx_length_errors =
996 stats[EF10_STAT_rx_gtjumbo] +
997 stats[EF10_STAT_rx_length_error];
998 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
999 core_stats->rx_frame_errors = stats[EF10_STAT_rx_align_error];
1000 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1001 core_stats->rx_errors = (core_stats->rx_length_errors +
1002 core_stats->rx_crc_errors +
1003 core_stats->rx_frame_errors);
1004 }
1005
1006 return stats_count;
1007}
1008
1009static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1010{
1011 struct efx_nic *efx = channel->efx;
1012 unsigned int mode, value;
1013 efx_dword_t timer_cmd;
1014
1015 if (channel->irq_moderation) {
1016 mode = 3;
1017 value = channel->irq_moderation - 1;
1018 } else {
1019 mode = 0;
1020 value = 0;
1021 }
1022
1023 if (EFX_EF10_WORKAROUND_35388(efx)) {
1024 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1025 EFE_DD_EVQ_IND_TIMER_FLAGS,
1026 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1027 ERF_DD_EVQ_IND_TIMER_VAL, value);
1028 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1029 channel->channel);
1030 } else {
1031 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1032 ERF_DZ_TC_TIMER_VAL, value);
1033 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1034 channel->channel);
1035 }
1036}
1037
1038static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1039{
1040 wol->supported = 0;
1041 wol->wolopts = 0;
1042 memset(&wol->sopass, 0, sizeof(wol->sopass));
1043}
1044
1045static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1046{
1047 if (type != 0)
1048 return -EINVAL;
1049 return 0;
1050}
1051
1052static void efx_ef10_mcdi_request(struct efx_nic *efx,
1053 const efx_dword_t *hdr, size_t hdr_len,
1054 const efx_dword_t *sdu, size_t sdu_len)
1055{
1056 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1057 u8 *pdu = nic_data->mcdi_buf.addr;
1058
1059 memcpy(pdu, hdr, hdr_len);
1060 memcpy(pdu + hdr_len, sdu, sdu_len);
1061 wmb();
1062
1063 /* The hardware provides 'low' and 'high' (doorbell) registers
1064 * for passing the 64-bit address of an MCDI request to
1065 * firmware. However the dwords are swapped by firmware. The
1066 * least significant bits of the doorbell are then 0 for all
1067 * MCDI requests due to alignment.
1068 */
1069 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1070 ER_DZ_MC_DB_LWRD);
1071 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1072 ER_DZ_MC_DB_HWRD);
1073}
1074
1075static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1076{
1077 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1078 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1079
1080 rmb();
1081 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1082}
1083
1084static void
1085efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1086 size_t offset, size_t outlen)
1087{
1088 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1089 const u8 *pdu = nic_data->mcdi_buf.addr;
1090
1091 memcpy(outbuf, pdu + offset, outlen);
1092}
1093
1094static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1095{
1096 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1097 int rc;
1098
1099 rc = efx_ef10_get_warm_boot_count(efx);
1100 if (rc < 0) {
1101 /* The firmware is presumably in the process of
1102 * rebooting. However, we are supposed to report each
1103 * reboot just once, so we must only do that once we
1104 * can read and store the updated warm boot count.
1105 */
1106 return 0;
1107 }
1108
1109 if (rc == nic_data->warm_boot_count)
1110 return 0;
1111
1112 nic_data->warm_boot_count = rc;
1113
1114 /* All our allocations have been reset */
1115 efx_ef10_reset_mc_allocations(efx);
1116
1117 /* The datapath firmware might have been changed */
1118 nic_data->must_check_datapath_caps = true;
1119
1120 /* MAC statistics have been cleared on the NIC; clear the local
1121 * statistic that we update with efx_update_diff_stat().
1122 */
1123 nic_data->stats[EF10_STAT_rx_bad_bytes] = 0;
1124
1125 return -EIO;
1126}
1127
1128/* Handle an MSI interrupt
1129 *
1130 * Handle an MSI hardware interrupt. This routine schedules event
1131 * queue processing. No interrupt acknowledgement cycle is necessary.
1132 * Also, we never need to check that the interrupt is for us, since
1133 * MSI interrupts cannot be shared.
1134 */
1135static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1136{
1137 struct efx_msi_context *context = dev_id;
1138 struct efx_nic *efx = context->efx;
1139
1140 netif_vdbg(efx, intr, efx->net_dev,
1141 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1142
1143 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1144 /* Note test interrupts */
1145 if (context->index == efx->irq_level)
1146 efx->last_irq_cpu = raw_smp_processor_id();
1147
1148 /* Schedule processing of the channel */
1149 efx_schedule_channel_irq(efx->channel[context->index]);
1150 }
1151
1152 return IRQ_HANDLED;
1153}
1154
1155static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1156{
1157 struct efx_nic *efx = dev_id;
1158 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1159 struct efx_channel *channel;
1160 efx_dword_t reg;
1161 u32 queues;
1162
1163 /* Read the ISR which also ACKs the interrupts */
1164 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR);
1165 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1166
1167 if (queues == 0)
1168 return IRQ_NONE;
1169
1170 if (likely(soft_enabled)) {
1171 /* Note test interrupts */
1172 if (queues & (1U << efx->irq_level))
1173 efx->last_irq_cpu = raw_smp_processor_id();
1174
1175 efx_for_each_channel(channel, efx) {
1176 if (queues & 1)
1177 efx_schedule_channel_irq(channel);
1178 queues >>= 1;
1179 }
1180 }
1181
1182 netif_vdbg(efx, intr, efx->net_dev,
1183 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1184 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1185
1186 return IRQ_HANDLED;
1187}
1188
1189static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1190{
1191 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1192
1193 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1194
1195 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1196 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1197 inbuf, sizeof(inbuf), NULL, 0, NULL);
1198}
1199
1200static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1201{
1202 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1203 (tx_queue->ptr_mask + 1) *
1204 sizeof(efx_qword_t),
1205 GFP_KERNEL);
1206}
1207
1208/* This writes to the TX_DESC_WPTR and also pushes data */
1209static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1210 const efx_qword_t *txd)
1211{
1212 unsigned int write_ptr;
1213 efx_oword_t reg;
1214
1215 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1216 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1217 reg.qword[0] = *txd;
1218 efx_writeo_page(tx_queue->efx, ®,
1219 ER_DZ_TX_DESC_UPD, tx_queue->queue);
1220}
1221
1222static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1223{
1224 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1225 EFX_BUF_SIZE));
1226 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_TXQ_OUT_LEN);
1227 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1228 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1229 struct efx_channel *channel = tx_queue->channel;
1230 struct efx_nic *efx = tx_queue->efx;
1231 size_t inlen, outlen;
1232 dma_addr_t dma_addr;
1233 efx_qword_t *txd;
1234 int rc;
1235 int i;
1236
1237 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1238 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1239 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1240 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1241 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1242 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1243 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1244 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
1245 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1246
1247 dma_addr = tx_queue->txd.buf.dma_addr;
1248
1249 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1250 tx_queue->queue, entries, (u64)dma_addr);
1251
1252 for (i = 0; i < entries; ++i) {
1253 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1254 dma_addr += EFX_BUF_SIZE;
1255 }
1256
1257 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1258
1259 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
1260 outbuf, sizeof(outbuf), &outlen);
1261 if (rc)
1262 goto fail;
1263
1264 /* A previous user of this TX queue might have set us up the
1265 * bomb by writing a descriptor to the TX push collector but
1266 * not the doorbell. (Each collector belongs to a port, not a
1267 * queue or function, so cannot easily be reset.) We must
1268 * attempt to push a no-op descriptor in its place.
1269 */
1270 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1271 tx_queue->insert_count = 1;
1272 txd = efx_tx_desc(tx_queue, 0);
1273 EFX_POPULATE_QWORD_4(*txd,
1274 ESF_DZ_TX_DESC_IS_OPT, true,
1275 ESF_DZ_TX_OPTION_TYPE,
1276 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1277 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1278 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1279 tx_queue->write_count = 1;
1280 wmb();
1281 efx_ef10_push_tx_desc(tx_queue, txd);
1282
1283 return;
1284
1285fail:
1286 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1287 tx_queue->queue);
1288}
1289
1290static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1291{
1292 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
1293 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_TXQ_OUT_LEN);
1294 struct efx_nic *efx = tx_queue->efx;
1295 size_t outlen;
1296 int rc;
1297
1298 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1299 tx_queue->queue);
1300
1301 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
1302 outbuf, sizeof(outbuf), &outlen);
1303
1304 if (rc && rc != -EALREADY)
1305 goto fail;
1306
1307 return;
1308
1309fail:
1310 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1311 outbuf, outlen, rc);
1312}
1313
1314static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1315{
1316 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1317}
1318
1319/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1320static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1321{
1322 unsigned int write_ptr;
1323 efx_dword_t reg;
1324
1325 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1326 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1327 efx_writed_page(tx_queue->efx, ®,
1328 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1329}
1330
1331static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1332{
1333 unsigned int old_write_count = tx_queue->write_count;
1334 struct efx_tx_buffer *buffer;
1335 unsigned int write_ptr;
1336 efx_qword_t *txd;
1337
1338 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
1339
1340 do {
1341 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1342 buffer = &tx_queue->buffer[write_ptr];
1343 txd = efx_tx_desc(tx_queue, write_ptr);
1344 ++tx_queue->write_count;
1345
1346 /* Create TX descriptor ring entry */
1347 if (buffer->flags & EFX_TX_BUF_OPTION) {
1348 *txd = buffer->option;
1349 } else {
1350 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1351 EFX_POPULATE_QWORD_3(
1352 *txd,
1353 ESF_DZ_TX_KER_CONT,
1354 buffer->flags & EFX_TX_BUF_CONT,
1355 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1356 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1357 }
1358 } while (tx_queue->write_count != tx_queue->insert_count);
1359
1360 wmb(); /* Ensure descriptors are written before they are fetched */
1361
1362 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1363 txd = efx_tx_desc(tx_queue,
1364 old_write_count & tx_queue->ptr_mask);
1365 efx_ef10_push_tx_desc(tx_queue, txd);
1366 ++tx_queue->pushes;
1367 } else {
1368 efx_ef10_notify_tx_desc(tx_queue);
1369 }
1370}
1371
1372static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context)
1373{
1374 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1375 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
1376 size_t outlen;
1377 int rc;
1378
1379 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
1380 EVB_PORT_ID_ASSIGNED);
1381 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE,
1382 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE);
1383 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES,
1384 EFX_MAX_CHANNELS);
1385
1386 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1387 outbuf, sizeof(outbuf), &outlen);
1388 if (rc != 0)
1389 return rc;
1390
1391 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1392 return -EIO;
1393
1394 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1395
1396 return 0;
1397}
1398
1399static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1400{
1401 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1402 int rc;
1403
1404 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1405 context);
1406
1407 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1408 NULL, 0, NULL);
1409 WARN_ON(rc != 0);
1410}
1411
1412static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context)
1413{
1414 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1415 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1416 int i, rc;
1417
1418 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1419 context);
1420 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1421 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1422
1423 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1424 MCDI_PTR(tablebuf,
1425 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
1426 (u8) efx->rx_indir_table[i];
1427
1428 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1429 sizeof(tablebuf), NULL, 0, NULL);
1430 if (rc != 0)
1431 return rc;
1432
1433 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1434 context);
1435 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1436 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1437 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1438 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1439 efx->rx_hash_key[i];
1440
1441 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1442 sizeof(keybuf), NULL, 0, NULL);
1443}
1444
1445static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1446{
1447 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1448
1449 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1450 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1451 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1452}
1453
1454static void efx_ef10_rx_push_rss_config(struct efx_nic *efx)
1455{
1456 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1457 int rc;
1458
1459 netif_dbg(efx, drv, efx->net_dev, "pushing RSS config\n");
1460
1461 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) {
1462 rc = efx_ef10_alloc_rss_context(efx, &nic_data->rx_rss_context);
1463 if (rc != 0)
1464 goto fail;
1465 }
1466
1467 rc = efx_ef10_populate_rss_table(efx, nic_data->rx_rss_context);
1468 if (rc != 0)
1469 goto fail;
1470
1471 return;
1472
1473fail:
1474 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1475}
1476
1477static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
1478{
1479 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
1480 (rx_queue->ptr_mask + 1) *
1481 sizeof(efx_qword_t),
1482 GFP_KERNEL);
1483}
1484
1485static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
1486{
1487 MCDI_DECLARE_BUF(inbuf,
1488 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1489 EFX_BUF_SIZE));
1490 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_RXQ_OUT_LEN);
1491 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1492 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
1493 struct efx_nic *efx = rx_queue->efx;
1494 size_t inlen, outlen;
1495 dma_addr_t dma_addr;
1496 int rc;
1497 int i;
1498
1499 rx_queue->scatter_n = 0;
1500 rx_queue->scatter_len = 0;
1501
1502 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
1503 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
1504 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
1505 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
1506 efx_rx_queue_index(rx_queue));
1507 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
1508 INIT_RXQ_IN_FLAG_PREFIX, 1,
1509 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
1510 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
1511 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1512
1513 dma_addr = rx_queue->rxd.buf.dma_addr;
1514
1515 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
1516 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
1517
1518 for (i = 0; i < entries; ++i) {
1519 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
1520 dma_addr += EFX_BUF_SIZE;
1521 }
1522
1523 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
1524
1525 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
1526 outbuf, sizeof(outbuf), &outlen);
1527 if (rc)
1528 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
1529 efx_rx_queue_index(rx_queue));
1530}
1531
1532static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
1533{
1534 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
1535 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_RXQ_OUT_LEN);
1536 struct efx_nic *efx = rx_queue->efx;
1537 size_t outlen;
1538 int rc;
1539
1540 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
1541 efx_rx_queue_index(rx_queue));
1542
1543 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
1544 outbuf, sizeof(outbuf), &outlen);
1545
1546 if (rc && rc != -EALREADY)
1547 goto fail;
1548
1549 return;
1550
1551fail:
1552 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
1553 outbuf, outlen, rc);
1554}
1555
1556static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
1557{
1558 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
1559}
1560
1561/* This creates an entry in the RX descriptor queue */
1562static inline void
1563efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
1564{
1565 struct efx_rx_buffer *rx_buf;
1566 efx_qword_t *rxd;
1567
1568 rxd = efx_rx_desc(rx_queue, index);
1569 rx_buf = efx_rx_buffer(rx_queue, index);
1570 EFX_POPULATE_QWORD_2(*rxd,
1571 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
1572 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
1573}
1574
1575static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
1576{
1577 struct efx_nic *efx = rx_queue->efx;
1578 unsigned int write_count;
1579 efx_dword_t reg;
1580
1581 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
1582 write_count = rx_queue->added_count & ~7;
1583 if (rx_queue->notified_count == write_count)
1584 return;
1585
1586 do
1587 efx_ef10_build_rx_desc(
1588 rx_queue,
1589 rx_queue->notified_count & rx_queue->ptr_mask);
1590 while (++rx_queue->notified_count != write_count);
1591
1592 wmb();
1593 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
1594 write_count & rx_queue->ptr_mask);
1595 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD,
1596 efx_rx_queue_index(rx_queue));
1597}
1598
1599static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
1600
1601static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
1602{
1603 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1604 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
1605 efx_qword_t event;
1606
1607 EFX_POPULATE_QWORD_2(event,
1608 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
1609 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
1610
1611 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
1612
1613 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
1614 * already swapped the data to little-endian order.
1615 */
1616 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
1617 sizeof(efx_qword_t));
1618
1619 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
1620 inbuf, sizeof(inbuf), 0,
1621 efx_ef10_rx_defer_refill_complete, 0);
1622}
1623
1624static void
1625efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
1626 int rc, efx_dword_t *outbuf,
1627 size_t outlen_actual)
1628{
1629 /* nothing to do */
1630}
1631
1632static int efx_ef10_ev_probe(struct efx_channel *channel)
1633{
1634 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
1635 (channel->eventq_mask + 1) *
1636 sizeof(efx_qword_t),
1637 GFP_KERNEL);
1638}
1639
1640static int efx_ef10_ev_init(struct efx_channel *channel)
1641{
1642 MCDI_DECLARE_BUF(inbuf,
1643 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
1644 EFX_BUF_SIZE));
1645 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
1646 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
1647 struct efx_nic *efx = channel->efx;
1648 struct efx_ef10_nic_data *nic_data;
1649 bool supports_rx_merge;
1650 size_t inlen, outlen;
1651 dma_addr_t dma_addr;
1652 int rc;
1653 int i;
1654
1655 nic_data = efx->nic_data;
1656 supports_rx_merge =
1657 !!(nic_data->datapath_caps &
1658 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
1659
1660 /* Fill event queue with all ones (i.e. empty events) */
1661 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1662
1663 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
1664 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
1665 /* INIT_EVQ expects index in vector table, not absolute */
1666 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
1667 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
1668 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
1669 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
1670 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
1671 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
1672 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
1673 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
1674 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
1675 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
1676 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
1677 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
1678 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
1679
1680 dma_addr = channel->eventq.buf.dma_addr;
1681 for (i = 0; i < entries; ++i) {
1682 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
1683 dma_addr += EFX_BUF_SIZE;
1684 }
1685
1686 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
1687
1688 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
1689 outbuf, sizeof(outbuf), &outlen);
1690 /* IRQ return is ignored */
1691 return rc;
1692}
1693
1694static void efx_ef10_ev_fini(struct efx_channel *channel)
1695{
1696 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
1697 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_EVQ_OUT_LEN);
1698 struct efx_nic *efx = channel->efx;
1699 size_t outlen;
1700 int rc;
1701
1702 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
1703
1704 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
1705 outbuf, sizeof(outbuf), &outlen);
1706
1707 if (rc && rc != -EALREADY)
1708 goto fail;
1709
1710 return;
1711
1712fail:
1713 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
1714 outbuf, outlen, rc);
1715}
1716
1717static void efx_ef10_ev_remove(struct efx_channel *channel)
1718{
1719 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
1720}
1721
1722static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
1723 unsigned int rx_queue_label)
1724{
1725 struct efx_nic *efx = rx_queue->efx;
1726
1727 netif_info(efx, hw, efx->net_dev,
1728 "rx event arrived on queue %d labeled as queue %u\n",
1729 efx_rx_queue_index(rx_queue), rx_queue_label);
1730
1731 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1732}
1733
1734static void
1735efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
1736 unsigned int actual, unsigned int expected)
1737{
1738 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
1739 struct efx_nic *efx = rx_queue->efx;
1740
1741 netif_info(efx, hw, efx->net_dev,
1742 "dropped %d events (index=%d expected=%d)\n",
1743 dropped, actual, expected);
1744
1745 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1746}
1747
1748/* partially received RX was aborted. clean up. */
1749static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
1750{
1751 unsigned int rx_desc_ptr;
1752
1753 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
1754 "scattered RX aborted (dropping %u buffers)\n",
1755 rx_queue->scatter_n);
1756
1757 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
1758
1759 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
1760 0, EFX_RX_PKT_DISCARD);
1761
1762 rx_queue->removed_count += rx_queue->scatter_n;
1763 rx_queue->scatter_n = 0;
1764 rx_queue->scatter_len = 0;
1765 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
1766}
1767
1768static int efx_ef10_handle_rx_event(struct efx_channel *channel,
1769 const efx_qword_t *event)
1770{
1771 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
1772 unsigned int n_descs, n_packets, i;
1773 struct efx_nic *efx = channel->efx;
1774 struct efx_rx_queue *rx_queue;
1775 bool rx_cont;
1776 u16 flags = 0;
1777
1778 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1779 return 0;
1780
1781 /* Basic packet information */
1782 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
1783 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
1784 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
1785 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
1786 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
1787
1788 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
1789 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
1790 EFX_QWORD_FMT "\n",
1791 EFX_QWORD_VAL(*event));
1792
1793 rx_queue = efx_channel_get_rx_queue(channel);
1794
1795 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
1796 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
1797
1798 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
1799 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1800
1801 if (n_descs != rx_queue->scatter_n + 1) {
1802 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1803
1804 /* detect rx abort */
1805 if (unlikely(n_descs == rx_queue->scatter_n)) {
1806 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
1807 netdev_WARN(efx->net_dev,
1808 "invalid RX abort: scatter_n=%u event="
1809 EFX_QWORD_FMT "\n",
1810 rx_queue->scatter_n,
1811 EFX_QWORD_VAL(*event));
1812 efx_ef10_handle_rx_abort(rx_queue);
1813 return 0;
1814 }
1815
1816 /* Check that RX completion merging is valid, i.e.
1817 * the current firmware supports it and this is a
1818 * non-scattered packet.
1819 */
1820 if (!(nic_data->datapath_caps &
1821 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
1822 rx_queue->scatter_n != 0 || rx_cont) {
1823 efx_ef10_handle_rx_bad_lbits(
1824 rx_queue, next_ptr_lbits,
1825 (rx_queue->removed_count +
1826 rx_queue->scatter_n + 1) &
1827 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1828 return 0;
1829 }
1830
1831 /* Merged completion for multiple non-scattered packets */
1832 rx_queue->scatter_n = 1;
1833 rx_queue->scatter_len = 0;
1834 n_packets = n_descs;
1835 ++channel->n_rx_merge_events;
1836 channel->n_rx_merge_packets += n_packets;
1837 flags |= EFX_RX_PKT_PREFIX_LEN;
1838 } else {
1839 ++rx_queue->scatter_n;
1840 rx_queue->scatter_len += rx_bytes;
1841 if (rx_cont)
1842 return 0;
1843 n_packets = 1;
1844 }
1845
1846 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
1847 flags |= EFX_RX_PKT_DISCARD;
1848
1849 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
1850 channel->n_rx_ip_hdr_chksum_err += n_packets;
1851 } else if (unlikely(EFX_QWORD_FIELD(*event,
1852 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
1853 channel->n_rx_tcp_udp_chksum_err += n_packets;
1854 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
1855 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
1856 flags |= EFX_RX_PKT_CSUMMED;
1857 }
1858
1859 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
1860 flags |= EFX_RX_PKT_TCP;
1861
1862 channel->irq_mod_score += 2 * n_packets;
1863
1864 /* Handle received packet(s) */
1865 for (i = 0; i < n_packets; i++) {
1866 efx_rx_packet(rx_queue,
1867 rx_queue->removed_count & rx_queue->ptr_mask,
1868 rx_queue->scatter_n, rx_queue->scatter_len,
1869 flags);
1870 rx_queue->removed_count += rx_queue->scatter_n;
1871 }
1872
1873 rx_queue->scatter_n = 0;
1874 rx_queue->scatter_len = 0;
1875
1876 return n_packets;
1877}
1878
1879static int
1880efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
1881{
1882 struct efx_nic *efx = channel->efx;
1883 struct efx_tx_queue *tx_queue;
1884 unsigned int tx_ev_desc_ptr;
1885 unsigned int tx_ev_q_label;
1886 int tx_descs = 0;
1887
1888 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1889 return 0;
1890
1891 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
1892 return 0;
1893
1894 /* Transmit completion */
1895 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
1896 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
1897 tx_queue = efx_channel_get_tx_queue(channel,
1898 tx_ev_q_label % EFX_TXQ_TYPES);
1899 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
1900 tx_queue->ptr_mask);
1901 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
1902
1903 return tx_descs;
1904}
1905
1906static void
1907efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1908{
1909 struct efx_nic *efx = channel->efx;
1910 int subcode;
1911
1912 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
1913
1914 switch (subcode) {
1915 case ESE_DZ_DRV_TIMER_EV:
1916 case ESE_DZ_DRV_WAKE_UP_EV:
1917 break;
1918 case ESE_DZ_DRV_START_UP_EV:
1919 /* event queue init complete. ok. */
1920 break;
1921 default:
1922 netif_err(efx, hw, efx->net_dev,
1923 "channel %d unknown driver event type %d"
1924 " (data " EFX_QWORD_FMT ")\n",
1925 channel->channel, subcode,
1926 EFX_QWORD_VAL(*event));
1927
1928 }
1929}
1930
1931static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
1932 efx_qword_t *event)
1933{
1934 struct efx_nic *efx = channel->efx;
1935 u32 subcode;
1936
1937 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
1938
1939 switch (subcode) {
1940 case EFX_EF10_TEST:
1941 channel->event_test_cpu = raw_smp_processor_id();
1942 break;
1943 case EFX_EF10_REFILL:
1944 /* The queue must be empty, so we won't receive any rx
1945 * events, so efx_process_channel() won't refill the
1946 * queue. Refill it here
1947 */
1948 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
1949 break;
1950 default:
1951 netif_err(efx, hw, efx->net_dev,
1952 "channel %d unknown driver event type %u"
1953 " (data " EFX_QWORD_FMT ")\n",
1954 channel->channel, (unsigned) subcode,
1955 EFX_QWORD_VAL(*event));
1956 }
1957}
1958
1959static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
1960{
1961 struct efx_nic *efx = channel->efx;
1962 efx_qword_t event, *p_event;
1963 unsigned int read_ptr;
1964 int ev_code;
1965 int tx_descs = 0;
1966 int spent = 0;
1967
1968 if (quota <= 0)
1969 return spent;
1970
1971 read_ptr = channel->eventq_read_ptr;
1972
1973 for (;;) {
1974 p_event = efx_event(channel, read_ptr);
1975 event = *p_event;
1976
1977 if (!efx_event_present(&event))
1978 break;
1979
1980 EFX_SET_QWORD(*p_event);
1981
1982 ++read_ptr;
1983
1984 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
1985
1986 netif_vdbg(efx, drv, efx->net_dev,
1987 "processing event on %d " EFX_QWORD_FMT "\n",
1988 channel->channel, EFX_QWORD_VAL(event));
1989
1990 switch (ev_code) {
1991 case ESE_DZ_EV_CODE_MCDI_EV:
1992 efx_mcdi_process_event(channel, &event);
1993 break;
1994 case ESE_DZ_EV_CODE_RX_EV:
1995 spent += efx_ef10_handle_rx_event(channel, &event);
1996 if (spent >= quota) {
1997 /* XXX can we split a merged event to
1998 * avoid going over-quota?
1999 */
2000 spent = quota;
2001 goto out;
2002 }
2003 break;
2004 case ESE_DZ_EV_CODE_TX_EV:
2005 tx_descs += efx_ef10_handle_tx_event(channel, &event);
2006 if (tx_descs > efx->txq_entries) {
2007 spent = quota;
2008 goto out;
2009 } else if (++spent == quota) {
2010 goto out;
2011 }
2012 break;
2013 case ESE_DZ_EV_CODE_DRIVER_EV:
2014 efx_ef10_handle_driver_event(channel, &event);
2015 if (++spent == quota)
2016 goto out;
2017 break;
2018 case EFX_EF10_DRVGEN_EV:
2019 efx_ef10_handle_driver_generated_event(channel, &event);
2020 break;
2021 default:
2022 netif_err(efx, hw, efx->net_dev,
2023 "channel %d unknown event type %d"
2024 " (data " EFX_QWORD_FMT ")\n",
2025 channel->channel, ev_code,
2026 EFX_QWORD_VAL(event));
2027 }
2028 }
2029
2030out:
2031 channel->eventq_read_ptr = read_ptr;
2032 return spent;
2033}
2034
2035static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2036{
2037 struct efx_nic *efx = channel->efx;
2038 efx_dword_t rptr;
2039
2040 if (EFX_EF10_WORKAROUND_35388(efx)) {
2041 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2042 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2043 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2044 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2045
2046 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2047 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2048 ERF_DD_EVQ_IND_RPTR,
2049 (channel->eventq_read_ptr &
2050 channel->eventq_mask) >>
2051 ERF_DD_EVQ_IND_RPTR_WIDTH);
2052 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2053 channel->channel);
2054 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2055 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2056 ERF_DD_EVQ_IND_RPTR,
2057 channel->eventq_read_ptr &
2058 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2059 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2060 channel->channel);
2061 } else {
2062 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2063 channel->eventq_read_ptr &
2064 channel->eventq_mask);
2065 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2066 }
2067}
2068
2069static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2070{
2071 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2072 struct efx_nic *efx = channel->efx;
2073 efx_qword_t event;
2074 int rc;
2075
2076 EFX_POPULATE_QWORD_2(event,
2077 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2078 ESF_DZ_EV_DATA, EFX_EF10_TEST);
2079
2080 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2081
2082 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2083 * already swapped the data to little-endian order.
2084 */
2085 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2086 sizeof(efx_qword_t));
2087
2088 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2089 NULL, 0, NULL);
2090 if (rc != 0)
2091 goto fail;
2092
2093 return;
2094
2095fail:
2096 WARN_ON(true);
2097 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2098}
2099
2100void efx_ef10_handle_drain_event(struct efx_nic *efx)
2101{
2102 if (atomic_dec_and_test(&efx->active_queues))
2103 wake_up(&efx->flush_wq);
2104
2105 WARN_ON(atomic_read(&efx->active_queues) < 0);
2106}
2107
2108static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2109{
2110 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2111 struct efx_channel *channel;
2112 struct efx_tx_queue *tx_queue;
2113 struct efx_rx_queue *rx_queue;
2114 int pending;
2115
2116 /* If the MC has just rebooted, the TX/RX queues will have already been
2117 * torn down, but efx->active_queues needs to be set to zero.
2118 */
2119 if (nic_data->must_realloc_vis) {
2120 atomic_set(&efx->active_queues, 0);
2121 return 0;
2122 }
2123
2124 /* Do not attempt to write to the NIC during EEH recovery */
2125 if (efx->state != STATE_RECOVERY) {
2126 efx_for_each_channel(channel, efx) {
2127 efx_for_each_channel_rx_queue(rx_queue, channel)
2128 efx_ef10_rx_fini(rx_queue);
2129 efx_for_each_channel_tx_queue(tx_queue, channel)
2130 efx_ef10_tx_fini(tx_queue);
2131 }
2132
2133 wait_event_timeout(efx->flush_wq,
2134 atomic_read(&efx->active_queues) == 0,
2135 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2136 pending = atomic_read(&efx->active_queues);
2137 if (pending) {
2138 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2139 pending);
2140 return -ETIMEDOUT;
2141 }
2142 }
2143
2144 return 0;
2145}
2146
2147static void efx_ef10_prepare_flr(struct efx_nic *efx)
2148{
2149 atomic_set(&efx->active_queues, 0);
2150}
2151
2152static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2153 const struct efx_filter_spec *right)
2154{
2155 if ((left->match_flags ^ right->match_flags) |
2156 ((left->flags ^ right->flags) &
2157 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2158 return false;
2159
2160 return memcmp(&left->outer_vid, &right->outer_vid,
2161 sizeof(struct efx_filter_spec) -
2162 offsetof(struct efx_filter_spec, outer_vid)) == 0;
2163}
2164
2165static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2166{
2167 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2168 return jhash2((const u32 *)&spec->outer_vid,
2169 (sizeof(struct efx_filter_spec) -
2170 offsetof(struct efx_filter_spec, outer_vid)) / 4,
2171 0);
2172 /* XXX should we randomise the initval? */
2173}
2174
2175/* Decide whether a filter should be exclusive or else should allow
2176 * delivery to additional recipients. Currently we decide that
2177 * filters for specific local unicast MAC and IP addresses are
2178 * exclusive.
2179 */
2180static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2181{
2182 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2183 !is_multicast_ether_addr(spec->loc_mac))
2184 return true;
2185
2186 if ((spec->match_flags &
2187 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2188 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2189 if (spec->ether_type == htons(ETH_P_IP) &&
2190 !ipv4_is_multicast(spec->loc_host[0]))
2191 return true;
2192 if (spec->ether_type == htons(ETH_P_IPV6) &&
2193 ((const u8 *)spec->loc_host)[0] != 0xff)
2194 return true;
2195 }
2196
2197 return false;
2198}
2199
2200static struct efx_filter_spec *
2201efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2202 unsigned int filter_idx)
2203{
2204 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2205 ~EFX_EF10_FILTER_FLAGS);
2206}
2207
2208static unsigned int
2209efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2210 unsigned int filter_idx)
2211{
2212 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2213}
2214
2215static void
2216efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2217 unsigned int filter_idx,
2218 const struct efx_filter_spec *spec,
2219 unsigned int flags)
2220{
2221 table->entry[filter_idx].spec = (unsigned long)spec | flags;
2222}
2223
2224static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2225 const struct efx_filter_spec *spec,
2226 efx_dword_t *inbuf, u64 handle,
2227 bool replacing)
2228{
2229 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2230
2231 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2232
2233 if (replacing) {
2234 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2235 MC_CMD_FILTER_OP_IN_OP_REPLACE);
2236 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2237 } else {
2238 u32 match_fields = 0;
2239
2240 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2241 efx_ef10_filter_is_exclusive(spec) ?
2242 MC_CMD_FILTER_OP_IN_OP_INSERT :
2243 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2244
2245 /* Convert match flags and values. Unlike almost
2246 * everything else in MCDI, these fields are in
2247 * network byte order.
2248 */
2249 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2250 match_fields |=
2251 is_multicast_ether_addr(spec->loc_mac) ?
2252 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2253 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2254#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
2255 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
2256 match_fields |= \
2257 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2258 mcdi_field ## _LBN; \
2259 BUILD_BUG_ON( \
2260 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2261 sizeof(spec->gen_field)); \
2262 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2263 &spec->gen_field, sizeof(spec->gen_field)); \
2264 }
2265 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2266 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2267 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2268 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2269 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2270 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2271 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2272 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2273 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2274 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2275#undef COPY_FIELD
2276 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2277 match_fields);
2278 }
2279
2280 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
2281 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2282 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2283 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2284 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
2285 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2286 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
2287 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2288 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2289 0 : spec->dmaq_id);
2290 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2291 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2292 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2293 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2294 if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2295 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2296 spec->rss_context !=
2297 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2298 spec->rss_context : nic_data->rx_rss_context);
2299}
2300
2301static int efx_ef10_filter_push(struct efx_nic *efx,
2302 const struct efx_filter_spec *spec,
2303 u64 *handle, bool replacing)
2304{
2305 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2306 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2307 int rc;
2308
2309 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
2310 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2311 outbuf, sizeof(outbuf), NULL);
2312 if (rc == 0)
2313 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2314 if (rc == -ENOSPC)
2315 rc = -EBUSY; /* to match efx_farch_filter_insert() */
2316 return rc;
2317}
2318
2319static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
2320 enum efx_filter_match_flags match_flags)
2321{
2322 unsigned int match_pri;
2323
2324 for (match_pri = 0;
2325 match_pri < table->rx_match_count;
2326 match_pri++)
2327 if (table->rx_match_flags[match_pri] == match_flags)
2328 return match_pri;
2329
2330 return -EPROTONOSUPPORT;
2331}
2332
2333static s32 efx_ef10_filter_insert(struct efx_nic *efx,
2334 struct efx_filter_spec *spec,
2335 bool replace_equal)
2336{
2337 struct efx_ef10_filter_table *table = efx->filter_state;
2338 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2339 struct efx_filter_spec *saved_spec;
2340 unsigned int match_pri, hash;
2341 unsigned int priv_flags;
2342 bool replacing = false;
2343 int ins_index = -1;
2344 DEFINE_WAIT(wait);
2345 bool is_mc_recip;
2346 s32 rc;
2347
2348 /* For now, only support RX filters */
2349 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
2350 EFX_FILTER_FLAG_RX)
2351 return -EINVAL;
2352
2353 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
2354 if (rc < 0)
2355 return rc;
2356 match_pri = rc;
2357
2358 hash = efx_ef10_filter_hash(spec);
2359 is_mc_recip = efx_filter_is_mc_recipient(spec);
2360 if (is_mc_recip)
2361 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2362
2363 /* Find any existing filters with the same match tuple or
2364 * else a free slot to insert at. If any of them are busy,
2365 * we have to wait and retry.
2366 */
2367 for (;;) {
2368 unsigned int depth = 1;
2369 unsigned int i;
2370
2371 spin_lock_bh(&efx->filter_lock);
2372
2373 for (;;) {
2374 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2375 saved_spec = efx_ef10_filter_entry_spec(table, i);
2376
2377 if (!saved_spec) {
2378 if (ins_index < 0)
2379 ins_index = i;
2380 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2381 if (table->entry[i].spec &
2382 EFX_EF10_FILTER_FLAG_BUSY)
2383 break;
2384 if (spec->priority < saved_spec->priority &&
2385 spec->priority != EFX_FILTER_PRI_AUTO) {
2386 rc = -EPERM;
2387 goto out_unlock;
2388 }
2389 if (!is_mc_recip) {
2390 /* This is the only one */
2391 if (spec->priority ==
2392 saved_spec->priority &&
2393 !replace_equal) {
2394 rc = -EEXIST;
2395 goto out_unlock;
2396 }
2397 ins_index = i;
2398 goto found;
2399 } else if (spec->priority >
2400 saved_spec->priority ||
2401 (spec->priority ==
2402 saved_spec->priority &&
2403 replace_equal)) {
2404 if (ins_index < 0)
2405 ins_index = i;
2406 else
2407 __set_bit(depth, mc_rem_map);
2408 }
2409 }
2410
2411 /* Once we reach the maximum search depth, use
2412 * the first suitable slot or return -EBUSY if
2413 * there was none
2414 */
2415 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2416 if (ins_index < 0) {
2417 rc = -EBUSY;
2418 goto out_unlock;
2419 }
2420 goto found;
2421 }
2422
2423 ++depth;
2424 }
2425
2426 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2427 spin_unlock_bh(&efx->filter_lock);
2428 schedule();
2429 }
2430
2431found:
2432 /* Create a software table entry if necessary, and mark it
2433 * busy. We might yet fail to insert, but any attempt to
2434 * insert a conflicting filter while we're waiting for the
2435 * firmware must find the busy entry.
2436 */
2437 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2438 if (saved_spec) {
2439 if (spec->priority == EFX_FILTER_PRI_AUTO &&
2440 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
2441 /* Just make sure it won't be removed */
2442 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
2443 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
2444 table->entry[ins_index].spec &=
2445 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
2446 rc = ins_index;
2447 goto out_unlock;
2448 }
2449 replacing = true;
2450 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
2451 } else {
2452 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2453 if (!saved_spec) {
2454 rc = -ENOMEM;
2455 goto out_unlock;
2456 }
2457 *saved_spec = *spec;
2458 priv_flags = 0;
2459 }
2460 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2461 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
2462
2463 /* Mark lower-priority multicast recipients busy prior to removal */
2464 if (is_mc_recip) {
2465 unsigned int depth, i;
2466
2467 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2468 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2469 if (test_bit(depth, mc_rem_map))
2470 table->entry[i].spec |=
2471 EFX_EF10_FILTER_FLAG_BUSY;
2472 }
2473 }
2474
2475 spin_unlock_bh(&efx->filter_lock);
2476
2477 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
2478 replacing);
2479
2480 /* Finalise the software table entry */
2481 spin_lock_bh(&efx->filter_lock);
2482 if (rc == 0) {
2483 if (replacing) {
2484 /* Update the fields that may differ */
2485 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
2486 saved_spec->flags |=
2487 EFX_FILTER_FLAG_RX_OVER_AUTO;
2488 saved_spec->priority = spec->priority;
2489 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
2490 saved_spec->flags |= spec->flags;
2491 saved_spec->rss_context = spec->rss_context;
2492 saved_spec->dmaq_id = spec->dmaq_id;
2493 }
2494 } else if (!replacing) {
2495 kfree(saved_spec);
2496 saved_spec = NULL;
2497 }
2498 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
2499
2500 /* Remove and finalise entries for lower-priority multicast
2501 * recipients
2502 */
2503 if (is_mc_recip) {
2504 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2505 unsigned int depth, i;
2506
2507 memset(inbuf, 0, sizeof(inbuf));
2508
2509 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2510 if (!test_bit(depth, mc_rem_map))
2511 continue;
2512
2513 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2514 saved_spec = efx_ef10_filter_entry_spec(table, i);
2515 priv_flags = efx_ef10_filter_entry_flags(table, i);
2516
2517 if (rc == 0) {
2518 spin_unlock_bh(&efx->filter_lock);
2519 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2520 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2521 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2522 table->entry[i].handle);
2523 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2524 inbuf, sizeof(inbuf),
2525 NULL, 0, NULL);
2526 spin_lock_bh(&efx->filter_lock);
2527 }
2528
2529 if (rc == 0) {
2530 kfree(saved_spec);
2531 saved_spec = NULL;
2532 priv_flags = 0;
2533 } else {
2534 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
2535 }
2536 efx_ef10_filter_set_entry(table, i, saved_spec,
2537 priv_flags);
2538 }
2539 }
2540
2541 /* If successful, return the inserted filter ID */
2542 if (rc == 0)
2543 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
2544
2545 wake_up_all(&table->waitq);
2546out_unlock:
2547 spin_unlock_bh(&efx->filter_lock);
2548 finish_wait(&table->waitq, &wait);
2549 return rc;
2550}
2551
2552static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
2553{
2554 /* no need to do anything here on EF10 */
2555}
2556
2557/* Remove a filter.
2558 * If !by_index, remove by ID
2559 * If by_index, remove by index
2560 * Filter ID may come from userland and must be range-checked.
2561 */
2562static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
2563 unsigned int priority_mask,
2564 u32 filter_id, bool by_index)
2565{
2566 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2567 struct efx_ef10_filter_table *table = efx->filter_state;
2568 MCDI_DECLARE_BUF(inbuf,
2569 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2570 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2571 struct efx_filter_spec *spec;
2572 DEFINE_WAIT(wait);
2573 int rc;
2574
2575 /* Find the software table entry and mark it busy. Don't
2576 * remove it yet; any attempt to update while we're waiting
2577 * for the firmware must find the busy entry.
2578 */
2579 for (;;) {
2580 spin_lock_bh(&efx->filter_lock);
2581 if (!(table->entry[filter_idx].spec &
2582 EFX_EF10_FILTER_FLAG_BUSY))
2583 break;
2584 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2585 spin_unlock_bh(&efx->filter_lock);
2586 schedule();
2587 }
2588
2589 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2590 if (!spec ||
2591 (!by_index &&
2592 efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
2593 filter_id / HUNT_FILTER_TBL_ROWS)) {
2594 rc = -ENOENT;
2595 goto out_unlock;
2596 }
2597
2598 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
2599 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
2600 /* Just remove flags */
2601 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
2602 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
2603 rc = 0;
2604 goto out_unlock;
2605 }
2606
2607 if (!(priority_mask & (1U << spec->priority))) {
2608 rc = -ENOENT;
2609 goto out_unlock;
2610 }
2611
2612 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2613 spin_unlock_bh(&efx->filter_lock);
2614
2615 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
2616 /* Reset to an automatic filter */
2617
2618 struct efx_filter_spec new_spec = *spec;
2619
2620 new_spec.priority = EFX_FILTER_PRI_AUTO;
2621 new_spec.flags = (EFX_FILTER_FLAG_RX |
2622 EFX_FILTER_FLAG_RX_RSS);
2623 new_spec.dmaq_id = 0;
2624 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
2625 rc = efx_ef10_filter_push(efx, &new_spec,
2626 &table->entry[filter_idx].handle,
2627 true);
2628
2629 spin_lock_bh(&efx->filter_lock);
2630 if (rc == 0)
2631 *spec = new_spec;
2632 } else {
2633 /* Really remove the filter */
2634
2635 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2636 efx_ef10_filter_is_exclusive(spec) ?
2637 MC_CMD_FILTER_OP_IN_OP_REMOVE :
2638 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2639 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2640 table->entry[filter_idx].handle);
2641 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2642 inbuf, sizeof(inbuf), NULL, 0, NULL);
2643
2644 spin_lock_bh(&efx->filter_lock);
2645 if (rc == 0) {
2646 kfree(spec);
2647 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2648 }
2649 }
2650
2651 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2652 wake_up_all(&table->waitq);
2653out_unlock:
2654 spin_unlock_bh(&efx->filter_lock);
2655 finish_wait(&table->waitq, &wait);
2656 return rc;
2657}
2658
2659static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
2660 enum efx_filter_priority priority,
2661 u32 filter_id)
2662{
2663 return efx_ef10_filter_remove_internal(efx, 1U << priority,
2664 filter_id, false);
2665}
2666
2667static int efx_ef10_filter_get_safe(struct efx_nic *efx,
2668 enum efx_filter_priority priority,
2669 u32 filter_id, struct efx_filter_spec *spec)
2670{
2671 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2672 struct efx_ef10_filter_table *table = efx->filter_state;
2673 const struct efx_filter_spec *saved_spec;
2674 int rc;
2675
2676 spin_lock_bh(&efx->filter_lock);
2677 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
2678 if (saved_spec && saved_spec->priority == priority &&
2679 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
2680 filter_id / HUNT_FILTER_TBL_ROWS) {
2681 *spec = *saved_spec;
2682 rc = 0;
2683 } else {
2684 rc = -ENOENT;
2685 }
2686 spin_unlock_bh(&efx->filter_lock);
2687 return rc;
2688}
2689
2690static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
2691 enum efx_filter_priority priority)
2692{
2693 unsigned int priority_mask;
2694 unsigned int i;
2695 int rc;
2696
2697 priority_mask = (((1U << (priority + 1)) - 1) &
2698 ~(1U << EFX_FILTER_PRI_AUTO));
2699
2700 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
2701 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
2702 i, true);
2703 if (rc && rc != -ENOENT)
2704 return rc;
2705 }
2706
2707 return 0;
2708}
2709
2710static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
2711 enum efx_filter_priority priority)
2712{
2713 struct efx_ef10_filter_table *table = efx->filter_state;
2714 unsigned int filter_idx;
2715 s32 count = 0;
2716
2717 spin_lock_bh(&efx->filter_lock);
2718 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2719 if (table->entry[filter_idx].spec &&
2720 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
2721 priority)
2722 ++count;
2723 }
2724 spin_unlock_bh(&efx->filter_lock);
2725 return count;
2726}
2727
2728static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
2729{
2730 struct efx_ef10_filter_table *table = efx->filter_state;
2731
2732 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
2733}
2734
2735static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
2736 enum efx_filter_priority priority,
2737 u32 *buf, u32 size)
2738{
2739 struct efx_ef10_filter_table *table = efx->filter_state;
2740 struct efx_filter_spec *spec;
2741 unsigned int filter_idx;
2742 s32 count = 0;
2743
2744 spin_lock_bh(&efx->filter_lock);
2745 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2746 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2747 if (spec && spec->priority == priority) {
2748 if (count == size) {
2749 count = -EMSGSIZE;
2750 break;
2751 }
2752 buf[count++] = (efx_ef10_filter_rx_match_pri(
2753 table, spec->match_flags) *
2754 HUNT_FILTER_TBL_ROWS +
2755 filter_idx);
2756 }
2757 }
2758 spin_unlock_bh(&efx->filter_lock);
2759 return count;
2760}
2761
2762#ifdef CONFIG_RFS_ACCEL
2763
2764static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
2765
2766static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
2767 struct efx_filter_spec *spec)
2768{
2769 struct efx_ef10_filter_table *table = efx->filter_state;
2770 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2771 struct efx_filter_spec *saved_spec;
2772 unsigned int hash, i, depth = 1;
2773 bool replacing = false;
2774 int ins_index = -1;
2775 u64 cookie;
2776 s32 rc;
2777
2778 /* Must be an RX filter without RSS and not for a multicast
2779 * destination address (RFS only works for connected sockets).
2780 * These restrictions allow us to pass only a tiny amount of
2781 * data through to the completion function.
2782 */
2783 EFX_WARN_ON_PARANOID(spec->flags !=
2784 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
2785 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
2786 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
2787
2788 hash = efx_ef10_filter_hash(spec);
2789
2790 spin_lock_bh(&efx->filter_lock);
2791
2792 /* Find any existing filter with the same match tuple or else
2793 * a free slot to insert at. If an existing filter is busy,
2794 * we have to give up.
2795 */
2796 for (;;) {
2797 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2798 saved_spec = efx_ef10_filter_entry_spec(table, i);
2799
2800 if (!saved_spec) {
2801 if (ins_index < 0)
2802 ins_index = i;
2803 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2804 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
2805 rc = -EBUSY;
2806 goto fail_unlock;
2807 }
2808 if (spec->priority < saved_spec->priority) {
2809 rc = -EPERM;
2810 goto fail_unlock;
2811 }
2812 ins_index = i;
2813 break;
2814 }
2815
2816 /* Once we reach the maximum search depth, use the
2817 * first suitable slot or return -EBUSY if there was
2818 * none
2819 */
2820 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2821 if (ins_index < 0) {
2822 rc = -EBUSY;
2823 goto fail_unlock;
2824 }
2825 break;
2826 }
2827
2828 ++depth;
2829 }
2830
2831 /* Create a software table entry if necessary, and mark it
2832 * busy. We might yet fail to insert, but any attempt to
2833 * insert a conflicting filter while we're waiting for the
2834 * firmware must find the busy entry.
2835 */
2836 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2837 if (saved_spec) {
2838 replacing = true;
2839 } else {
2840 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2841 if (!saved_spec) {
2842 rc = -ENOMEM;
2843 goto fail_unlock;
2844 }
2845 *saved_spec = *spec;
2846 }
2847 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2848 EFX_EF10_FILTER_FLAG_BUSY);
2849
2850 spin_unlock_bh(&efx->filter_lock);
2851
2852 /* Pack up the variables needed on completion */
2853 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
2854
2855 efx_ef10_filter_push_prep(efx, spec, inbuf,
2856 table->entry[ins_index].handle, replacing);
2857 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2858 MC_CMD_FILTER_OP_OUT_LEN,
2859 efx_ef10_filter_rfs_insert_complete, cookie);
2860
2861 return ins_index;
2862
2863fail_unlock:
2864 spin_unlock_bh(&efx->filter_lock);
2865 return rc;
2866}
2867
2868static void
2869efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
2870 int rc, efx_dword_t *outbuf,
2871 size_t outlen_actual)
2872{
2873 struct efx_ef10_filter_table *table = efx->filter_state;
2874 unsigned int ins_index, dmaq_id;
2875 struct efx_filter_spec *spec;
2876 bool replacing;
2877
2878 /* Unpack the cookie */
2879 replacing = cookie >> 31;
2880 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
2881 dmaq_id = cookie & 0xffff;
2882
2883 spin_lock_bh(&efx->filter_lock);
2884 spec = efx_ef10_filter_entry_spec(table, ins_index);
2885 if (rc == 0) {
2886 table->entry[ins_index].handle =
2887 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2888 if (replacing)
2889 spec->dmaq_id = dmaq_id;
2890 } else if (!replacing) {
2891 kfree(spec);
2892 spec = NULL;
2893 }
2894 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
2895 spin_unlock_bh(&efx->filter_lock);
2896
2897 wake_up_all(&table->waitq);
2898}
2899
2900static void
2901efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2902 unsigned long filter_idx,
2903 int rc, efx_dword_t *outbuf,
2904 size_t outlen_actual);
2905
2906static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
2907 unsigned int filter_idx)
2908{
2909 struct efx_ef10_filter_table *table = efx->filter_state;
2910 struct efx_filter_spec *spec =
2911 efx_ef10_filter_entry_spec(table, filter_idx);
2912 MCDI_DECLARE_BUF(inbuf,
2913 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2914 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2915
2916 if (!spec ||
2917 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
2918 spec->priority != EFX_FILTER_PRI_HINT ||
2919 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
2920 flow_id, filter_idx))
2921 return false;
2922
2923 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2924 MC_CMD_FILTER_OP_IN_OP_REMOVE);
2925 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2926 table->entry[filter_idx].handle);
2927 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
2928 efx_ef10_filter_rfs_expire_complete, filter_idx))
2929 return false;
2930
2931 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2932 return true;
2933}
2934
2935static void
2936efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2937 unsigned long filter_idx,
2938 int rc, efx_dword_t *outbuf,
2939 size_t outlen_actual)
2940{
2941 struct efx_ef10_filter_table *table = efx->filter_state;
2942 struct efx_filter_spec *spec =
2943 efx_ef10_filter_entry_spec(table, filter_idx);
2944
2945 spin_lock_bh(&efx->filter_lock);
2946 if (rc == 0) {
2947 kfree(spec);
2948 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2949 }
2950 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2951 wake_up_all(&table->waitq);
2952 spin_unlock_bh(&efx->filter_lock);
2953}
2954
2955#endif /* CONFIG_RFS_ACCEL */
2956
2957static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
2958{
2959 int match_flags = 0;
2960
2961#define MAP_FLAG(gen_flag, mcdi_field) { \
2962 u32 old_mcdi_flags = mcdi_flags; \
2963 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2964 mcdi_field ## _LBN); \
2965 if (mcdi_flags != old_mcdi_flags) \
2966 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
2967 }
2968 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
2969 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
2970 MAP_FLAG(REM_HOST, SRC_IP);
2971 MAP_FLAG(LOC_HOST, DST_IP);
2972 MAP_FLAG(REM_MAC, SRC_MAC);
2973 MAP_FLAG(REM_PORT, SRC_PORT);
2974 MAP_FLAG(LOC_MAC, DST_MAC);
2975 MAP_FLAG(LOC_PORT, DST_PORT);
2976 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
2977 MAP_FLAG(INNER_VID, INNER_VLAN);
2978 MAP_FLAG(OUTER_VID, OUTER_VLAN);
2979 MAP_FLAG(IP_PROTO, IP_PROTO);
2980#undef MAP_FLAG
2981
2982 /* Did we map them all? */
2983 if (mcdi_flags)
2984 return -EINVAL;
2985
2986 return match_flags;
2987}
2988
2989static int efx_ef10_filter_table_probe(struct efx_nic *efx)
2990{
2991 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
2992 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
2993 unsigned int pd_match_pri, pd_match_count;
2994 struct efx_ef10_filter_table *table;
2995 size_t outlen;
2996 int rc;
2997
2998 table = kzalloc(sizeof(*table), GFP_KERNEL);
2999 if (!table)
3000 return -ENOMEM;
3001
3002 /* Find out which RX filter types are supported, and their priorities */
3003 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3004 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3005 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3006 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3007 &outlen);
3008 if (rc)
3009 goto fail;
3010 pd_match_count = MCDI_VAR_ARRAY_LEN(
3011 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3012 table->rx_match_count = 0;
3013
3014 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3015 u32 mcdi_flags =
3016 MCDI_ARRAY_DWORD(
3017 outbuf,
3018 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3019 pd_match_pri);
3020 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3021 if (rc < 0) {
3022 netif_dbg(efx, probe, efx->net_dev,
3023 "%s: fw flags %#x pri %u not supported in driver\n",
3024 __func__, mcdi_flags, pd_match_pri);
3025 } else {
3026 netif_dbg(efx, probe, efx->net_dev,
3027 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3028 __func__, mcdi_flags, pd_match_pri,
3029 rc, table->rx_match_count);
3030 table->rx_match_flags[table->rx_match_count++] = rc;
3031 }
3032 }
3033
3034 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3035 if (!table->entry) {
3036 rc = -ENOMEM;
3037 goto fail;
3038 }
3039
3040 efx->filter_state = table;
3041 init_waitqueue_head(&table->waitq);
3042 return 0;
3043
3044fail:
3045 kfree(table);
3046 return rc;
3047}
3048
3049static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3050{
3051 struct efx_ef10_filter_table *table = efx->filter_state;
3052 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3053 struct efx_filter_spec *spec;
3054 unsigned int filter_idx;
3055 bool failed = false;
3056 int rc;
3057
3058 if (!nic_data->must_restore_filters)
3059 return;
3060
3061 spin_lock_bh(&efx->filter_lock);
3062
3063 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3064 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3065 if (!spec)
3066 continue;
3067
3068 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3069 spin_unlock_bh(&efx->filter_lock);
3070
3071 rc = efx_ef10_filter_push(efx, spec,
3072 &table->entry[filter_idx].handle,
3073 false);
3074 if (rc)
3075 failed = true;
3076
3077 spin_lock_bh(&efx->filter_lock);
3078 if (rc) {
3079 kfree(spec);
3080 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3081 } else {
3082 table->entry[filter_idx].spec &=
3083 ~EFX_EF10_FILTER_FLAG_BUSY;
3084 }
3085 }
3086
3087 spin_unlock_bh(&efx->filter_lock);
3088
3089 if (failed)
3090 netif_err(efx, hw, efx->net_dev,
3091 "unable to restore all filters\n");
3092 else
3093 nic_data->must_restore_filters = false;
3094}
3095
3096static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3097{
3098 struct efx_ef10_filter_table *table = efx->filter_state;
3099 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3100 struct efx_filter_spec *spec;
3101 unsigned int filter_idx;
3102 int rc;
3103
3104 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3105 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3106 if (!spec)
3107 continue;
3108
3109 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3110 efx_ef10_filter_is_exclusive(spec) ?
3111 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3112 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3113 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3114 table->entry[filter_idx].handle);
3115 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3116 NULL, 0, NULL);
3117 if (rc)
3118 netdev_WARN(efx->net_dev,
3119 "filter_idx=%#x handle=%#llx\n",
3120 filter_idx,
3121 table->entry[filter_idx].handle);
3122 kfree(spec);
3123 }
3124
3125 vfree(table->entry);
3126 kfree(table);
3127}
3128
3129static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
3130{
3131 struct efx_ef10_filter_table *table = efx->filter_state;
3132 struct net_device *net_dev = efx->net_dev;
3133 struct efx_filter_spec spec;
3134 bool remove_failed = false;
3135 struct netdev_hw_addr *uc;
3136 struct netdev_hw_addr *mc;
3137 unsigned int filter_idx;
3138 int i, n, rc;
3139
3140 if (!efx_dev_registered(efx))
3141 return;
3142
3143 /* Mark old filters that may need to be removed */
3144 spin_lock_bh(&efx->filter_lock);
3145 n = table->dev_uc_count < 0 ? 1 : table->dev_uc_count;
3146 for (i = 0; i < n; i++) {
3147 filter_idx = table->dev_uc_list[i].id % HUNT_FILTER_TBL_ROWS;
3148 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
3149 }
3150 n = table->dev_mc_count < 0 ? 1 : table->dev_mc_count;
3151 for (i = 0; i < n; i++) {
3152 filter_idx = table->dev_mc_list[i].id % HUNT_FILTER_TBL_ROWS;
3153 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
3154 }
3155 spin_unlock_bh(&efx->filter_lock);
3156
3157 /* Copy/convert the address lists; add the primary station
3158 * address and broadcast address
3159 */
3160 netif_addr_lock_bh(net_dev);
3161 if (net_dev->flags & IFF_PROMISC ||
3162 netdev_uc_count(net_dev) >= EFX_EF10_FILTER_DEV_UC_MAX) {
3163 table->dev_uc_count = -1;
3164 } else {
3165 table->dev_uc_count = 1 + netdev_uc_count(net_dev);
3166 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
3167 i = 1;
3168 netdev_for_each_uc_addr(uc, net_dev) {
3169 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
3170 i++;
3171 }
3172 }
3173 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) ||
3174 netdev_mc_count(net_dev) >= EFX_EF10_FILTER_DEV_MC_MAX) {
3175 table->dev_mc_count = -1;
3176 } else {
3177 table->dev_mc_count = 1 + netdev_mc_count(net_dev);
3178 eth_broadcast_addr(table->dev_mc_list[0].addr);
3179 i = 1;
3180 netdev_for_each_mc_addr(mc, net_dev) {
3181 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
3182 i++;
3183 }
3184 }
3185 netif_addr_unlock_bh(net_dev);
3186
3187 /* Insert/renew unicast filters */
3188 if (table->dev_uc_count >= 0) {
3189 for (i = 0; i < table->dev_uc_count; i++) {
3190 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3191 EFX_FILTER_FLAG_RX_RSS,
3192 0);
3193 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3194 table->dev_uc_list[i].addr);
3195 rc = efx_ef10_filter_insert(efx, &spec, true);
3196 if (rc < 0) {
3197 /* Fall back to unicast-promisc */
3198 while (i--)
3199 efx_ef10_filter_remove_safe(
3200 efx, EFX_FILTER_PRI_AUTO,
3201 table->dev_uc_list[i].id);
3202 table->dev_uc_count = -1;
3203 break;
3204 }
3205 table->dev_uc_list[i].id = rc;
3206 }
3207 }
3208 if (table->dev_uc_count < 0) {
3209 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3210 EFX_FILTER_FLAG_RX_RSS,
3211 0);
3212 efx_filter_set_uc_def(&spec);
3213 rc = efx_ef10_filter_insert(efx, &spec, true);
3214 if (rc < 0) {
3215 WARN_ON(1);
3216 table->dev_uc_count = 0;
3217 } else {
3218 table->dev_uc_list[0].id = rc;
3219 }
3220 }
3221
3222 /* Insert/renew multicast filters */
3223 if (table->dev_mc_count >= 0) {
3224 for (i = 0; i < table->dev_mc_count; i++) {
3225 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3226 EFX_FILTER_FLAG_RX_RSS,
3227 0);
3228 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3229 table->dev_mc_list[i].addr);
3230 rc = efx_ef10_filter_insert(efx, &spec, true);
3231 if (rc < 0) {
3232 /* Fall back to multicast-promisc */
3233 while (i--)
3234 efx_ef10_filter_remove_safe(
3235 efx, EFX_FILTER_PRI_AUTO,
3236 table->dev_mc_list[i].id);
3237 table->dev_mc_count = -1;
3238 break;
3239 }
3240 table->dev_mc_list[i].id = rc;
3241 }
3242 }
3243 if (table->dev_mc_count < 0) {
3244 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3245 EFX_FILTER_FLAG_RX_RSS,
3246 0);
3247 efx_filter_set_mc_def(&spec);
3248 rc = efx_ef10_filter_insert(efx, &spec, true);
3249 if (rc < 0) {
3250 WARN_ON(1);
3251 table->dev_mc_count = 0;
3252 } else {
3253 table->dev_mc_list[0].id = rc;
3254 }
3255 }
3256
3257 /* Remove filters that weren't renewed. Since nothing else
3258 * changes the AUTO_OLD flag or removes these filters, we
3259 * don't need to hold the filter_lock while scanning for
3260 * these filters.
3261 */
3262 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3263 if (ACCESS_ONCE(table->entry[i].spec) &
3264 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
3265 if (efx_ef10_filter_remove_internal(
3266 efx, 1U << EFX_FILTER_PRI_AUTO,
3267 i, true) < 0)
3268 remove_failed = true;
3269 }
3270 }
3271 WARN_ON(remove_failed);
3272}
3273
3274static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
3275{
3276 efx_ef10_filter_sync_rx_mode(efx);
3277
3278 return efx_mcdi_set_mac(efx);
3279}
3280
3281static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
3282{
3283 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
3284
3285 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
3286 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
3287 NULL, 0, NULL);
3288}
3289
3290/* MC BISTs follow a different poll mechanism to phy BISTs.
3291 * The BIST is done in the poll handler on the MC, and the MCDI command
3292 * will block until the BIST is done.
3293 */
3294static int efx_ef10_poll_bist(struct efx_nic *efx)
3295{
3296 int rc;
3297 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
3298 size_t outlen;
3299 u32 result;
3300
3301 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
3302 outbuf, sizeof(outbuf), &outlen);
3303 if (rc != 0)
3304 return rc;
3305
3306 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
3307 return -EIO;
3308
3309 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
3310 switch (result) {
3311 case MC_CMD_POLL_BIST_PASSED:
3312 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
3313 return 0;
3314 case MC_CMD_POLL_BIST_TIMEOUT:
3315 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
3316 return -EIO;
3317 case MC_CMD_POLL_BIST_FAILED:
3318 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
3319 return -EIO;
3320 default:
3321 netif_err(efx, hw, efx->net_dev,
3322 "BIST returned unknown result %u", result);
3323 return -EIO;
3324 }
3325}
3326
3327static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
3328{
3329 int rc;
3330
3331 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
3332
3333 rc = efx_ef10_start_bist(efx, bist_type);
3334 if (rc != 0)
3335 return rc;
3336
3337 return efx_ef10_poll_bist(efx);
3338}
3339
3340static int
3341efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
3342{
3343 int rc, rc2;
3344
3345 efx_reset_down(efx, RESET_TYPE_WORLD);
3346
3347 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
3348 NULL, 0, NULL, 0, NULL);
3349 if (rc != 0)
3350 goto out;
3351
3352 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
3353 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
3354
3355 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
3356
3357out:
3358 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
3359 return rc ? rc : rc2;
3360}
3361
3362#ifdef CONFIG_SFC_MTD
3363
3364struct efx_ef10_nvram_type_info {
3365 u16 type, type_mask;
3366 u8 port;
3367 const char *name;
3368};
3369
3370static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
3371 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
3372 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
3373 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
3374 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
3375 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
3376 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
3377 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
3378 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
3379 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
3380 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
3381 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
3382};
3383
3384static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
3385 struct efx_mcdi_mtd_partition *part,
3386 unsigned int type)
3387{
3388 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
3389 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
3390 const struct efx_ef10_nvram_type_info *info;
3391 size_t size, erase_size, outlen;
3392 bool protected;
3393 int rc;
3394
3395 for (info = efx_ef10_nvram_types; ; info++) {
3396 if (info ==
3397 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
3398 return -ENODEV;
3399 if ((type & ~info->type_mask) == info->type)
3400 break;
3401 }
3402 if (info->port != efx_port_num(efx))
3403 return -ENODEV;
3404
3405 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
3406 if (rc)
3407 return rc;
3408 if (protected)
3409 return -ENODEV; /* hide it */
3410
3411 part->nvram_type = type;
3412
3413 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
3414 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
3415 outbuf, sizeof(outbuf), &outlen);
3416 if (rc)
3417 return rc;
3418 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
3419 return -EIO;
3420 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
3421 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
3422 part->fw_subtype = MCDI_DWORD(outbuf,
3423 NVRAM_METADATA_OUT_SUBTYPE);
3424
3425 part->common.dev_type_name = "EF10 NVRAM manager";
3426 part->common.type_name = info->name;
3427
3428 part->common.mtd.type = MTD_NORFLASH;
3429 part->common.mtd.flags = MTD_CAP_NORFLASH;
3430 part->common.mtd.size = size;
3431 part->common.mtd.erasesize = erase_size;
3432
3433 return 0;
3434}
3435
3436static int efx_ef10_mtd_probe(struct efx_nic *efx)
3437{
3438 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
3439 struct efx_mcdi_mtd_partition *parts;
3440 size_t outlen, n_parts_total, i, n_parts;
3441 unsigned int type;
3442 int rc;
3443
3444 ASSERT_RTNL();
3445
3446 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
3447 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
3448 outbuf, sizeof(outbuf), &outlen);
3449 if (rc)
3450 return rc;
3451 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
3452 return -EIO;
3453
3454 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
3455 if (n_parts_total >
3456 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
3457 return -EIO;
3458
3459 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
3460 if (!parts)
3461 return -ENOMEM;
3462
3463 n_parts = 0;
3464 for (i = 0; i < n_parts_total; i++) {
3465 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
3466 i);
3467 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
3468 if (rc == 0)
3469 n_parts++;
3470 else if (rc != -ENODEV)
3471 goto fail;
3472 }
3473
3474 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
3475fail:
3476 if (rc)
3477 kfree(parts);
3478 return rc;
3479}
3480
3481#endif /* CONFIG_SFC_MTD */
3482
3483static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
3484{
3485 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
3486}
3487
3488static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
3489 bool temp)
3490{
3491 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
3492 int rc;
3493
3494 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
3495 channel->sync_events_state == SYNC_EVENTS_VALID ||
3496 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
3497 return 0;
3498 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
3499
3500 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
3501 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3502 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
3503 channel->channel);
3504
3505 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3506 inbuf, sizeof(inbuf), NULL, 0, NULL);
3507
3508 if (rc != 0)
3509 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3510 SYNC_EVENTS_DISABLED;
3511
3512 return rc;
3513}
3514
3515static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
3516 bool temp)
3517{
3518 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
3519 int rc;
3520
3521 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
3522 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
3523 return 0;
3524 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
3525 channel->sync_events_state = SYNC_EVENTS_DISABLED;
3526 return 0;
3527 }
3528 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3529 SYNC_EVENTS_DISABLED;
3530
3531 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
3532 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3533 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
3534 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
3535 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
3536 channel->channel);
3537
3538 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3539 inbuf, sizeof(inbuf), NULL, 0, NULL);
3540
3541 return rc;
3542}
3543
3544static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
3545 bool temp)
3546{
3547 int (*set)(struct efx_channel *channel, bool temp);
3548 struct efx_channel *channel;
3549
3550 set = en ?
3551 efx_ef10_rx_enable_timestamping :
3552 efx_ef10_rx_disable_timestamping;
3553
3554 efx_for_each_channel(channel, efx) {
3555 int rc = set(channel, temp);
3556 if (en && rc != 0) {
3557 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
3558 return rc;
3559 }
3560 }
3561
3562 return 0;
3563}
3564
3565static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
3566 struct hwtstamp_config *init)
3567{
3568 int rc;
3569
3570 switch (init->rx_filter) {
3571 case HWTSTAMP_FILTER_NONE:
3572 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
3573 /* if TX timestamping is still requested then leave PTP on */
3574 return efx_ptp_change_mode(efx,
3575 init->tx_type != HWTSTAMP_TX_OFF, 0);
3576 case HWTSTAMP_FILTER_ALL:
3577 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3578 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3579 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3580 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3581 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3582 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3583 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3584 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3585 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3586 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3587 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3588 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3589 init->rx_filter = HWTSTAMP_FILTER_ALL;
3590 rc = efx_ptp_change_mode(efx, true, 0);
3591 if (!rc)
3592 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
3593 if (rc)
3594 efx_ptp_change_mode(efx, false, 0);
3595 return rc;
3596 default:
3597 return -ERANGE;
3598 }
3599}
3600
3601const struct efx_nic_type efx_hunt_a0_nic_type = {
3602 .mem_map_size = efx_ef10_mem_map_size,
3603 .probe = efx_ef10_probe,
3604 .remove = efx_ef10_remove,
3605 .dimension_resources = efx_ef10_dimension_resources,
3606 .init = efx_ef10_init_nic,
3607 .fini = efx_port_dummy_op_void,
3608 .map_reset_reason = efx_mcdi_map_reset_reason,
3609 .map_reset_flags = efx_ef10_map_reset_flags,
3610 .reset = efx_ef10_reset,
3611 .probe_port = efx_mcdi_port_probe,
3612 .remove_port = efx_mcdi_port_remove,
3613 .fini_dmaq = efx_ef10_fini_dmaq,
3614 .prepare_flr = efx_ef10_prepare_flr,
3615 .finish_flr = efx_port_dummy_op_void,
3616 .describe_stats = efx_ef10_describe_stats,
3617 .update_stats = efx_ef10_update_stats,
3618 .start_stats = efx_mcdi_mac_start_stats,
3619 .pull_stats = efx_mcdi_mac_pull_stats,
3620 .stop_stats = efx_mcdi_mac_stop_stats,
3621 .set_id_led = efx_mcdi_set_id_led,
3622 .push_irq_moderation = efx_ef10_push_irq_moderation,
3623 .reconfigure_mac = efx_ef10_mac_reconfigure,
3624 .check_mac_fault = efx_mcdi_mac_check_fault,
3625 .reconfigure_port = efx_mcdi_port_reconfigure,
3626 .get_wol = efx_ef10_get_wol,
3627 .set_wol = efx_ef10_set_wol,
3628 .resume_wol = efx_port_dummy_op_void,
3629 .test_chip = efx_ef10_test_chip,
3630 .test_nvram = efx_mcdi_nvram_test_all,
3631 .mcdi_request = efx_ef10_mcdi_request,
3632 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
3633 .mcdi_read_response = efx_ef10_mcdi_read_response,
3634 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
3635 .irq_enable_master = efx_port_dummy_op_void,
3636 .irq_test_generate = efx_ef10_irq_test_generate,
3637 .irq_disable_non_ev = efx_port_dummy_op_void,
3638 .irq_handle_msi = efx_ef10_msi_interrupt,
3639 .irq_handle_legacy = efx_ef10_legacy_interrupt,
3640 .tx_probe = efx_ef10_tx_probe,
3641 .tx_init = efx_ef10_tx_init,
3642 .tx_remove = efx_ef10_tx_remove,
3643 .tx_write = efx_ef10_tx_write,
3644 .rx_push_rss_config = efx_ef10_rx_push_rss_config,
3645 .rx_probe = efx_ef10_rx_probe,
3646 .rx_init = efx_ef10_rx_init,
3647 .rx_remove = efx_ef10_rx_remove,
3648 .rx_write = efx_ef10_rx_write,
3649 .rx_defer_refill = efx_ef10_rx_defer_refill,
3650 .ev_probe = efx_ef10_ev_probe,
3651 .ev_init = efx_ef10_ev_init,
3652 .ev_fini = efx_ef10_ev_fini,
3653 .ev_remove = efx_ef10_ev_remove,
3654 .ev_process = efx_ef10_ev_process,
3655 .ev_read_ack = efx_ef10_ev_read_ack,
3656 .ev_test_generate = efx_ef10_ev_test_generate,
3657 .filter_table_probe = efx_ef10_filter_table_probe,
3658 .filter_table_restore = efx_ef10_filter_table_restore,
3659 .filter_table_remove = efx_ef10_filter_table_remove,
3660 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
3661 .filter_insert = efx_ef10_filter_insert,
3662 .filter_remove_safe = efx_ef10_filter_remove_safe,
3663 .filter_get_safe = efx_ef10_filter_get_safe,
3664 .filter_clear_rx = efx_ef10_filter_clear_rx,
3665 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
3666 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
3667 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
3668#ifdef CONFIG_RFS_ACCEL
3669 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
3670 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
3671#endif
3672#ifdef CONFIG_SFC_MTD
3673 .mtd_probe = efx_ef10_mtd_probe,
3674 .mtd_rename = efx_mcdi_mtd_rename,
3675 .mtd_read = efx_mcdi_mtd_read,
3676 .mtd_erase = efx_mcdi_mtd_erase,
3677 .mtd_write = efx_mcdi_mtd_write,
3678 .mtd_sync = efx_mcdi_mtd_sync,
3679#endif
3680 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
3681 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
3682 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
3683
3684 .revision = EFX_REV_HUNT_A0,
3685 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
3686 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
3687 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
3688 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
3689 .can_rx_scatter = true,
3690 .always_rx_scatter = true,
3691 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3692 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
3693 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3694 NETIF_F_RXHASH | NETIF_F_NTUPLE),
3695 .mcdi_max_ver = 2,
3696 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
3697 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
3698 1 << HWTSTAMP_FILTER_ALL,
3699};
1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
17#include "selftest.h"
18#include "ef10_sriov.h"
19#include <linux/in.h>
20#include <linux/jhash.h>
21#include <linux/wait.h>
22#include <linux/workqueue.h>
23
24/* Hardware control for EF10 architecture including 'Huntington'. */
25
26#define EFX_EF10_DRVGEN_EV 7
27enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30};
31
32/* The reserved RSS context value */
33#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
34/* The maximum size of a shared RSS context */
35/* TODO: this should really be from the mcdi protocol export */
36#define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
37
38/* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50#define HUNT_FILTER_TBL_ROWS 8192
51
52#define EFX_EF10_FILTER_ID_INVALID 0xffff
53struct efx_ef10_dev_addr {
54 u8 addr[ETH_ALEN];
55 u16 id;
56};
57
58struct efx_ef10_filter_table {
59/* The RX match field masks supported by this fw & hw, in order of priority */
60 enum efx_filter_match_flags rx_match_flags[
61 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
62 unsigned int rx_match_count;
63
64 struct {
65 unsigned long spec; /* pointer to spec plus flag bits */
66/* BUSY flag indicates that an update is in progress. AUTO_OLD is
67 * used to mark and sweep MAC filters for the device address lists.
68 */
69#define EFX_EF10_FILTER_FLAG_BUSY 1UL
70#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
71#define EFX_EF10_FILTER_FLAGS 3UL
72 u64 handle; /* firmware handle */
73 } *entry;
74 wait_queue_head_t waitq;
75/* Shadow of net_device address lists, guarded by mac_lock */
76#define EFX_EF10_FILTER_DEV_UC_MAX 32
77#define EFX_EF10_FILTER_DEV_MC_MAX 256
78 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
79 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
80 int dev_uc_count;
81 int dev_mc_count;
82/* Indices (like efx_ef10_dev_addr.id) for promisc/allmulti filters */
83 u16 ucdef_id;
84 u16 bcast_id;
85 u16 mcdef_id;
86};
87
88/* An arbitrary search limit for the software hash table */
89#define EFX_EF10_FILTER_SEARCH_LIMIT 200
90
91static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
92static void efx_ef10_filter_table_remove(struct efx_nic *efx);
93
94static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
95{
96 efx_dword_t reg;
97
98 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS);
99 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
100 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
101}
102
103static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
104{
105 int bar;
106
107 bar = efx->type->mem_bar;
108 return resource_size(&efx->pci_dev->resource[bar]);
109}
110
111static bool efx_ef10_is_vf(struct efx_nic *efx)
112{
113 return efx->type->is_vf;
114}
115
116static int efx_ef10_get_pf_index(struct efx_nic *efx)
117{
118 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
119 struct efx_ef10_nic_data *nic_data = efx->nic_data;
120 size_t outlen;
121 int rc;
122
123 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
124 sizeof(outbuf), &outlen);
125 if (rc)
126 return rc;
127 if (outlen < sizeof(outbuf))
128 return -EIO;
129
130 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
131 return 0;
132}
133
134#ifdef CONFIG_SFC_SRIOV
135static int efx_ef10_get_vf_index(struct efx_nic *efx)
136{
137 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
138 struct efx_ef10_nic_data *nic_data = efx->nic_data;
139 size_t outlen;
140 int rc;
141
142 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
143 sizeof(outbuf), &outlen);
144 if (rc)
145 return rc;
146 if (outlen < sizeof(outbuf))
147 return -EIO;
148
149 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
150 return 0;
151}
152#endif
153
154static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
155{
156 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
157 struct efx_ef10_nic_data *nic_data = efx->nic_data;
158 size_t outlen;
159 int rc;
160
161 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
162
163 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
164 outbuf, sizeof(outbuf), &outlen);
165 if (rc)
166 return rc;
167 if (outlen < sizeof(outbuf)) {
168 netif_err(efx, drv, efx->net_dev,
169 "unable to read datapath firmware capabilities\n");
170 return -EIO;
171 }
172
173 nic_data->datapath_caps =
174 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
175
176 /* record the DPCPU firmware IDs to determine VEB vswitching support.
177 */
178 nic_data->rx_dpcpu_fw_id =
179 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
180 nic_data->tx_dpcpu_fw_id =
181 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
182
183 if (!(nic_data->datapath_caps &
184 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
185 netif_err(efx, probe, efx->net_dev,
186 "current firmware does not support an RX prefix\n");
187 return -ENODEV;
188 }
189
190 return 0;
191}
192
193static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
194{
195 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
196 int rc;
197
198 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
199 outbuf, sizeof(outbuf), NULL);
200 if (rc)
201 return rc;
202 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
203 return rc > 0 ? rc : -ERANGE;
204}
205
206static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
207{
208 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
209 size_t outlen;
210 int rc;
211
212 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
213
214 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
215 outbuf, sizeof(outbuf), &outlen);
216 if (rc)
217 return rc;
218 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
219 return -EIO;
220
221 ether_addr_copy(mac_address,
222 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
223 return 0;
224}
225
226static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
227{
228 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
229 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
230 size_t outlen;
231 int num_addrs, rc;
232
233 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
234 EVB_PORT_ID_ASSIGNED);
235 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
236 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
237
238 if (rc)
239 return rc;
240 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
241 return -EIO;
242
243 num_addrs = MCDI_DWORD(outbuf,
244 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
245
246 WARN_ON(num_addrs != 1);
247
248 ether_addr_copy(mac_address,
249 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
250
251 return 0;
252}
253
254static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
255 struct device_attribute *attr,
256 char *buf)
257{
258 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
259
260 return sprintf(buf, "%d\n",
261 ((efx->mcdi->fn_flags) &
262 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
263 ? 1 : 0);
264}
265
266static ssize_t efx_ef10_show_primary_flag(struct device *dev,
267 struct device_attribute *attr,
268 char *buf)
269{
270 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
271
272 return sprintf(buf, "%d\n",
273 ((efx->mcdi->fn_flags) &
274 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
275 ? 1 : 0);
276}
277
278static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
279 NULL);
280static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
281
282static int efx_ef10_probe(struct efx_nic *efx)
283{
284 struct efx_ef10_nic_data *nic_data;
285 struct net_device *net_dev = efx->net_dev;
286 int i, rc;
287
288 /* We can have one VI for each 8K region. However, until we
289 * use TX option descriptors we need two TX queues per channel.
290 */
291 efx->max_channels = min_t(unsigned int,
292 EFX_MAX_CHANNELS,
293 efx_ef10_mem_map_size(efx) /
294 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
295 efx->max_tx_channels = efx->max_channels;
296 if (WARN_ON(efx->max_channels == 0))
297 return -EIO;
298
299 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
300 if (!nic_data)
301 return -ENOMEM;
302 efx->nic_data = nic_data;
303
304 /* we assume later that we can copy from this buffer in dwords */
305 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
306
307 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
308 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
309 if (rc)
310 goto fail1;
311
312 /* Get the MC's warm boot count. In case it's rebooting right
313 * now, be prepared to retry.
314 */
315 i = 0;
316 for (;;) {
317 rc = efx_ef10_get_warm_boot_count(efx);
318 if (rc >= 0)
319 break;
320 if (++i == 5)
321 goto fail2;
322 ssleep(1);
323 }
324 nic_data->warm_boot_count = rc;
325
326 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
327
328 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
329
330 /* In case we're recovering from a crash (kexec), we want to
331 * cancel any outstanding request by the previous user of this
332 * function. We send a special message using the least
333 * significant bits of the 'high' (doorbell) register.
334 */
335 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
336
337 rc = efx_mcdi_init(efx);
338 if (rc)
339 goto fail2;
340
341 /* Reset (most) configuration for this function */
342 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
343 if (rc)
344 goto fail3;
345
346 /* Enable event logging */
347 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
348 if (rc)
349 goto fail3;
350
351 rc = device_create_file(&efx->pci_dev->dev,
352 &dev_attr_link_control_flag);
353 if (rc)
354 goto fail3;
355
356 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
357 if (rc)
358 goto fail4;
359
360 rc = efx_ef10_get_pf_index(efx);
361 if (rc)
362 goto fail5;
363
364 rc = efx_ef10_init_datapath_caps(efx);
365 if (rc < 0)
366 goto fail5;
367
368 efx->rx_packet_len_offset =
369 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
370
371 rc = efx_mcdi_port_get_number(efx);
372 if (rc < 0)
373 goto fail5;
374 efx->port_num = rc;
375 net_dev->dev_port = rc;
376
377 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
378 if (rc)
379 goto fail5;
380
381 rc = efx_ef10_get_sysclk_freq(efx);
382 if (rc < 0)
383 goto fail5;
384 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
385
386 /* Check whether firmware supports bug 35388 workaround.
387 * First try to enable it, then if we get EPERM, just
388 * ask if it's already enabled
389 */
390 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true, NULL);
391 if (rc == 0) {
392 nic_data->workaround_35388 = true;
393 } else if (rc == -EPERM) {
394 unsigned int enabled;
395
396 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled);
397 if (rc)
398 goto fail3;
399 nic_data->workaround_35388 = enabled &
400 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388;
401 } else if (rc != -ENOSYS && rc != -ENOENT) {
402 goto fail5;
403 }
404 netif_dbg(efx, probe, efx->net_dev,
405 "workaround for bug 35388 is %sabled\n",
406 nic_data->workaround_35388 ? "en" : "dis");
407
408 rc = efx_mcdi_mon_probe(efx);
409 if (rc && rc != -EPERM)
410 goto fail5;
411
412 efx_ptp_probe(efx, NULL);
413
414#ifdef CONFIG_SFC_SRIOV
415 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
416 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
417 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
418
419 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
420 } else
421#endif
422 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
423
424 return 0;
425
426fail5:
427 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
428fail4:
429 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
430fail3:
431 efx_mcdi_fini(efx);
432fail2:
433 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
434fail1:
435 kfree(nic_data);
436 efx->nic_data = NULL;
437 return rc;
438}
439
440static int efx_ef10_free_vis(struct efx_nic *efx)
441{
442 MCDI_DECLARE_BUF_ERR(outbuf);
443 size_t outlen;
444 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
445 outbuf, sizeof(outbuf), &outlen);
446
447 /* -EALREADY means nothing to free, so ignore */
448 if (rc == -EALREADY)
449 rc = 0;
450 if (rc)
451 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
452 rc);
453 return rc;
454}
455
456#ifdef EFX_USE_PIO
457
458static void efx_ef10_free_piobufs(struct efx_nic *efx)
459{
460 struct efx_ef10_nic_data *nic_data = efx->nic_data;
461 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
462 unsigned int i;
463 int rc;
464
465 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
466
467 for (i = 0; i < nic_data->n_piobufs; i++) {
468 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
469 nic_data->piobuf_handle[i]);
470 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
471 NULL, 0, NULL);
472 WARN_ON(rc);
473 }
474
475 nic_data->n_piobufs = 0;
476}
477
478static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
479{
480 struct efx_ef10_nic_data *nic_data = efx->nic_data;
481 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
482 unsigned int i;
483 size_t outlen;
484 int rc = 0;
485
486 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
487
488 for (i = 0; i < n; i++) {
489 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
490 outbuf, sizeof(outbuf), &outlen);
491 if (rc) {
492 /* Don't display the MC error if we didn't have space
493 * for a VF.
494 */
495 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
496 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
497 0, outbuf, outlen, rc);
498 break;
499 }
500 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
501 rc = -EIO;
502 break;
503 }
504 nic_data->piobuf_handle[i] =
505 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
506 netif_dbg(efx, probe, efx->net_dev,
507 "allocated PIO buffer %u handle %x\n", i,
508 nic_data->piobuf_handle[i]);
509 }
510
511 nic_data->n_piobufs = i;
512 if (rc)
513 efx_ef10_free_piobufs(efx);
514 return rc;
515}
516
517static int efx_ef10_link_piobufs(struct efx_nic *efx)
518{
519 struct efx_ef10_nic_data *nic_data = efx->nic_data;
520 _MCDI_DECLARE_BUF(inbuf,
521 max(MC_CMD_LINK_PIOBUF_IN_LEN,
522 MC_CMD_UNLINK_PIOBUF_IN_LEN));
523 struct efx_channel *channel;
524 struct efx_tx_queue *tx_queue;
525 unsigned int offset, index;
526 int rc;
527
528 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
529 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
530
531 memset(inbuf, 0, sizeof(inbuf));
532
533 /* Link a buffer to each VI in the write-combining mapping */
534 for (index = 0; index < nic_data->n_piobufs; ++index) {
535 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
536 nic_data->piobuf_handle[index]);
537 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
538 nic_data->pio_write_vi_base + index);
539 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
540 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
541 NULL, 0, NULL);
542 if (rc) {
543 netif_err(efx, drv, efx->net_dev,
544 "failed to link VI %u to PIO buffer %u (%d)\n",
545 nic_data->pio_write_vi_base + index, index,
546 rc);
547 goto fail;
548 }
549 netif_dbg(efx, probe, efx->net_dev,
550 "linked VI %u to PIO buffer %u\n",
551 nic_data->pio_write_vi_base + index, index);
552 }
553
554 /* Link a buffer to each TX queue */
555 efx_for_each_channel(channel, efx) {
556 efx_for_each_channel_tx_queue(tx_queue, channel) {
557 /* We assign the PIO buffers to queues in
558 * reverse order to allow for the following
559 * special case.
560 */
561 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
562 tx_queue->channel->channel - 1) *
563 efx_piobuf_size);
564 index = offset / ER_DZ_TX_PIOBUF_SIZE;
565 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
566
567 /* When the host page size is 4K, the first
568 * host page in the WC mapping may be within
569 * the same VI page as the last TX queue. We
570 * can only link one buffer to each VI.
571 */
572 if (tx_queue->queue == nic_data->pio_write_vi_base) {
573 BUG_ON(index != 0);
574 rc = 0;
575 } else {
576 MCDI_SET_DWORD(inbuf,
577 LINK_PIOBUF_IN_PIOBUF_HANDLE,
578 nic_data->piobuf_handle[index]);
579 MCDI_SET_DWORD(inbuf,
580 LINK_PIOBUF_IN_TXQ_INSTANCE,
581 tx_queue->queue);
582 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
583 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
584 NULL, 0, NULL);
585 }
586
587 if (rc) {
588 /* This is non-fatal; the TX path just
589 * won't use PIO for this queue
590 */
591 netif_err(efx, drv, efx->net_dev,
592 "failed to link VI %u to PIO buffer %u (%d)\n",
593 tx_queue->queue, index, rc);
594 tx_queue->piobuf = NULL;
595 } else {
596 tx_queue->piobuf =
597 nic_data->pio_write_base +
598 index * EFX_VI_PAGE_SIZE + offset;
599 tx_queue->piobuf_offset = offset;
600 netif_dbg(efx, probe, efx->net_dev,
601 "linked VI %u to PIO buffer %u offset %x addr %p\n",
602 tx_queue->queue, index,
603 tx_queue->piobuf_offset,
604 tx_queue->piobuf);
605 }
606 }
607 }
608
609 return 0;
610
611fail:
612 while (index--) {
613 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
614 nic_data->pio_write_vi_base + index);
615 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
616 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
617 NULL, 0, NULL);
618 }
619 return rc;
620}
621
622#else /* !EFX_USE_PIO */
623
624static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
625{
626 return n == 0 ? 0 : -ENOBUFS;
627}
628
629static int efx_ef10_link_piobufs(struct efx_nic *efx)
630{
631 return 0;
632}
633
634static void efx_ef10_free_piobufs(struct efx_nic *efx)
635{
636}
637
638#endif /* EFX_USE_PIO */
639
640static void efx_ef10_remove(struct efx_nic *efx)
641{
642 struct efx_ef10_nic_data *nic_data = efx->nic_data;
643 int rc;
644
645#ifdef CONFIG_SFC_SRIOV
646 struct efx_ef10_nic_data *nic_data_pf;
647 struct pci_dev *pci_dev_pf;
648 struct efx_nic *efx_pf;
649 struct ef10_vf *vf;
650
651 if (efx->pci_dev->is_virtfn) {
652 pci_dev_pf = efx->pci_dev->physfn;
653 if (pci_dev_pf) {
654 efx_pf = pci_get_drvdata(pci_dev_pf);
655 nic_data_pf = efx_pf->nic_data;
656 vf = nic_data_pf->vf + nic_data->vf_index;
657 vf->efx = NULL;
658 } else
659 netif_info(efx, drv, efx->net_dev,
660 "Could not get the PF id from VF\n");
661 }
662#endif
663
664 efx_ptp_remove(efx);
665
666 efx_mcdi_mon_remove(efx);
667
668 efx_ef10_rx_free_indir_table(efx);
669
670 if (nic_data->wc_membase)
671 iounmap(nic_data->wc_membase);
672
673 rc = efx_ef10_free_vis(efx);
674 WARN_ON(rc != 0);
675
676 if (!nic_data->must_restore_piobufs)
677 efx_ef10_free_piobufs(efx);
678
679 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
680 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
681
682 efx_mcdi_fini(efx);
683 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
684 kfree(nic_data);
685}
686
687static int efx_ef10_probe_pf(struct efx_nic *efx)
688{
689 return efx_ef10_probe(efx);
690}
691
692int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
693{
694 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
695
696 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
697 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
698 NULL, 0, NULL);
699}
700
701int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
702{
703 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
704
705 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
706 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
707 NULL, 0, NULL);
708}
709
710int efx_ef10_vport_add_mac(struct efx_nic *efx,
711 unsigned int port_id, u8 *mac)
712{
713 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
714
715 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
716 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
717
718 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
719 sizeof(inbuf), NULL, 0, NULL);
720}
721
722int efx_ef10_vport_del_mac(struct efx_nic *efx,
723 unsigned int port_id, u8 *mac)
724{
725 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
726
727 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
728 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
729
730 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
731 sizeof(inbuf), NULL, 0, NULL);
732}
733
734#ifdef CONFIG_SFC_SRIOV
735static int efx_ef10_probe_vf(struct efx_nic *efx)
736{
737 int rc;
738 struct pci_dev *pci_dev_pf;
739
740 /* If the parent PF has no VF data structure, it doesn't know about this
741 * VF so fail probe. The VF needs to be re-created. This can happen
742 * if the PF driver is unloaded while the VF is assigned to a guest.
743 */
744 pci_dev_pf = efx->pci_dev->physfn;
745 if (pci_dev_pf) {
746 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
747 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
748
749 if (!nic_data_pf->vf) {
750 netif_info(efx, drv, efx->net_dev,
751 "The VF cannot link to its parent PF; "
752 "please destroy and re-create the VF\n");
753 return -EBUSY;
754 }
755 }
756
757 rc = efx_ef10_probe(efx);
758 if (rc)
759 return rc;
760
761 rc = efx_ef10_get_vf_index(efx);
762 if (rc)
763 goto fail;
764
765 if (efx->pci_dev->is_virtfn) {
766 if (efx->pci_dev->physfn) {
767 struct efx_nic *efx_pf =
768 pci_get_drvdata(efx->pci_dev->physfn);
769 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
770 struct efx_ef10_nic_data *nic_data = efx->nic_data;
771
772 nic_data_p->vf[nic_data->vf_index].efx = efx;
773 nic_data_p->vf[nic_data->vf_index].pci_dev =
774 efx->pci_dev;
775 } else
776 netif_info(efx, drv, efx->net_dev,
777 "Could not get the PF id from VF\n");
778 }
779
780 return 0;
781
782fail:
783 efx_ef10_remove(efx);
784 return rc;
785}
786#else
787static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
788{
789 return 0;
790}
791#endif
792
793static int efx_ef10_alloc_vis(struct efx_nic *efx,
794 unsigned int min_vis, unsigned int max_vis)
795{
796 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
797 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
798 struct efx_ef10_nic_data *nic_data = efx->nic_data;
799 size_t outlen;
800 int rc;
801
802 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
803 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
804 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
805 outbuf, sizeof(outbuf), &outlen);
806 if (rc != 0)
807 return rc;
808
809 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
810 return -EIO;
811
812 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
813 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
814
815 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
816 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
817 return 0;
818}
819
820/* Note that the failure path of this function does not free
821 * resources, as this will be done by efx_ef10_remove().
822 */
823static int efx_ef10_dimension_resources(struct efx_nic *efx)
824{
825 struct efx_ef10_nic_data *nic_data = efx->nic_data;
826 unsigned int uc_mem_map_size, wc_mem_map_size;
827 unsigned int min_vis = max(EFX_TXQ_TYPES,
828 efx_separate_tx_channels ? 2 : 1);
829 unsigned int channel_vis, pio_write_vi_base, max_vis;
830 void __iomem *membase;
831 int rc;
832
833 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
834
835#ifdef EFX_USE_PIO
836 /* Try to allocate PIO buffers if wanted and if the full
837 * number of PIO buffers would be sufficient to allocate one
838 * copy-buffer per TX channel. Failure is non-fatal, as there
839 * are only a small number of PIO buffers shared between all
840 * functions of the controller.
841 */
842 if (efx_piobuf_size != 0 &&
843 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
844 efx->n_tx_channels) {
845 unsigned int n_piobufs =
846 DIV_ROUND_UP(efx->n_tx_channels,
847 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
848
849 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
850 if (rc)
851 netif_err(efx, probe, efx->net_dev,
852 "failed to allocate PIO buffers (%d)\n", rc);
853 else
854 netif_dbg(efx, probe, efx->net_dev,
855 "allocated %u PIO buffers\n", n_piobufs);
856 }
857#else
858 nic_data->n_piobufs = 0;
859#endif
860
861 /* PIO buffers should be mapped with write-combining enabled,
862 * and we want to make single UC and WC mappings rather than
863 * several of each (in fact that's the only option if host
864 * page size is >4K). So we may allocate some extra VIs just
865 * for writing PIO buffers through.
866 *
867 * The UC mapping contains (channel_vis - 1) complete VIs and the
868 * first half of the next VI. Then the WC mapping begins with
869 * the second half of this last VI.
870 */
871 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
872 ER_DZ_TX_PIOBUF);
873 if (nic_data->n_piobufs) {
874 /* pio_write_vi_base rounds down to give the number of complete
875 * VIs inside the UC mapping.
876 */
877 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
878 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
879 nic_data->n_piobufs) *
880 EFX_VI_PAGE_SIZE) -
881 uc_mem_map_size);
882 max_vis = pio_write_vi_base + nic_data->n_piobufs;
883 } else {
884 pio_write_vi_base = 0;
885 wc_mem_map_size = 0;
886 max_vis = channel_vis;
887 }
888
889 /* In case the last attached driver failed to free VIs, do it now */
890 rc = efx_ef10_free_vis(efx);
891 if (rc != 0)
892 return rc;
893
894 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
895 if (rc != 0)
896 return rc;
897
898 if (nic_data->n_allocated_vis < channel_vis) {
899 netif_info(efx, drv, efx->net_dev,
900 "Could not allocate enough VIs to satisfy RSS"
901 " requirements. Performance may not be optimal.\n");
902 /* We didn't get the VIs to populate our channels.
903 * We could keep what we got but then we'd have more
904 * interrupts than we need.
905 * Instead calculate new max_channels and restart
906 */
907 efx->max_channels = nic_data->n_allocated_vis;
908 efx->max_tx_channels =
909 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
910
911 efx_ef10_free_vis(efx);
912 return -EAGAIN;
913 }
914
915 /* If we didn't get enough VIs to map all the PIO buffers, free the
916 * PIO buffers
917 */
918 if (nic_data->n_piobufs &&
919 nic_data->n_allocated_vis <
920 pio_write_vi_base + nic_data->n_piobufs) {
921 netif_dbg(efx, probe, efx->net_dev,
922 "%u VIs are not sufficient to map %u PIO buffers\n",
923 nic_data->n_allocated_vis, nic_data->n_piobufs);
924 efx_ef10_free_piobufs(efx);
925 }
926
927 /* Shrink the original UC mapping of the memory BAR */
928 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
929 if (!membase) {
930 netif_err(efx, probe, efx->net_dev,
931 "could not shrink memory BAR to %x\n",
932 uc_mem_map_size);
933 return -ENOMEM;
934 }
935 iounmap(efx->membase);
936 efx->membase = membase;
937
938 /* Set up the WC mapping if needed */
939 if (wc_mem_map_size) {
940 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
941 uc_mem_map_size,
942 wc_mem_map_size);
943 if (!nic_data->wc_membase) {
944 netif_err(efx, probe, efx->net_dev,
945 "could not allocate WC mapping of size %x\n",
946 wc_mem_map_size);
947 return -ENOMEM;
948 }
949 nic_data->pio_write_vi_base = pio_write_vi_base;
950 nic_data->pio_write_base =
951 nic_data->wc_membase +
952 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
953 uc_mem_map_size);
954
955 rc = efx_ef10_link_piobufs(efx);
956 if (rc)
957 efx_ef10_free_piobufs(efx);
958 }
959
960 netif_dbg(efx, probe, efx->net_dev,
961 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
962 &efx->membase_phys, efx->membase, uc_mem_map_size,
963 nic_data->wc_membase, wc_mem_map_size);
964
965 return 0;
966}
967
968static int efx_ef10_init_nic(struct efx_nic *efx)
969{
970 struct efx_ef10_nic_data *nic_data = efx->nic_data;
971 int rc;
972
973 if (nic_data->must_check_datapath_caps) {
974 rc = efx_ef10_init_datapath_caps(efx);
975 if (rc)
976 return rc;
977 nic_data->must_check_datapath_caps = false;
978 }
979
980 if (nic_data->must_realloc_vis) {
981 /* We cannot let the number of VIs change now */
982 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
983 nic_data->n_allocated_vis);
984 if (rc)
985 return rc;
986 nic_data->must_realloc_vis = false;
987 }
988
989 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
990 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
991 if (rc == 0) {
992 rc = efx_ef10_link_piobufs(efx);
993 if (rc)
994 efx_ef10_free_piobufs(efx);
995 }
996
997 /* Log an error on failure, but this is non-fatal */
998 if (rc)
999 netif_err(efx, drv, efx->net_dev,
1000 "failed to restore PIO buffers (%d)\n", rc);
1001 nic_data->must_restore_piobufs = false;
1002 }
1003
1004 /* don't fail init if RSS setup doesn't work */
1005 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
1006
1007 return 0;
1008}
1009
1010static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1011{
1012 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1013#ifdef CONFIG_SFC_SRIOV
1014 unsigned int i;
1015#endif
1016
1017 /* All our allocations have been reset */
1018 nic_data->must_realloc_vis = true;
1019 nic_data->must_restore_filters = true;
1020 nic_data->must_restore_piobufs = true;
1021 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1022
1023 /* Driver-created vswitches and vports must be re-created */
1024 nic_data->must_probe_vswitching = true;
1025 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1026#ifdef CONFIG_SFC_SRIOV
1027 if (nic_data->vf)
1028 for (i = 0; i < efx->vf_count; i++)
1029 nic_data->vf[i].vport_id = 0;
1030#endif
1031}
1032
1033static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1034{
1035 if (reason == RESET_TYPE_MC_FAILURE)
1036 return RESET_TYPE_DATAPATH;
1037
1038 return efx_mcdi_map_reset_reason(reason);
1039}
1040
1041static int efx_ef10_map_reset_flags(u32 *flags)
1042{
1043 enum {
1044 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1045 ETH_RESET_SHARED_SHIFT),
1046 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1047 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1048 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1049 ETH_RESET_SHARED_SHIFT)
1050 };
1051
1052 /* We assume for now that our PCI function is permitted to
1053 * reset everything.
1054 */
1055
1056 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1057 *flags &= ~EF10_RESET_MC;
1058 return RESET_TYPE_WORLD;
1059 }
1060
1061 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1062 *flags &= ~EF10_RESET_PORT;
1063 return RESET_TYPE_ALL;
1064 }
1065
1066 /* no invisible reset implemented */
1067
1068 return -EINVAL;
1069}
1070
1071static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1072{
1073 int rc = efx_mcdi_reset(efx, reset_type);
1074
1075 /* Unprivileged functions return -EPERM, but need to return success
1076 * here so that the datapath is brought back up.
1077 */
1078 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1079 rc = 0;
1080
1081 /* If it was a port reset, trigger reallocation of MC resources.
1082 * Note that on an MC reset nothing needs to be done now because we'll
1083 * detect the MC reset later and handle it then.
1084 * For an FLR, we never get an MC reset event, but the MC has reset all
1085 * resources assigned to us, so we have to trigger reallocation now.
1086 */
1087 if ((reset_type == RESET_TYPE_ALL ||
1088 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1089 efx_ef10_reset_mc_allocations(efx);
1090 return rc;
1091}
1092
1093#define EF10_DMA_STAT(ext_name, mcdi_name) \
1094 [EF10_STAT_ ## ext_name] = \
1095 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1096#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1097 [EF10_STAT_ ## int_name] = \
1098 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1099#define EF10_OTHER_STAT(ext_name) \
1100 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1101#define GENERIC_SW_STAT(ext_name) \
1102 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1103
1104static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1105 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1106 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1107 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1108 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1109 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1110 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1111 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1112 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1113 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1114 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1115 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1116 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1117 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1118 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1119 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1120 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1121 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1122 EF10_OTHER_STAT(port_rx_good_bytes),
1123 EF10_OTHER_STAT(port_rx_bad_bytes),
1124 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1125 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1126 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1127 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1128 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1129 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1130 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1131 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1132 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1133 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1134 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1135 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1136 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1137 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1138 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1139 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1140 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1141 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1142 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1143 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1144 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1145 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1146 GENERIC_SW_STAT(rx_nodesc_trunc),
1147 GENERIC_SW_STAT(rx_noskb_drops),
1148 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1149 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1150 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1151 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1152 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1153 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1154 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1155 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1156 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1157 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1158 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1159 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1160 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1161 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1162 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1163 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1164 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1165 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1166 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1167 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1168 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1169 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1170 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1171 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1172 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1173 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1174 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1175 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1176 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1177 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1178};
1179
1180#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1181 (1ULL << EF10_STAT_port_tx_packets) | \
1182 (1ULL << EF10_STAT_port_tx_pause) | \
1183 (1ULL << EF10_STAT_port_tx_unicast) | \
1184 (1ULL << EF10_STAT_port_tx_multicast) | \
1185 (1ULL << EF10_STAT_port_tx_broadcast) | \
1186 (1ULL << EF10_STAT_port_rx_bytes) | \
1187 (1ULL << \
1188 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1189 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1190 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1191 (1ULL << EF10_STAT_port_rx_packets) | \
1192 (1ULL << EF10_STAT_port_rx_good) | \
1193 (1ULL << EF10_STAT_port_rx_bad) | \
1194 (1ULL << EF10_STAT_port_rx_pause) | \
1195 (1ULL << EF10_STAT_port_rx_control) | \
1196 (1ULL << EF10_STAT_port_rx_unicast) | \
1197 (1ULL << EF10_STAT_port_rx_multicast) | \
1198 (1ULL << EF10_STAT_port_rx_broadcast) | \
1199 (1ULL << EF10_STAT_port_rx_lt64) | \
1200 (1ULL << EF10_STAT_port_rx_64) | \
1201 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1202 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1203 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1204 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1205 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1206 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1207 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1208 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1209 (1ULL << EF10_STAT_port_rx_overflow) | \
1210 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1211 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1212 (1ULL << GENERIC_STAT_rx_noskb_drops))
1213
1214/* These statistics are only provided by the 10G MAC. For a 10G/40G
1215 * switchable port we do not expose these because they might not
1216 * include all the packets they should.
1217 */
1218#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1219 (1ULL << EF10_STAT_port_tx_lt64) | \
1220 (1ULL << EF10_STAT_port_tx_64) | \
1221 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1222 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1223 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1224 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1225 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1226 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1227
1228/* These statistics are only provided by the 40G MAC. For a 10G/40G
1229 * switchable port we do expose these because the errors will otherwise
1230 * be silent.
1231 */
1232#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1233 (1ULL << EF10_STAT_port_rx_length_error))
1234
1235/* These statistics are only provided if the firmware supports the
1236 * capability PM_AND_RXDP_COUNTERS.
1237 */
1238#define HUNT_PM_AND_RXDP_STAT_MASK ( \
1239 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1240 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1241 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1242 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1243 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1244 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1245 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1246 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1247 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1248 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1249 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1250 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1251
1252static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1253{
1254 u64 raw_mask = HUNT_COMMON_STAT_MASK;
1255 u32 port_caps = efx_mcdi_phy_get_caps(efx);
1256 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1257
1258 if (!(efx->mcdi->fn_flags &
1259 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1260 return 0;
1261
1262 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
1263 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1264 else
1265 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1266
1267 if (nic_data->datapath_caps &
1268 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1269 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1270
1271 return raw_mask;
1272}
1273
1274static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1275{
1276 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1277 u64 raw_mask[2];
1278
1279 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1280
1281 /* Only show vadaptor stats when EVB capability is present */
1282 if (nic_data->datapath_caps &
1283 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1284 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1285 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1286 } else {
1287 raw_mask[1] = 0;
1288 }
1289
1290#if BITS_PER_LONG == 64
1291 mask[0] = raw_mask[0];
1292 mask[1] = raw_mask[1];
1293#else
1294 mask[0] = raw_mask[0] & 0xffffffff;
1295 mask[1] = raw_mask[0] >> 32;
1296 mask[2] = raw_mask[1] & 0xffffffff;
1297 mask[3] = raw_mask[1] >> 32;
1298#endif
1299}
1300
1301static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1302{
1303 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1304
1305 efx_ef10_get_stat_mask(efx, mask);
1306 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1307 mask, names);
1308}
1309
1310static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1311 struct rtnl_link_stats64 *core_stats)
1312{
1313 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1314 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1315 u64 *stats = nic_data->stats;
1316 size_t stats_count = 0, index;
1317
1318 efx_ef10_get_stat_mask(efx, mask);
1319
1320 if (full_stats) {
1321 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1322 if (efx_ef10_stat_desc[index].name) {
1323 *full_stats++ = stats[index];
1324 ++stats_count;
1325 }
1326 }
1327 }
1328
1329 if (!core_stats)
1330 return stats_count;
1331
1332 if (nic_data->datapath_caps &
1333 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1334 /* Use vadaptor stats. */
1335 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1336 stats[EF10_STAT_rx_multicast] +
1337 stats[EF10_STAT_rx_broadcast];
1338 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1339 stats[EF10_STAT_tx_multicast] +
1340 stats[EF10_STAT_tx_broadcast];
1341 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1342 stats[EF10_STAT_rx_multicast_bytes] +
1343 stats[EF10_STAT_rx_broadcast_bytes];
1344 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1345 stats[EF10_STAT_tx_multicast_bytes] +
1346 stats[EF10_STAT_tx_broadcast_bytes];
1347 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1348 stats[GENERIC_STAT_rx_noskb_drops];
1349 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1350 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1351 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1352 core_stats->rx_errors = core_stats->rx_crc_errors;
1353 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1354 } else {
1355 /* Use port stats. */
1356 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1357 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1358 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1359 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1360 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1361 stats[GENERIC_STAT_rx_nodesc_trunc] +
1362 stats[GENERIC_STAT_rx_noskb_drops];
1363 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1364 core_stats->rx_length_errors =
1365 stats[EF10_STAT_port_rx_gtjumbo] +
1366 stats[EF10_STAT_port_rx_length_error];
1367 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1368 core_stats->rx_frame_errors =
1369 stats[EF10_STAT_port_rx_align_error];
1370 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1371 core_stats->rx_errors = (core_stats->rx_length_errors +
1372 core_stats->rx_crc_errors +
1373 core_stats->rx_frame_errors);
1374 }
1375
1376 return stats_count;
1377}
1378
1379static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1380{
1381 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1382 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1383 __le64 generation_start, generation_end;
1384 u64 *stats = nic_data->stats;
1385 __le64 *dma_stats;
1386
1387 efx_ef10_get_stat_mask(efx, mask);
1388
1389 dma_stats = efx->stats_buffer.addr;
1390 nic_data = efx->nic_data;
1391
1392 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1393 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1394 return 0;
1395 rmb();
1396 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1397 stats, efx->stats_buffer.addr, false);
1398 rmb();
1399 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1400 if (generation_end != generation_start)
1401 return -EAGAIN;
1402
1403 /* Update derived statistics */
1404 efx_nic_fix_nodesc_drop_stat(efx,
1405 &stats[EF10_STAT_port_rx_nodesc_drops]);
1406 stats[EF10_STAT_port_rx_good_bytes] =
1407 stats[EF10_STAT_port_rx_bytes] -
1408 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1409 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1410 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1411 efx_update_sw_stats(efx, stats);
1412 return 0;
1413}
1414
1415
1416static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1417 struct rtnl_link_stats64 *core_stats)
1418{
1419 int retry;
1420
1421 /* If we're unlucky enough to read statistics during the DMA, wait
1422 * up to 10ms for it to finish (typically takes <500us)
1423 */
1424 for (retry = 0; retry < 100; ++retry) {
1425 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1426 break;
1427 udelay(100);
1428 }
1429
1430 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1431}
1432
1433static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1434{
1435 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1436 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1437 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1438 __le64 generation_start, generation_end;
1439 u64 *stats = nic_data->stats;
1440 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1441 struct efx_buffer stats_buf;
1442 __le64 *dma_stats;
1443 int rc;
1444
1445 spin_unlock_bh(&efx->stats_lock);
1446
1447 if (in_interrupt()) {
1448 /* If in atomic context, cannot update stats. Just update the
1449 * software stats and return so the caller can continue.
1450 */
1451 spin_lock_bh(&efx->stats_lock);
1452 efx_update_sw_stats(efx, stats);
1453 return 0;
1454 }
1455
1456 efx_ef10_get_stat_mask(efx, mask);
1457
1458 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
1459 if (rc) {
1460 spin_lock_bh(&efx->stats_lock);
1461 return rc;
1462 }
1463
1464 dma_stats = stats_buf.addr;
1465 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1466
1467 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1468 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
1469 MAC_STATS_IN_DMA, 1);
1470 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1471 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1472
1473 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1474 NULL, 0, NULL);
1475 spin_lock_bh(&efx->stats_lock);
1476 if (rc) {
1477 /* Expect ENOENT if DMA queues have not been set up */
1478 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1479 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1480 sizeof(inbuf), NULL, 0, rc);
1481 goto out;
1482 }
1483
1484 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1485 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1486 WARN_ON_ONCE(1);
1487 goto out;
1488 }
1489 rmb();
1490 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1491 stats, stats_buf.addr, false);
1492 rmb();
1493 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1494 if (generation_end != generation_start) {
1495 rc = -EAGAIN;
1496 goto out;
1497 }
1498
1499 efx_update_sw_stats(efx, stats);
1500out:
1501 efx_nic_free_buffer(efx, &stats_buf);
1502 return rc;
1503}
1504
1505static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1506 struct rtnl_link_stats64 *core_stats)
1507{
1508 if (efx_ef10_try_update_nic_stats_vf(efx))
1509 return 0;
1510
1511 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1512}
1513
1514static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1515{
1516 struct efx_nic *efx = channel->efx;
1517 unsigned int mode, value;
1518 efx_dword_t timer_cmd;
1519
1520 if (channel->irq_moderation) {
1521 mode = 3;
1522 value = channel->irq_moderation - 1;
1523 } else {
1524 mode = 0;
1525 value = 0;
1526 }
1527
1528 if (EFX_EF10_WORKAROUND_35388(efx)) {
1529 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1530 EFE_DD_EVQ_IND_TIMER_FLAGS,
1531 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1532 ERF_DD_EVQ_IND_TIMER_VAL, value);
1533 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1534 channel->channel);
1535 } else {
1536 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1537 ERF_DZ_TC_TIMER_VAL, value);
1538 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1539 channel->channel);
1540 }
1541}
1542
1543static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1544 struct ethtool_wolinfo *wol) {}
1545
1546static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1547{
1548 return -EOPNOTSUPP;
1549}
1550
1551static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1552{
1553 wol->supported = 0;
1554 wol->wolopts = 0;
1555 memset(&wol->sopass, 0, sizeof(wol->sopass));
1556}
1557
1558static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1559{
1560 if (type != 0)
1561 return -EINVAL;
1562 return 0;
1563}
1564
1565static void efx_ef10_mcdi_request(struct efx_nic *efx,
1566 const efx_dword_t *hdr, size_t hdr_len,
1567 const efx_dword_t *sdu, size_t sdu_len)
1568{
1569 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1570 u8 *pdu = nic_data->mcdi_buf.addr;
1571
1572 memcpy(pdu, hdr, hdr_len);
1573 memcpy(pdu + hdr_len, sdu, sdu_len);
1574 wmb();
1575
1576 /* The hardware provides 'low' and 'high' (doorbell) registers
1577 * for passing the 64-bit address of an MCDI request to
1578 * firmware. However the dwords are swapped by firmware. The
1579 * least significant bits of the doorbell are then 0 for all
1580 * MCDI requests due to alignment.
1581 */
1582 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1583 ER_DZ_MC_DB_LWRD);
1584 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1585 ER_DZ_MC_DB_HWRD);
1586}
1587
1588static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1589{
1590 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1591 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1592
1593 rmb();
1594 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1595}
1596
1597static void
1598efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1599 size_t offset, size_t outlen)
1600{
1601 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1602 const u8 *pdu = nic_data->mcdi_buf.addr;
1603
1604 memcpy(outbuf, pdu + offset, outlen);
1605}
1606
1607static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
1608{
1609 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1610
1611 /* All our allocations have been reset */
1612 efx_ef10_reset_mc_allocations(efx);
1613
1614 /* The datapath firmware might have been changed */
1615 nic_data->must_check_datapath_caps = true;
1616
1617 /* MAC statistics have been cleared on the NIC; clear the local
1618 * statistic that we update with efx_update_diff_stat().
1619 */
1620 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1621}
1622
1623static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1624{
1625 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1626 int rc;
1627
1628 rc = efx_ef10_get_warm_boot_count(efx);
1629 if (rc < 0) {
1630 /* The firmware is presumably in the process of
1631 * rebooting. However, we are supposed to report each
1632 * reboot just once, so we must only do that once we
1633 * can read and store the updated warm boot count.
1634 */
1635 return 0;
1636 }
1637
1638 if (rc == nic_data->warm_boot_count)
1639 return 0;
1640
1641 nic_data->warm_boot_count = rc;
1642 efx_ef10_mcdi_reboot_detected(efx);
1643
1644 return -EIO;
1645}
1646
1647/* Handle an MSI interrupt
1648 *
1649 * Handle an MSI hardware interrupt. This routine schedules event
1650 * queue processing. No interrupt acknowledgement cycle is necessary.
1651 * Also, we never need to check that the interrupt is for us, since
1652 * MSI interrupts cannot be shared.
1653 */
1654static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1655{
1656 struct efx_msi_context *context = dev_id;
1657 struct efx_nic *efx = context->efx;
1658
1659 netif_vdbg(efx, intr, efx->net_dev,
1660 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1661
1662 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1663 /* Note test interrupts */
1664 if (context->index == efx->irq_level)
1665 efx->last_irq_cpu = raw_smp_processor_id();
1666
1667 /* Schedule processing of the channel */
1668 efx_schedule_channel_irq(efx->channel[context->index]);
1669 }
1670
1671 return IRQ_HANDLED;
1672}
1673
1674static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1675{
1676 struct efx_nic *efx = dev_id;
1677 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1678 struct efx_channel *channel;
1679 efx_dword_t reg;
1680 u32 queues;
1681
1682 /* Read the ISR which also ACKs the interrupts */
1683 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR);
1684 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1685
1686 if (queues == 0)
1687 return IRQ_NONE;
1688
1689 if (likely(soft_enabled)) {
1690 /* Note test interrupts */
1691 if (queues & (1U << efx->irq_level))
1692 efx->last_irq_cpu = raw_smp_processor_id();
1693
1694 efx_for_each_channel(channel, efx) {
1695 if (queues & 1)
1696 efx_schedule_channel_irq(channel);
1697 queues >>= 1;
1698 }
1699 }
1700
1701 netif_vdbg(efx, intr, efx->net_dev,
1702 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1703 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1704
1705 return IRQ_HANDLED;
1706}
1707
1708static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1709{
1710 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1711
1712 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1713
1714 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1715 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1716 inbuf, sizeof(inbuf), NULL, 0, NULL);
1717}
1718
1719static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1720{
1721 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1722 (tx_queue->ptr_mask + 1) *
1723 sizeof(efx_qword_t),
1724 GFP_KERNEL);
1725}
1726
1727/* This writes to the TX_DESC_WPTR and also pushes data */
1728static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1729 const efx_qword_t *txd)
1730{
1731 unsigned int write_ptr;
1732 efx_oword_t reg;
1733
1734 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1735 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1736 reg.qword[0] = *txd;
1737 efx_writeo_page(tx_queue->efx, ®,
1738 ER_DZ_TX_DESC_UPD, tx_queue->queue);
1739}
1740
1741static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1742{
1743 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1744 EFX_BUF_SIZE));
1745 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1746 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1747 struct efx_channel *channel = tx_queue->channel;
1748 struct efx_nic *efx = tx_queue->efx;
1749 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1750 size_t inlen;
1751 dma_addr_t dma_addr;
1752 efx_qword_t *txd;
1753 int rc;
1754 int i;
1755 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
1756
1757 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1758 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1759 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1760 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1761 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1762 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1763 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1764 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
1765 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
1766
1767 dma_addr = tx_queue->txd.buf.dma_addr;
1768
1769 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1770 tx_queue->queue, entries, (u64)dma_addr);
1771
1772 for (i = 0; i < entries; ++i) {
1773 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1774 dma_addr += EFX_BUF_SIZE;
1775 }
1776
1777 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1778
1779 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
1780 NULL, 0, NULL);
1781 if (rc)
1782 goto fail;
1783
1784 /* A previous user of this TX queue might have set us up the
1785 * bomb by writing a descriptor to the TX push collector but
1786 * not the doorbell. (Each collector belongs to a port, not a
1787 * queue or function, so cannot easily be reset.) We must
1788 * attempt to push a no-op descriptor in its place.
1789 */
1790 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1791 tx_queue->insert_count = 1;
1792 txd = efx_tx_desc(tx_queue, 0);
1793 EFX_POPULATE_QWORD_4(*txd,
1794 ESF_DZ_TX_DESC_IS_OPT, true,
1795 ESF_DZ_TX_OPTION_TYPE,
1796 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1797 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1798 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1799 tx_queue->write_count = 1;
1800
1801 if (nic_data->datapath_caps &
1802 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
1803 tx_queue->tso_version = 1;
1804 }
1805
1806 wmb();
1807 efx_ef10_push_tx_desc(tx_queue, txd);
1808
1809 return;
1810
1811fail:
1812 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1813 tx_queue->queue);
1814}
1815
1816static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1817{
1818 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
1819 MCDI_DECLARE_BUF_ERR(outbuf);
1820 struct efx_nic *efx = tx_queue->efx;
1821 size_t outlen;
1822 int rc;
1823
1824 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1825 tx_queue->queue);
1826
1827 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
1828 outbuf, sizeof(outbuf), &outlen);
1829
1830 if (rc && rc != -EALREADY)
1831 goto fail;
1832
1833 return;
1834
1835fail:
1836 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1837 outbuf, outlen, rc);
1838}
1839
1840static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1841{
1842 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1843}
1844
1845/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1846static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1847{
1848 unsigned int write_ptr;
1849 efx_dword_t reg;
1850
1851 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1852 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1853 efx_writed_page(tx_queue->efx, ®,
1854 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1855}
1856
1857static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1858{
1859 unsigned int old_write_count = tx_queue->write_count;
1860 struct efx_tx_buffer *buffer;
1861 unsigned int write_ptr;
1862 efx_qword_t *txd;
1863
1864 tx_queue->xmit_more_available = false;
1865 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
1866 return;
1867
1868 do {
1869 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1870 buffer = &tx_queue->buffer[write_ptr];
1871 txd = efx_tx_desc(tx_queue, write_ptr);
1872 ++tx_queue->write_count;
1873
1874 /* Create TX descriptor ring entry */
1875 if (buffer->flags & EFX_TX_BUF_OPTION) {
1876 *txd = buffer->option;
1877 } else {
1878 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1879 EFX_POPULATE_QWORD_3(
1880 *txd,
1881 ESF_DZ_TX_KER_CONT,
1882 buffer->flags & EFX_TX_BUF_CONT,
1883 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1884 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1885 }
1886 } while (tx_queue->write_count != tx_queue->insert_count);
1887
1888 wmb(); /* Ensure descriptors are written before they are fetched */
1889
1890 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1891 txd = efx_tx_desc(tx_queue,
1892 old_write_count & tx_queue->ptr_mask);
1893 efx_ef10_push_tx_desc(tx_queue, txd);
1894 ++tx_queue->pushes;
1895 } else {
1896 efx_ef10_notify_tx_desc(tx_queue);
1897 }
1898}
1899
1900static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
1901 bool exclusive, unsigned *context_size)
1902{
1903 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1904 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
1905 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1906 size_t outlen;
1907 int rc;
1908 u32 alloc_type = exclusive ?
1909 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
1910 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
1911 unsigned rss_spread = exclusive ?
1912 efx->rss_spread :
1913 min(rounddown_pow_of_two(efx->rss_spread),
1914 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
1915
1916 if (!exclusive && rss_spread == 1) {
1917 *context = EFX_EF10_RSS_CONTEXT_INVALID;
1918 if (context_size)
1919 *context_size = 1;
1920 return 0;
1921 }
1922
1923 if (nic_data->datapath_caps &
1924 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
1925 return -EOPNOTSUPP;
1926
1927 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
1928 nic_data->vport_id);
1929 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
1930 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
1931
1932 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1933 outbuf, sizeof(outbuf), &outlen);
1934 if (rc != 0)
1935 return rc;
1936
1937 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1938 return -EIO;
1939
1940 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1941
1942 if (context_size)
1943 *context_size = rss_spread;
1944
1945 return 0;
1946}
1947
1948static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1949{
1950 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1951 int rc;
1952
1953 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1954 context);
1955
1956 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1957 NULL, 0, NULL);
1958 WARN_ON(rc != 0);
1959}
1960
1961static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
1962 const u32 *rx_indir_table)
1963{
1964 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1965 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1966 int i, rc;
1967
1968 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1969 context);
1970 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1971 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1972
1973 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1974 MCDI_PTR(tablebuf,
1975 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
1976 (u8) rx_indir_table[i];
1977
1978 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1979 sizeof(tablebuf), NULL, 0, NULL);
1980 if (rc != 0)
1981 return rc;
1982
1983 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1984 context);
1985 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1986 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1987 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1988 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1989 efx->rx_hash_key[i];
1990
1991 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1992 sizeof(keybuf), NULL, 0, NULL);
1993}
1994
1995static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1996{
1997 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1998
1999 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2000 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2001 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2002}
2003
2004static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2005 unsigned *context_size)
2006{
2007 u32 new_rx_rss_context;
2008 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2009 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2010 false, context_size);
2011
2012 if (rc != 0)
2013 return rc;
2014
2015 nic_data->rx_rss_context = new_rx_rss_context;
2016 nic_data->rx_rss_context_exclusive = false;
2017 efx_set_default_rx_indir_table(efx);
2018 return 0;
2019}
2020
2021static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2022 const u32 *rx_indir_table)
2023{
2024 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2025 int rc;
2026 u32 new_rx_rss_context;
2027
2028 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2029 !nic_data->rx_rss_context_exclusive) {
2030 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2031 true, NULL);
2032 if (rc == -EOPNOTSUPP)
2033 return rc;
2034 else if (rc != 0)
2035 goto fail1;
2036 } else {
2037 new_rx_rss_context = nic_data->rx_rss_context;
2038 }
2039
2040 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2041 rx_indir_table);
2042 if (rc != 0)
2043 goto fail2;
2044
2045 if (nic_data->rx_rss_context != new_rx_rss_context)
2046 efx_ef10_rx_free_indir_table(efx);
2047 nic_data->rx_rss_context = new_rx_rss_context;
2048 nic_data->rx_rss_context_exclusive = true;
2049 if (rx_indir_table != efx->rx_indir_table)
2050 memcpy(efx->rx_indir_table, rx_indir_table,
2051 sizeof(efx->rx_indir_table));
2052 return 0;
2053
2054fail2:
2055 if (new_rx_rss_context != nic_data->rx_rss_context)
2056 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2057fail1:
2058 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2059 return rc;
2060}
2061
2062static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2063 const u32 *rx_indir_table)
2064{
2065 int rc;
2066
2067 if (efx->rss_spread == 1)
2068 return 0;
2069
2070 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
2071
2072 if (rc == -ENOBUFS && !user) {
2073 unsigned context_size;
2074 bool mismatch = false;
2075 size_t i;
2076
2077 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2078 i++)
2079 mismatch = rx_indir_table[i] !=
2080 ethtool_rxfh_indir_default(i, efx->rss_spread);
2081
2082 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2083 if (rc == 0) {
2084 if (context_size != efx->rss_spread)
2085 netif_warn(efx, probe, efx->net_dev,
2086 "Could not allocate an exclusive RSS"
2087 " context; allocated a shared one of"
2088 " different size."
2089 " Wanted %u, got %u.\n",
2090 efx->rss_spread, context_size);
2091 else if (mismatch)
2092 netif_warn(efx, probe, efx->net_dev,
2093 "Could not allocate an exclusive RSS"
2094 " context; allocated a shared one but"
2095 " could not apply custom"
2096 " indirection.\n");
2097 else
2098 netif_info(efx, probe, efx->net_dev,
2099 "Could not allocate an exclusive RSS"
2100 " context; allocated a shared one.\n");
2101 }
2102 }
2103 return rc;
2104}
2105
2106static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2107 const u32 *rx_indir_table
2108 __attribute__ ((unused)))
2109{
2110 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2111
2112 if (user)
2113 return -EOPNOTSUPP;
2114 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2115 return 0;
2116 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
2117}
2118
2119static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2120{
2121 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2122 (rx_queue->ptr_mask + 1) *
2123 sizeof(efx_qword_t),
2124 GFP_KERNEL);
2125}
2126
2127static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2128{
2129 MCDI_DECLARE_BUF(inbuf,
2130 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2131 EFX_BUF_SIZE));
2132 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2133 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2134 struct efx_nic *efx = rx_queue->efx;
2135 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2136 size_t inlen;
2137 dma_addr_t dma_addr;
2138 int rc;
2139 int i;
2140 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
2141
2142 rx_queue->scatter_n = 0;
2143 rx_queue->scatter_len = 0;
2144
2145 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2146 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2147 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2148 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2149 efx_rx_queue_index(rx_queue));
2150 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2151 INIT_RXQ_IN_FLAG_PREFIX, 1,
2152 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
2153 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
2154 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
2155
2156 dma_addr = rx_queue->rxd.buf.dma_addr;
2157
2158 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2159 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2160
2161 for (i = 0; i < entries; ++i) {
2162 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2163 dma_addr += EFX_BUF_SIZE;
2164 }
2165
2166 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2167
2168 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
2169 NULL, 0, NULL);
2170 if (rc)
2171 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2172 efx_rx_queue_index(rx_queue));
2173}
2174
2175static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2176{
2177 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
2178 MCDI_DECLARE_BUF_ERR(outbuf);
2179 struct efx_nic *efx = rx_queue->efx;
2180 size_t outlen;
2181 int rc;
2182
2183 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2184 efx_rx_queue_index(rx_queue));
2185
2186 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
2187 outbuf, sizeof(outbuf), &outlen);
2188
2189 if (rc && rc != -EALREADY)
2190 goto fail;
2191
2192 return;
2193
2194fail:
2195 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2196 outbuf, outlen, rc);
2197}
2198
2199static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2200{
2201 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2202}
2203
2204/* This creates an entry in the RX descriptor queue */
2205static inline void
2206efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2207{
2208 struct efx_rx_buffer *rx_buf;
2209 efx_qword_t *rxd;
2210
2211 rxd = efx_rx_desc(rx_queue, index);
2212 rx_buf = efx_rx_buffer(rx_queue, index);
2213 EFX_POPULATE_QWORD_2(*rxd,
2214 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2215 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2216}
2217
2218static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2219{
2220 struct efx_nic *efx = rx_queue->efx;
2221 unsigned int write_count;
2222 efx_dword_t reg;
2223
2224 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2225 write_count = rx_queue->added_count & ~7;
2226 if (rx_queue->notified_count == write_count)
2227 return;
2228
2229 do
2230 efx_ef10_build_rx_desc(
2231 rx_queue,
2232 rx_queue->notified_count & rx_queue->ptr_mask);
2233 while (++rx_queue->notified_count != write_count);
2234
2235 wmb();
2236 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2237 write_count & rx_queue->ptr_mask);
2238 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD,
2239 efx_rx_queue_index(rx_queue));
2240}
2241
2242static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2243
2244static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2245{
2246 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2247 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2248 efx_qword_t event;
2249
2250 EFX_POPULATE_QWORD_2(event,
2251 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2252 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2253
2254 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2255
2256 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2257 * already swapped the data to little-endian order.
2258 */
2259 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2260 sizeof(efx_qword_t));
2261
2262 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2263 inbuf, sizeof(inbuf), 0,
2264 efx_ef10_rx_defer_refill_complete, 0);
2265}
2266
2267static void
2268efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2269 int rc, efx_dword_t *outbuf,
2270 size_t outlen_actual)
2271{
2272 /* nothing to do */
2273}
2274
2275static int efx_ef10_ev_probe(struct efx_channel *channel)
2276{
2277 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2278 (channel->eventq_mask + 1) *
2279 sizeof(efx_qword_t),
2280 GFP_KERNEL);
2281}
2282
2283static void efx_ef10_ev_fini(struct efx_channel *channel)
2284{
2285 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2286 MCDI_DECLARE_BUF_ERR(outbuf);
2287 struct efx_nic *efx = channel->efx;
2288 size_t outlen;
2289 int rc;
2290
2291 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2292
2293 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2294 outbuf, sizeof(outbuf), &outlen);
2295
2296 if (rc && rc != -EALREADY)
2297 goto fail;
2298
2299 return;
2300
2301fail:
2302 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2303 outbuf, outlen, rc);
2304}
2305
2306static int efx_ef10_ev_init(struct efx_channel *channel)
2307{
2308 MCDI_DECLARE_BUF(inbuf,
2309 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2310 EFX_BUF_SIZE));
2311 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
2312 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2313 struct efx_nic *efx = channel->efx;
2314 struct efx_ef10_nic_data *nic_data;
2315 bool supports_rx_merge;
2316 size_t inlen, outlen;
2317 unsigned int enabled, implemented;
2318 dma_addr_t dma_addr;
2319 int rc;
2320 int i;
2321
2322 nic_data = efx->nic_data;
2323 supports_rx_merge =
2324 !!(nic_data->datapath_caps &
2325 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2326
2327 /* Fill event queue with all ones (i.e. empty events) */
2328 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2329
2330 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2331 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2332 /* INIT_EVQ expects index in vector table, not absolute */
2333 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
2334 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2335 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2336 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2337 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2338 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
2339 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2340 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2341 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2342 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2343 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2344 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2345 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2346
2347 dma_addr = channel->eventq.buf.dma_addr;
2348 for (i = 0; i < entries; ++i) {
2349 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2350 dma_addr += EFX_BUF_SIZE;
2351 }
2352
2353 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2354
2355 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2356 outbuf, sizeof(outbuf), &outlen);
2357 /* IRQ return is ignored */
2358 if (channel->channel || rc)
2359 return rc;
2360
2361 /* Successfully created event queue on channel 0 */
2362 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
2363 if (rc == -ENOSYS) {
2364 /* GET_WORKAROUNDS was implemented before the bug26807
2365 * workaround, thus the latter must be unavailable in this fw
2366 */
2367 nic_data->workaround_26807 = false;
2368 rc = 0;
2369 } else if (rc) {
2370 goto fail;
2371 } else {
2372 nic_data->workaround_26807 =
2373 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2374
2375 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
2376 !nic_data->workaround_26807) {
2377 unsigned int flags;
2378
2379 rc = efx_mcdi_set_workaround(efx,
2380 MC_CMD_WORKAROUND_BUG26807,
2381 true, &flags);
2382
2383 if (!rc) {
2384 if (flags &
2385 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2386 netif_info(efx, drv, efx->net_dev,
2387 "other functions on NIC have been reset\n");
2388
2389 /* With MCFW v4.6.x and earlier, the
2390 * boot count will have incremented,
2391 * so re-read the warm_boot_count
2392 * value now to ensure this function
2393 * doesn't think it has changed next
2394 * time it checks.
2395 */
2396 rc = efx_ef10_get_warm_boot_count(efx);
2397 if (rc >= 0) {
2398 nic_data->warm_boot_count = rc;
2399 rc = 0;
2400 }
2401 }
2402 nic_data->workaround_26807 = true;
2403 } else if (rc == -EPERM) {
2404 rc = 0;
2405 }
2406 }
2407 }
2408
2409 if (!rc)
2410 return 0;
2411
2412fail:
2413 efx_ef10_ev_fini(channel);
2414 return rc;
2415}
2416
2417static void efx_ef10_ev_remove(struct efx_channel *channel)
2418{
2419 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2420}
2421
2422static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2423 unsigned int rx_queue_label)
2424{
2425 struct efx_nic *efx = rx_queue->efx;
2426
2427 netif_info(efx, hw, efx->net_dev,
2428 "rx event arrived on queue %d labeled as queue %u\n",
2429 efx_rx_queue_index(rx_queue), rx_queue_label);
2430
2431 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2432}
2433
2434static void
2435efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2436 unsigned int actual, unsigned int expected)
2437{
2438 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2439 struct efx_nic *efx = rx_queue->efx;
2440
2441 netif_info(efx, hw, efx->net_dev,
2442 "dropped %d events (index=%d expected=%d)\n",
2443 dropped, actual, expected);
2444
2445 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2446}
2447
2448/* partially received RX was aborted. clean up. */
2449static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2450{
2451 unsigned int rx_desc_ptr;
2452
2453 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2454 "scattered RX aborted (dropping %u buffers)\n",
2455 rx_queue->scatter_n);
2456
2457 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2458
2459 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2460 0, EFX_RX_PKT_DISCARD);
2461
2462 rx_queue->removed_count += rx_queue->scatter_n;
2463 rx_queue->scatter_n = 0;
2464 rx_queue->scatter_len = 0;
2465 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2466}
2467
2468static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2469 const efx_qword_t *event)
2470{
2471 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2472 unsigned int n_descs, n_packets, i;
2473 struct efx_nic *efx = channel->efx;
2474 struct efx_rx_queue *rx_queue;
2475 bool rx_cont;
2476 u16 flags = 0;
2477
2478 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2479 return 0;
2480
2481 /* Basic packet information */
2482 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2483 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2484 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2485 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2486 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2487
2488 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2489 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2490 EFX_QWORD_FMT "\n",
2491 EFX_QWORD_VAL(*event));
2492
2493 rx_queue = efx_channel_get_rx_queue(channel);
2494
2495 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2496 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2497
2498 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2499 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2500
2501 if (n_descs != rx_queue->scatter_n + 1) {
2502 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2503
2504 /* detect rx abort */
2505 if (unlikely(n_descs == rx_queue->scatter_n)) {
2506 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2507 netdev_WARN(efx->net_dev,
2508 "invalid RX abort: scatter_n=%u event="
2509 EFX_QWORD_FMT "\n",
2510 rx_queue->scatter_n,
2511 EFX_QWORD_VAL(*event));
2512 efx_ef10_handle_rx_abort(rx_queue);
2513 return 0;
2514 }
2515
2516 /* Check that RX completion merging is valid, i.e.
2517 * the current firmware supports it and this is a
2518 * non-scattered packet.
2519 */
2520 if (!(nic_data->datapath_caps &
2521 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2522 rx_queue->scatter_n != 0 || rx_cont) {
2523 efx_ef10_handle_rx_bad_lbits(
2524 rx_queue, next_ptr_lbits,
2525 (rx_queue->removed_count +
2526 rx_queue->scatter_n + 1) &
2527 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2528 return 0;
2529 }
2530
2531 /* Merged completion for multiple non-scattered packets */
2532 rx_queue->scatter_n = 1;
2533 rx_queue->scatter_len = 0;
2534 n_packets = n_descs;
2535 ++channel->n_rx_merge_events;
2536 channel->n_rx_merge_packets += n_packets;
2537 flags |= EFX_RX_PKT_PREFIX_LEN;
2538 } else {
2539 ++rx_queue->scatter_n;
2540 rx_queue->scatter_len += rx_bytes;
2541 if (rx_cont)
2542 return 0;
2543 n_packets = 1;
2544 }
2545
2546 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2547 flags |= EFX_RX_PKT_DISCARD;
2548
2549 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2550 channel->n_rx_ip_hdr_chksum_err += n_packets;
2551 } else if (unlikely(EFX_QWORD_FIELD(*event,
2552 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
2553 channel->n_rx_tcp_udp_chksum_err += n_packets;
2554 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
2555 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
2556 flags |= EFX_RX_PKT_CSUMMED;
2557 }
2558
2559 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
2560 flags |= EFX_RX_PKT_TCP;
2561
2562 channel->irq_mod_score += 2 * n_packets;
2563
2564 /* Handle received packet(s) */
2565 for (i = 0; i < n_packets; i++) {
2566 efx_rx_packet(rx_queue,
2567 rx_queue->removed_count & rx_queue->ptr_mask,
2568 rx_queue->scatter_n, rx_queue->scatter_len,
2569 flags);
2570 rx_queue->removed_count += rx_queue->scatter_n;
2571 }
2572
2573 rx_queue->scatter_n = 0;
2574 rx_queue->scatter_len = 0;
2575
2576 return n_packets;
2577}
2578
2579static int
2580efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2581{
2582 struct efx_nic *efx = channel->efx;
2583 struct efx_tx_queue *tx_queue;
2584 unsigned int tx_ev_desc_ptr;
2585 unsigned int tx_ev_q_label;
2586 int tx_descs = 0;
2587
2588 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2589 return 0;
2590
2591 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2592 return 0;
2593
2594 /* Transmit completion */
2595 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2596 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2597 tx_queue = efx_channel_get_tx_queue(channel,
2598 tx_ev_q_label % EFX_TXQ_TYPES);
2599 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
2600 tx_queue->ptr_mask);
2601 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2602
2603 return tx_descs;
2604}
2605
2606static void
2607efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2608{
2609 struct efx_nic *efx = channel->efx;
2610 int subcode;
2611
2612 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2613
2614 switch (subcode) {
2615 case ESE_DZ_DRV_TIMER_EV:
2616 case ESE_DZ_DRV_WAKE_UP_EV:
2617 break;
2618 case ESE_DZ_DRV_START_UP_EV:
2619 /* event queue init complete. ok. */
2620 break;
2621 default:
2622 netif_err(efx, hw, efx->net_dev,
2623 "channel %d unknown driver event type %d"
2624 " (data " EFX_QWORD_FMT ")\n",
2625 channel->channel, subcode,
2626 EFX_QWORD_VAL(*event));
2627
2628 }
2629}
2630
2631static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
2632 efx_qword_t *event)
2633{
2634 struct efx_nic *efx = channel->efx;
2635 u32 subcode;
2636
2637 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
2638
2639 switch (subcode) {
2640 case EFX_EF10_TEST:
2641 channel->event_test_cpu = raw_smp_processor_id();
2642 break;
2643 case EFX_EF10_REFILL:
2644 /* The queue must be empty, so we won't receive any rx
2645 * events, so efx_process_channel() won't refill the
2646 * queue. Refill it here
2647 */
2648 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
2649 break;
2650 default:
2651 netif_err(efx, hw, efx->net_dev,
2652 "channel %d unknown driver event type %u"
2653 " (data " EFX_QWORD_FMT ")\n",
2654 channel->channel, (unsigned) subcode,
2655 EFX_QWORD_VAL(*event));
2656 }
2657}
2658
2659static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
2660{
2661 struct efx_nic *efx = channel->efx;
2662 efx_qword_t event, *p_event;
2663 unsigned int read_ptr;
2664 int ev_code;
2665 int tx_descs = 0;
2666 int spent = 0;
2667
2668 if (quota <= 0)
2669 return spent;
2670
2671 read_ptr = channel->eventq_read_ptr;
2672
2673 for (;;) {
2674 p_event = efx_event(channel, read_ptr);
2675 event = *p_event;
2676
2677 if (!efx_event_present(&event))
2678 break;
2679
2680 EFX_SET_QWORD(*p_event);
2681
2682 ++read_ptr;
2683
2684 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
2685
2686 netif_vdbg(efx, drv, efx->net_dev,
2687 "processing event on %d " EFX_QWORD_FMT "\n",
2688 channel->channel, EFX_QWORD_VAL(event));
2689
2690 switch (ev_code) {
2691 case ESE_DZ_EV_CODE_MCDI_EV:
2692 efx_mcdi_process_event(channel, &event);
2693 break;
2694 case ESE_DZ_EV_CODE_RX_EV:
2695 spent += efx_ef10_handle_rx_event(channel, &event);
2696 if (spent >= quota) {
2697 /* XXX can we split a merged event to
2698 * avoid going over-quota?
2699 */
2700 spent = quota;
2701 goto out;
2702 }
2703 break;
2704 case ESE_DZ_EV_CODE_TX_EV:
2705 tx_descs += efx_ef10_handle_tx_event(channel, &event);
2706 if (tx_descs > efx->txq_entries) {
2707 spent = quota;
2708 goto out;
2709 } else if (++spent == quota) {
2710 goto out;
2711 }
2712 break;
2713 case ESE_DZ_EV_CODE_DRIVER_EV:
2714 efx_ef10_handle_driver_event(channel, &event);
2715 if (++spent == quota)
2716 goto out;
2717 break;
2718 case EFX_EF10_DRVGEN_EV:
2719 efx_ef10_handle_driver_generated_event(channel, &event);
2720 break;
2721 default:
2722 netif_err(efx, hw, efx->net_dev,
2723 "channel %d unknown event type %d"
2724 " (data " EFX_QWORD_FMT ")\n",
2725 channel->channel, ev_code,
2726 EFX_QWORD_VAL(event));
2727 }
2728 }
2729
2730out:
2731 channel->eventq_read_ptr = read_ptr;
2732 return spent;
2733}
2734
2735static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2736{
2737 struct efx_nic *efx = channel->efx;
2738 efx_dword_t rptr;
2739
2740 if (EFX_EF10_WORKAROUND_35388(efx)) {
2741 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2742 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2743 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2744 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2745
2746 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2747 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2748 ERF_DD_EVQ_IND_RPTR,
2749 (channel->eventq_read_ptr &
2750 channel->eventq_mask) >>
2751 ERF_DD_EVQ_IND_RPTR_WIDTH);
2752 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2753 channel->channel);
2754 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2755 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2756 ERF_DD_EVQ_IND_RPTR,
2757 channel->eventq_read_ptr &
2758 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2759 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2760 channel->channel);
2761 } else {
2762 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2763 channel->eventq_read_ptr &
2764 channel->eventq_mask);
2765 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2766 }
2767}
2768
2769static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2770{
2771 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2772 struct efx_nic *efx = channel->efx;
2773 efx_qword_t event;
2774 int rc;
2775
2776 EFX_POPULATE_QWORD_2(event,
2777 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2778 ESF_DZ_EV_DATA, EFX_EF10_TEST);
2779
2780 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2781
2782 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2783 * already swapped the data to little-endian order.
2784 */
2785 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2786 sizeof(efx_qword_t));
2787
2788 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2789 NULL, 0, NULL);
2790 if (rc != 0)
2791 goto fail;
2792
2793 return;
2794
2795fail:
2796 WARN_ON(true);
2797 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2798}
2799
2800void efx_ef10_handle_drain_event(struct efx_nic *efx)
2801{
2802 if (atomic_dec_and_test(&efx->active_queues))
2803 wake_up(&efx->flush_wq);
2804
2805 WARN_ON(atomic_read(&efx->active_queues) < 0);
2806}
2807
2808static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2809{
2810 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2811 struct efx_channel *channel;
2812 struct efx_tx_queue *tx_queue;
2813 struct efx_rx_queue *rx_queue;
2814 int pending;
2815
2816 /* If the MC has just rebooted, the TX/RX queues will have already been
2817 * torn down, but efx->active_queues needs to be set to zero.
2818 */
2819 if (nic_data->must_realloc_vis) {
2820 atomic_set(&efx->active_queues, 0);
2821 return 0;
2822 }
2823
2824 /* Do not attempt to write to the NIC during EEH recovery */
2825 if (efx->state != STATE_RECOVERY) {
2826 efx_for_each_channel(channel, efx) {
2827 efx_for_each_channel_rx_queue(rx_queue, channel)
2828 efx_ef10_rx_fini(rx_queue);
2829 efx_for_each_channel_tx_queue(tx_queue, channel)
2830 efx_ef10_tx_fini(tx_queue);
2831 }
2832
2833 wait_event_timeout(efx->flush_wq,
2834 atomic_read(&efx->active_queues) == 0,
2835 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2836 pending = atomic_read(&efx->active_queues);
2837 if (pending) {
2838 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2839 pending);
2840 return -ETIMEDOUT;
2841 }
2842 }
2843
2844 return 0;
2845}
2846
2847static void efx_ef10_prepare_flr(struct efx_nic *efx)
2848{
2849 atomic_set(&efx->active_queues, 0);
2850}
2851
2852static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2853 const struct efx_filter_spec *right)
2854{
2855 if ((left->match_flags ^ right->match_flags) |
2856 ((left->flags ^ right->flags) &
2857 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2858 return false;
2859
2860 return memcmp(&left->outer_vid, &right->outer_vid,
2861 sizeof(struct efx_filter_spec) -
2862 offsetof(struct efx_filter_spec, outer_vid)) == 0;
2863}
2864
2865static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2866{
2867 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2868 return jhash2((const u32 *)&spec->outer_vid,
2869 (sizeof(struct efx_filter_spec) -
2870 offsetof(struct efx_filter_spec, outer_vid)) / 4,
2871 0);
2872 /* XXX should we randomise the initval? */
2873}
2874
2875/* Decide whether a filter should be exclusive or else should allow
2876 * delivery to additional recipients. Currently we decide that
2877 * filters for specific local unicast MAC and IP addresses are
2878 * exclusive.
2879 */
2880static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2881{
2882 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2883 !is_multicast_ether_addr(spec->loc_mac))
2884 return true;
2885
2886 if ((spec->match_flags &
2887 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2888 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2889 if (spec->ether_type == htons(ETH_P_IP) &&
2890 !ipv4_is_multicast(spec->loc_host[0]))
2891 return true;
2892 if (spec->ether_type == htons(ETH_P_IPV6) &&
2893 ((const u8 *)spec->loc_host)[0] != 0xff)
2894 return true;
2895 }
2896
2897 return false;
2898}
2899
2900static struct efx_filter_spec *
2901efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2902 unsigned int filter_idx)
2903{
2904 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2905 ~EFX_EF10_FILTER_FLAGS);
2906}
2907
2908static unsigned int
2909efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2910 unsigned int filter_idx)
2911{
2912 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2913}
2914
2915static void
2916efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2917 unsigned int filter_idx,
2918 const struct efx_filter_spec *spec,
2919 unsigned int flags)
2920{
2921 table->entry[filter_idx].spec = (unsigned long)spec | flags;
2922}
2923
2924static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2925 const struct efx_filter_spec *spec,
2926 efx_dword_t *inbuf, u64 handle,
2927 bool replacing)
2928{
2929 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2930 u32 flags = spec->flags;
2931
2932 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2933
2934 /* Remove RSS flag if we don't have an RSS context. */
2935 if (flags & EFX_FILTER_FLAG_RX_RSS &&
2936 spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
2937 nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
2938 flags &= ~EFX_FILTER_FLAG_RX_RSS;
2939
2940 if (replacing) {
2941 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2942 MC_CMD_FILTER_OP_IN_OP_REPLACE);
2943 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2944 } else {
2945 u32 match_fields = 0;
2946
2947 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2948 efx_ef10_filter_is_exclusive(spec) ?
2949 MC_CMD_FILTER_OP_IN_OP_INSERT :
2950 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2951
2952 /* Convert match flags and values. Unlike almost
2953 * everything else in MCDI, these fields are in
2954 * network byte order.
2955 */
2956 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2957 match_fields |=
2958 is_multicast_ether_addr(spec->loc_mac) ?
2959 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2960 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2961#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
2962 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
2963 match_fields |= \
2964 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2965 mcdi_field ## _LBN; \
2966 BUILD_BUG_ON( \
2967 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2968 sizeof(spec->gen_field)); \
2969 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2970 &spec->gen_field, sizeof(spec->gen_field)); \
2971 }
2972 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2973 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2974 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2975 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2976 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2977 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2978 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2979 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2980 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2981 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2982#undef COPY_FIELD
2983 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2984 match_fields);
2985 }
2986
2987 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
2988 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2989 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2990 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2991 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
2992 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
2993 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2994 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
2995 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2996 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2997 0 : spec->dmaq_id);
2998 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2999 (flags & EFX_FILTER_FLAG_RX_RSS) ?
3000 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3001 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
3002 if (flags & EFX_FILTER_FLAG_RX_RSS)
3003 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3004 spec->rss_context !=
3005 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3006 spec->rss_context : nic_data->rx_rss_context);
3007}
3008
3009static int efx_ef10_filter_push(struct efx_nic *efx,
3010 const struct efx_filter_spec *spec,
3011 u64 *handle, bool replacing)
3012{
3013 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3014 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
3015 int rc;
3016
3017 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3018 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3019 outbuf, sizeof(outbuf), NULL);
3020 if (rc == 0)
3021 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3022 if (rc == -ENOSPC)
3023 rc = -EBUSY; /* to match efx_farch_filter_insert() */
3024 return rc;
3025}
3026
3027static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
3028 enum efx_filter_match_flags match_flags)
3029{
3030 unsigned int match_pri;
3031
3032 for (match_pri = 0;
3033 match_pri < table->rx_match_count;
3034 match_pri++)
3035 if (table->rx_match_flags[match_pri] == match_flags)
3036 return match_pri;
3037
3038 return -EPROTONOSUPPORT;
3039}
3040
3041static s32 efx_ef10_filter_insert(struct efx_nic *efx,
3042 struct efx_filter_spec *spec,
3043 bool replace_equal)
3044{
3045 struct efx_ef10_filter_table *table = efx->filter_state;
3046 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3047 struct efx_filter_spec *saved_spec;
3048 unsigned int match_pri, hash;
3049 unsigned int priv_flags;
3050 bool replacing = false;
3051 int ins_index = -1;
3052 DEFINE_WAIT(wait);
3053 bool is_mc_recip;
3054 s32 rc;
3055
3056 /* For now, only support RX filters */
3057 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
3058 EFX_FILTER_FLAG_RX)
3059 return -EINVAL;
3060
3061 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
3062 if (rc < 0)
3063 return rc;
3064 match_pri = rc;
3065
3066 hash = efx_ef10_filter_hash(spec);
3067 is_mc_recip = efx_filter_is_mc_recipient(spec);
3068 if (is_mc_recip)
3069 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3070
3071 /* Find any existing filters with the same match tuple or
3072 * else a free slot to insert at. If any of them are busy,
3073 * we have to wait and retry.
3074 */
3075 for (;;) {
3076 unsigned int depth = 1;
3077 unsigned int i;
3078
3079 spin_lock_bh(&efx->filter_lock);
3080
3081 for (;;) {
3082 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3083 saved_spec = efx_ef10_filter_entry_spec(table, i);
3084
3085 if (!saved_spec) {
3086 if (ins_index < 0)
3087 ins_index = i;
3088 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3089 if (table->entry[i].spec &
3090 EFX_EF10_FILTER_FLAG_BUSY)
3091 break;
3092 if (spec->priority < saved_spec->priority &&
3093 spec->priority != EFX_FILTER_PRI_AUTO) {
3094 rc = -EPERM;
3095 goto out_unlock;
3096 }
3097 if (!is_mc_recip) {
3098 /* This is the only one */
3099 if (spec->priority ==
3100 saved_spec->priority &&
3101 !replace_equal) {
3102 rc = -EEXIST;
3103 goto out_unlock;
3104 }
3105 ins_index = i;
3106 goto found;
3107 } else if (spec->priority >
3108 saved_spec->priority ||
3109 (spec->priority ==
3110 saved_spec->priority &&
3111 replace_equal)) {
3112 if (ins_index < 0)
3113 ins_index = i;
3114 else
3115 __set_bit(depth, mc_rem_map);
3116 }
3117 }
3118
3119 /* Once we reach the maximum search depth, use
3120 * the first suitable slot or return -EBUSY if
3121 * there was none
3122 */
3123 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3124 if (ins_index < 0) {
3125 rc = -EBUSY;
3126 goto out_unlock;
3127 }
3128 goto found;
3129 }
3130
3131 ++depth;
3132 }
3133
3134 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3135 spin_unlock_bh(&efx->filter_lock);
3136 schedule();
3137 }
3138
3139found:
3140 /* Create a software table entry if necessary, and mark it
3141 * busy. We might yet fail to insert, but any attempt to
3142 * insert a conflicting filter while we're waiting for the
3143 * firmware must find the busy entry.
3144 */
3145 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3146 if (saved_spec) {
3147 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3148 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
3149 /* Just make sure it won't be removed */
3150 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3151 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
3152 table->entry[ins_index].spec &=
3153 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3154 rc = ins_index;
3155 goto out_unlock;
3156 }
3157 replacing = true;
3158 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3159 } else {
3160 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3161 if (!saved_spec) {
3162 rc = -ENOMEM;
3163 goto out_unlock;
3164 }
3165 *saved_spec = *spec;
3166 priv_flags = 0;
3167 }
3168 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3169 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3170
3171 /* Mark lower-priority multicast recipients busy prior to removal */
3172 if (is_mc_recip) {
3173 unsigned int depth, i;
3174
3175 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3176 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3177 if (test_bit(depth, mc_rem_map))
3178 table->entry[i].spec |=
3179 EFX_EF10_FILTER_FLAG_BUSY;
3180 }
3181 }
3182
3183 spin_unlock_bh(&efx->filter_lock);
3184
3185 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3186 replacing);
3187
3188 /* Finalise the software table entry */
3189 spin_lock_bh(&efx->filter_lock);
3190 if (rc == 0) {
3191 if (replacing) {
3192 /* Update the fields that may differ */
3193 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3194 saved_spec->flags |=
3195 EFX_FILTER_FLAG_RX_OVER_AUTO;
3196 saved_spec->priority = spec->priority;
3197 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
3198 saved_spec->flags |= spec->flags;
3199 saved_spec->rss_context = spec->rss_context;
3200 saved_spec->dmaq_id = spec->dmaq_id;
3201 }
3202 } else if (!replacing) {
3203 kfree(saved_spec);
3204 saved_spec = NULL;
3205 }
3206 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3207
3208 /* Remove and finalise entries for lower-priority multicast
3209 * recipients
3210 */
3211 if (is_mc_recip) {
3212 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3213 unsigned int depth, i;
3214
3215 memset(inbuf, 0, sizeof(inbuf));
3216
3217 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3218 if (!test_bit(depth, mc_rem_map))
3219 continue;
3220
3221 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3222 saved_spec = efx_ef10_filter_entry_spec(table, i);
3223 priv_flags = efx_ef10_filter_entry_flags(table, i);
3224
3225 if (rc == 0) {
3226 spin_unlock_bh(&efx->filter_lock);
3227 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3228 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3229 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3230 table->entry[i].handle);
3231 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3232 inbuf, sizeof(inbuf),
3233 NULL, 0, NULL);
3234 spin_lock_bh(&efx->filter_lock);
3235 }
3236
3237 if (rc == 0) {
3238 kfree(saved_spec);
3239 saved_spec = NULL;
3240 priv_flags = 0;
3241 } else {
3242 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3243 }
3244 efx_ef10_filter_set_entry(table, i, saved_spec,
3245 priv_flags);
3246 }
3247 }
3248
3249 /* If successful, return the inserted filter ID */
3250 if (rc == 0)
3251 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3252
3253 wake_up_all(&table->waitq);
3254out_unlock:
3255 spin_unlock_bh(&efx->filter_lock);
3256 finish_wait(&table->waitq, &wait);
3257 return rc;
3258}
3259
3260static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
3261{
3262 /* no need to do anything here on EF10 */
3263}
3264
3265/* Remove a filter.
3266 * If !by_index, remove by ID
3267 * If by_index, remove by index
3268 * Filter ID may come from userland and must be range-checked.
3269 */
3270static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
3271 unsigned int priority_mask,
3272 u32 filter_id, bool by_index)
3273{
3274 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3275 struct efx_ef10_filter_table *table = efx->filter_state;
3276 MCDI_DECLARE_BUF(inbuf,
3277 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3278 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3279 struct efx_filter_spec *spec;
3280 DEFINE_WAIT(wait);
3281 int rc;
3282
3283 /* Find the software table entry and mark it busy. Don't
3284 * remove it yet; any attempt to update while we're waiting
3285 * for the firmware must find the busy entry.
3286 */
3287 for (;;) {
3288 spin_lock_bh(&efx->filter_lock);
3289 if (!(table->entry[filter_idx].spec &
3290 EFX_EF10_FILTER_FLAG_BUSY))
3291 break;
3292 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3293 spin_unlock_bh(&efx->filter_lock);
3294 schedule();
3295 }
3296
3297 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3298 if (!spec ||
3299 (!by_index &&
3300 efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
3301 filter_id / HUNT_FILTER_TBL_ROWS)) {
3302 rc = -ENOENT;
3303 goto out_unlock;
3304 }
3305
3306 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
3307 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
3308 /* Just remove flags */
3309 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
3310 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3311 rc = 0;
3312 goto out_unlock;
3313 }
3314
3315 if (!(priority_mask & (1U << spec->priority))) {
3316 rc = -ENOENT;
3317 goto out_unlock;
3318 }
3319
3320 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3321 spin_unlock_bh(&efx->filter_lock);
3322
3323 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
3324 /* Reset to an automatic filter */
3325
3326 struct efx_filter_spec new_spec = *spec;
3327
3328 new_spec.priority = EFX_FILTER_PRI_AUTO;
3329 new_spec.flags = (EFX_FILTER_FLAG_RX |
3330 (efx_rss_enabled(efx) ?
3331 EFX_FILTER_FLAG_RX_RSS : 0));
3332 new_spec.dmaq_id = 0;
3333 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3334 rc = efx_ef10_filter_push(efx, &new_spec,
3335 &table->entry[filter_idx].handle,
3336 true);
3337
3338 spin_lock_bh(&efx->filter_lock);
3339 if (rc == 0)
3340 *spec = new_spec;
3341 } else {
3342 /* Really remove the filter */
3343
3344 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3345 efx_ef10_filter_is_exclusive(spec) ?
3346 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3347 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3348 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3349 table->entry[filter_idx].handle);
3350 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3351 inbuf, sizeof(inbuf), NULL, 0, NULL);
3352
3353 spin_lock_bh(&efx->filter_lock);
3354 if (rc == 0) {
3355 kfree(spec);
3356 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3357 }
3358 }
3359
3360 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3361 wake_up_all(&table->waitq);
3362out_unlock:
3363 spin_unlock_bh(&efx->filter_lock);
3364 finish_wait(&table->waitq, &wait);
3365 return rc;
3366}
3367
3368static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3369 enum efx_filter_priority priority,
3370 u32 filter_id)
3371{
3372 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3373 filter_id, false);
3374}
3375
3376static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
3377{
3378 return filter_id % HUNT_FILTER_TBL_ROWS;
3379}
3380
3381static int efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
3382 enum efx_filter_priority priority,
3383 u32 filter_id)
3384{
3385 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3386 filter_id, true);
3387}
3388
3389static int efx_ef10_filter_get_safe(struct efx_nic *efx,
3390 enum efx_filter_priority priority,
3391 u32 filter_id, struct efx_filter_spec *spec)
3392{
3393 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3394 struct efx_ef10_filter_table *table = efx->filter_state;
3395 const struct efx_filter_spec *saved_spec;
3396 int rc;
3397
3398 spin_lock_bh(&efx->filter_lock);
3399 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
3400 if (saved_spec && saved_spec->priority == priority &&
3401 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
3402 filter_id / HUNT_FILTER_TBL_ROWS) {
3403 *spec = *saved_spec;
3404 rc = 0;
3405 } else {
3406 rc = -ENOENT;
3407 }
3408 spin_unlock_bh(&efx->filter_lock);
3409 return rc;
3410}
3411
3412static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
3413 enum efx_filter_priority priority)
3414{
3415 unsigned int priority_mask;
3416 unsigned int i;
3417 int rc;
3418
3419 priority_mask = (((1U << (priority + 1)) - 1) &
3420 ~(1U << EFX_FILTER_PRI_AUTO));
3421
3422 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3423 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3424 i, true);
3425 if (rc && rc != -ENOENT)
3426 return rc;
3427 }
3428
3429 return 0;
3430}
3431
3432static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3433 enum efx_filter_priority priority)
3434{
3435 struct efx_ef10_filter_table *table = efx->filter_state;
3436 unsigned int filter_idx;
3437 s32 count = 0;
3438
3439 spin_lock_bh(&efx->filter_lock);
3440 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3441 if (table->entry[filter_idx].spec &&
3442 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3443 priority)
3444 ++count;
3445 }
3446 spin_unlock_bh(&efx->filter_lock);
3447 return count;
3448}
3449
3450static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3451{
3452 struct efx_ef10_filter_table *table = efx->filter_state;
3453
3454 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3455}
3456
3457static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3458 enum efx_filter_priority priority,
3459 u32 *buf, u32 size)
3460{
3461 struct efx_ef10_filter_table *table = efx->filter_state;
3462 struct efx_filter_spec *spec;
3463 unsigned int filter_idx;
3464 s32 count = 0;
3465
3466 spin_lock_bh(&efx->filter_lock);
3467 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3468 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3469 if (spec && spec->priority == priority) {
3470 if (count == size) {
3471 count = -EMSGSIZE;
3472 break;
3473 }
3474 buf[count++] = (efx_ef10_filter_rx_match_pri(
3475 table, spec->match_flags) *
3476 HUNT_FILTER_TBL_ROWS +
3477 filter_idx);
3478 }
3479 }
3480 spin_unlock_bh(&efx->filter_lock);
3481 return count;
3482}
3483
3484#ifdef CONFIG_RFS_ACCEL
3485
3486static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3487
3488static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3489 struct efx_filter_spec *spec)
3490{
3491 struct efx_ef10_filter_table *table = efx->filter_state;
3492 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3493 struct efx_filter_spec *saved_spec;
3494 unsigned int hash, i, depth = 1;
3495 bool replacing = false;
3496 int ins_index = -1;
3497 u64 cookie;
3498 s32 rc;
3499
3500 /* Must be an RX filter without RSS and not for a multicast
3501 * destination address (RFS only works for connected sockets).
3502 * These restrictions allow us to pass only a tiny amount of
3503 * data through to the completion function.
3504 */
3505 EFX_WARN_ON_PARANOID(spec->flags !=
3506 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3507 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3508 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3509
3510 hash = efx_ef10_filter_hash(spec);
3511
3512 spin_lock_bh(&efx->filter_lock);
3513
3514 /* Find any existing filter with the same match tuple or else
3515 * a free slot to insert at. If an existing filter is busy,
3516 * we have to give up.
3517 */
3518 for (;;) {
3519 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3520 saved_spec = efx_ef10_filter_entry_spec(table, i);
3521
3522 if (!saved_spec) {
3523 if (ins_index < 0)
3524 ins_index = i;
3525 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3526 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
3527 rc = -EBUSY;
3528 goto fail_unlock;
3529 }
3530 if (spec->priority < saved_spec->priority) {
3531 rc = -EPERM;
3532 goto fail_unlock;
3533 }
3534 ins_index = i;
3535 break;
3536 }
3537
3538 /* Once we reach the maximum search depth, use the
3539 * first suitable slot or return -EBUSY if there was
3540 * none
3541 */
3542 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3543 if (ins_index < 0) {
3544 rc = -EBUSY;
3545 goto fail_unlock;
3546 }
3547 break;
3548 }
3549
3550 ++depth;
3551 }
3552
3553 /* Create a software table entry if necessary, and mark it
3554 * busy. We might yet fail to insert, but any attempt to
3555 * insert a conflicting filter while we're waiting for the
3556 * firmware must find the busy entry.
3557 */
3558 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3559 if (saved_spec) {
3560 replacing = true;
3561 } else {
3562 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3563 if (!saved_spec) {
3564 rc = -ENOMEM;
3565 goto fail_unlock;
3566 }
3567 *saved_spec = *spec;
3568 }
3569 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3570 EFX_EF10_FILTER_FLAG_BUSY);
3571
3572 spin_unlock_bh(&efx->filter_lock);
3573
3574 /* Pack up the variables needed on completion */
3575 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
3576
3577 efx_ef10_filter_push_prep(efx, spec, inbuf,
3578 table->entry[ins_index].handle, replacing);
3579 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3580 MC_CMD_FILTER_OP_OUT_LEN,
3581 efx_ef10_filter_rfs_insert_complete, cookie);
3582
3583 return ins_index;
3584
3585fail_unlock:
3586 spin_unlock_bh(&efx->filter_lock);
3587 return rc;
3588}
3589
3590static void
3591efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
3592 int rc, efx_dword_t *outbuf,
3593 size_t outlen_actual)
3594{
3595 struct efx_ef10_filter_table *table = efx->filter_state;
3596 unsigned int ins_index, dmaq_id;
3597 struct efx_filter_spec *spec;
3598 bool replacing;
3599
3600 /* Unpack the cookie */
3601 replacing = cookie >> 31;
3602 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
3603 dmaq_id = cookie & 0xffff;
3604
3605 spin_lock_bh(&efx->filter_lock);
3606 spec = efx_ef10_filter_entry_spec(table, ins_index);
3607 if (rc == 0) {
3608 table->entry[ins_index].handle =
3609 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3610 if (replacing)
3611 spec->dmaq_id = dmaq_id;
3612 } else if (!replacing) {
3613 kfree(spec);
3614 spec = NULL;
3615 }
3616 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
3617 spin_unlock_bh(&efx->filter_lock);
3618
3619 wake_up_all(&table->waitq);
3620}
3621
3622static void
3623efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3624 unsigned long filter_idx,
3625 int rc, efx_dword_t *outbuf,
3626 size_t outlen_actual);
3627
3628static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
3629 unsigned int filter_idx)
3630{
3631 struct efx_ef10_filter_table *table = efx->filter_state;
3632 struct efx_filter_spec *spec =
3633 efx_ef10_filter_entry_spec(table, filter_idx);
3634 MCDI_DECLARE_BUF(inbuf,
3635 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3636 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3637
3638 if (!spec ||
3639 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
3640 spec->priority != EFX_FILTER_PRI_HINT ||
3641 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
3642 flow_id, filter_idx))
3643 return false;
3644
3645 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3646 MC_CMD_FILTER_OP_IN_OP_REMOVE);
3647 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3648 table->entry[filter_idx].handle);
3649 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
3650 efx_ef10_filter_rfs_expire_complete, filter_idx))
3651 return false;
3652
3653 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3654 return true;
3655}
3656
3657static void
3658efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3659 unsigned long filter_idx,
3660 int rc, efx_dword_t *outbuf,
3661 size_t outlen_actual)
3662{
3663 struct efx_ef10_filter_table *table = efx->filter_state;
3664 struct efx_filter_spec *spec =
3665 efx_ef10_filter_entry_spec(table, filter_idx);
3666
3667 spin_lock_bh(&efx->filter_lock);
3668 if (rc == 0) {
3669 kfree(spec);
3670 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3671 }
3672 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3673 wake_up_all(&table->waitq);
3674 spin_unlock_bh(&efx->filter_lock);
3675}
3676
3677#endif /* CONFIG_RFS_ACCEL */
3678
3679static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
3680{
3681 int match_flags = 0;
3682
3683#define MAP_FLAG(gen_flag, mcdi_field) { \
3684 u32 old_mcdi_flags = mcdi_flags; \
3685 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3686 mcdi_field ## _LBN); \
3687 if (mcdi_flags != old_mcdi_flags) \
3688 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
3689 }
3690 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
3691 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
3692 MAP_FLAG(REM_HOST, SRC_IP);
3693 MAP_FLAG(LOC_HOST, DST_IP);
3694 MAP_FLAG(REM_MAC, SRC_MAC);
3695 MAP_FLAG(REM_PORT, SRC_PORT);
3696 MAP_FLAG(LOC_MAC, DST_MAC);
3697 MAP_FLAG(LOC_PORT, DST_PORT);
3698 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
3699 MAP_FLAG(INNER_VID, INNER_VLAN);
3700 MAP_FLAG(OUTER_VID, OUTER_VLAN);
3701 MAP_FLAG(IP_PROTO, IP_PROTO);
3702#undef MAP_FLAG
3703
3704 /* Did we map them all? */
3705 if (mcdi_flags)
3706 return -EINVAL;
3707
3708 return match_flags;
3709}
3710
3711static int efx_ef10_filter_table_probe(struct efx_nic *efx)
3712{
3713 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
3714 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
3715 unsigned int pd_match_pri, pd_match_count;
3716 struct efx_ef10_filter_table *table;
3717 size_t outlen;
3718 int rc;
3719
3720 table = kzalloc(sizeof(*table), GFP_KERNEL);
3721 if (!table)
3722 return -ENOMEM;
3723
3724 /* Find out which RX filter types are supported, and their priorities */
3725 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3726 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3727 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3728 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3729 &outlen);
3730 if (rc)
3731 goto fail;
3732 pd_match_count = MCDI_VAR_ARRAY_LEN(
3733 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3734 table->rx_match_count = 0;
3735
3736 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3737 u32 mcdi_flags =
3738 MCDI_ARRAY_DWORD(
3739 outbuf,
3740 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3741 pd_match_pri);
3742 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3743 if (rc < 0) {
3744 netif_dbg(efx, probe, efx->net_dev,
3745 "%s: fw flags %#x pri %u not supported in driver\n",
3746 __func__, mcdi_flags, pd_match_pri);
3747 } else {
3748 netif_dbg(efx, probe, efx->net_dev,
3749 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3750 __func__, mcdi_flags, pd_match_pri,
3751 rc, table->rx_match_count);
3752 table->rx_match_flags[table->rx_match_count++] = rc;
3753 }
3754 }
3755
3756 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3757 if (!table->entry) {
3758 rc = -ENOMEM;
3759 goto fail;
3760 }
3761
3762 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID;
3763 table->bcast_id = EFX_EF10_FILTER_ID_INVALID;
3764 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3765
3766 efx->filter_state = table;
3767 init_waitqueue_head(&table->waitq);
3768 return 0;
3769
3770fail:
3771 kfree(table);
3772 return rc;
3773}
3774
3775/* Caller must hold efx->filter_sem for read if race against
3776 * efx_ef10_filter_table_remove() is possible
3777 */
3778static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3779{
3780 struct efx_ef10_filter_table *table = efx->filter_state;
3781 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3782 struct efx_filter_spec *spec;
3783 unsigned int filter_idx;
3784 bool failed = false;
3785 int rc;
3786
3787 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
3788
3789 if (!nic_data->must_restore_filters)
3790 return;
3791
3792 if (!table)
3793 return;
3794
3795 spin_lock_bh(&efx->filter_lock);
3796
3797 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3798 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3799 if (!spec)
3800 continue;
3801
3802 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3803 spin_unlock_bh(&efx->filter_lock);
3804
3805 rc = efx_ef10_filter_push(efx, spec,
3806 &table->entry[filter_idx].handle,
3807 false);
3808 if (rc)
3809 failed = true;
3810
3811 spin_lock_bh(&efx->filter_lock);
3812 if (rc) {
3813 kfree(spec);
3814 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3815 } else {
3816 table->entry[filter_idx].spec &=
3817 ~EFX_EF10_FILTER_FLAG_BUSY;
3818 }
3819 }
3820
3821 spin_unlock_bh(&efx->filter_lock);
3822
3823 if (failed)
3824 netif_err(efx, hw, efx->net_dev,
3825 "unable to restore all filters\n");
3826 else
3827 nic_data->must_restore_filters = false;
3828}
3829
3830/* Caller must hold efx->filter_sem for write */
3831static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3832{
3833 struct efx_ef10_filter_table *table = efx->filter_state;
3834 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3835 struct efx_filter_spec *spec;
3836 unsigned int filter_idx;
3837 int rc;
3838
3839 efx->filter_state = NULL;
3840 if (!table)
3841 return;
3842
3843 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3844 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3845 if (!spec)
3846 continue;
3847
3848 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3849 efx_ef10_filter_is_exclusive(spec) ?
3850 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3851 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3852 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3853 table->entry[filter_idx].handle);
3854 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
3855 sizeof(inbuf), NULL, 0, NULL);
3856 if (rc)
3857 netif_info(efx, drv, efx->net_dev,
3858 "%s: filter %04x remove failed\n",
3859 __func__, filter_idx);
3860 kfree(spec);
3861 }
3862
3863 vfree(table->entry);
3864 kfree(table);
3865}
3866
3867#define EFX_EF10_FILTER_DO_MARK_OLD(id) \
3868 if (id != EFX_EF10_FILTER_ID_INVALID) { \
3869 filter_idx = efx_ef10_filter_get_unsafe_id(efx, id); \
3870 if (!table->entry[filter_idx].spec) \
3871 netif_dbg(efx, drv, efx->net_dev, \
3872 "%s: marked null spec old %04x:%04x\n", \
3873 __func__, id, filter_idx); \
3874 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;\
3875 }
3876static void efx_ef10_filter_mark_old(struct efx_nic *efx)
3877{
3878 struct efx_ef10_filter_table *table = efx->filter_state;
3879 unsigned int filter_idx, i;
3880
3881 if (!table)
3882 return;
3883
3884 /* Mark old filters that may need to be removed */
3885 spin_lock_bh(&efx->filter_lock);
3886 for (i = 0; i < table->dev_uc_count; i++)
3887 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_uc_list[i].id);
3888 for (i = 0; i < table->dev_mc_count; i++)
3889 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_mc_list[i].id);
3890 EFX_EF10_FILTER_DO_MARK_OLD(table->ucdef_id);
3891 EFX_EF10_FILTER_DO_MARK_OLD(table->bcast_id);
3892 EFX_EF10_FILTER_DO_MARK_OLD(table->mcdef_id);
3893 spin_unlock_bh(&efx->filter_lock);
3894}
3895#undef EFX_EF10_FILTER_DO_MARK_OLD
3896
3897static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx, bool *promisc)
3898{
3899 struct efx_ef10_filter_table *table = efx->filter_state;
3900 struct net_device *net_dev = efx->net_dev;
3901 struct netdev_hw_addr *uc;
3902 int addr_count;
3903 unsigned int i;
3904
3905 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID;
3906 addr_count = netdev_uc_count(net_dev);
3907 if (net_dev->flags & IFF_PROMISC)
3908 *promisc = true;
3909 table->dev_uc_count = 1 + addr_count;
3910 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
3911 i = 1;
3912 netdev_for_each_uc_addr(uc, net_dev) {
3913 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
3914 *promisc = true;
3915 break;
3916 }
3917 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
3918 table->dev_uc_list[i].id = EFX_EF10_FILTER_ID_INVALID;
3919 i++;
3920 }
3921}
3922
3923static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx, bool *promisc)
3924{
3925 struct efx_ef10_filter_table *table = efx->filter_state;
3926 struct net_device *net_dev = efx->net_dev;
3927 struct netdev_hw_addr *mc;
3928 unsigned int i, addr_count;
3929
3930 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3931 table->bcast_id = EFX_EF10_FILTER_ID_INVALID;
3932 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI))
3933 *promisc = true;
3934
3935 addr_count = netdev_mc_count(net_dev);
3936 i = 0;
3937 netdev_for_each_mc_addr(mc, net_dev) {
3938 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
3939 *promisc = true;
3940 break;
3941 }
3942 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
3943 table->dev_mc_list[i].id = EFX_EF10_FILTER_ID_INVALID;
3944 i++;
3945 }
3946
3947 table->dev_mc_count = i;
3948}
3949
3950static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
3951 bool multicast, bool rollback)
3952{
3953 struct efx_ef10_filter_table *table = efx->filter_state;
3954 struct efx_ef10_dev_addr *addr_list;
3955 enum efx_filter_flags filter_flags;
3956 struct efx_filter_spec spec;
3957 u8 baddr[ETH_ALEN];
3958 unsigned int i, j;
3959 int addr_count;
3960 int rc;
3961
3962 if (multicast) {
3963 addr_list = table->dev_mc_list;
3964 addr_count = table->dev_mc_count;
3965 } else {
3966 addr_list = table->dev_uc_list;
3967 addr_count = table->dev_uc_count;
3968 }
3969
3970 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
3971
3972 /* Insert/renew filters */
3973 for (i = 0; i < addr_count; i++) {
3974 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
3975 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3976 addr_list[i].addr);
3977 rc = efx_ef10_filter_insert(efx, &spec, true);
3978 if (rc < 0) {
3979 if (rollback) {
3980 netif_info(efx, drv, efx->net_dev,
3981 "efx_ef10_filter_insert failed rc=%d\n",
3982 rc);
3983 /* Fall back to promiscuous */
3984 for (j = 0; j < i; j++) {
3985 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID)
3986 continue;
3987 efx_ef10_filter_remove_unsafe(
3988 efx, EFX_FILTER_PRI_AUTO,
3989 addr_list[j].id);
3990 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID;
3991 }
3992 return rc;
3993 } else {
3994 /* mark as not inserted, and carry on */
3995 rc = EFX_EF10_FILTER_ID_INVALID;
3996 }
3997 }
3998 addr_list[i].id = efx_ef10_filter_get_unsafe_id(efx, rc);
3999 }
4000
4001 if (multicast && rollback) {
4002 /* Also need an Ethernet broadcast filter */
4003 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4004 eth_broadcast_addr(baddr);
4005 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, baddr);
4006 rc = efx_ef10_filter_insert(efx, &spec, true);
4007 if (rc < 0) {
4008 netif_warn(efx, drv, efx->net_dev,
4009 "Broadcast filter insert failed rc=%d\n", rc);
4010 /* Fall back to promiscuous */
4011 for (j = 0; j < i; j++) {
4012 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID)
4013 continue;
4014 efx_ef10_filter_remove_unsafe(
4015 efx, EFX_FILTER_PRI_AUTO,
4016 addr_list[j].id);
4017 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID;
4018 }
4019 return rc;
4020 } else {
4021 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc);
4022 }
4023 }
4024
4025 return 0;
4026}
4027
4028static int efx_ef10_filter_insert_def(struct efx_nic *efx, bool multicast,
4029 bool rollback)
4030{
4031 struct efx_ef10_filter_table *table = efx->filter_state;
4032 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4033 enum efx_filter_flags filter_flags;
4034 struct efx_filter_spec spec;
4035 u8 baddr[ETH_ALEN];
4036 int rc;
4037
4038 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4039
4040 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4041
4042 if (multicast)
4043 efx_filter_set_mc_def(&spec);
4044 else
4045 efx_filter_set_uc_def(&spec);
4046
4047 rc = efx_ef10_filter_insert(efx, &spec, true);
4048 if (rc < 0) {
4049 netif_printk(efx, drv, rc == -EPERM ? KERN_DEBUG : KERN_WARNING,
4050 efx->net_dev,
4051 "%scast mismatch filter insert failed rc=%d\n",
4052 multicast ? "Multi" : "Uni", rc);
4053 } else if (multicast) {
4054 table->mcdef_id = efx_ef10_filter_get_unsafe_id(efx, rc);
4055 if (!nic_data->workaround_26807) {
4056 /* Also need an Ethernet broadcast filter */
4057 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
4058 filter_flags, 0);
4059 eth_broadcast_addr(baddr);
4060 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
4061 baddr);
4062 rc = efx_ef10_filter_insert(efx, &spec, true);
4063 if (rc < 0) {
4064 netif_warn(efx, drv, efx->net_dev,
4065 "Broadcast filter insert failed rc=%d\n",
4066 rc);
4067 if (rollback) {
4068 /* Roll back the mc_def filter */
4069 efx_ef10_filter_remove_unsafe(
4070 efx, EFX_FILTER_PRI_AUTO,
4071 table->mcdef_id);
4072 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
4073 return rc;
4074 }
4075 } else {
4076 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc);
4077 }
4078 }
4079 rc = 0;
4080 } else {
4081 table->ucdef_id = rc;
4082 rc = 0;
4083 }
4084 return rc;
4085}
4086
4087/* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
4088 * flag or removes these filters, we don't need to hold the filter_lock while
4089 * scanning for these filters.
4090 */
4091static void efx_ef10_filter_remove_old(struct efx_nic *efx)
4092{
4093 struct efx_ef10_filter_table *table = efx->filter_state;
4094 int remove_failed = 0;
4095 int remove_noent = 0;
4096 int rc;
4097 int i;
4098
4099 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4100 if (ACCESS_ONCE(table->entry[i].spec) &
4101 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
4102 rc = efx_ef10_filter_remove_internal(efx,
4103 1U << EFX_FILTER_PRI_AUTO, i, true);
4104 if (rc == -ENOENT)
4105 remove_noent++;
4106 else if (rc)
4107 remove_failed++;
4108 }
4109 }
4110
4111 if (remove_failed)
4112 netif_info(efx, drv, efx->net_dev,
4113 "%s: failed to remove %d filters\n",
4114 __func__, remove_failed);
4115 if (remove_noent)
4116 netif_info(efx, drv, efx->net_dev,
4117 "%s: failed to remove %d non-existent filters\n",
4118 __func__, remove_noent);
4119}
4120
4121static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4122{
4123 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4124 u8 mac_old[ETH_ALEN];
4125 int rc, rc2;
4126
4127 /* Only reconfigure a PF-created vport */
4128 if (is_zero_ether_addr(nic_data->vport_mac))
4129 return 0;
4130
4131 efx_device_detach_sync(efx);
4132 efx_net_stop(efx->net_dev);
4133 down_write(&efx->filter_sem);
4134 efx_ef10_filter_table_remove(efx);
4135 up_write(&efx->filter_sem);
4136
4137 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4138 if (rc)
4139 goto restore_filters;
4140
4141 ether_addr_copy(mac_old, nic_data->vport_mac);
4142 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4143 nic_data->vport_mac);
4144 if (rc)
4145 goto restore_vadaptor;
4146
4147 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4148 efx->net_dev->dev_addr);
4149 if (!rc) {
4150 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4151 } else {
4152 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4153 if (rc2) {
4154 /* Failed to add original MAC, so clear vport_mac */
4155 eth_zero_addr(nic_data->vport_mac);
4156 goto reset_nic;
4157 }
4158 }
4159
4160restore_vadaptor:
4161 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4162 if (rc2)
4163 goto reset_nic;
4164restore_filters:
4165 down_write(&efx->filter_sem);
4166 rc2 = efx_ef10_filter_table_probe(efx);
4167 up_write(&efx->filter_sem);
4168 if (rc2)
4169 goto reset_nic;
4170
4171 rc2 = efx_net_open(efx->net_dev);
4172 if (rc2)
4173 goto reset_nic;
4174
4175 netif_device_attach(efx->net_dev);
4176
4177 return rc;
4178
4179reset_nic:
4180 netif_err(efx, drv, efx->net_dev,
4181 "Failed to restore when changing MAC address - scheduling reset\n");
4182 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4183
4184 return rc ? rc : rc2;
4185}
4186
4187/* Caller must hold efx->filter_sem for read if race against
4188 * efx_ef10_filter_table_remove() is possible
4189 */
4190static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
4191{
4192 struct efx_ef10_filter_table *table = efx->filter_state;
4193 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4194 struct net_device *net_dev = efx->net_dev;
4195 bool uc_promisc = false, mc_promisc = false;
4196
4197 if (!efx_dev_registered(efx))
4198 return;
4199
4200 if (!table)
4201 return;
4202
4203 efx_ef10_filter_mark_old(efx);
4204
4205 /* Copy/convert the address lists; add the primary station
4206 * address and broadcast address
4207 */
4208 netif_addr_lock_bh(net_dev);
4209 efx_ef10_filter_uc_addr_list(efx, &uc_promisc);
4210 efx_ef10_filter_mc_addr_list(efx, &mc_promisc);
4211 netif_addr_unlock_bh(net_dev);
4212
4213 /* Insert/renew unicast filters */
4214 if (uc_promisc) {
4215 efx_ef10_filter_insert_def(efx, false, false);
4216 efx_ef10_filter_insert_addr_list(efx, false, false);
4217 } else {
4218 /* If any of the filters failed to insert, fall back to
4219 * promiscuous mode - add in the uc_def filter. But keep
4220 * our individual unicast filters.
4221 */
4222 if (efx_ef10_filter_insert_addr_list(efx, false, false))
4223 efx_ef10_filter_insert_def(efx, false, false);
4224 }
4225
4226 /* Insert/renew multicast filters */
4227 /* If changing promiscuous state with cascaded multicast filters, remove
4228 * old filters first, so that packets are dropped rather than duplicated
4229 */
4230 if (nic_data->workaround_26807 && efx->mc_promisc != mc_promisc)
4231 efx_ef10_filter_remove_old(efx);
4232 if (mc_promisc) {
4233 if (nic_data->workaround_26807) {
4234 /* If we failed to insert promiscuous filters, rollback
4235 * and fall back to individual multicast filters
4236 */
4237 if (efx_ef10_filter_insert_def(efx, true, true)) {
4238 /* Changing promisc state, so remove old filters */
4239 efx_ef10_filter_remove_old(efx);
4240 efx_ef10_filter_insert_addr_list(efx, true, false);
4241 }
4242 } else {
4243 /* If we failed to insert promiscuous filters, don't
4244 * rollback. Regardless, also insert the mc_list
4245 */
4246 efx_ef10_filter_insert_def(efx, true, false);
4247 efx_ef10_filter_insert_addr_list(efx, true, false);
4248 }
4249 } else {
4250 /* If any filters failed to insert, rollback and fall back to
4251 * promiscuous mode - mc_def filter and maybe broadcast. If
4252 * that fails, roll back again and insert as many of our
4253 * individual multicast filters as we can.
4254 */
4255 if (efx_ef10_filter_insert_addr_list(efx, true, true)) {
4256 /* Changing promisc state, so remove old filters */
4257 if (nic_data->workaround_26807)
4258 efx_ef10_filter_remove_old(efx);
4259 if (efx_ef10_filter_insert_def(efx, true, true))
4260 efx_ef10_filter_insert_addr_list(efx, true, false);
4261 }
4262 }
4263
4264 efx_ef10_filter_remove_old(efx);
4265 efx->mc_promisc = mc_promisc;
4266}
4267
4268static int efx_ef10_set_mac_address(struct efx_nic *efx)
4269{
4270 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
4271 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4272 bool was_enabled = efx->port_enabled;
4273 int rc;
4274
4275 efx_device_detach_sync(efx);
4276 efx_net_stop(efx->net_dev);
4277 down_write(&efx->filter_sem);
4278 efx_ef10_filter_table_remove(efx);
4279
4280 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
4281 efx->net_dev->dev_addr);
4282 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
4283 nic_data->vport_id);
4284 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
4285 sizeof(inbuf), NULL, 0, NULL);
4286
4287 efx_ef10_filter_table_probe(efx);
4288 up_write(&efx->filter_sem);
4289 if (was_enabled)
4290 efx_net_open(efx->net_dev);
4291 netif_device_attach(efx->net_dev);
4292
4293#ifdef CONFIG_SFC_SRIOV
4294 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
4295 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
4296
4297 if (rc == -EPERM) {
4298 struct efx_nic *efx_pf;
4299
4300 /* Switch to PF and change MAC address on vport */
4301 efx_pf = pci_get_drvdata(pci_dev_pf);
4302
4303 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
4304 nic_data->vf_index,
4305 efx->net_dev->dev_addr);
4306 } else if (!rc) {
4307 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
4308 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
4309 unsigned int i;
4310
4311 /* MAC address successfully changed by VF (with MAC
4312 * spoofing) so update the parent PF if possible.
4313 */
4314 for (i = 0; i < efx_pf->vf_count; ++i) {
4315 struct ef10_vf *vf = nic_data->vf + i;
4316
4317 if (vf->efx == efx) {
4318 ether_addr_copy(vf->mac,
4319 efx->net_dev->dev_addr);
4320 return 0;
4321 }
4322 }
4323 }
4324 } else
4325#endif
4326 if (rc == -EPERM) {
4327 netif_err(efx, drv, efx->net_dev,
4328 "Cannot change MAC address; use sfboot to enable"
4329 " mac-spoofing on this interface\n");
4330 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
4331 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4332 * fall-back to the method of changing the MAC address on the
4333 * vport. This only applies to PFs because such versions of
4334 * MCFW do not support VFs.
4335 */
4336 rc = efx_ef10_vport_set_mac_address(efx);
4337 } else {
4338 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
4339 sizeof(inbuf), NULL, 0, rc);
4340 }
4341
4342 return rc;
4343}
4344
4345static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
4346{
4347 efx_ef10_filter_sync_rx_mode(efx);
4348
4349 return efx_mcdi_set_mac(efx);
4350}
4351
4352static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
4353{
4354 efx_ef10_filter_sync_rx_mode(efx);
4355
4356 return 0;
4357}
4358
4359static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
4360{
4361 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
4362
4363 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
4364 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
4365 NULL, 0, NULL);
4366}
4367
4368/* MC BISTs follow a different poll mechanism to phy BISTs.
4369 * The BIST is done in the poll handler on the MC, and the MCDI command
4370 * will block until the BIST is done.
4371 */
4372static int efx_ef10_poll_bist(struct efx_nic *efx)
4373{
4374 int rc;
4375 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
4376 size_t outlen;
4377 u32 result;
4378
4379 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
4380 outbuf, sizeof(outbuf), &outlen);
4381 if (rc != 0)
4382 return rc;
4383
4384 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
4385 return -EIO;
4386
4387 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
4388 switch (result) {
4389 case MC_CMD_POLL_BIST_PASSED:
4390 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
4391 return 0;
4392 case MC_CMD_POLL_BIST_TIMEOUT:
4393 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
4394 return -EIO;
4395 case MC_CMD_POLL_BIST_FAILED:
4396 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
4397 return -EIO;
4398 default:
4399 netif_err(efx, hw, efx->net_dev,
4400 "BIST returned unknown result %u", result);
4401 return -EIO;
4402 }
4403}
4404
4405static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
4406{
4407 int rc;
4408
4409 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
4410
4411 rc = efx_ef10_start_bist(efx, bist_type);
4412 if (rc != 0)
4413 return rc;
4414
4415 return efx_ef10_poll_bist(efx);
4416}
4417
4418static int
4419efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
4420{
4421 int rc, rc2;
4422
4423 efx_reset_down(efx, RESET_TYPE_WORLD);
4424
4425 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
4426 NULL, 0, NULL, 0, NULL);
4427 if (rc != 0)
4428 goto out;
4429
4430 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
4431 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
4432
4433 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
4434
4435out:
4436 if (rc == -EPERM)
4437 rc = 0;
4438 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
4439 return rc ? rc : rc2;
4440}
4441
4442#ifdef CONFIG_SFC_MTD
4443
4444struct efx_ef10_nvram_type_info {
4445 u16 type, type_mask;
4446 u8 port;
4447 const char *name;
4448};
4449
4450static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
4451 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
4452 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
4453 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
4454 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
4455 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
4456 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
4457 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
4458 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
4459 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
4460 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
4461 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
4462};
4463
4464static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
4465 struct efx_mcdi_mtd_partition *part,
4466 unsigned int type)
4467{
4468 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
4469 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
4470 const struct efx_ef10_nvram_type_info *info;
4471 size_t size, erase_size, outlen;
4472 bool protected;
4473 int rc;
4474
4475 for (info = efx_ef10_nvram_types; ; info++) {
4476 if (info ==
4477 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
4478 return -ENODEV;
4479 if ((type & ~info->type_mask) == info->type)
4480 break;
4481 }
4482 if (info->port != efx_port_num(efx))
4483 return -ENODEV;
4484
4485 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
4486 if (rc)
4487 return rc;
4488 if (protected)
4489 return -ENODEV; /* hide it */
4490
4491 part->nvram_type = type;
4492
4493 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
4494 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
4495 outbuf, sizeof(outbuf), &outlen);
4496 if (rc)
4497 return rc;
4498 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
4499 return -EIO;
4500 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
4501 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
4502 part->fw_subtype = MCDI_DWORD(outbuf,
4503 NVRAM_METADATA_OUT_SUBTYPE);
4504
4505 part->common.dev_type_name = "EF10 NVRAM manager";
4506 part->common.type_name = info->name;
4507
4508 part->common.mtd.type = MTD_NORFLASH;
4509 part->common.mtd.flags = MTD_CAP_NORFLASH;
4510 part->common.mtd.size = size;
4511 part->common.mtd.erasesize = erase_size;
4512
4513 return 0;
4514}
4515
4516static int efx_ef10_mtd_probe(struct efx_nic *efx)
4517{
4518 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
4519 struct efx_mcdi_mtd_partition *parts;
4520 size_t outlen, n_parts_total, i, n_parts;
4521 unsigned int type;
4522 int rc;
4523
4524 ASSERT_RTNL();
4525
4526 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
4527 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
4528 outbuf, sizeof(outbuf), &outlen);
4529 if (rc)
4530 return rc;
4531 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
4532 return -EIO;
4533
4534 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
4535 if (n_parts_total >
4536 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
4537 return -EIO;
4538
4539 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
4540 if (!parts)
4541 return -ENOMEM;
4542
4543 n_parts = 0;
4544 for (i = 0; i < n_parts_total; i++) {
4545 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
4546 i);
4547 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
4548 if (rc == 0)
4549 n_parts++;
4550 else if (rc != -ENODEV)
4551 goto fail;
4552 }
4553
4554 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
4555fail:
4556 if (rc)
4557 kfree(parts);
4558 return rc;
4559}
4560
4561#endif /* CONFIG_SFC_MTD */
4562
4563static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
4564{
4565 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
4566}
4567
4568static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
4569 u32 host_time) {}
4570
4571static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
4572 bool temp)
4573{
4574 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
4575 int rc;
4576
4577 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
4578 channel->sync_events_state == SYNC_EVENTS_VALID ||
4579 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
4580 return 0;
4581 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
4582
4583 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
4584 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4585 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
4586 channel->channel);
4587
4588 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4589 inbuf, sizeof(inbuf), NULL, 0, NULL);
4590
4591 if (rc != 0)
4592 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4593 SYNC_EVENTS_DISABLED;
4594
4595 return rc;
4596}
4597
4598static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
4599 bool temp)
4600{
4601 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
4602 int rc;
4603
4604 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
4605 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
4606 return 0;
4607 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
4608 channel->sync_events_state = SYNC_EVENTS_DISABLED;
4609 return 0;
4610 }
4611 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4612 SYNC_EVENTS_DISABLED;
4613
4614 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
4615 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4616 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
4617 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
4618 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
4619 channel->channel);
4620
4621 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4622 inbuf, sizeof(inbuf), NULL, 0, NULL);
4623
4624 return rc;
4625}
4626
4627static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
4628 bool temp)
4629{
4630 int (*set)(struct efx_channel *channel, bool temp);
4631 struct efx_channel *channel;
4632
4633 set = en ?
4634 efx_ef10_rx_enable_timestamping :
4635 efx_ef10_rx_disable_timestamping;
4636
4637 efx_for_each_channel(channel, efx) {
4638 int rc = set(channel, temp);
4639 if (en && rc != 0) {
4640 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
4641 return rc;
4642 }
4643 }
4644
4645 return 0;
4646}
4647
4648static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
4649 struct hwtstamp_config *init)
4650{
4651 return -EOPNOTSUPP;
4652}
4653
4654static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
4655 struct hwtstamp_config *init)
4656{
4657 int rc;
4658
4659 switch (init->rx_filter) {
4660 case HWTSTAMP_FILTER_NONE:
4661 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
4662 /* if TX timestamping is still requested then leave PTP on */
4663 return efx_ptp_change_mode(efx,
4664 init->tx_type != HWTSTAMP_TX_OFF, 0);
4665 case HWTSTAMP_FILTER_ALL:
4666 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4667 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4668 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4669 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4670 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4671 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4672 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4673 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4674 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4675 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4676 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4677 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4678 init->rx_filter = HWTSTAMP_FILTER_ALL;
4679 rc = efx_ptp_change_mode(efx, true, 0);
4680 if (!rc)
4681 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
4682 if (rc)
4683 efx_ptp_change_mode(efx, false, 0);
4684 return rc;
4685 default:
4686 return -ERANGE;
4687 }
4688}
4689
4690const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
4691 .is_vf = true,
4692 .mem_bar = EFX_MEM_VF_BAR,
4693 .mem_map_size = efx_ef10_mem_map_size,
4694 .probe = efx_ef10_probe_vf,
4695 .remove = efx_ef10_remove,
4696 .dimension_resources = efx_ef10_dimension_resources,
4697 .init = efx_ef10_init_nic,
4698 .fini = efx_port_dummy_op_void,
4699 .map_reset_reason = efx_ef10_map_reset_reason,
4700 .map_reset_flags = efx_ef10_map_reset_flags,
4701 .reset = efx_ef10_reset,
4702 .probe_port = efx_mcdi_port_probe,
4703 .remove_port = efx_mcdi_port_remove,
4704 .fini_dmaq = efx_ef10_fini_dmaq,
4705 .prepare_flr = efx_ef10_prepare_flr,
4706 .finish_flr = efx_port_dummy_op_void,
4707 .describe_stats = efx_ef10_describe_stats,
4708 .update_stats = efx_ef10_update_stats_vf,
4709 .start_stats = efx_port_dummy_op_void,
4710 .pull_stats = efx_port_dummy_op_void,
4711 .stop_stats = efx_port_dummy_op_void,
4712 .set_id_led = efx_mcdi_set_id_led,
4713 .push_irq_moderation = efx_ef10_push_irq_moderation,
4714 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
4715 .check_mac_fault = efx_mcdi_mac_check_fault,
4716 .reconfigure_port = efx_mcdi_port_reconfigure,
4717 .get_wol = efx_ef10_get_wol_vf,
4718 .set_wol = efx_ef10_set_wol_vf,
4719 .resume_wol = efx_port_dummy_op_void,
4720 .mcdi_request = efx_ef10_mcdi_request,
4721 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4722 .mcdi_read_response = efx_ef10_mcdi_read_response,
4723 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4724 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
4725 .irq_enable_master = efx_port_dummy_op_void,
4726 .irq_test_generate = efx_ef10_irq_test_generate,
4727 .irq_disable_non_ev = efx_port_dummy_op_void,
4728 .irq_handle_msi = efx_ef10_msi_interrupt,
4729 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4730 .tx_probe = efx_ef10_tx_probe,
4731 .tx_init = efx_ef10_tx_init,
4732 .tx_remove = efx_ef10_tx_remove,
4733 .tx_write = efx_ef10_tx_write,
4734 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
4735 .rx_probe = efx_ef10_rx_probe,
4736 .rx_init = efx_ef10_rx_init,
4737 .rx_remove = efx_ef10_rx_remove,
4738 .rx_write = efx_ef10_rx_write,
4739 .rx_defer_refill = efx_ef10_rx_defer_refill,
4740 .ev_probe = efx_ef10_ev_probe,
4741 .ev_init = efx_ef10_ev_init,
4742 .ev_fini = efx_ef10_ev_fini,
4743 .ev_remove = efx_ef10_ev_remove,
4744 .ev_process = efx_ef10_ev_process,
4745 .ev_read_ack = efx_ef10_ev_read_ack,
4746 .ev_test_generate = efx_ef10_ev_test_generate,
4747 .filter_table_probe = efx_ef10_filter_table_probe,
4748 .filter_table_restore = efx_ef10_filter_table_restore,
4749 .filter_table_remove = efx_ef10_filter_table_remove,
4750 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4751 .filter_insert = efx_ef10_filter_insert,
4752 .filter_remove_safe = efx_ef10_filter_remove_safe,
4753 .filter_get_safe = efx_ef10_filter_get_safe,
4754 .filter_clear_rx = efx_ef10_filter_clear_rx,
4755 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4756 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4757 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4758#ifdef CONFIG_RFS_ACCEL
4759 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4760 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4761#endif
4762#ifdef CONFIG_SFC_MTD
4763 .mtd_probe = efx_port_dummy_op_int,
4764#endif
4765 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
4766 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4767#ifdef CONFIG_SFC_SRIOV
4768 .vswitching_probe = efx_ef10_vswitching_probe_vf,
4769 .vswitching_restore = efx_ef10_vswitching_restore_vf,
4770 .vswitching_remove = efx_ef10_vswitching_remove_vf,
4771 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
4772#endif
4773 .get_mac_address = efx_ef10_get_mac_address_vf,
4774 .set_mac_address = efx_ef10_set_mac_address,
4775
4776 .revision = EFX_REV_HUNT_A0,
4777 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4778 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4779 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4780 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4781 .can_rx_scatter = true,
4782 .always_rx_scatter = true,
4783 .max_interrupt_mode = EFX_INT_MODE_MSIX,
4784 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4785 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4786 NETIF_F_RXHASH | NETIF_F_NTUPLE),
4787 .mcdi_max_ver = 2,
4788 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4789 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4790 1 << HWTSTAMP_FILTER_ALL,
4791};
4792
4793const struct efx_nic_type efx_hunt_a0_nic_type = {
4794 .is_vf = false,
4795 .mem_bar = EFX_MEM_BAR,
4796 .mem_map_size = efx_ef10_mem_map_size,
4797 .probe = efx_ef10_probe_pf,
4798 .remove = efx_ef10_remove,
4799 .dimension_resources = efx_ef10_dimension_resources,
4800 .init = efx_ef10_init_nic,
4801 .fini = efx_port_dummy_op_void,
4802 .map_reset_reason = efx_ef10_map_reset_reason,
4803 .map_reset_flags = efx_ef10_map_reset_flags,
4804 .reset = efx_ef10_reset,
4805 .probe_port = efx_mcdi_port_probe,
4806 .remove_port = efx_mcdi_port_remove,
4807 .fini_dmaq = efx_ef10_fini_dmaq,
4808 .prepare_flr = efx_ef10_prepare_flr,
4809 .finish_flr = efx_port_dummy_op_void,
4810 .describe_stats = efx_ef10_describe_stats,
4811 .update_stats = efx_ef10_update_stats_pf,
4812 .start_stats = efx_mcdi_mac_start_stats,
4813 .pull_stats = efx_mcdi_mac_pull_stats,
4814 .stop_stats = efx_mcdi_mac_stop_stats,
4815 .set_id_led = efx_mcdi_set_id_led,
4816 .push_irq_moderation = efx_ef10_push_irq_moderation,
4817 .reconfigure_mac = efx_ef10_mac_reconfigure,
4818 .check_mac_fault = efx_mcdi_mac_check_fault,
4819 .reconfigure_port = efx_mcdi_port_reconfigure,
4820 .get_wol = efx_ef10_get_wol,
4821 .set_wol = efx_ef10_set_wol,
4822 .resume_wol = efx_port_dummy_op_void,
4823 .test_chip = efx_ef10_test_chip,
4824 .test_nvram = efx_mcdi_nvram_test_all,
4825 .mcdi_request = efx_ef10_mcdi_request,
4826 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4827 .mcdi_read_response = efx_ef10_mcdi_read_response,
4828 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4829 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
4830 .irq_enable_master = efx_port_dummy_op_void,
4831 .irq_test_generate = efx_ef10_irq_test_generate,
4832 .irq_disable_non_ev = efx_port_dummy_op_void,
4833 .irq_handle_msi = efx_ef10_msi_interrupt,
4834 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4835 .tx_probe = efx_ef10_tx_probe,
4836 .tx_init = efx_ef10_tx_init,
4837 .tx_remove = efx_ef10_tx_remove,
4838 .tx_write = efx_ef10_tx_write,
4839 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
4840 .rx_probe = efx_ef10_rx_probe,
4841 .rx_init = efx_ef10_rx_init,
4842 .rx_remove = efx_ef10_rx_remove,
4843 .rx_write = efx_ef10_rx_write,
4844 .rx_defer_refill = efx_ef10_rx_defer_refill,
4845 .ev_probe = efx_ef10_ev_probe,
4846 .ev_init = efx_ef10_ev_init,
4847 .ev_fini = efx_ef10_ev_fini,
4848 .ev_remove = efx_ef10_ev_remove,
4849 .ev_process = efx_ef10_ev_process,
4850 .ev_read_ack = efx_ef10_ev_read_ack,
4851 .ev_test_generate = efx_ef10_ev_test_generate,
4852 .filter_table_probe = efx_ef10_filter_table_probe,
4853 .filter_table_restore = efx_ef10_filter_table_restore,
4854 .filter_table_remove = efx_ef10_filter_table_remove,
4855 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4856 .filter_insert = efx_ef10_filter_insert,
4857 .filter_remove_safe = efx_ef10_filter_remove_safe,
4858 .filter_get_safe = efx_ef10_filter_get_safe,
4859 .filter_clear_rx = efx_ef10_filter_clear_rx,
4860 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4861 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4862 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4863#ifdef CONFIG_RFS_ACCEL
4864 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4865 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4866#endif
4867#ifdef CONFIG_SFC_MTD
4868 .mtd_probe = efx_ef10_mtd_probe,
4869 .mtd_rename = efx_mcdi_mtd_rename,
4870 .mtd_read = efx_mcdi_mtd_read,
4871 .mtd_erase = efx_mcdi_mtd_erase,
4872 .mtd_write = efx_mcdi_mtd_write,
4873 .mtd_sync = efx_mcdi_mtd_sync,
4874#endif
4875 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
4876 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
4877 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
4878#ifdef CONFIG_SFC_SRIOV
4879 .sriov_configure = efx_ef10_sriov_configure,
4880 .sriov_init = efx_ef10_sriov_init,
4881 .sriov_fini = efx_ef10_sriov_fini,
4882 .sriov_wanted = efx_ef10_sriov_wanted,
4883 .sriov_reset = efx_ef10_sriov_reset,
4884 .sriov_flr = efx_ef10_sriov_flr,
4885 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
4886 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
4887 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
4888 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4889 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
4890 .vswitching_probe = efx_ef10_vswitching_probe_pf,
4891 .vswitching_restore = efx_ef10_vswitching_restore_pf,
4892 .vswitching_remove = efx_ef10_vswitching_remove_pf,
4893#endif
4894 .get_mac_address = efx_ef10_get_mac_address_pf,
4895 .set_mac_address = efx_ef10_set_mac_address,
4896
4897 .revision = EFX_REV_HUNT_A0,
4898 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4899 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4900 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4901 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4902 .can_rx_scatter = true,
4903 .always_rx_scatter = true,
4904 .max_interrupt_mode = EFX_INT_MODE_MSIX,
4905 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4906 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4907 NETIF_F_RXHASH | NETIF_F_NTUPLE),
4908 .mcdi_max_ver = 2,
4909 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4910 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4911 1 << HWTSTAMP_FILTER_ALL,
4912};