1/*
   2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   3 *
   4 * This software is licensed under the terms of the GNU General Public
   5 * License version 2, as published by the Free Software Foundation, and
   6 * may be copied, distributed, and modified under those terms.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 */
  13
  14#include <linux/kernel.h>
  15#include <linux/bitops.h>
  16#include <linux/err.h>
  17#include <linux/platform_device.h>
  18#include <linux/module.h>
  19#include <linux/of.h>
  20#include <linux/of_device.h>
  21#include <linux/clk-provider.h>
  22#include <linux/regmap.h>
  23#include <linux/reset-controller.h>
  24
  25#include <dt-bindings/clock/qcom,gcc-msm8974.h>
  26#include <dt-bindings/reset/qcom,gcc-msm8974.h>
  27
 
  28#include "clk-regmap.h"
  29#include "clk-pll.h"
  30#include "clk-rcg.h"
  31#include "clk-branch.h"
  32#include "reset.h"
 
  33
  34#define P_XO	0
  35#define P_GPLL0	1
  36#define P_GPLL1	1
 
 
 
 
 
 
 
 
 
 
 
 
 
  37
  38static const u8 gcc_xo_gpll0_map[] = {
  39	[P_XO]		= 0,
  40	[P_GPLL0]	= 1,
 
  41};
  42
  43static const char *gcc_xo_gpll0[] = {
  44	"xo",
  45	"gpll0_vote",
 
  46};
  47
  48#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
  49
  50static struct clk_pll gpll0 = {
  51	.l_reg = 0x0004,
  52	.m_reg = 0x0008,
  53	.n_reg = 0x000c,
  54	.config_reg = 0x0014,
  55	.mode_reg = 0x0000,
  56	.status_reg = 0x001c,
  57	.status_bit = 17,
  58	.clkr.hw.init = &(struct clk_init_data){
  59		.name = "gpll0",
  60		.parent_names = (const char *[]){ "xo" },
  61		.num_parents = 1,
  62		.ops = &clk_pll_ops,
  63	},
  64};
  65
  66static struct clk_regmap gpll0_vote = {
  67	.enable_reg = 0x1480,
  68	.enable_mask = BIT(0),
  69	.hw.init = &(struct clk_init_data){
  70		.name = "gpll0_vote",
  71		.parent_names = (const char *[]){ "gpll0" },
  72		.num_parents = 1,
  73		.ops = &clk_pll_vote_ops,
  74	},
  75};
  76
  77static struct clk_rcg2 config_noc_clk_src = {
  78	.cmd_rcgr = 0x0150,
  79	.hid_width = 5,
  80	.parent_map = gcc_xo_gpll0_map,
  81	.clkr.hw.init = &(struct clk_init_data){
  82		.name = "config_noc_clk_src",
  83		.parent_names = gcc_xo_gpll0,
  84		.num_parents = 2,
  85		.ops = &clk_rcg2_ops,
  86	},
  87};
  88
  89static struct clk_rcg2 periph_noc_clk_src = {
  90	.cmd_rcgr = 0x0190,
  91	.hid_width = 5,
  92	.parent_map = gcc_xo_gpll0_map,
  93	.clkr.hw.init = &(struct clk_init_data){
  94		.name = "periph_noc_clk_src",
  95		.parent_names = gcc_xo_gpll0,
  96		.num_parents = 2,
  97		.ops = &clk_rcg2_ops,
  98	},
  99};
 100
 101static struct clk_rcg2 system_noc_clk_src = {
 102	.cmd_rcgr = 0x0120,
 103	.hid_width = 5,
 104	.parent_map = gcc_xo_gpll0_map,
 105	.clkr.hw.init = &(struct clk_init_data){
 106		.name = "system_noc_clk_src",
 107		.parent_names = gcc_xo_gpll0,
 108		.num_parents = 2,
 109		.ops = &clk_rcg2_ops,
 110	},
 111};
 112
 113static struct clk_pll gpll1 = {
 114	.l_reg = 0x0044,
 115	.m_reg = 0x0048,
 116	.n_reg = 0x004c,
 117	.config_reg = 0x0054,
 118	.mode_reg = 0x0040,
 119	.status_reg = 0x005c,
 120	.status_bit = 17,
 121	.clkr.hw.init = &(struct clk_init_data){
 122		.name = "gpll1",
 123		.parent_names = (const char *[]){ "xo" },
 124		.num_parents = 1,
 125		.ops = &clk_pll_ops,
 126	},
 127};
 128
 129static struct clk_regmap gpll1_vote = {
 130	.enable_reg = 0x1480,
 131	.enable_mask = BIT(1),
 132	.hw.init = &(struct clk_init_data){
 133		.name = "gpll1_vote",
 134		.parent_names = (const char *[]){ "gpll1" },
 135		.num_parents = 1,
 136		.ops = &clk_pll_vote_ops,
 137	},
 138};
 139
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 140static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
 141	F(125000000, P_GPLL0, 1, 5, 24),
 142	{ }
 143};
 144
 145static struct clk_rcg2 usb30_master_clk_src = {
 146	.cmd_rcgr = 0x03d4,
 147	.mnd_width = 8,
 148	.hid_width = 5,
 149	.parent_map = gcc_xo_gpll0_map,
 150	.freq_tbl = ftbl_gcc_usb30_master_clk,
 151	.clkr.hw.init = &(struct clk_init_data){
 152		.name = "usb30_master_clk_src",
 153		.parent_names = gcc_xo_gpll0,
 154		.num_parents = 2,
 155		.ops = &clk_rcg2_ops,
 156	},
 157};
 158
 159static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
 160	F(19200000, P_XO, 1, 0, 0),
 161	F(37500000, P_GPLL0, 16, 0, 0),
 162	F(50000000, P_GPLL0, 12, 0, 0),
 163	{ }
 164};
 165
 166static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 167	.cmd_rcgr = 0x0660,
 168	.hid_width = 5,
 169	.parent_map = gcc_xo_gpll0_map,
 170	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 171	.clkr.hw.init = &(struct clk_init_data){
 172		.name = "blsp1_qup1_i2c_apps_clk_src",
 173		.parent_names = gcc_xo_gpll0,
 174		.num_parents = 2,
 175		.ops = &clk_rcg2_ops,
 176	},
 177};
 178
 179static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = {
 180	F(960000, P_XO, 10, 1, 2),
 181	F(4800000, P_XO, 4, 0, 0),
 182	F(9600000, P_XO, 2, 0, 0),
 183	F(15000000, P_GPLL0, 10, 1, 4),
 184	F(19200000, P_XO, 1, 0, 0),
 185	F(25000000, P_GPLL0, 12, 1, 2),
 186	F(50000000, P_GPLL0, 12, 0, 0),
 187	{ }
 188};
 189
 190static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 191	.cmd_rcgr = 0x064c,
 192	.mnd_width = 8,
 193	.hid_width = 5,
 194	.parent_map = gcc_xo_gpll0_map,
 195	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 196	.clkr.hw.init = &(struct clk_init_data){
 197		.name = "blsp1_qup1_spi_apps_clk_src",
 198		.parent_names = gcc_xo_gpll0,
 199		.num_parents = 2,
 200		.ops = &clk_rcg2_ops,
 201	},
 202};
 203
 204static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 205	.cmd_rcgr = 0x06e0,
 206	.hid_width = 5,
 207	.parent_map = gcc_xo_gpll0_map,
 208	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 209	.clkr.hw.init = &(struct clk_init_data){
 210		.name = "blsp1_qup2_i2c_apps_clk_src",
 211		.parent_names = gcc_xo_gpll0,
 212		.num_parents = 2,
 213		.ops = &clk_rcg2_ops,
 214	},
 215};
 216
 217static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 218	.cmd_rcgr = 0x06cc,
 219	.mnd_width = 8,
 220	.hid_width = 5,
 221	.parent_map = gcc_xo_gpll0_map,
 222	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 223	.clkr.hw.init = &(struct clk_init_data){
 224		.name = "blsp1_qup2_spi_apps_clk_src",
 225		.parent_names = gcc_xo_gpll0,
 226		.num_parents = 2,
 227		.ops = &clk_rcg2_ops,
 228	},
 229};
 230
 231static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 232	.cmd_rcgr = 0x0760,
 233	.hid_width = 5,
 234	.parent_map = gcc_xo_gpll0_map,
 235	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 236	.clkr.hw.init = &(struct clk_init_data){
 237		.name = "blsp1_qup3_i2c_apps_clk_src",
 238		.parent_names = gcc_xo_gpll0,
 239		.num_parents = 2,
 240		.ops = &clk_rcg2_ops,
 241	},
 242};
 243
 244static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 245	.cmd_rcgr = 0x074c,
 246	.mnd_width = 8,
 247	.hid_width = 5,
 248	.parent_map = gcc_xo_gpll0_map,
 249	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 250	.clkr.hw.init = &(struct clk_init_data){
 251		.name = "blsp1_qup3_spi_apps_clk_src",
 252		.parent_names = gcc_xo_gpll0,
 253		.num_parents = 2,
 254		.ops = &clk_rcg2_ops,
 255	},
 256};
 257
 258static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 259	.cmd_rcgr = 0x07e0,
 260	.hid_width = 5,
 261	.parent_map = gcc_xo_gpll0_map,
 262	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 263	.clkr.hw.init = &(struct clk_init_data){
 264		.name = "blsp1_qup4_i2c_apps_clk_src",
 265		.parent_names = gcc_xo_gpll0,
 266		.num_parents = 2,
 267		.ops = &clk_rcg2_ops,
 268	},
 269};
 270
 271static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 272	.cmd_rcgr = 0x07cc,
 273	.mnd_width = 8,
 274	.hid_width = 5,
 275	.parent_map = gcc_xo_gpll0_map,
 276	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 277	.clkr.hw.init = &(struct clk_init_data){
 278		.name = "blsp1_qup4_spi_apps_clk_src",
 279		.parent_names = gcc_xo_gpll0,
 280		.num_parents = 2,
 281		.ops = &clk_rcg2_ops,
 282	},
 283};
 284
 285static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 286	.cmd_rcgr = 0x0860,
 287	.hid_width = 5,
 288	.parent_map = gcc_xo_gpll0_map,
 289	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 290	.clkr.hw.init = &(struct clk_init_data){
 291		.name = "blsp1_qup5_i2c_apps_clk_src",
 292		.parent_names = gcc_xo_gpll0,
 293		.num_parents = 2,
 294		.ops = &clk_rcg2_ops,
 295	},
 296};
 297
 298static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 299	.cmd_rcgr = 0x084c,
 300	.mnd_width = 8,
 301	.hid_width = 5,
 302	.parent_map = gcc_xo_gpll0_map,
 303	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 304	.clkr.hw.init = &(struct clk_init_data){
 305		.name = "blsp1_qup5_spi_apps_clk_src",
 306		.parent_names = gcc_xo_gpll0,
 307		.num_parents = 2,
 308		.ops = &clk_rcg2_ops,
 309	},
 310};
 311
 312static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 313	.cmd_rcgr = 0x08e0,
 314	.hid_width = 5,
 315	.parent_map = gcc_xo_gpll0_map,
 316	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 317	.clkr.hw.init = &(struct clk_init_data){
 318		.name = "blsp1_qup6_i2c_apps_clk_src",
 319		.parent_names = gcc_xo_gpll0,
 320		.num_parents = 2,
 321		.ops = &clk_rcg2_ops,
 322	},
 323};
 324
 325static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 326	.cmd_rcgr = 0x08cc,
 327	.mnd_width = 8,
 328	.hid_width = 5,
 329	.parent_map = gcc_xo_gpll0_map,
 330	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 331	.clkr.hw.init = &(struct clk_init_data){
 332		.name = "blsp1_qup6_spi_apps_clk_src",
 333		.parent_names = gcc_xo_gpll0,
 334		.num_parents = 2,
 335		.ops = &clk_rcg2_ops,
 336	},
 337};
 338
 339static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = {
 340	F(3686400, P_GPLL0, 1, 96, 15625),
 341	F(7372800, P_GPLL0, 1, 192, 15625),
 342	F(14745600, P_GPLL0, 1, 384, 15625),
 343	F(16000000, P_GPLL0, 5, 2, 15),
 344	F(19200000, P_XO, 1, 0, 0),
 345	F(24000000, P_GPLL0, 5, 1, 5),
 346	F(32000000, P_GPLL0, 1, 4, 75),
 347	F(40000000, P_GPLL0, 15, 0, 0),
 348	F(46400000, P_GPLL0, 1, 29, 375),
 349	F(48000000, P_GPLL0, 12.5, 0, 0),
 350	F(51200000, P_GPLL0, 1, 32, 375),
 351	F(56000000, P_GPLL0, 1, 7, 75),
 352	F(58982400, P_GPLL0, 1, 1536, 15625),
 353	F(60000000, P_GPLL0, 10, 0, 0),
 354	F(63160000, P_GPLL0, 9.5, 0, 0),
 355	{ }
 356};
 357
 358static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 359	.cmd_rcgr = 0x068c,
 360	.mnd_width = 16,
 361	.hid_width = 5,
 362	.parent_map = gcc_xo_gpll0_map,
 363	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 364	.clkr.hw.init = &(struct clk_init_data){
 365		.name = "blsp1_uart1_apps_clk_src",
 366		.parent_names = gcc_xo_gpll0,
 367		.num_parents = 2,
 368		.ops = &clk_rcg2_ops,
 369	},
 370};
 371
 372static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 373	.cmd_rcgr = 0x070c,
 374	.mnd_width = 16,
 375	.hid_width = 5,
 376	.parent_map = gcc_xo_gpll0_map,
 377	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 378	.clkr.hw.init = &(struct clk_init_data){
 379		.name = "blsp1_uart2_apps_clk_src",
 380		.parent_names = gcc_xo_gpll0,
 381		.num_parents = 2,
 382		.ops = &clk_rcg2_ops,
 383	},
 384};
 385
 386static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 387	.cmd_rcgr = 0x078c,
 388	.mnd_width = 16,
 389	.hid_width = 5,
 390	.parent_map = gcc_xo_gpll0_map,
 391	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 392	.clkr.hw.init = &(struct clk_init_data){
 393		.name = "blsp1_uart3_apps_clk_src",
 394		.parent_names = gcc_xo_gpll0,
 395		.num_parents = 2,
 396		.ops = &clk_rcg2_ops,
 397	},
 398};
 399
 400static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 401	.cmd_rcgr = 0x080c,
 402	.mnd_width = 16,
 403	.hid_width = 5,
 404	.parent_map = gcc_xo_gpll0_map,
 405	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 406	.clkr.hw.init = &(struct clk_init_data){
 407		.name = "blsp1_uart4_apps_clk_src",
 408		.parent_names = gcc_xo_gpll0,
 409		.num_parents = 2,
 410		.ops = &clk_rcg2_ops,
 411	},
 412};
 413
 414static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 415	.cmd_rcgr = 0x088c,
 416	.mnd_width = 16,
 417	.hid_width = 5,
 418	.parent_map = gcc_xo_gpll0_map,
 419	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 420	.clkr.hw.init = &(struct clk_init_data){
 421		.name = "blsp1_uart5_apps_clk_src",
 422		.parent_names = gcc_xo_gpll0,
 423		.num_parents = 2,
 424		.ops = &clk_rcg2_ops,
 425	},
 426};
 427
 428static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 429	.cmd_rcgr = 0x090c,
 430	.mnd_width = 16,
 431	.hid_width = 5,
 432	.parent_map = gcc_xo_gpll0_map,
 433	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 434	.clkr.hw.init = &(struct clk_init_data){
 435		.name = "blsp1_uart6_apps_clk_src",
 436		.parent_names = gcc_xo_gpll0,
 437		.num_parents = 2,
 438		.ops = &clk_rcg2_ops,
 439	},
 440};
 441
 442static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 443	.cmd_rcgr = 0x09a0,
 444	.hid_width = 5,
 445	.parent_map = gcc_xo_gpll0_map,
 446	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 447	.clkr.hw.init = &(struct clk_init_data){
 448		.name = "blsp2_qup1_i2c_apps_clk_src",
 449		.parent_names = gcc_xo_gpll0,
 450		.num_parents = 2,
 451		.ops = &clk_rcg2_ops,
 452	},
 453};
 454
 455static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 456	.cmd_rcgr = 0x098c,
 457	.mnd_width = 8,
 458	.hid_width = 5,
 459	.parent_map = gcc_xo_gpll0_map,
 460	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 461	.clkr.hw.init = &(struct clk_init_data){
 462		.name = "blsp2_qup1_spi_apps_clk_src",
 463		.parent_names = gcc_xo_gpll0,
 464		.num_parents = 2,
 465		.ops = &clk_rcg2_ops,
 466	},
 467};
 468
 469static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 470	.cmd_rcgr = 0x0a20,
 471	.hid_width = 5,
 472	.parent_map = gcc_xo_gpll0_map,
 473	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 474	.clkr.hw.init = &(struct clk_init_data){
 475		.name = "blsp2_qup2_i2c_apps_clk_src",
 476		.parent_names = gcc_xo_gpll0,
 477		.num_parents = 2,
 478		.ops = &clk_rcg2_ops,
 479	},
 480};
 481
 482static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 483	.cmd_rcgr = 0x0a0c,
 484	.mnd_width = 8,
 485	.hid_width = 5,
 486	.parent_map = gcc_xo_gpll0_map,
 487	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 488	.clkr.hw.init = &(struct clk_init_data){
 489		.name = "blsp2_qup2_spi_apps_clk_src",
 490		.parent_names = gcc_xo_gpll0,
 491		.num_parents = 2,
 492		.ops = &clk_rcg2_ops,
 493	},
 494};
 495
 496static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 497	.cmd_rcgr = 0x0aa0,
 498	.hid_width = 5,
 499	.parent_map = gcc_xo_gpll0_map,
 500	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 501	.clkr.hw.init = &(struct clk_init_data){
 502		.name = "blsp2_qup3_i2c_apps_clk_src",
 503		.parent_names = gcc_xo_gpll0,
 504		.num_parents = 2,
 505		.ops = &clk_rcg2_ops,
 506	},
 507};
 508
 509static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 510	.cmd_rcgr = 0x0a8c,
 511	.mnd_width = 8,
 512	.hid_width = 5,
 513	.parent_map = gcc_xo_gpll0_map,
 514	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 515	.clkr.hw.init = &(struct clk_init_data){
 516		.name = "blsp2_qup3_spi_apps_clk_src",
 517		.parent_names = gcc_xo_gpll0,
 518		.num_parents = 2,
 519		.ops = &clk_rcg2_ops,
 520	},
 521};
 522
 523static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 524	.cmd_rcgr = 0x0b20,
 525	.hid_width = 5,
 526	.parent_map = gcc_xo_gpll0_map,
 527	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 528	.clkr.hw.init = &(struct clk_init_data){
 529		.name = "blsp2_qup4_i2c_apps_clk_src",
 530		.parent_names = gcc_xo_gpll0,
 531		.num_parents = 2,
 532		.ops = &clk_rcg2_ops,
 533	},
 534};
 535
 536static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 537	.cmd_rcgr = 0x0b0c,
 538	.mnd_width = 8,
 539	.hid_width = 5,
 540	.parent_map = gcc_xo_gpll0_map,
 541	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 542	.clkr.hw.init = &(struct clk_init_data){
 543		.name = "blsp2_qup4_spi_apps_clk_src",
 544		.parent_names = gcc_xo_gpll0,
 545		.num_parents = 2,
 546		.ops = &clk_rcg2_ops,
 547	},
 548};
 549
 550static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 551	.cmd_rcgr = 0x0ba0,
 552	.hid_width = 5,
 553	.parent_map = gcc_xo_gpll0_map,
 554	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 555	.clkr.hw.init = &(struct clk_init_data){
 556		.name = "blsp2_qup5_i2c_apps_clk_src",
 557		.parent_names = gcc_xo_gpll0,
 558		.num_parents = 2,
 559		.ops = &clk_rcg2_ops,
 560	},
 561};
 562
 563static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 564	.cmd_rcgr = 0x0b8c,
 565	.mnd_width = 8,
 566	.hid_width = 5,
 567	.parent_map = gcc_xo_gpll0_map,
 568	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 569	.clkr.hw.init = &(struct clk_init_data){
 570		.name = "blsp2_qup5_spi_apps_clk_src",
 571		.parent_names = gcc_xo_gpll0,
 572		.num_parents = 2,
 573		.ops = &clk_rcg2_ops,
 574	},
 575};
 576
 577static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 578	.cmd_rcgr = 0x0c20,
 579	.hid_width = 5,
 580	.parent_map = gcc_xo_gpll0_map,
 581	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 582	.clkr.hw.init = &(struct clk_init_data){
 583		.name = "blsp2_qup6_i2c_apps_clk_src",
 584		.parent_names = gcc_xo_gpll0,
 585		.num_parents = 2,
 586		.ops = &clk_rcg2_ops,
 587	},
 588};
 589
 590static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 591	.cmd_rcgr = 0x0c0c,
 592	.mnd_width = 8,
 593	.hid_width = 5,
 594	.parent_map = gcc_xo_gpll0_map,
 595	.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 596	.clkr.hw.init = &(struct clk_init_data){
 597		.name = "blsp2_qup6_spi_apps_clk_src",
 598		.parent_names = gcc_xo_gpll0,
 599		.num_parents = 2,
 600		.ops = &clk_rcg2_ops,
 601	},
 602};
 603
 604static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 605	.cmd_rcgr = 0x09cc,
 606	.mnd_width = 16,
 607	.hid_width = 5,
 608	.parent_map = gcc_xo_gpll0_map,
 609	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 610	.clkr.hw.init = &(struct clk_init_data){
 611		.name = "blsp2_uart1_apps_clk_src",
 612		.parent_names = gcc_xo_gpll0,
 613		.num_parents = 2,
 614		.ops = &clk_rcg2_ops,
 615	},
 616};
 617
 618static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 619	.cmd_rcgr = 0x0a4c,
 620	.mnd_width = 16,
 621	.hid_width = 5,
 622	.parent_map = gcc_xo_gpll0_map,
 623	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 624	.clkr.hw.init = &(struct clk_init_data){
 625		.name = "blsp2_uart2_apps_clk_src",
 626		.parent_names = gcc_xo_gpll0,
 627		.num_parents = 2,
 628		.ops = &clk_rcg2_ops,
 629	},
 630};
 631
 632static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 633	.cmd_rcgr = 0x0acc,
 634	.mnd_width = 16,
 635	.hid_width = 5,
 636	.parent_map = gcc_xo_gpll0_map,
 637	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 638	.clkr.hw.init = &(struct clk_init_data){
 639		.name = "blsp2_uart3_apps_clk_src",
 640		.parent_names = gcc_xo_gpll0,
 641		.num_parents = 2,
 642		.ops = &clk_rcg2_ops,
 643	},
 644};
 645
 646static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 647	.cmd_rcgr = 0x0b4c,
 648	.mnd_width = 16,
 649	.hid_width = 5,
 650	.parent_map = gcc_xo_gpll0_map,
 651	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 652	.clkr.hw.init = &(struct clk_init_data){
 653		.name = "blsp2_uart4_apps_clk_src",
 654		.parent_names = gcc_xo_gpll0,
 655		.num_parents = 2,
 656		.ops = &clk_rcg2_ops,
 657	},
 658};
 659
 660static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
 661	.cmd_rcgr = 0x0bcc,
 662	.mnd_width = 16,
 663	.hid_width = 5,
 664	.parent_map = gcc_xo_gpll0_map,
 665	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 666	.clkr.hw.init = &(struct clk_init_data){
 667		.name = "blsp2_uart5_apps_clk_src",
 668		.parent_names = gcc_xo_gpll0,
 669		.num_parents = 2,
 670		.ops = &clk_rcg2_ops,
 671	},
 672};
 673
 674static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
 675	.cmd_rcgr = 0x0c4c,
 676	.mnd_width = 16,
 677	.hid_width = 5,
 678	.parent_map = gcc_xo_gpll0_map,
 679	.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 680	.clkr.hw.init = &(struct clk_init_data){
 681		.name = "blsp2_uart6_apps_clk_src",
 682		.parent_names = gcc_xo_gpll0,
 683		.num_parents = 2,
 684		.ops = &clk_rcg2_ops,
 685	},
 686};
 687
 688static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
 689	F(50000000, P_GPLL0, 12, 0, 0),
 690	F(75000000, P_GPLL0, 8, 0, 0),
 691	F(100000000, P_GPLL0, 6, 0, 0),
 692	F(150000000, P_GPLL0, 4, 0, 0),
 693	{ }
 694};
 695
 696static struct clk_rcg2 ce1_clk_src = {
 697	.cmd_rcgr = 0x1050,
 698	.hid_width = 5,
 699	.parent_map = gcc_xo_gpll0_map,
 700	.freq_tbl = ftbl_gcc_ce1_clk,
 701	.clkr.hw.init = &(struct clk_init_data){
 702		.name = "ce1_clk_src",
 703		.parent_names = gcc_xo_gpll0,
 704		.num_parents = 2,
 705		.ops = &clk_rcg2_ops,
 706	},
 707};
 708
 709static const struct freq_tbl ftbl_gcc_ce2_clk[] = {
 710	F(50000000, P_GPLL0, 12, 0, 0),
 711	F(75000000, P_GPLL0, 8, 0, 0),
 712	F(100000000, P_GPLL0, 6, 0, 0),
 713	F(150000000, P_GPLL0, 4, 0, 0),
 714	{ }
 715};
 716
 717static struct clk_rcg2 ce2_clk_src = {
 718	.cmd_rcgr = 0x1090,
 719	.hid_width = 5,
 720	.parent_map = gcc_xo_gpll0_map,
 721	.freq_tbl = ftbl_gcc_ce2_clk,
 722	.clkr.hw.init = &(struct clk_init_data){
 723		.name = "ce2_clk_src",
 724		.parent_names = gcc_xo_gpll0,
 725		.num_parents = 2,
 726		.ops = &clk_rcg2_ops,
 727	},
 728};
 729
 730static const struct freq_tbl ftbl_gcc_gp_clk[] = {
 731	F(4800000, P_XO, 4, 0, 0),
 732	F(6000000, P_GPLL0, 10, 1, 10),
 733	F(6750000, P_GPLL0, 1, 1, 89),
 734	F(8000000, P_GPLL0, 15, 1, 5),
 735	F(9600000, P_XO, 2, 0, 0),
 736	F(16000000, P_GPLL0, 1, 2, 75),
 737	F(19200000, P_XO, 1, 0, 0),
 738	F(24000000, P_GPLL0, 5, 1, 5),
 739	{ }
 740};
 741
 742
 743static struct clk_rcg2 gp1_clk_src = {
 744	.cmd_rcgr = 0x1904,
 745	.mnd_width = 8,
 746	.hid_width = 5,
 747	.parent_map = gcc_xo_gpll0_map,
 748	.freq_tbl = ftbl_gcc_gp_clk,
 749	.clkr.hw.init = &(struct clk_init_data){
 750		.name = "gp1_clk_src",
 751		.parent_names = gcc_xo_gpll0,
 752		.num_parents = 2,
 753		.ops = &clk_rcg2_ops,
 754	},
 755};
 756
 757static struct clk_rcg2 gp2_clk_src = {
 758	.cmd_rcgr = 0x1944,
 759	.mnd_width = 8,
 760	.hid_width = 5,
 761	.parent_map = gcc_xo_gpll0_map,
 762	.freq_tbl = ftbl_gcc_gp_clk,
 763	.clkr.hw.init = &(struct clk_init_data){
 764		.name = "gp2_clk_src",
 765		.parent_names = gcc_xo_gpll0,
 766		.num_parents = 2,
 767		.ops = &clk_rcg2_ops,
 768	},
 769};
 770
 771static struct clk_rcg2 gp3_clk_src = {
 772	.cmd_rcgr = 0x1984,
 773	.mnd_width = 8,
 774	.hid_width = 5,
 775	.parent_map = gcc_xo_gpll0_map,
 776	.freq_tbl = ftbl_gcc_gp_clk,
 777	.clkr.hw.init = &(struct clk_init_data){
 778		.name = "gp3_clk_src",
 779		.parent_names = gcc_xo_gpll0,
 780		.num_parents = 2,
 781		.ops = &clk_rcg2_ops,
 782	},
 783};
 784
 785static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
 786	F(60000000, P_GPLL0, 10, 0, 0),
 787	{ }
 788};
 789
 790static struct clk_rcg2 pdm2_clk_src = {
 791	.cmd_rcgr = 0x0cd0,
 792	.hid_width = 5,
 793	.parent_map = gcc_xo_gpll0_map,
 794	.freq_tbl = ftbl_gcc_pdm2_clk,
 795	.clkr.hw.init = &(struct clk_init_data){
 796		.name = "pdm2_clk_src",
 797		.parent_names = gcc_xo_gpll0,
 798		.num_parents = 2,
 799		.ops = &clk_rcg2_ops,
 800	},
 801};
 802
 803static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
 804	F(144000, P_XO, 16, 3, 25),
 805	F(400000, P_XO, 12, 1, 4),
 806	F(20000000, P_GPLL0, 15, 1, 2),
 807	F(25000000, P_GPLL0, 12, 1, 2),
 808	F(50000000, P_GPLL0, 12, 0, 0),
 809	F(100000000, P_GPLL0, 6, 0, 0),
 810	F(200000000, P_GPLL0, 3, 0, 0),
 811	{ }
 812};
 813
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 814static struct clk_rcg2 sdcc1_apps_clk_src = {
 815	.cmd_rcgr = 0x04d0,
 816	.mnd_width = 8,
 817	.hid_width = 5,
 818	.parent_map = gcc_xo_gpll0_map,
 819	.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
 820	.clkr.hw.init = &(struct clk_init_data){
 821		.name = "sdcc1_apps_clk_src",
 822		.parent_names = gcc_xo_gpll0,
 823		.num_parents = 2,
 824		.ops = &clk_rcg2_ops,
 825	},
 826};
 827
 828static struct clk_rcg2 sdcc2_apps_clk_src = {
 829	.cmd_rcgr = 0x0510,
 830	.mnd_width = 8,
 831	.hid_width = 5,
 832	.parent_map = gcc_xo_gpll0_map,
 833	.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
 834	.clkr.hw.init = &(struct clk_init_data){
 835		.name = "sdcc2_apps_clk_src",
 836		.parent_names = gcc_xo_gpll0,
 837		.num_parents = 2,
 838		.ops = &clk_rcg2_ops,
 839	},
 840};
 841
 842static struct clk_rcg2 sdcc3_apps_clk_src = {
 843	.cmd_rcgr = 0x0550,
 844	.mnd_width = 8,
 845	.hid_width = 5,
 846	.parent_map = gcc_xo_gpll0_map,
 847	.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
 848	.clkr.hw.init = &(struct clk_init_data){
 849		.name = "sdcc3_apps_clk_src",
 850		.parent_names = gcc_xo_gpll0,
 851		.num_parents = 2,
 852		.ops = &clk_rcg2_ops,
 853	},
 854};
 855
 856static struct clk_rcg2 sdcc4_apps_clk_src = {
 857	.cmd_rcgr = 0x0590,
 858	.mnd_width = 8,
 859	.hid_width = 5,
 860	.parent_map = gcc_xo_gpll0_map,
 861	.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
 862	.clkr.hw.init = &(struct clk_init_data){
 863		.name = "sdcc4_apps_clk_src",
 864		.parent_names = gcc_xo_gpll0,
 865		.num_parents = 2,
 866		.ops = &clk_rcg2_ops,
 867	},
 868};
 869
 870static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = {
 871	F(105000, P_XO, 2, 1, 91),
 872	{ }
 873};
 874
 875static struct clk_rcg2 tsif_ref_clk_src = {
 876	.cmd_rcgr = 0x0d90,
 877	.mnd_width = 8,
 878	.hid_width = 5,
 879	.parent_map = gcc_xo_gpll0_map,
 880	.freq_tbl = ftbl_gcc_tsif_ref_clk,
 881	.clkr.hw.init = &(struct clk_init_data){
 882		.name = "tsif_ref_clk_src",
 883		.parent_names = gcc_xo_gpll0,
 884		.num_parents = 2,
 885		.ops = &clk_rcg2_ops,
 886	},
 887};
 888
 889static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
 890	F(60000000, P_GPLL0, 10, 0, 0),
 891	{ }
 892};
 893
 894static struct clk_rcg2 usb30_mock_utmi_clk_src = {
 895	.cmd_rcgr = 0x03e8,
 896	.hid_width = 5,
 897	.parent_map = gcc_xo_gpll0_map,
 898	.freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
 899	.clkr.hw.init = &(struct clk_init_data){
 900		.name = "usb30_mock_utmi_clk_src",
 901		.parent_names = gcc_xo_gpll0,
 902		.num_parents = 2,
 903		.ops = &clk_rcg2_ops,
 904	},
 905};
 906
 907static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
 908	F(60000000, P_GPLL0, 10, 0, 0),
 909	F(75000000, P_GPLL0, 8, 0, 0),
 910	{ }
 911};
 912
 913static struct clk_rcg2 usb_hs_system_clk_src = {
 914	.cmd_rcgr = 0x0490,
 915	.hid_width = 5,
 916	.parent_map = gcc_xo_gpll0_map,
 917	.freq_tbl = ftbl_gcc_usb_hs_system_clk,
 918	.clkr.hw.init = &(struct clk_init_data){
 919		.name = "usb_hs_system_clk_src",
 920		.parent_names = gcc_xo_gpll0,
 921		.num_parents = 2,
 922		.ops = &clk_rcg2_ops,
 923	},
 924};
 925
 926static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
 927	F(480000000, P_GPLL1, 1, 0, 0),
 928	{ }
 929};
 930
 931static u8 usb_hsic_clk_src_map[] = {
 932	[P_XO]		= 0,
 933	[P_GPLL1]	= 4,
 934};
 935
 936static struct clk_rcg2 usb_hsic_clk_src = {
 937	.cmd_rcgr = 0x0440,
 938	.hid_width = 5,
 939	.parent_map = usb_hsic_clk_src_map,
 940	.freq_tbl = ftbl_gcc_usb_hsic_clk,
 941	.clkr.hw.init = &(struct clk_init_data){
 942		.name = "usb_hsic_clk_src",
 943		.parent_names = (const char *[]){
 944			"xo",
 945			"gpll1_vote",
 946		},
 947		.num_parents = 2,
 948		.ops = &clk_rcg2_ops,
 949	},
 950};
 951
 952static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
 953	F(9600000, P_XO, 2, 0, 0),
 954	{ }
 955};
 956
 957static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
 958	.cmd_rcgr = 0x0458,
 959	.hid_width = 5,
 960	.parent_map = gcc_xo_gpll0_map,
 961	.freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
 962	.clkr.hw.init = &(struct clk_init_data){
 963		.name = "usb_hsic_io_cal_clk_src",
 964		.parent_names = gcc_xo_gpll0,
 965		.num_parents = 1,
 966		.ops = &clk_rcg2_ops,
 967	},
 968};
 969
 970static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
 971	F(60000000, P_GPLL0, 10, 0, 0),
 972	F(75000000, P_GPLL0, 8, 0, 0),
 973	{ }
 974};
 975
 976static struct clk_rcg2 usb_hsic_system_clk_src = {
 977	.cmd_rcgr = 0x041c,
 978	.hid_width = 5,
 979	.parent_map = gcc_xo_gpll0_map,
 980	.freq_tbl = ftbl_gcc_usb_hsic_system_clk,
 981	.clkr.hw.init = &(struct clk_init_data){
 982		.name = "usb_hsic_system_clk_src",
 983		.parent_names = gcc_xo_gpll0,
 984		.num_parents = 2,
 985		.ops = &clk_rcg2_ops,
 986	},
 987};
 988
 989static struct clk_regmap gcc_mmss_gpll0_clk_src = {
 990	.enable_reg = 0x1484,
 991	.enable_mask = BIT(26),
 992	.hw.init = &(struct clk_init_data){
 993		.name = "mmss_gpll0_vote",
 994		.parent_names = (const char *[]){
 995			"gpll0_vote",
 996		},
 997		.num_parents = 1,
 998		.ops = &clk_branch_simple_ops,
 999	},
1000};
1001
1002static struct clk_branch gcc_bam_dma_ahb_clk = {
1003	.halt_reg = 0x0d44,
1004	.halt_check = BRANCH_HALT_VOTED,
1005	.clkr = {
1006		.enable_reg = 0x1484,
1007		.enable_mask = BIT(12),
1008		.hw.init = &(struct clk_init_data){
1009			.name = "gcc_bam_dma_ahb_clk",
1010			.parent_names = (const char *[]){
1011				"periph_noc_clk_src",
1012			},
1013			.num_parents = 1,
1014			.ops = &clk_branch2_ops,
1015		},
1016	},
1017};
1018
1019static struct clk_branch gcc_blsp1_ahb_clk = {
1020	.halt_reg = 0x05c4,
1021	.halt_check = BRANCH_HALT_VOTED,
1022	.clkr = {
1023		.enable_reg = 0x1484,
1024		.enable_mask = BIT(17),
1025		.hw.init = &(struct clk_init_data){
1026			.name = "gcc_blsp1_ahb_clk",
1027			.parent_names = (const char *[]){
1028				"periph_noc_clk_src",
1029			},
1030			.num_parents = 1,
1031			.ops = &clk_branch2_ops,
1032		},
1033	},
1034};
1035
1036static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1037	.halt_reg = 0x0648,
1038	.clkr = {
1039		.enable_reg = 0x0648,
1040		.enable_mask = BIT(0),
1041		.hw.init = &(struct clk_init_data){
1042			.name = "gcc_blsp1_qup1_i2c_apps_clk",
1043			.parent_names = (const char *[]){
1044				"blsp1_qup1_i2c_apps_clk_src",
1045			},
1046			.num_parents = 1,
1047			.flags = CLK_SET_RATE_PARENT,
1048			.ops = &clk_branch2_ops,
1049		},
1050	},
1051};
1052
1053static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1054	.halt_reg = 0x0644,
1055	.clkr = {
1056		.enable_reg = 0x0644,
1057		.enable_mask = BIT(0),
1058		.hw.init = &(struct clk_init_data){
1059			.name = "gcc_blsp1_qup1_spi_apps_clk",
1060			.parent_names = (const char *[]){
1061				"blsp1_qup1_spi_apps_clk_src",
1062			},
1063			.num_parents = 1,
1064			.flags = CLK_SET_RATE_PARENT,
1065			.ops = &clk_branch2_ops,
1066		},
1067	},
1068};
1069
1070static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1071	.halt_reg = 0x06c8,
1072	.clkr = {
1073		.enable_reg = 0x06c8,
1074		.enable_mask = BIT(0),
1075		.hw.init = &(struct clk_init_data){
1076			.name = "gcc_blsp1_qup2_i2c_apps_clk",
1077			.parent_names = (const char *[]){
1078				"blsp1_qup2_i2c_apps_clk_src",
1079			},
1080			.num_parents = 1,
1081			.flags = CLK_SET_RATE_PARENT,
1082			.ops = &clk_branch2_ops,
1083		},
1084	},
1085};
1086
1087static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1088	.halt_reg = 0x06c4,
1089	.clkr = {
1090		.enable_reg = 0x06c4,
1091		.enable_mask = BIT(0),
1092		.hw.init = &(struct clk_init_data){
1093			.name = "gcc_blsp1_qup2_spi_apps_clk",
1094			.parent_names = (const char *[]){
1095				"blsp1_qup2_spi_apps_clk_src",
1096			},
1097			.num_parents = 1,
1098			.flags = CLK_SET_RATE_PARENT,
1099			.ops = &clk_branch2_ops,
1100		},
1101	},
1102};
1103
1104static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1105	.halt_reg = 0x0748,
1106	.clkr = {
1107		.enable_reg = 0x0748,
1108		.enable_mask = BIT(0),
1109		.hw.init = &(struct clk_init_data){
1110			.name = "gcc_blsp1_qup3_i2c_apps_clk",
1111			.parent_names = (const char *[]){
1112				"blsp1_qup3_i2c_apps_clk_src",
1113			},
1114			.num_parents = 1,
1115			.flags = CLK_SET_RATE_PARENT,
1116			.ops = &clk_branch2_ops,
1117		},
1118	},
1119};
1120
1121static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1122	.halt_reg = 0x0744,
1123	.clkr = {
1124		.enable_reg = 0x0744,
1125		.enable_mask = BIT(0),
1126		.hw.init = &(struct clk_init_data){
1127			.name = "gcc_blsp1_qup3_spi_apps_clk",
1128			.parent_names = (const char *[]){
1129				"blsp1_qup3_spi_apps_clk_src",
1130			},
1131			.num_parents = 1,
1132			.flags = CLK_SET_RATE_PARENT,
1133			.ops = &clk_branch2_ops,
1134		},
1135	},
1136};
1137
1138static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1139	.halt_reg = 0x07c8,
1140	.clkr = {
1141		.enable_reg = 0x07c8,
1142		.enable_mask = BIT(0),
1143		.hw.init = &(struct clk_init_data){
1144			.name = "gcc_blsp1_qup4_i2c_apps_clk",
1145			.parent_names = (const char *[]){
1146				"blsp1_qup4_i2c_apps_clk_src",
1147			},
1148			.num_parents = 1,
1149			.flags = CLK_SET_RATE_PARENT,
1150			.ops = &clk_branch2_ops,
1151		},
1152	},
1153};
1154
1155static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1156	.halt_reg = 0x07c4,
1157	.clkr = {
1158		.enable_reg = 0x07c4,
1159		.enable_mask = BIT(0),
1160		.hw.init = &(struct clk_init_data){
1161			.name = "gcc_blsp1_qup4_spi_apps_clk",
1162			.parent_names = (const char *[]){
1163				"blsp1_qup4_spi_apps_clk_src",
1164			},
1165			.num_parents = 1,
1166			.flags = CLK_SET_RATE_PARENT,
1167			.ops = &clk_branch2_ops,
1168		},
1169	},
1170};
1171
1172static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1173	.halt_reg = 0x0848,
1174	.clkr = {
1175		.enable_reg = 0x0848,
1176		.enable_mask = BIT(0),
1177		.hw.init = &(struct clk_init_data){
1178			.name = "gcc_blsp1_qup5_i2c_apps_clk",
1179			.parent_names = (const char *[]){
1180				"blsp1_qup5_i2c_apps_clk_src",
1181			},
1182			.num_parents = 1,
1183			.flags = CLK_SET_RATE_PARENT,
1184			.ops = &clk_branch2_ops,
1185		},
1186	},
1187};
1188
1189static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1190	.halt_reg = 0x0844,
1191	.clkr = {
1192		.enable_reg = 0x0844,
1193		.enable_mask = BIT(0),
1194		.hw.init = &(struct clk_init_data){
1195			.name = "gcc_blsp1_qup5_spi_apps_clk",
1196			.parent_names = (const char *[]){
1197				"blsp1_qup5_spi_apps_clk_src",
1198			},
1199			.num_parents = 1,
1200			.flags = CLK_SET_RATE_PARENT,
1201			.ops = &clk_branch2_ops,
1202		},
1203	},
1204};
1205
1206static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1207	.halt_reg = 0x08c8,
1208	.clkr = {
1209		.enable_reg = 0x08c8,
1210		.enable_mask = BIT(0),
1211		.hw.init = &(struct clk_init_data){
1212			.name = "gcc_blsp1_qup6_i2c_apps_clk",
1213			.parent_names = (const char *[]){
1214				"blsp1_qup6_i2c_apps_clk_src",
1215			},
1216			.num_parents = 1,
1217			.flags = CLK_SET_RATE_PARENT,
1218			.ops = &clk_branch2_ops,
1219		},
1220	},
1221};
1222
1223static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1224	.halt_reg = 0x08c4,
1225	.clkr = {
1226		.enable_reg = 0x08c4,
1227		.enable_mask = BIT(0),
1228		.hw.init = &(struct clk_init_data){
1229			.name = "gcc_blsp1_qup6_spi_apps_clk",
1230			.parent_names = (const char *[]){
1231				"blsp1_qup6_spi_apps_clk_src",
1232			},
1233			.num_parents = 1,
1234			.flags = CLK_SET_RATE_PARENT,
1235			.ops = &clk_branch2_ops,
1236		},
1237	},
1238};
1239
1240static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1241	.halt_reg = 0x0684,
1242	.clkr = {
1243		.enable_reg = 0x0684,
1244		.enable_mask = BIT(0),
1245		.hw.init = &(struct clk_init_data){
1246			.name = "gcc_blsp1_uart1_apps_clk",
1247			.parent_names = (const char *[]){
1248				"blsp1_uart1_apps_clk_src",
1249			},
1250			.num_parents = 1,
1251			.flags = CLK_SET_RATE_PARENT,
1252			.ops = &clk_branch2_ops,
1253		},
1254	},
1255};
1256
1257static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1258	.halt_reg = 0x0704,
1259	.clkr = {
1260		.enable_reg = 0x0704,
1261		.enable_mask = BIT(0),
1262		.hw.init = &(struct clk_init_data){
1263			.name = "gcc_blsp1_uart2_apps_clk",
1264			.parent_names = (const char *[]){
1265				"blsp1_uart2_apps_clk_src",
1266			},
1267			.num_parents = 1,
1268			.flags = CLK_SET_RATE_PARENT,
1269			.ops = &clk_branch2_ops,
1270		},
1271	},
1272};
1273
1274static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1275	.halt_reg = 0x0784,
1276	.clkr = {
1277		.enable_reg = 0x0784,
1278		.enable_mask = BIT(0),
1279		.hw.init = &(struct clk_init_data){
1280			.name = "gcc_blsp1_uart3_apps_clk",
1281			.parent_names = (const char *[]){
1282				"blsp1_uart3_apps_clk_src",
1283			},
1284			.num_parents = 1,
1285			.flags = CLK_SET_RATE_PARENT,
1286			.ops = &clk_branch2_ops,
1287		},
1288	},
1289};
1290
1291static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1292	.halt_reg = 0x0804,
1293	.clkr = {
1294		.enable_reg = 0x0804,
1295		.enable_mask = BIT(0),
1296		.hw.init = &(struct clk_init_data){
1297			.name = "gcc_blsp1_uart4_apps_clk",
1298			.parent_names = (const char *[]){
1299				"blsp1_uart4_apps_clk_src",
1300			},
1301			.num_parents = 1,
1302			.flags = CLK_SET_RATE_PARENT,
1303			.ops = &clk_branch2_ops,
1304		},
1305	},
1306};
1307
1308static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1309	.halt_reg = 0x0884,
1310	.clkr = {
1311		.enable_reg = 0x0884,
1312		.enable_mask = BIT(0),
1313		.hw.init = &(struct clk_init_data){
1314			.name = "gcc_blsp1_uart5_apps_clk",
1315			.parent_names = (const char *[]){
1316				"blsp1_uart5_apps_clk_src",
1317			},
1318			.num_parents = 1,
1319			.flags = CLK_SET_RATE_PARENT,
1320			.ops = &clk_branch2_ops,
1321		},
1322	},
1323};
1324
1325static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1326	.halt_reg = 0x0904,
1327	.clkr = {
1328		.enable_reg = 0x0904,
1329		.enable_mask = BIT(0),
1330		.hw.init = &(struct clk_init_data){
1331			.name = "gcc_blsp1_uart6_apps_clk",
1332			.parent_names = (const char *[]){
1333				"blsp1_uart6_apps_clk_src",
1334			},
1335			.num_parents = 1,
1336			.flags = CLK_SET_RATE_PARENT,
1337			.ops = &clk_branch2_ops,
1338		},
1339	},
1340};
1341
1342static struct clk_branch gcc_blsp2_ahb_clk = {
1343	.halt_reg = 0x05c4,
1344	.halt_check = BRANCH_HALT_VOTED,
1345	.clkr = {
1346		.enable_reg = 0x1484,
1347		.enable_mask = BIT(15),
1348		.hw.init = &(struct clk_init_data){
1349			.name = "gcc_blsp2_ahb_clk",
1350			.parent_names = (const char *[]){
1351				"periph_noc_clk_src",
1352			},
1353			.num_parents = 1,
1354			.ops = &clk_branch2_ops,
1355		},
1356	},
1357};
1358
1359static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1360	.halt_reg = 0x0988,
1361	.clkr = {
1362		.enable_reg = 0x0988,
1363		.enable_mask = BIT(0),
1364		.hw.init = &(struct clk_init_data){
1365			.name = "gcc_blsp2_qup1_i2c_apps_clk",
1366			.parent_names = (const char *[]){
1367				"blsp2_qup1_i2c_apps_clk_src",
1368			},
1369			.num_parents = 1,
1370			.flags = CLK_SET_RATE_PARENT,
1371			.ops = &clk_branch2_ops,
1372		},
1373	},
1374};
1375
1376static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1377	.halt_reg = 0x0984,
1378	.clkr = {
1379		.enable_reg = 0x0984,
1380		.enable_mask = BIT(0),
1381		.hw.init = &(struct clk_init_data){
1382			.name = "gcc_blsp2_qup1_spi_apps_clk",
1383			.parent_names = (const char *[]){
1384				"blsp2_qup1_spi_apps_clk_src",
1385			},
1386			.num_parents = 1,
1387			.flags = CLK_SET_RATE_PARENT,
1388			.ops = &clk_branch2_ops,
1389		},
1390	},
1391};
1392
1393static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1394	.halt_reg = 0x0a08,
1395	.clkr = {
1396		.enable_reg = 0x0a08,
1397		.enable_mask = BIT(0),
1398		.hw.init = &(struct clk_init_data){
1399			.name = "gcc_blsp2_qup2_i2c_apps_clk",
1400			.parent_names = (const char *[]){
1401				"blsp2_qup2_i2c_apps_clk_src",
1402			},
1403			.num_parents = 1,
1404			.flags = CLK_SET_RATE_PARENT,
1405			.ops = &clk_branch2_ops,
1406		},
1407	},
1408};
1409
1410static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1411	.halt_reg = 0x0a04,
1412	.clkr = {
1413		.enable_reg = 0x0a04,
1414		.enable_mask = BIT(0),
1415		.hw.init = &(struct clk_init_data){
1416			.name = "gcc_blsp2_qup2_spi_apps_clk",
1417			.parent_names = (const char *[]){
1418				"blsp2_qup2_spi_apps_clk_src",
1419			},
1420			.num_parents = 1,
1421			.flags = CLK_SET_RATE_PARENT,
1422			.ops = &clk_branch2_ops,
1423		},
1424	},
1425};
1426
1427static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1428	.halt_reg = 0x0a88,
1429	.clkr = {
1430		.enable_reg = 0x0a88,
1431		.enable_mask = BIT(0),
1432		.hw.init = &(struct clk_init_data){
1433			.name = "gcc_blsp2_qup3_i2c_apps_clk",
1434			.parent_names = (const char *[]){
1435				"blsp2_qup3_i2c_apps_clk_src",
1436			},
1437			.num_parents = 1,
1438			.flags = CLK_SET_RATE_PARENT,
1439			.ops = &clk_branch2_ops,
1440		},
1441	},
1442};
1443
1444static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1445	.halt_reg = 0x0a84,
1446	.clkr = {
1447		.enable_reg = 0x0a84,
1448		.enable_mask = BIT(0),
1449		.hw.init = &(struct clk_init_data){
1450			.name = "gcc_blsp2_qup3_spi_apps_clk",
1451			.parent_names = (const char *[]){
1452				"blsp2_qup3_spi_apps_clk_src",
1453			},
1454			.num_parents = 1,
1455			.flags = CLK_SET_RATE_PARENT,
1456			.ops = &clk_branch2_ops,
1457		},
1458	},
1459};
1460
1461static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1462	.halt_reg = 0x0b08,
1463	.clkr = {
1464		.enable_reg = 0x0b08,
1465		.enable_mask = BIT(0),
1466		.hw.init = &(struct clk_init_data){
1467			.name = "gcc_blsp2_qup4_i2c_apps_clk",
1468			.parent_names = (const char *[]){
1469				"blsp2_qup4_i2c_apps_clk_src",
1470			},
1471			.num_parents = 1,
1472			.flags = CLK_SET_RATE_PARENT,
1473			.ops = &clk_branch2_ops,
1474		},
1475	},
1476};
1477
1478static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1479	.halt_reg = 0x0b04,
1480	.clkr = {
1481		.enable_reg = 0x0b04,
1482		.enable_mask = BIT(0),
1483		.hw.init = &(struct clk_init_data){
1484			.name = "gcc_blsp2_qup4_spi_apps_clk",
1485			.parent_names = (const char *[]){
1486				"blsp2_qup4_spi_apps_clk_src",
1487			},
1488			.num_parents = 1,
1489			.flags = CLK_SET_RATE_PARENT,
1490			.ops = &clk_branch2_ops,
1491		},
1492	},
1493};
1494
1495static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1496	.halt_reg = 0x0b88,
1497	.clkr = {
1498		.enable_reg = 0x0b88,
1499		.enable_mask = BIT(0),
1500		.hw.init = &(struct clk_init_data){
1501			.name = "gcc_blsp2_qup5_i2c_apps_clk",
1502			.parent_names = (const char *[]){
1503				"blsp2_qup5_i2c_apps_clk_src",
1504			},
1505			.num_parents = 1,
1506			.flags = CLK_SET_RATE_PARENT,
1507			.ops = &clk_branch2_ops,
1508		},
1509	},
1510};
1511
1512static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1513	.halt_reg = 0x0b84,
1514	.clkr = {
1515		.enable_reg = 0x0b84,
1516		.enable_mask = BIT(0),
1517		.hw.init = &(struct clk_init_data){
1518			.name = "gcc_blsp2_qup5_spi_apps_clk",
1519			.parent_names = (const char *[]){
1520				"blsp2_qup5_spi_apps_clk_src",
1521			},
1522			.num_parents = 1,
1523			.flags = CLK_SET_RATE_PARENT,
1524			.ops = &clk_branch2_ops,
1525		},
1526	},
1527};
1528
1529static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1530	.halt_reg = 0x0c08,
1531	.clkr = {
1532		.enable_reg = 0x0c08,
1533		.enable_mask = BIT(0),
1534		.hw.init = &(struct clk_init_data){
1535			.name = "gcc_blsp2_qup6_i2c_apps_clk",
1536			.parent_names = (const char *[]){
1537				"blsp2_qup6_i2c_apps_clk_src",
1538			},
1539			.num_parents = 1,
1540			.flags = CLK_SET_RATE_PARENT,
1541			.ops = &clk_branch2_ops,
1542		},
1543	},
1544};
1545
1546static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1547	.halt_reg = 0x0c04,
1548	.clkr = {
1549		.enable_reg = 0x0c04,
1550		.enable_mask = BIT(0),
1551		.hw.init = &(struct clk_init_data){
1552			.name = "gcc_blsp2_qup6_spi_apps_clk",
1553			.parent_names = (const char *[]){
1554				"blsp2_qup6_spi_apps_clk_src",
1555			},
1556			.num_parents = 1,
1557			.flags = CLK_SET_RATE_PARENT,
1558			.ops = &clk_branch2_ops,
1559		},
1560	},
1561};
1562
1563static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1564	.halt_reg = 0x09c4,
1565	.clkr = {
1566		.enable_reg = 0x09c4,
1567		.enable_mask = BIT(0),
1568		.hw.init = &(struct clk_init_data){
1569			.name = "gcc_blsp2_uart1_apps_clk",
1570			.parent_names = (const char *[]){
1571				"blsp2_uart1_apps_clk_src",
1572			},
1573			.num_parents = 1,
1574			.flags = CLK_SET_RATE_PARENT,
1575			.ops = &clk_branch2_ops,
1576		},
1577	},
1578};
1579
1580static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1581	.halt_reg = 0x0a44,
1582	.clkr = {
1583		.enable_reg = 0x0a44,
1584		.enable_mask = BIT(0),
1585		.hw.init = &(struct clk_init_data){
1586			.name = "gcc_blsp2_uart2_apps_clk",
1587			.parent_names = (const char *[]){
1588				"blsp2_uart2_apps_clk_src",
1589			},
1590			.num_parents = 1,
1591			.flags = CLK_SET_RATE_PARENT,
1592			.ops = &clk_branch2_ops,
1593		},
1594	},
1595};
1596
1597static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1598	.halt_reg = 0x0ac4,
1599	.clkr = {
1600		.enable_reg = 0x0ac4,
1601		.enable_mask = BIT(0),
1602		.hw.init = &(struct clk_init_data){
1603			.name = "gcc_blsp2_uart3_apps_clk",
1604			.parent_names = (const char *[]){
1605				"blsp2_uart3_apps_clk_src",
1606			},
1607			.num_parents = 1,
1608			.flags = CLK_SET_RATE_PARENT,
1609			.ops = &clk_branch2_ops,
1610		},
1611	},
1612};
1613
1614static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1615	.halt_reg = 0x0b44,
1616	.clkr = {
1617		.enable_reg = 0x0b44,
1618		.enable_mask = BIT(0),
1619		.hw.init = &(struct clk_init_data){
1620			.name = "gcc_blsp2_uart4_apps_clk",
1621			.parent_names = (const char *[]){
1622				"blsp2_uart4_apps_clk_src",
1623			},
1624			.num_parents = 1,
1625			.flags = CLK_SET_RATE_PARENT,
1626			.ops = &clk_branch2_ops,
1627		},
1628	},
1629};
1630
1631static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1632	.halt_reg = 0x0bc4,
1633	.clkr = {
1634		.enable_reg = 0x0bc4,
1635		.enable_mask = BIT(0),
1636		.hw.init = &(struct clk_init_data){
1637			.name = "gcc_blsp2_uart5_apps_clk",
1638			.parent_names = (const char *[]){
1639				"blsp2_uart5_apps_clk_src",
1640			},
1641			.num_parents = 1,
1642			.flags = CLK_SET_RATE_PARENT,
1643			.ops = &clk_branch2_ops,
1644		},
1645	},
1646};
1647
1648static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1649	.halt_reg = 0x0c44,
1650	.clkr = {
1651		.enable_reg = 0x0c44,
1652		.enable_mask = BIT(0),
1653		.hw.init = &(struct clk_init_data){
1654			.name = "gcc_blsp2_uart6_apps_clk",
1655			.parent_names = (const char *[]){
1656				"blsp2_uart6_apps_clk_src",
1657			},
1658			.num_parents = 1,
1659			.flags = CLK_SET_RATE_PARENT,
1660			.ops = &clk_branch2_ops,
1661		},
1662	},
1663};
1664
1665static struct clk_branch gcc_boot_rom_ahb_clk = {
1666	.halt_reg = 0x0e04,
1667	.halt_check = BRANCH_HALT_VOTED,
1668	.clkr = {
1669		.enable_reg = 0x1484,
1670		.enable_mask = BIT(10),
1671		.hw.init = &(struct clk_init_data){
1672			.name = "gcc_boot_rom_ahb_clk",
1673			.parent_names = (const char *[]){
1674				"config_noc_clk_src",
1675			},
1676			.num_parents = 1,
1677			.ops = &clk_branch2_ops,
1678		},
1679	},
1680};
1681
1682static struct clk_branch gcc_ce1_ahb_clk = {
1683	.halt_reg = 0x104c,
1684	.halt_check = BRANCH_HALT_VOTED,
1685	.clkr = {
1686		.enable_reg = 0x1484,
1687		.enable_mask = BIT(3),
1688		.hw.init = &(struct clk_init_data){
1689			.name = "gcc_ce1_ahb_clk",
1690			.parent_names = (const char *[]){
1691				"config_noc_clk_src",
1692			},
1693			.num_parents = 1,
1694			.ops = &clk_branch2_ops,
1695		},
1696	},
1697};
1698
1699static struct clk_branch gcc_ce1_axi_clk = {
1700	.halt_reg = 0x1048,
1701	.halt_check = BRANCH_HALT_VOTED,
1702	.clkr = {
1703		.enable_reg = 0x1484,
1704		.enable_mask = BIT(4),
1705		.hw.init = &(struct clk_init_data){
1706			.name = "gcc_ce1_axi_clk",
1707			.parent_names = (const char *[]){
1708				"system_noc_clk_src",
1709			},
1710			.num_parents = 1,
1711			.ops = &clk_branch2_ops,
1712		},
1713	},
1714};
1715
1716static struct clk_branch gcc_ce1_clk = {
1717	.halt_reg = 0x1050,
1718	.halt_check = BRANCH_HALT_VOTED,
1719	.clkr = {
1720		.enable_reg = 0x1484,
1721		.enable_mask = BIT(5),
1722		.hw.init = &(struct clk_init_data){
1723			.name = "gcc_ce1_clk",
1724			.parent_names = (const char *[]){
1725				"ce1_clk_src",
1726			},
1727			.num_parents = 1,
 
1728			.ops = &clk_branch2_ops,
1729		},
1730	},
1731};
1732
1733static struct clk_branch gcc_ce2_ahb_clk = {
1734	.halt_reg = 0x108c,
1735	.halt_check = BRANCH_HALT_VOTED,
1736	.clkr = {
1737		.enable_reg = 0x1484,
1738		.enable_mask = BIT(0),
1739		.hw.init = &(struct clk_init_data){
1740			.name = "gcc_ce2_ahb_clk",
1741			.parent_names = (const char *[]){
1742				"config_noc_clk_src",
1743			},
1744			.num_parents = 1,
1745			.ops = &clk_branch2_ops,
1746		},
1747	},
1748};
1749
1750static struct clk_branch gcc_ce2_axi_clk = {
1751	.halt_reg = 0x1088,
1752	.halt_check = BRANCH_HALT_VOTED,
1753	.clkr = {
1754		.enable_reg = 0x1484,
1755		.enable_mask = BIT(1),
1756		.hw.init = &(struct clk_init_data){
1757			.name = "gcc_ce2_axi_clk",
1758			.parent_names = (const char *[]){
1759				"system_noc_clk_src",
1760			},
1761			.num_parents = 1,
1762			.ops = &clk_branch2_ops,
1763		},
1764	},
1765};
1766
1767static struct clk_branch gcc_ce2_clk = {
1768	.halt_reg = 0x1090,
1769	.halt_check = BRANCH_HALT_VOTED,
1770	.clkr = {
1771		.enable_reg = 0x1484,
1772		.enable_mask = BIT(2),
1773		.hw.init = &(struct clk_init_data){
1774			.name = "gcc_ce2_clk",
1775			.parent_names = (const char *[]){
1776				"ce2_clk_src",
1777			},
1778			.num_parents = 1,
1779			.flags = CLK_SET_RATE_PARENT,
1780			.ops = &clk_branch2_ops,
1781		},
1782	},
1783};
1784
1785static struct clk_branch gcc_gp1_clk = {
1786	.halt_reg = 0x1900,
1787	.clkr = {
1788		.enable_reg = 0x1900,
1789		.enable_mask = BIT(0),
1790		.hw.init = &(struct clk_init_data){
1791			.name = "gcc_gp1_clk",
1792			.parent_names = (const char *[]){
1793				"gp1_clk_src",
1794			},
1795			.num_parents = 1,
1796			.flags = CLK_SET_RATE_PARENT,
1797			.ops = &clk_branch2_ops,
1798		},
1799	},
1800};
1801
1802static struct clk_branch gcc_gp2_clk = {
1803	.halt_reg = 0x1940,
1804	.clkr = {
1805		.enable_reg = 0x1940,
1806		.enable_mask = BIT(0),
1807		.hw.init = &(struct clk_init_data){
1808			.name = "gcc_gp2_clk",
1809			.parent_names = (const char *[]){
1810				"gp2_clk_src",
1811			},
1812			.num_parents = 1,
1813			.flags = CLK_SET_RATE_PARENT,
1814			.ops = &clk_branch2_ops,
1815		},
1816	},
1817};
1818
1819static struct clk_branch gcc_gp3_clk = {
1820	.halt_reg = 0x1980,
1821	.clkr = {
1822		.enable_reg = 0x1980,
1823		.enable_mask = BIT(0),
1824		.hw.init = &(struct clk_init_data){
1825			.name = "gcc_gp3_clk",
1826			.parent_names = (const char *[]){
1827				"gp3_clk_src",
1828			},
1829			.num_parents = 1,
1830			.flags = CLK_SET_RATE_PARENT,
1831			.ops = &clk_branch2_ops,
1832		},
1833	},
1834};
1835
1836static struct clk_branch gcc_lpass_q6_axi_clk = {
1837	.halt_reg = 0x11c0,
1838	.clkr = {
1839		.enable_reg = 0x11c0,
1840		.enable_mask = BIT(0),
1841		.hw.init = &(struct clk_init_data){
1842			.name = "gcc_lpass_q6_axi_clk",
1843			.parent_names = (const char *[]){
1844				"system_noc_clk_src",
1845			},
1846			.num_parents = 1,
1847			.ops = &clk_branch2_ops,
1848		},
1849	},
1850};
1851
1852static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1853	.halt_reg = 0x024c,
1854	.clkr = {
1855		.enable_reg = 0x024c,
1856		.enable_mask = BIT(0),
1857		.hw.init = &(struct clk_init_data){
1858			.name = "gcc_mmss_noc_cfg_ahb_clk",
1859			.parent_names = (const char *[]){
1860				"config_noc_clk_src",
1861			},
1862			.num_parents = 1,
1863			.ops = &clk_branch2_ops,
1864			.flags = CLK_IGNORE_UNUSED,
1865		},
1866	},
1867};
1868
1869static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
1870	.halt_reg = 0x0248,
1871	.clkr = {
1872		.enable_reg = 0x0248,
1873		.enable_mask = BIT(0),
1874		.hw.init = &(struct clk_init_data){
1875			.name = "gcc_ocmem_noc_cfg_ahb_clk",
1876			.parent_names = (const char *[]){
1877				"config_noc_clk_src",
1878			},
1879			.num_parents = 1,
1880			.ops = &clk_branch2_ops,
1881		},
1882	},
1883};
1884
1885static struct clk_branch gcc_mss_cfg_ahb_clk = {
1886	.halt_reg = 0x0280,
1887	.clkr = {
1888		.enable_reg = 0x0280,
1889		.enable_mask = BIT(0),
1890		.hw.init = &(struct clk_init_data){
1891			.name = "gcc_mss_cfg_ahb_clk",
1892			.parent_names = (const char *[]){
1893				"config_noc_clk_src",
1894			},
1895			.num_parents = 1,
1896			.ops = &clk_branch2_ops,
1897		},
1898	},
1899};
1900
1901static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1902	.halt_reg = 0x0284,
1903	.clkr = {
1904		.enable_reg = 0x0284,
1905		.enable_mask = BIT(0),
1906		.hw.init = &(struct clk_init_data){
1907			.name = "gcc_mss_q6_bimc_axi_clk",
1908			.flags = CLK_IS_ROOT,
1909			.ops = &clk_branch2_ops,
1910		},
1911	},
1912};
1913
1914static struct clk_branch gcc_pdm2_clk = {
1915	.halt_reg = 0x0ccc,
1916	.clkr = {
1917		.enable_reg = 0x0ccc,
1918		.enable_mask = BIT(0),
1919		.hw.init = &(struct clk_init_data){
1920			.name = "gcc_pdm2_clk",
1921			.parent_names = (const char *[]){
1922				"pdm2_clk_src",
1923			},
1924			.num_parents = 1,
1925			.flags = CLK_SET_RATE_PARENT,
1926			.ops = &clk_branch2_ops,
1927		},
1928	},
1929};
1930
1931static struct clk_branch gcc_pdm_ahb_clk = {
1932	.halt_reg = 0x0cc4,
1933	.clkr = {
1934		.enable_reg = 0x0cc4,
1935		.enable_mask = BIT(0),
1936		.hw.init = &(struct clk_init_data){
1937			.name = "gcc_pdm_ahb_clk",
1938			.parent_names = (const char *[]){
1939				"periph_noc_clk_src",
1940			},
1941			.num_parents = 1,
1942			.ops = &clk_branch2_ops,
1943		},
1944	},
1945};
1946
1947static struct clk_branch gcc_prng_ahb_clk = {
1948	.halt_reg = 0x0d04,
1949	.halt_check = BRANCH_HALT_VOTED,
1950	.clkr = {
1951		.enable_reg = 0x1484,
1952		.enable_mask = BIT(13),
1953		.hw.init = &(struct clk_init_data){
1954			.name = "gcc_prng_ahb_clk",
1955			.parent_names = (const char *[]){
1956				"periph_noc_clk_src",
1957			},
1958			.num_parents = 1,
1959			.ops = &clk_branch2_ops,
1960		},
1961	},
1962};
1963
1964static struct clk_branch gcc_sdcc1_ahb_clk = {
1965	.halt_reg = 0x04c8,
1966	.clkr = {
1967		.enable_reg = 0x04c8,
1968		.enable_mask = BIT(0),
1969		.hw.init = &(struct clk_init_data){
1970			.name = "gcc_sdcc1_ahb_clk",
1971			.parent_names = (const char *[]){
1972				"periph_noc_clk_src",
1973			},
1974			.num_parents = 1,
1975			.ops = &clk_branch2_ops,
1976		},
1977	},
1978};
1979
1980static struct clk_branch gcc_sdcc1_apps_clk = {
1981	.halt_reg = 0x04c4,
1982	.clkr = {
1983		.enable_reg = 0x04c4,
1984		.enable_mask = BIT(0),
1985		.hw.init = &(struct clk_init_data){
1986			.name = "gcc_sdcc1_apps_clk",
1987			.parent_names = (const char *[]){
1988				"sdcc1_apps_clk_src",
1989			},
1990			.num_parents = 1,
1991			.flags = CLK_SET_RATE_PARENT,
1992			.ops = &clk_branch2_ops,
1993		},
1994	},
1995};
1996
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1997static struct clk_branch gcc_sdcc2_ahb_clk = {
1998	.halt_reg = 0x0508,
1999	.clkr = {
2000		.enable_reg = 0x0508,
2001		.enable_mask = BIT(0),
2002		.hw.init = &(struct clk_init_data){
2003			.name = "gcc_sdcc2_ahb_clk",
2004			.parent_names = (const char *[]){
2005				"periph_noc_clk_src",
2006			},
2007			.num_parents = 1,
2008			.ops = &clk_branch2_ops,
2009		},
2010	},
2011};
2012
2013static struct clk_branch gcc_sdcc2_apps_clk = {
2014	.halt_reg = 0x0504,
2015	.clkr = {
2016		.enable_reg = 0x0504,
2017		.enable_mask = BIT(0),
2018		.hw.init = &(struct clk_init_data){
2019			.name = "gcc_sdcc2_apps_clk",
2020			.parent_names = (const char *[]){
2021				"sdcc2_apps_clk_src",
2022			},
2023			.num_parents = 1,
2024			.flags = CLK_SET_RATE_PARENT,
2025			.ops = &clk_branch2_ops,
2026		},
2027	},
2028};
2029
2030static struct clk_branch gcc_sdcc3_ahb_clk = {
2031	.halt_reg = 0x0548,
2032	.clkr = {
2033		.enable_reg = 0x0548,
2034		.enable_mask = BIT(0),
2035		.hw.init = &(struct clk_init_data){
2036			.name = "gcc_sdcc3_ahb_clk",
2037			.parent_names = (const char *[]){
2038				"periph_noc_clk_src",
2039			},
2040			.num_parents = 1,
2041			.ops = &clk_branch2_ops,
2042		},
2043	},
2044};
2045
2046static struct clk_branch gcc_sdcc3_apps_clk = {
2047	.halt_reg = 0x0544,
2048	.clkr = {
2049		.enable_reg = 0x0544,
2050		.enable_mask = BIT(0),
2051		.hw.init = &(struct clk_init_data){
2052			.name = "gcc_sdcc3_apps_clk",
2053			.parent_names = (const char *[]){
2054				"sdcc3_apps_clk_src",
2055			},
2056			.num_parents = 1,
2057			.flags = CLK_SET_RATE_PARENT,
2058			.ops = &clk_branch2_ops,
2059		},
2060	},
2061};
2062
2063static struct clk_branch gcc_sdcc4_ahb_clk = {
2064	.halt_reg = 0x0588,
2065	.clkr = {
2066		.enable_reg = 0x0588,
2067		.enable_mask = BIT(0),
2068		.hw.init = &(struct clk_init_data){
2069			.name = "gcc_sdcc4_ahb_clk",
2070			.parent_names = (const char *[]){
2071				"periph_noc_clk_src",
2072			},
2073			.num_parents = 1,
2074			.ops = &clk_branch2_ops,
2075		},
2076	},
2077};
2078
2079static struct clk_branch gcc_sdcc4_apps_clk = {
2080	.halt_reg = 0x0584,
2081	.clkr = {
2082		.enable_reg = 0x0584,
2083		.enable_mask = BIT(0),
2084		.hw.init = &(struct clk_init_data){
2085			.name = "gcc_sdcc4_apps_clk",
2086			.parent_names = (const char *[]){
2087				"sdcc4_apps_clk_src",
2088			},
2089			.num_parents = 1,
2090			.flags = CLK_SET_RATE_PARENT,
2091			.ops = &clk_branch2_ops,
2092		},
2093	},
2094};
2095
2096static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2097	.halt_reg = 0x0108,
2098	.clkr = {
2099		.enable_reg = 0x0108,
2100		.enable_mask = BIT(0),
2101		.hw.init = &(struct clk_init_data){
2102			.name = "gcc_sys_noc_usb3_axi_clk",
2103			.parent_names = (const char *[]){
2104				"usb30_master_clk_src",
2105			},
2106			.num_parents = 1,
2107			.flags = CLK_SET_RATE_PARENT,
2108			.ops = &clk_branch2_ops,
2109		},
2110	},
2111};
2112
2113static struct clk_branch gcc_tsif_ahb_clk = {
2114	.halt_reg = 0x0d84,
2115	.clkr = {
2116		.enable_reg = 0x0d84,
2117		.enable_mask = BIT(0),
2118		.hw.init = &(struct clk_init_data){
2119			.name = "gcc_tsif_ahb_clk",
2120			.parent_names = (const char *[]){
2121				"periph_noc_clk_src",
2122			},
2123			.num_parents = 1,
2124			.ops = &clk_branch2_ops,
2125		},
2126	},
2127};
2128
2129static struct clk_branch gcc_tsif_ref_clk = {
2130	.halt_reg = 0x0d88,
2131	.clkr = {
2132		.enable_reg = 0x0d88,
2133		.enable_mask = BIT(0),
2134		.hw.init = &(struct clk_init_data){
2135			.name = "gcc_tsif_ref_clk",
2136			.parent_names = (const char *[]){
2137				"tsif_ref_clk_src",
2138			},
2139			.num_parents = 1,
2140			.flags = CLK_SET_RATE_PARENT,
2141			.ops = &clk_branch2_ops,
2142		},
2143	},
2144};
2145
2146static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2147	.halt_reg = 0x04ac,
2148	.clkr = {
2149		.enable_reg = 0x04ac,
2150		.enable_mask = BIT(0),
2151		.hw.init = &(struct clk_init_data){
2152			.name = "gcc_usb2a_phy_sleep_clk",
2153			.parent_names = (const char *[]){
2154				"sleep_clk_src",
2155			},
2156			.num_parents = 1,
2157			.ops = &clk_branch2_ops,
2158		},
2159	},
2160};
2161
2162static struct clk_branch gcc_usb2b_phy_sleep_clk = {
2163	.halt_reg = 0x04b4,
2164	.clkr = {
2165		.enable_reg = 0x04b4,
2166		.enable_mask = BIT(0),
2167		.hw.init = &(struct clk_init_data){
2168			.name = "gcc_usb2b_phy_sleep_clk",
2169			.parent_names = (const char *[]){
2170				"sleep_clk_src",
2171			},
2172			.num_parents = 1,
2173			.ops = &clk_branch2_ops,
2174		},
2175	},
2176};
2177
2178static struct clk_branch gcc_usb30_master_clk = {
2179	.halt_reg = 0x03c8,
2180	.clkr = {
2181		.enable_reg = 0x03c8,
2182		.enable_mask = BIT(0),
2183		.hw.init = &(struct clk_init_data){
2184			.name = "gcc_usb30_master_clk",
2185			.parent_names = (const char *[]){
2186				"usb30_master_clk_src",
2187			},
2188			.num_parents = 1,
2189			.flags = CLK_SET_RATE_PARENT,
2190			.ops = &clk_branch2_ops,
2191		},
2192	},
2193};
2194
2195static struct clk_branch gcc_usb30_mock_utmi_clk = {
2196	.halt_reg = 0x03d0,
2197	.clkr = {
2198		.enable_reg = 0x03d0,
2199		.enable_mask = BIT(0),
2200		.hw.init = &(struct clk_init_data){
2201			.name = "gcc_usb30_mock_utmi_clk",
2202			.parent_names = (const char *[]){
2203				"usb30_mock_utmi_clk_src",
2204			},
2205			.num_parents = 1,
2206			.flags = CLK_SET_RATE_PARENT,
2207			.ops = &clk_branch2_ops,
2208		},
2209	},
2210};
2211
2212static struct clk_branch gcc_usb30_sleep_clk = {
2213	.halt_reg = 0x03cc,
2214	.clkr = {
2215		.enable_reg = 0x03cc,
2216		.enable_mask = BIT(0),
2217		.hw.init = &(struct clk_init_data){
2218			.name = "gcc_usb30_sleep_clk",
2219			.parent_names = (const char *[]){
2220				"sleep_clk_src",
2221			},
2222			.num_parents = 1,
2223			.ops = &clk_branch2_ops,
2224		},
2225	},
2226};
2227
2228static struct clk_branch gcc_usb_hs_ahb_clk = {
2229	.halt_reg = 0x0488,
2230	.clkr = {
2231		.enable_reg = 0x0488,
2232		.enable_mask = BIT(0),
2233		.hw.init = &(struct clk_init_data){
2234			.name = "gcc_usb_hs_ahb_clk",
2235			.parent_names = (const char *[]){
2236				"periph_noc_clk_src",
2237			},
2238			.num_parents = 1,
2239			.ops = &clk_branch2_ops,
2240		},
2241	},
2242};
2243
2244static struct clk_branch gcc_usb_hs_system_clk = {
2245	.halt_reg = 0x0484,
2246	.clkr = {
2247		.enable_reg = 0x0484,
2248		.enable_mask = BIT(0),
2249		.hw.init = &(struct clk_init_data){
2250			.name = "gcc_usb_hs_system_clk",
2251			.parent_names = (const char *[]){
2252				"usb_hs_system_clk_src",
2253			},
2254			.num_parents = 1,
2255			.flags = CLK_SET_RATE_PARENT,
2256			.ops = &clk_branch2_ops,
2257		},
2258	},
2259};
2260
2261static struct clk_branch gcc_usb_hsic_ahb_clk = {
2262	.halt_reg = 0x0408,
2263	.clkr = {
2264		.enable_reg = 0x0408,
2265		.enable_mask = BIT(0),
2266		.hw.init = &(struct clk_init_data){
2267			.name = "gcc_usb_hsic_ahb_clk",
2268			.parent_names = (const char *[]){
2269				"periph_noc_clk_src",
2270			},
2271			.num_parents = 1,
2272			.ops = &clk_branch2_ops,
2273		},
2274	},
2275};
2276
2277static struct clk_branch gcc_usb_hsic_clk = {
2278	.halt_reg = 0x0410,
2279	.clkr = {
2280		.enable_reg = 0x0410,
2281		.enable_mask = BIT(0),
2282		.hw.init = &(struct clk_init_data){
2283			.name = "gcc_usb_hsic_clk",
2284			.parent_names = (const char *[]){
2285				"usb_hsic_clk_src",
2286			},
2287			.num_parents = 1,
2288			.flags = CLK_SET_RATE_PARENT,
2289			.ops = &clk_branch2_ops,
2290		},
2291	},
2292};
2293
2294static struct clk_branch gcc_usb_hsic_io_cal_clk = {
2295	.halt_reg = 0x0414,
2296	.clkr = {
2297		.enable_reg = 0x0414,
2298		.enable_mask = BIT(0),
2299		.hw.init = &(struct clk_init_data){
2300			.name = "gcc_usb_hsic_io_cal_clk",
2301			.parent_names = (const char *[]){
2302				"usb_hsic_io_cal_clk_src",
2303			},
2304			.num_parents = 1,
2305			.flags = CLK_SET_RATE_PARENT,
2306			.ops = &clk_branch2_ops,
2307		},
2308	},
2309};
2310
2311static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
2312	.halt_reg = 0x0418,
2313	.clkr = {
2314		.enable_reg = 0x0418,
2315		.enable_mask = BIT(0),
2316		.hw.init = &(struct clk_init_data){
2317			.name = "gcc_usb_hsic_io_cal_sleep_clk",
2318			.parent_names = (const char *[]){
2319				"sleep_clk_src",
2320			},
2321			.num_parents = 1,
2322			.ops = &clk_branch2_ops,
2323		},
2324	},
2325};
2326
2327static struct clk_branch gcc_usb_hsic_system_clk = {
2328	.halt_reg = 0x040c,
2329	.clkr = {
2330		.enable_reg = 0x040c,
2331		.enable_mask = BIT(0),
2332		.hw.init = &(struct clk_init_data){
2333			.name = "gcc_usb_hsic_system_clk",
2334			.parent_names = (const char *[]){
2335				"usb_hsic_system_clk_src",
2336			},
2337			.num_parents = 1,
2338			.flags = CLK_SET_RATE_PARENT,
2339			.ops = &clk_branch2_ops,
2340		},
2341	},
2342};
2343
 
 
 
 
 
 
 
 
2344static struct clk_regmap *gcc_msm8974_clocks[] = {
2345	[GPLL0] = &gpll0.clkr,
2346	[GPLL0_VOTE] = &gpll0_vote,
2347	[CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
2348	[PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
2349	[SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
2350	[GPLL1] = &gpll1.clkr,
2351	[GPLL1_VOTE] = &gpll1_vote,
2352	[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2353	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2354	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2355	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2356	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2357	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2358	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2359	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2360	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2361	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2362	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2363	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2364	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2365	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2366	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2367	[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2368	[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2369	[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2370	[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2371	[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2372	[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2373	[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2374	[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2375	[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2376	[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2377	[BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2378	[BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2379	[BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2380	[BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2381	[BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2382	[BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2383	[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2384	[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2385	[BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2386	[BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2387	[BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2388	[BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2389	[CE1_CLK_SRC] = &ce1_clk_src.clkr,
2390	[CE2_CLK_SRC] = &ce2_clk_src.clkr,
2391	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
2392	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
2393	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
2394	[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2395	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2396	[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2397	[SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2398	[SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2399	[TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2400	[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2401	[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2402	[USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
2403	[USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
2404	[USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
2405	[GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
2406	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2407	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2408	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2409	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2410	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2411	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2412	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2413	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2414	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2415	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2416	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2417	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2418	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2419	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2420	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2421	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2422	[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2423	[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2424	[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2425	[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2426	[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2427	[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2428	[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2429	[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2430	[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2431	[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2432	[GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2433	[GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2434	[GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2435	[GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2436	[GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2437	[GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2438	[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2439	[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2440	[GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2441	[GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2442	[GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2443	[GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2444	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2445	[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2446	[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2447	[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2448	[GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr,
2449	[GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr,
2450	[GCC_CE2_CLK] = &gcc_ce2_clk.clkr,
2451	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2452	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2453	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2454	[GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
2455	[GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
2456	[GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr,
2457	[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2458	[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2459	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2460	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2461	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2462	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2463	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2464	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2465	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2466	[GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
2467	[GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2468	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2469	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2470	[GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2471	[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2472	[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2473	[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2474	[GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr,
2475	[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2476	[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2477	[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2478	[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2479	[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2480	[GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
2481	[GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
2482	[GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
2483	[GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
2484	[GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
2485	[GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src,
 
 
 
 
2486};
2487
2488static const struct qcom_reset_map gcc_msm8974_resets[] = {
2489	[GCC_SYSTEM_NOC_BCR] = { 0x0100 },
2490	[GCC_CONFIG_NOC_BCR] = { 0x0140 },
2491	[GCC_PERIPH_NOC_BCR] = { 0x0180 },
2492	[GCC_IMEM_BCR] = { 0x0200 },
2493	[GCC_MMSS_BCR] = { 0x0240 },
2494	[GCC_QDSS_BCR] = { 0x0300 },
2495	[GCC_USB_30_BCR] = { 0x03c0 },
2496	[GCC_USB3_PHY_BCR] = { 0x03fc },
2497	[GCC_USB_HS_HSIC_BCR] = { 0x0400 },
2498	[GCC_USB_HS_BCR] = { 0x0480 },
2499	[GCC_USB2A_PHY_BCR] = { 0x04a8 },
2500	[GCC_USB2B_PHY_BCR] = { 0x04b0 },
2501	[GCC_SDCC1_BCR] = { 0x04c0 },
2502	[GCC_SDCC2_BCR] = { 0x0500 },
2503	[GCC_SDCC3_BCR] = { 0x0540 },
2504	[GCC_SDCC4_BCR] = { 0x0580 },
2505	[GCC_BLSP1_BCR] = { 0x05c0 },
2506	[GCC_BLSP1_QUP1_BCR] = { 0x0640 },
2507	[GCC_BLSP1_UART1_BCR] = { 0x0680 },
2508	[GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
2509	[GCC_BLSP1_UART2_BCR] = { 0x0700 },
2510	[GCC_BLSP1_QUP3_BCR] = { 0x0740 },
2511	[GCC_BLSP1_UART3_BCR] = { 0x0780 },
2512	[GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
2513	[GCC_BLSP1_UART4_BCR] = { 0x0800 },
2514	[GCC_BLSP1_QUP5_BCR] = { 0x0840 },
2515	[GCC_BLSP1_UART5_BCR] = { 0x0880 },
2516	[GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
2517	[GCC_BLSP1_UART6_BCR] = { 0x0900 },
2518	[GCC_BLSP2_BCR] = { 0x0940 },
2519	[GCC_BLSP2_QUP1_BCR] = { 0x0980 },
2520	[GCC_BLSP2_UART1_BCR] = { 0x09c0 },
2521	[GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
2522	[GCC_BLSP2_UART2_BCR] = { 0x0a40 },
2523	[GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
2524	[GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
2525	[GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
2526	[GCC_BLSP2_UART4_BCR] = { 0x0b40 },
2527	[GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
2528	[GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
2529	[GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
2530	[GCC_BLSP2_UART6_BCR] = { 0x0c40 },
2531	[GCC_PDM_BCR] = { 0x0cc0 },
2532	[GCC_BAM_DMA_BCR] = { 0x0d40 },
2533	[GCC_TSIF_BCR] = { 0x0d80 },
2534	[GCC_TCSR_BCR] = { 0x0dc0 },
2535	[GCC_BOOT_ROM_BCR] = { 0x0e00 },
2536	[GCC_MSG_RAM_BCR] = { 0x0e40 },
2537	[GCC_TLMM_BCR] = { 0x0e80 },
2538	[GCC_MPM_BCR] = { 0x0ec0 },
2539	[GCC_SEC_CTRL_BCR] = { 0x0f40 },
2540	[GCC_SPMI_BCR] = { 0x0fc0 },
2541	[GCC_SPDM_BCR] = { 0x1000 },
2542	[GCC_CE1_BCR] = { 0x1040 },
2543	[GCC_CE2_BCR] = { 0x1080 },
2544	[GCC_BIMC_BCR] = { 0x1100 },
2545	[GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
2546	[GCC_MPM_AHB_RESET] = {	0x0ec4, 1 },
2547	[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
2548	[GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
2549	[GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
2550	[GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
2551	[GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
2552	[GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
2553	[GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
2554	[GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
2555	[GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
2556	[GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
2557	[GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
2558	[GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
2559	[GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
2560	[GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
2561	[GCC_DEHR_BCR] = { 0x1300 },
2562	[GCC_RBCPR_BCR] = { 0x1380 },
2563	[GCC_MSS_RESTART] = { 0x1680 },
2564	[GCC_LPASS_RESTART] = { 0x16c0 },
2565	[GCC_WCSS_RESTART] = { 0x1700 },
2566	[GCC_VENUS_RESTART] = { 0x1740 },
2567};
2568
 
 
 
 
2569static const struct regmap_config gcc_msm8974_regmap_config = {
2570	.reg_bits	= 32,
2571	.reg_stride	= 4,
2572	.val_bits	= 32,
2573	.max_register	= 0x1fc0,
2574	.fast_io	= true,
2575};
2576
 
 
 
 
 
 
 
 
 
 
2577static const struct of_device_id gcc_msm8974_match_table[] = {
2578	{ .compatible = "qcom,gcc-msm8974" },
 
 
2579	{ }
2580};
2581MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table);
2582
2583struct qcom_cc {
2584	struct qcom_reset_controller reset;
2585	struct clk_onecell_data data;
2586	struct clk *clks[];
2587};
 
 
 
 
 
 
 
 
 
2588
2589static int gcc_msm8974_probe(struct platform_device *pdev)
2590{
2591	void __iomem *base;
2592	struct resource *res;
2593	int i, ret;
2594	struct device *dev = &pdev->dev;
2595	struct clk *clk;
2596	struct clk_onecell_data *data;
2597	struct clk **clks;
2598	struct regmap *regmap;
2599	size_t num_clks;
2600	struct qcom_reset_controller *reset;
2601	struct qcom_cc *cc;
2602
2603	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2604	base = devm_ioremap_resource(dev, res);
2605	if (IS_ERR(base))
2606		return PTR_ERR(base);
2607
2608	regmap = devm_regmap_init_mmio(dev, base, &gcc_msm8974_regmap_config);
2609	if (IS_ERR(regmap))
2610		return PTR_ERR(regmap);
2611
2612	num_clks = ARRAY_SIZE(gcc_msm8974_clocks);
2613	cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2614			  GFP_KERNEL);
2615	if (!cc)
2616		return -ENOMEM;
2617
2618	clks = cc->clks;
2619	data = &cc->data;
2620	data->clks = clks;
2621	data->clk_num = num_clks;
2622
2623	/* Temporary until RPM clocks supported */
2624	clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
2625	if (IS_ERR(clk))
2626		return PTR_ERR(clk);
2627
2628	/* Should move to DT node? */
2629	clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
2630				      CLK_IS_ROOT, 32768);
2631	if (IS_ERR(clk))
2632		return PTR_ERR(clk);
2633
2634	for (i = 0; i < num_clks; i++) {
2635		if (!gcc_msm8974_clocks[i])
2636			continue;
2637		clk = devm_clk_register_regmap(dev, gcc_msm8974_clocks[i]);
2638		if (IS_ERR(clk))
2639			return PTR_ERR(clk);
2640		clks[i] = clk;
2641	}
2642
2643	ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2644	if (ret)
2645		return ret;
 
2646
2647	reset = &cc->reset;
2648	reset->rcdev.of_node = dev->of_node;
2649	reset->rcdev.ops = &qcom_reset_ops,
2650	reset->rcdev.owner = THIS_MODULE,
2651	reset->rcdev.nr_resets = ARRAY_SIZE(gcc_msm8974_resets),
2652	reset->regmap = regmap;
2653	reset->reset_map = gcc_msm8974_resets,
2654	platform_set_drvdata(pdev, &reset->rcdev);
2655
2656	ret = reset_controller_register(&reset->rcdev);
2657	if (ret)
2658		of_clk_del_provider(dev->of_node);
2659
2660	return ret;
2661}
 
2662
2663static int gcc_msm8974_remove(struct platform_device *pdev)
2664{
2665	of_clk_del_provider(pdev->dev.of_node);
2666	reset_controller_unregister(platform_get_drvdata(pdev));
2667	return 0;
2668}
2669
2670static struct platform_driver gcc_msm8974_driver = {
2671	.probe		= gcc_msm8974_probe,
2672	.remove		= gcc_msm8974_remove,
2673	.driver		= {
2674		.name	= "gcc-msm8974",
2675		.owner	= THIS_MODULE,
2676		.of_match_table = gcc_msm8974_match_table,
2677	},
2678};
2679
2680static int __init gcc_msm8974_init(void)
2681{
2682	return platform_driver_register(&gcc_msm8974_driver);
2683}
2684core_initcall(gcc_msm8974_init);
2685
2686static void __exit gcc_msm8974_exit(void)
2687{
2688	platform_driver_unregister(&gcc_msm8974_driver);
2689}
2690module_exit(gcc_msm8974_exit);
2691
2692MODULE_DESCRIPTION("QCOM GCC MSM8974 Driver");
2693MODULE_LICENSE("GPL v2");
2694MODULE_ALIAS("platform:gcc-msm8974");