1/*
   2 * Copyright 2015 Linaro Limited
   3 *
   4 * This software is licensed under the terms of the GNU General Public
   5 * License version 2, as published by the Free Software Foundation, and
   6 * may be copied, distributed, and modified under those terms.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 */
  13
  14#include <linux/kernel.h>
  15#include <linux/bitops.h>
  16#include <linux/err.h>
  17#include <linux/platform_device.h>
  18#include <linux/module.h>
  19#include <linux/of.h>
  20#include <linux/of_device.h>
  21#include <linux/clk-provider.h>
  22#include <linux/regmap.h>
  23#include <linux/reset-controller.h>
  24
  25#include <dt-bindings/clock/qcom,gcc-msm8916.h>
  26#include <dt-bindings/reset/qcom,gcc-msm8916.h>
  27
  28#include "common.h"
  29#include "clk-regmap.h"
  30#include "clk-pll.h"
  31#include "clk-rcg.h"
  32#include "clk-branch.h"
  33#include "reset.h"
  34#include "gdsc.h"
  35
  36enum {
  37	P_XO,
  38	P_GPLL0,
  39	P_GPLL0_AUX,
  40	P_BIMC,
  41	P_GPLL1,
  42	P_GPLL1_AUX,
  43	P_GPLL2,
  44	P_GPLL2_AUX,
  45	P_SLEEP_CLK,
  46	P_DSI0_PHYPLL_BYTE,
  47	P_DSI0_PHYPLL_DSI,
  48	P_EXT_PRI_I2S,
  49	P_EXT_SEC_I2S,
  50	P_EXT_MCLK,
  51};
  52
  53static const struct parent_map gcc_xo_gpll0_map[] = {
  54	{ P_XO, 0 },
  55	{ P_GPLL0, 1 },
  56};
  57
  58static const char * const gcc_xo_gpll0[] = {
  59	"xo",
  60	"gpll0_vote",
  61};
  62
  63static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
  64	{ P_XO, 0 },
  65	{ P_GPLL0, 1 },
  66	{ P_BIMC, 2 },
  67};
  68
  69static const char * const gcc_xo_gpll0_bimc[] = {
  70	"xo",
  71	"gpll0_vote",
  72	"bimc_pll_vote",
  73};
  74
  75static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {
  76	{ P_XO, 0 },
  77	{ P_GPLL0_AUX, 3 },
  78	{ P_GPLL1, 1 },
  79	{ P_GPLL2_AUX, 2 },
  80};
  81
  82static const char * const gcc_xo_gpll0a_gpll1_gpll2a[] = {
  83	"xo",
  84	"gpll0_vote",
  85	"gpll1_vote",
  86	"gpll2_vote",
  87};
  88
  89static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
  90	{ P_XO, 0 },
  91	{ P_GPLL0, 1 },
  92	{ P_GPLL2, 2 },
  93};
  94
  95static const char * const gcc_xo_gpll0_gpll2[] = {
  96	"xo",
  97	"gpll0_vote",
  98	"gpll2_vote",
  99};
 100
 101static const struct parent_map gcc_xo_gpll0a_map[] = {
 102	{ P_XO, 0 },
 103	{ P_GPLL0_AUX, 2 },
 104};
 105
 106static const char * const gcc_xo_gpll0a[] = {
 107	"xo",
 108	"gpll0_vote",
 109};
 110
 111static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
 112	{ P_XO, 0 },
 113	{ P_GPLL0, 1 },
 114	{ P_GPLL1_AUX, 2 },
 115	{ P_SLEEP_CLK, 6 },
 116};
 117
 118static const char * const gcc_xo_gpll0_gpll1a_sleep[] = {
 119	"xo",
 120	"gpll0_vote",
 121	"gpll1_vote",
 122	"sleep_clk",
 123};
 124
 125static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
 126	{ P_XO, 0 },
 127	{ P_GPLL0, 1 },
 128	{ P_GPLL1_AUX, 2 },
 129};
 130
 131static const char * const gcc_xo_gpll0_gpll1a[] = {
 132	"xo",
 133	"gpll0_vote",
 134	"gpll1_vote",
 135};
 136
 137static const struct parent_map gcc_xo_dsibyte_map[] = {
 138	{ P_XO, 0, },
 139	{ P_DSI0_PHYPLL_BYTE, 2 },
 140};
 141
 142static const char * const gcc_xo_dsibyte[] = {
 143	"xo",
 144	"dsi0pllbyte",
 145};
 146
 147static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
 148	{ P_XO, 0 },
 149	{ P_GPLL0_AUX, 2 },
 150	{ P_DSI0_PHYPLL_BYTE, 1 },
 151};
 152
 153static const char * const gcc_xo_gpll0a_dsibyte[] = {
 154	"xo",
 155	"gpll0_vote",
 156	"dsi0pllbyte",
 157};
 158
 159static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = {
 160	{ P_XO, 0 },
 161	{ P_GPLL0, 1 },
 162	{ P_DSI0_PHYPLL_DSI, 2 },
 163};
 164
 165static const char * const gcc_xo_gpll0_dsiphy[] = {
 166	"xo",
 167	"gpll0_vote",
 168	"dsi0pll",
 169};
 170
 171static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
 172	{ P_XO, 0 },
 173	{ P_GPLL0_AUX, 2 },
 174	{ P_DSI0_PHYPLL_DSI, 1 },
 175};
 176
 177static const char * const gcc_xo_gpll0a_dsiphy[] = {
 178	"xo",
 179	"gpll0_vote",
 180	"dsi0pll",
 181};
 182
 183static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = {
 184	{ P_XO, 0 },
 185	{ P_GPLL0_AUX, 1 },
 186	{ P_GPLL1, 3 },
 187	{ P_GPLL2, 2 },
 188};
 189
 190static const char * const gcc_xo_gpll0a_gpll1_gpll2[] = {
 191	"xo",
 192	"gpll0_vote",
 193	"gpll1_vote",
 194	"gpll2_vote",
 195};
 196
 197static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
 198	{ P_XO, 0 },
 199	{ P_GPLL0, 1 },
 200	{ P_GPLL1, 2 },
 201	{ P_SLEEP_CLK, 6 }
 202};
 203
 204static const char * const gcc_xo_gpll0_gpll1_sleep[] = {
 205	"xo",
 206	"gpll0_vote",
 207	"gpll1_vote",
 208	"sleep_clk",
 209};
 210
 211static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
 212	{ P_XO, 0 },
 213	{ P_GPLL1, 1 },
 214	{ P_EXT_PRI_I2S, 2 },
 215	{ P_EXT_MCLK, 3 },
 216	{ P_SLEEP_CLK, 6 }
 217};
 218
 219static const char * const gcc_xo_gpll1_epi2s_emclk_sleep[] = {
 220	"xo",
 221	"gpll1_vote",
 222	"ext_pri_i2s",
 223	"ext_mclk",
 224	"sleep_clk",
 225};
 226
 227static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
 228	{ P_XO, 0 },
 229	{ P_GPLL1, 1 },
 230	{ P_EXT_SEC_I2S, 2 },
 231	{ P_EXT_MCLK, 3 },
 232	{ P_SLEEP_CLK, 6 }
 233};
 234
 235static const char * const gcc_xo_gpll1_esi2s_emclk_sleep[] = {
 236	"xo",
 237	"gpll1_vote",
 238	"ext_sec_i2s",
 239	"ext_mclk",
 240	"sleep_clk",
 241};
 242
 243static const struct parent_map gcc_xo_sleep_map[] = {
 244	{ P_XO, 0 },
 245	{ P_SLEEP_CLK, 6 }
 246};
 247
 248static const char * const gcc_xo_sleep[] = {
 249	"xo",
 250	"sleep_clk",
 251};
 252
 253static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
 254	{ P_XO, 0 },
 255	{ P_GPLL1, 1 },
 256	{ P_EXT_MCLK, 2 },
 257	{ P_SLEEP_CLK, 6 }
 258};
 259
 260static const char * const gcc_xo_gpll1_emclk_sleep[] = {
 261	"xo",
 262	"gpll1_vote",
 263	"ext_mclk",
 264	"sleep_clk",
 265};
 266
 267#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 268
 269static struct clk_pll gpll0 = {
 270	.l_reg = 0x21004,
 271	.m_reg = 0x21008,
 272	.n_reg = 0x2100c,
 273	.config_reg = 0x21014,
 274	.mode_reg = 0x21000,
 275	.status_reg = 0x2101c,
 276	.status_bit = 17,
 277	.clkr.hw.init = &(struct clk_init_data){
 278		.name = "gpll0",
 279		.parent_names = (const char *[]){ "xo" },
 280		.num_parents = 1,
 281		.ops = &clk_pll_ops,
 282	},
 283};
 284
 285static struct clk_regmap gpll0_vote = {
 286	.enable_reg = 0x45000,
 287	.enable_mask = BIT(0),
 288	.hw.init = &(struct clk_init_data){
 289		.name = "gpll0_vote",
 290		.parent_names = (const char *[]){ "gpll0" },
 291		.num_parents = 1,
 292		.ops = &clk_pll_vote_ops,
 293	},
 294};
 295
 296static struct clk_pll gpll1 = {
 297	.l_reg = 0x20004,
 298	.m_reg = 0x20008,
 299	.n_reg = 0x2000c,
 300	.config_reg = 0x20014,
 301	.mode_reg = 0x20000,
 302	.status_reg = 0x2001c,
 303	.status_bit = 17,
 304	.clkr.hw.init = &(struct clk_init_data){
 305		.name = "gpll1",
 306		.parent_names = (const char *[]){ "xo" },
 307		.num_parents = 1,
 308		.ops = &clk_pll_ops,
 309	},
 310};
 311
 312static struct clk_regmap gpll1_vote = {
 313	.enable_reg = 0x45000,
 314	.enable_mask = BIT(1),
 315	.hw.init = &(struct clk_init_data){
 316		.name = "gpll1_vote",
 317		.parent_names = (const char *[]){ "gpll1" },
 318		.num_parents = 1,
 319		.ops = &clk_pll_vote_ops,
 320	},
 321};
 322
 323static struct clk_pll gpll2 = {
 324	.l_reg = 0x4a004,
 325	.m_reg = 0x4a008,
 326	.n_reg = 0x4a00c,
 327	.config_reg = 0x4a014,
 328	.mode_reg = 0x4a000,
 329	.status_reg = 0x4a01c,
 330	.status_bit = 17,
 331	.clkr.hw.init = &(struct clk_init_data){
 332		.name = "gpll2",
 333		.parent_names = (const char *[]){ "xo" },
 334		.num_parents = 1,
 335		.ops = &clk_pll_ops,
 336	},
 337};
 338
 339static struct clk_regmap gpll2_vote = {
 340	.enable_reg = 0x45000,
 341	.enable_mask = BIT(2),
 342	.hw.init = &(struct clk_init_data){
 343		.name = "gpll2_vote",
 344		.parent_names = (const char *[]){ "gpll2" },
 345		.num_parents = 1,
 346		.ops = &clk_pll_vote_ops,
 347	},
 348};
 349
 350static struct clk_pll bimc_pll = {
 351	.l_reg = 0x23004,
 352	.m_reg = 0x23008,
 353	.n_reg = 0x2300c,
 354	.config_reg = 0x23014,
 355	.mode_reg = 0x23000,
 356	.status_reg = 0x2301c,
 357	.status_bit = 17,
 358	.clkr.hw.init = &(struct clk_init_data){
 359		.name = "bimc_pll",
 360		.parent_names = (const char *[]){ "xo" },
 361		.num_parents = 1,
 362		.ops = &clk_pll_ops,
 363	},
 364};
 365
 366static struct clk_regmap bimc_pll_vote = {
 367	.enable_reg = 0x45000,
 368	.enable_mask = BIT(3),
 369	.hw.init = &(struct clk_init_data){
 370		.name = "bimc_pll_vote",
 371		.parent_names = (const char *[]){ "bimc_pll" },
 372		.num_parents = 1,
 373		.ops = &clk_pll_vote_ops,
 374	},
 375};
 376
 377static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 378	.cmd_rcgr = 0x27000,
 379	.hid_width = 5,
 380	.parent_map = gcc_xo_gpll0_bimc_map,
 381	.clkr.hw.init = &(struct clk_init_data){
 382		.name = "pcnoc_bfdcd_clk_src",
 383		.parent_names = gcc_xo_gpll0_bimc,
 384		.num_parents = 3,
 385		.ops = &clk_rcg2_ops,
 386	},
 387};
 388
 389static struct clk_rcg2 system_noc_bfdcd_clk_src = {
 390	.cmd_rcgr = 0x26004,
 391	.hid_width = 5,
 392	.parent_map = gcc_xo_gpll0_bimc_map,
 393	.clkr.hw.init = &(struct clk_init_data){
 394		.name = "system_noc_bfdcd_clk_src",
 395		.parent_names = gcc_xo_gpll0_bimc,
 396		.num_parents = 3,
 397		.ops = &clk_rcg2_ops,
 398	},
 399};
 400
 401static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
 402	F(40000000, P_GPLL0, 10, 1, 2),
 403	F(80000000, P_GPLL0, 10, 0, 0),
 404	{ }
 405};
 406
 407static struct clk_rcg2 camss_ahb_clk_src = {
 408	.cmd_rcgr = 0x5a000,
 409	.mnd_width = 8,
 410	.hid_width = 5,
 411	.parent_map = gcc_xo_gpll0_map,
 412	.freq_tbl = ftbl_gcc_camss_ahb_clk,
 413	.clkr.hw.init = &(struct clk_init_data){
 414		.name = "camss_ahb_clk_src",
 415		.parent_names = gcc_xo_gpll0,
 416		.num_parents = 2,
 417		.ops = &clk_rcg2_ops,
 418	},
 419};
 420
 421static const struct freq_tbl ftbl_apss_ahb_clk[] = {
 422	F(19200000, P_XO, 1, 0, 0),
 423	F(50000000, P_GPLL0, 16, 0, 0),
 424	F(100000000, P_GPLL0, 8, 0, 0),
 425	F(133330000, P_GPLL0, 6, 0, 0),
 426	{ }
 427};
 428
 429static struct clk_rcg2 apss_ahb_clk_src = {
 430	.cmd_rcgr = 0x46000,
 431	.hid_width = 5,
 432	.parent_map = gcc_xo_gpll0_map,
 433	.freq_tbl = ftbl_apss_ahb_clk,
 434	.clkr.hw.init = &(struct clk_init_data){
 435		.name = "apss_ahb_clk_src",
 436		.parent_names = gcc_xo_gpll0,
 437		.num_parents = 2,
 438		.ops = &clk_rcg2_ops,
 439	},
 440};
 441
 442static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
 443	F(100000000, P_GPLL0, 8, 0,	0),
 444	F(200000000, P_GPLL0, 4, 0,	0),
 445	{ }
 446};
 447
 448static struct clk_rcg2 csi0_clk_src = {
 449	.cmd_rcgr = 0x4e020,
 450	.hid_width = 5,
 451	.parent_map = gcc_xo_gpll0_map,
 452	.freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 453	.clkr.hw.init = &(struct clk_init_data){
 454		.name = "csi0_clk_src",
 455		.parent_names = gcc_xo_gpll0,
 456		.num_parents = 2,
 457		.ops = &clk_rcg2_ops,
 458	},
 459};
 460
 461static struct clk_rcg2 csi1_clk_src = {
 462	.cmd_rcgr = 0x4f020,
 463	.hid_width = 5,
 464	.parent_map = gcc_xo_gpll0_map,
 465	.freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 466	.clkr.hw.init = &(struct clk_init_data){
 467		.name = "csi1_clk_src",
 468		.parent_names = gcc_xo_gpll0,
 469		.num_parents = 2,
 470		.ops = &clk_rcg2_ops,
 471	},
 472};
 473
 474static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
 475	F(19200000, P_XO, 1, 0, 0),
 476	F(50000000, P_GPLL0_AUX, 16, 0, 0),
 477	F(80000000, P_GPLL0_AUX, 10, 0, 0),
 478	F(100000000, P_GPLL0_AUX, 8, 0, 0),
 479	F(160000000, P_GPLL0_AUX, 5, 0, 0),
 480	F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
 481	F(200000000, P_GPLL0_AUX, 4, 0, 0),
 482	F(266670000, P_GPLL0_AUX, 3, 0, 0),
 483	F(294912000, P_GPLL1, 3, 0, 0),
 484	F(310000000, P_GPLL2, 3, 0, 0),
 485	F(400000000, P_GPLL0_AUX, 2, 0, 0),
 486	{ }
 487};
 488
 489static struct clk_rcg2 gfx3d_clk_src = {
 490	.cmd_rcgr = 0x59000,
 491	.hid_width = 5,
 492	.parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map,
 493	.freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
 494	.clkr.hw.init = &(struct clk_init_data){
 495		.name = "gfx3d_clk_src",
 496		.parent_names = gcc_xo_gpll0a_gpll1_gpll2a,
 497		.num_parents = 4,
 498		.ops = &clk_rcg2_ops,
 499	},
 500};
 501
 502static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
 503	F(50000000, P_GPLL0, 16, 0, 0),
 504	F(80000000, P_GPLL0, 10, 0, 0),
 505	F(100000000, P_GPLL0, 8, 0, 0),
 506	F(160000000, P_GPLL0, 5, 0, 0),
 507	F(177780000, P_GPLL0, 4.5, 0, 0),
 508	F(200000000, P_GPLL0, 4, 0, 0),
 509	F(266670000, P_GPLL0, 3, 0, 0),
 510	F(320000000, P_GPLL0, 2.5, 0, 0),
 511	F(400000000, P_GPLL0, 2, 0, 0),
 512	F(465000000, P_GPLL2, 2, 0, 0),
 513	{ }
 514};
 515
 516static struct clk_rcg2 vfe0_clk_src = {
 517	.cmd_rcgr = 0x58000,
 518	.hid_width = 5,
 519	.parent_map = gcc_xo_gpll0_gpll2_map,
 520	.freq_tbl = ftbl_gcc_camss_vfe0_clk,
 521	.clkr.hw.init = &(struct clk_init_data){
 522		.name = "vfe0_clk_src",
 523		.parent_names = gcc_xo_gpll0_gpll2,
 524		.num_parents = 3,
 525		.ops = &clk_rcg2_ops,
 526	},
 527};
 528
 529static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
 530	F(19200000, P_XO, 1, 0, 0),
 531	F(50000000, P_GPLL0, 16, 0, 0),
 532	{ }
 533};
 534
 535static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 536	.cmd_rcgr = 0x0200c,
 537	.hid_width = 5,
 538	.parent_map = gcc_xo_gpll0_map,
 539	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 540	.clkr.hw.init = &(struct clk_init_data){
 541		.name = "blsp1_qup1_i2c_apps_clk_src",
 542		.parent_names = gcc_xo_gpll0,
 543		.num_parents = 2,
 544		.ops = &clk_rcg2_ops,
 545	},
 546};
 547
 548static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
 549	F(960000, P_XO, 10, 1, 2),
 550	F(4800000, P_XO, 4, 0, 0),
 551	F(9600000, P_XO, 2, 0, 0),
 552	F(16000000, P_GPLL0, 10, 1, 5),
 553	F(19200000, P_XO, 1, 0, 0),
 554	F(25000000, P_GPLL0, 16, 1, 2),
 555	F(50000000, P_GPLL0, 16, 0, 0),
 556	{ }
 557};
 558
 559static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 560	.cmd_rcgr = 0x02024,
 561	.mnd_width = 8,
 562	.hid_width = 5,
 563	.parent_map = gcc_xo_gpll0_map,
 564	.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 565	.clkr.hw.init = &(struct clk_init_data){
 566		.name = "blsp1_qup1_spi_apps_clk_src",
 567		.parent_names = gcc_xo_gpll0,
 568		.num_parents = 2,
 569		.ops = &clk_rcg2_ops,
 570	},
 571};
 572
 573static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 574	.cmd_rcgr = 0x03000,
 575	.hid_width = 5,
 576	.parent_map = gcc_xo_gpll0_map,
 577	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 578	.clkr.hw.init = &(struct clk_init_data){
 579		.name = "blsp1_qup2_i2c_apps_clk_src",
 580		.parent_names = gcc_xo_gpll0,
 581		.num_parents = 2,
 582		.ops = &clk_rcg2_ops,
 583	},
 584};
 585
 586static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 587	.cmd_rcgr = 0x03014,
 588	.mnd_width = 8,
 589	.hid_width = 5,
 590	.parent_map = gcc_xo_gpll0_map,
 591	.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 592	.clkr.hw.init = &(struct clk_init_data){
 593		.name = "blsp1_qup2_spi_apps_clk_src",
 594		.parent_names = gcc_xo_gpll0,
 595		.num_parents = 2,
 596		.ops = &clk_rcg2_ops,
 597	},
 598};
 599
 600static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 601	.cmd_rcgr = 0x04000,
 602	.hid_width = 5,
 603	.parent_map = gcc_xo_gpll0_map,
 604	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 605	.clkr.hw.init = &(struct clk_init_data){
 606		.name = "blsp1_qup3_i2c_apps_clk_src",
 607		.parent_names = gcc_xo_gpll0,
 608		.num_parents = 2,
 609		.ops = &clk_rcg2_ops,
 610	},
 611};
 612
 613static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 614	.cmd_rcgr = 0x04024,
 615	.mnd_width = 8,
 616	.hid_width = 5,
 617	.parent_map = gcc_xo_gpll0_map,
 618	.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 619	.clkr.hw.init = &(struct clk_init_data){
 620		.name = "blsp1_qup3_spi_apps_clk_src",
 621		.parent_names = gcc_xo_gpll0,
 622		.num_parents = 2,
 623		.ops = &clk_rcg2_ops,
 624	},
 625};
 626
 627static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 628	.cmd_rcgr = 0x05000,
 629	.hid_width = 5,
 630	.parent_map = gcc_xo_gpll0_map,
 631	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 632	.clkr.hw.init = &(struct clk_init_data){
 633		.name = "blsp1_qup4_i2c_apps_clk_src",
 634		.parent_names = gcc_xo_gpll0,
 635		.num_parents = 2,
 636		.ops = &clk_rcg2_ops,
 637	},
 638};
 639
 640static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 641	.cmd_rcgr = 0x05024,
 642	.mnd_width = 8,
 643	.hid_width = 5,
 644	.parent_map = gcc_xo_gpll0_map,
 645	.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 646	.clkr.hw.init = &(struct clk_init_data){
 647		.name = "blsp1_qup4_spi_apps_clk_src",
 648		.parent_names = gcc_xo_gpll0,
 649		.num_parents = 2,
 650		.ops = &clk_rcg2_ops,
 651	},
 652};
 653
 654static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 655	.cmd_rcgr = 0x06000,
 656	.hid_width = 5,
 657	.parent_map = gcc_xo_gpll0_map,
 658	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 659	.clkr.hw.init = &(struct clk_init_data){
 660		.name = "blsp1_qup5_i2c_apps_clk_src",
 661		.parent_names = gcc_xo_gpll0,
 662		.num_parents = 2,
 663		.ops = &clk_rcg2_ops,
 664	},
 665};
 666
 667static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 668	.cmd_rcgr = 0x06024,
 669	.mnd_width = 8,
 670	.hid_width = 5,
 671	.parent_map = gcc_xo_gpll0_map,
 672	.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 673	.clkr.hw.init = &(struct clk_init_data){
 674		.name = "blsp1_qup5_spi_apps_clk_src",
 675		.parent_names = gcc_xo_gpll0,
 676		.num_parents = 2,
 677		.ops = &clk_rcg2_ops,
 678	},
 679};
 680
 681static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 682	.cmd_rcgr = 0x07000,
 683	.hid_width = 5,
 684	.parent_map = gcc_xo_gpll0_map,
 685	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 686	.clkr.hw.init = &(struct clk_init_data){
 687		.name = "blsp1_qup6_i2c_apps_clk_src",
 688		.parent_names = gcc_xo_gpll0,
 689		.num_parents = 2,
 690		.ops = &clk_rcg2_ops,
 691	},
 692};
 693
 694static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 695	.cmd_rcgr = 0x07024,
 696	.mnd_width = 8,
 697	.hid_width = 5,
 698	.parent_map = gcc_xo_gpll0_map,
 699	.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 700	.clkr.hw.init = &(struct clk_init_data){
 701		.name = "blsp1_qup6_spi_apps_clk_src",
 702		.parent_names = gcc_xo_gpll0,
 703		.num_parents = 2,
 704		.ops = &clk_rcg2_ops,
 705	},
 706};
 707
 708static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
 709	F(3686400, P_GPLL0, 1, 72, 15625),
 710	F(7372800, P_GPLL0, 1, 144, 15625),
 711	F(14745600, P_GPLL0, 1, 288, 15625),
 712	F(16000000, P_GPLL0, 10, 1, 5),
 713	F(19200000, P_XO, 1, 0, 0),
 714	F(24000000, P_GPLL0, 1, 3, 100),
 715	F(25000000, P_GPLL0, 16, 1, 2),
 716	F(32000000, P_GPLL0, 1, 1, 25),
 717	F(40000000, P_GPLL0, 1, 1, 20),
 718	F(46400000, P_GPLL0, 1, 29, 500),
 719	F(48000000, P_GPLL0, 1, 3, 50),
 720	F(51200000, P_GPLL0, 1, 8, 125),
 721	F(56000000, P_GPLL0, 1, 7, 100),
 722	F(58982400, P_GPLL0, 1, 1152, 15625),
 723	F(60000000, P_GPLL0, 1, 3, 40),
 724	{ }
 725};
 726
 727static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 728	.cmd_rcgr = 0x02044,
 729	.mnd_width = 16,
 730	.hid_width = 5,
 731	.parent_map = gcc_xo_gpll0_map,
 732	.freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 733	.clkr.hw.init = &(struct clk_init_data){
 734		.name = "blsp1_uart1_apps_clk_src",
 735		.parent_names = gcc_xo_gpll0,
 736		.num_parents = 2,
 737		.ops = &clk_rcg2_ops,
 738	},
 739};
 740
 741static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 742	.cmd_rcgr = 0x03034,
 743	.mnd_width = 16,
 744	.hid_width = 5,
 745	.parent_map = gcc_xo_gpll0_map,
 746	.freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 747	.clkr.hw.init = &(struct clk_init_data){
 748		.name = "blsp1_uart2_apps_clk_src",
 749		.parent_names = gcc_xo_gpll0,
 750		.num_parents = 2,
 751		.ops = &clk_rcg2_ops,
 752	},
 753};
 754
 755static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
 756	F(19200000,	P_XO, 1, 0,	0),
 757	{ }
 758};
 759
 760static struct clk_rcg2 cci_clk_src = {
 761	.cmd_rcgr = 0x51000,
 762	.mnd_width = 8,
 763	.hid_width = 5,
 764	.parent_map = gcc_xo_gpll0a_map,
 765	.freq_tbl = ftbl_gcc_camss_cci_clk,
 766	.clkr.hw.init = &(struct clk_init_data){
 767		.name = "cci_clk_src",
 768		.parent_names = gcc_xo_gpll0a,
 769		.num_parents = 2,
 770		.ops = &clk_rcg2_ops,
 771	},
 772};
 773
 774static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
 775	F(100000000, P_GPLL0, 8, 0, 0),
 776	F(200000000, P_GPLL0, 4, 0, 0),
 777	{ }
 778};
 779
 780static struct clk_rcg2 camss_gp0_clk_src = {
 781	.cmd_rcgr = 0x54000,
 782	.mnd_width = 8,
 783	.hid_width = 5,
 784	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 785	.freq_tbl = ftbl_gcc_camss_gp0_1_clk,
 786	.clkr.hw.init = &(struct clk_init_data){
 787		.name = "camss_gp0_clk_src",
 788		.parent_names = gcc_xo_gpll0_gpll1a_sleep,
 789		.num_parents = 4,
 790		.ops = &clk_rcg2_ops,
 791	},
 792};
 793
 794static struct clk_rcg2 camss_gp1_clk_src = {
 795	.cmd_rcgr = 0x55000,
 796	.mnd_width = 8,
 797	.hid_width = 5,
 798	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 799	.freq_tbl = ftbl_gcc_camss_gp0_1_clk,
 800	.clkr.hw.init = &(struct clk_init_data){
 801		.name = "camss_gp1_clk_src",
 802		.parent_names = gcc_xo_gpll0_gpll1a_sleep,
 803		.num_parents = 4,
 804		.ops = &clk_rcg2_ops,
 805	},
 806};
 807
 808static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
 809	F(133330000, P_GPLL0, 6, 0,	0),
 810	F(266670000, P_GPLL0, 3, 0,	0),
 811	F(320000000, P_GPLL0, 2.5, 0, 0),
 812	{ }
 813};
 814
 815static struct clk_rcg2 jpeg0_clk_src = {
 816	.cmd_rcgr = 0x57000,
 817	.hid_width = 5,
 818	.parent_map = gcc_xo_gpll0_map,
 819	.freq_tbl = ftbl_gcc_camss_jpeg0_clk,
 820	.clkr.hw.init = &(struct clk_init_data){
 821		.name = "jpeg0_clk_src",
 822		.parent_names = gcc_xo_gpll0,
 823		.num_parents = 2,
 824		.ops = &clk_rcg2_ops,
 825	},
 826};
 827
 828static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
 829	F(9600000, P_XO, 2, 0, 0),
 830	F(23880000, P_GPLL0, 1, 2, 67),
 831	F(66670000, P_GPLL0, 12, 0, 0),
 832	{ }
 833};
 834
 835static struct clk_rcg2 mclk0_clk_src = {
 836	.cmd_rcgr = 0x52000,
 837	.mnd_width = 8,
 838	.hid_width = 5,
 839	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 840	.freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
 841	.clkr.hw.init = &(struct clk_init_data){
 842		.name = "mclk0_clk_src",
 843		.parent_names = gcc_xo_gpll0_gpll1a_sleep,
 844		.num_parents = 4,
 845		.ops = &clk_rcg2_ops,
 846	},
 847};
 848
 849static struct clk_rcg2 mclk1_clk_src = {
 850	.cmd_rcgr = 0x53000,
 851	.mnd_width = 8,
 852	.hid_width = 5,
 853	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 854	.freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
 855	.clkr.hw.init = &(struct clk_init_data){
 856		.name = "mclk1_clk_src",
 857		.parent_names = gcc_xo_gpll0_gpll1a_sleep,
 858		.num_parents = 4,
 859		.ops = &clk_rcg2_ops,
 860	},
 861};
 862
 863static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
 864	F(100000000, P_GPLL0, 8, 0,	0),
 865	F(200000000, P_GPLL0, 4, 0,	0),
 866	{ }
 867};
 868
 869static struct clk_rcg2 csi0phytimer_clk_src = {
 870	.cmd_rcgr = 0x4e000,
 871	.hid_width = 5,
 872	.parent_map = gcc_xo_gpll0_gpll1a_map,
 873	.freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
 874	.clkr.hw.init = &(struct clk_init_data){
 875		.name = "csi0phytimer_clk_src",
 876		.parent_names = gcc_xo_gpll0_gpll1a,
 877		.num_parents = 3,
 878		.ops = &clk_rcg2_ops,
 879	},
 880};
 881
 882static struct clk_rcg2 csi1phytimer_clk_src = {
 883	.cmd_rcgr = 0x4f000,
 884	.hid_width = 5,
 885	.parent_map = gcc_xo_gpll0_gpll1a_map,
 886	.freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
 887	.clkr.hw.init = &(struct clk_init_data){
 888		.name = "csi1phytimer_clk_src",
 889		.parent_names = gcc_xo_gpll0_gpll1a,
 890		.num_parents = 3,
 891		.ops = &clk_rcg2_ops,
 892	},
 893};
 894
 895static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
 896	F(160000000, P_GPLL0, 5, 0, 0),
 897	F(320000000, P_GPLL0, 2.5, 0, 0),
 898	F(465000000, P_GPLL2, 2, 0, 0),
 899	{ }
 900};
 901
 902static struct clk_rcg2 cpp_clk_src = {
 903	.cmd_rcgr = 0x58018,
 904	.hid_width = 5,
 905	.parent_map = gcc_xo_gpll0_gpll2_map,
 906	.freq_tbl = ftbl_gcc_camss_cpp_clk,
 907	.clkr.hw.init = &(struct clk_init_data){
 908		.name = "cpp_clk_src",
 909		.parent_names = gcc_xo_gpll0_gpll2,
 910		.num_parents = 3,
 911		.ops = &clk_rcg2_ops,
 912	},
 913};
 914
 915static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
 916	F(50000000, P_GPLL0, 16, 0, 0),
 917	F(80000000, P_GPLL0, 10, 0, 0),
 918	F(100000000, P_GPLL0, 8, 0, 0),
 919	F(160000000, P_GPLL0, 5, 0, 0),
 920	{ }
 921};
 922
 923static struct clk_rcg2 crypto_clk_src = {
 924	.cmd_rcgr = 0x16004,
 925	.hid_width = 5,
 926	.parent_map = gcc_xo_gpll0_map,
 927	.freq_tbl = ftbl_gcc_crypto_clk,
 928	.clkr.hw.init = &(struct clk_init_data){
 929		.name = "crypto_clk_src",
 930		.parent_names = gcc_xo_gpll0,
 931		.num_parents = 2,
 932		.ops = &clk_rcg2_ops,
 933	},
 934};
 935
 936static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
 937	F(19200000, P_XO, 1, 0,	0),
 938	{ }
 939};
 940
 941static struct clk_rcg2 gp1_clk_src = {
 942	.cmd_rcgr = 0x08004,
 943	.mnd_width = 8,
 944	.hid_width = 5,
 945	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 946	.freq_tbl = ftbl_gcc_gp1_3_clk,
 947	.clkr.hw.init = &(struct clk_init_data){
 948		.name = "gp1_clk_src",
 949		.parent_names = gcc_xo_gpll0_gpll1a_sleep,
 950		.num_parents = 3,
 951		.ops = &clk_rcg2_ops,
 952	},
 953};
 954
 955static struct clk_rcg2 gp2_clk_src = {
 956	.cmd_rcgr = 0x09004,
 957	.mnd_width = 8,
 958	.hid_width = 5,
 959	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 960	.freq_tbl = ftbl_gcc_gp1_3_clk,
 961	.clkr.hw.init = &(struct clk_init_data){
 962		.name = "gp2_clk_src",
 963		.parent_names = gcc_xo_gpll0_gpll1a_sleep,
 964		.num_parents = 3,
 965		.ops = &clk_rcg2_ops,
 966	},
 967};
 968
 969static struct clk_rcg2 gp3_clk_src = {
 970	.cmd_rcgr = 0x0a004,
 971	.mnd_width = 8,
 972	.hid_width = 5,
 973	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 974	.freq_tbl = ftbl_gcc_gp1_3_clk,
 975	.clkr.hw.init = &(struct clk_init_data){
 976		.name = "gp3_clk_src",
 977		.parent_names = gcc_xo_gpll0_gpll1a_sleep,
 978		.num_parents = 3,
 979		.ops = &clk_rcg2_ops,
 980	},
 981};
 982
 983static struct clk_rcg2 byte0_clk_src = {
 984	.cmd_rcgr = 0x4d044,
 985	.hid_width = 5,
 986	.parent_map = gcc_xo_gpll0a_dsibyte_map,
 987	.clkr.hw.init = &(struct clk_init_data){
 988		.name = "byte0_clk_src",
 989		.parent_names = gcc_xo_gpll0a_dsibyte,
 990		.num_parents = 3,
 991		.ops = &clk_byte2_ops,
 992		.flags = CLK_SET_RATE_PARENT,
 993	},
 994};
 995
 996static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
 997	F(19200000, P_XO, 1, 0, 0),
 998	{ }
 999};
1000
1001static struct clk_rcg2 esc0_clk_src = {
1002	.cmd_rcgr = 0x4d05c,
1003	.hid_width = 5,
1004	.parent_map = gcc_xo_dsibyte_map,
1005	.freq_tbl = ftbl_gcc_mdss_esc0_clk,
1006	.clkr.hw.init = &(struct clk_init_data){
1007		.name = "esc0_clk_src",
1008		.parent_names = gcc_xo_dsibyte,
1009		.num_parents = 2,
1010		.ops = &clk_rcg2_ops,
1011	},
1012};
1013
1014static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
1015	F(50000000, P_GPLL0, 16, 0, 0),
1016	F(80000000, P_GPLL0, 10, 0, 0),
1017	F(100000000, P_GPLL0, 8, 0, 0),
1018	F(160000000, P_GPLL0, 5, 0, 0),
1019	F(177780000, P_GPLL0, 4.5, 0, 0),
1020	F(200000000, P_GPLL0, 4, 0, 0),
1021	F(266670000, P_GPLL0, 3, 0, 0),
1022	F(320000000, P_GPLL0, 2.5, 0, 0),
1023	{ }
1024};
1025
1026static struct clk_rcg2 mdp_clk_src = {
1027	.cmd_rcgr = 0x4d014,
1028	.hid_width = 5,
1029	.parent_map = gcc_xo_gpll0_dsiphy_map,
1030	.freq_tbl = ftbl_gcc_mdss_mdp_clk,
1031	.clkr.hw.init = &(struct clk_init_data){
1032		.name = "mdp_clk_src",
1033		.parent_names = gcc_xo_gpll0_dsiphy,
1034		.num_parents = 3,
1035		.ops = &clk_rcg2_ops,
1036	},
1037};
1038
1039static struct clk_rcg2 pclk0_clk_src = {
1040	.cmd_rcgr = 0x4d000,
1041	.mnd_width = 8,
1042	.hid_width = 5,
1043	.parent_map = gcc_xo_gpll0a_dsiphy_map,
1044	.clkr.hw.init = &(struct clk_init_data){
1045		.name = "pclk0_clk_src",
1046		.parent_names = gcc_xo_gpll0a_dsiphy,
1047		.num_parents = 3,
1048		.ops = &clk_pixel_ops,
1049		.flags = CLK_SET_RATE_PARENT,
1050	},
1051};
1052
1053static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
1054	F(19200000, P_XO, 1, 0,	0),
1055	{ }
1056};
1057
1058static struct clk_rcg2 vsync_clk_src = {
1059	.cmd_rcgr = 0x4d02c,
1060	.hid_width = 5,
1061	.parent_map = gcc_xo_gpll0a_map,
1062	.freq_tbl = ftbl_gcc_mdss_vsync_clk,
1063	.clkr.hw.init = &(struct clk_init_data){
1064		.name = "vsync_clk_src",
1065		.parent_names = gcc_xo_gpll0a,
1066		.num_parents = 2,
1067		.ops = &clk_rcg2_ops,
1068	},
1069};
1070
1071static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1072	F(64000000, P_GPLL0, 12.5, 0, 0),
1073	{ }
1074};
1075
1076static struct clk_rcg2 pdm2_clk_src = {
1077	.cmd_rcgr = 0x44010,
1078	.hid_width = 5,
1079	.parent_map = gcc_xo_gpll0_map,
1080	.freq_tbl = ftbl_gcc_pdm2_clk,
1081	.clkr.hw.init = &(struct clk_init_data){
1082		.name = "pdm2_clk_src",
1083		.parent_names = gcc_xo_gpll0,
1084		.num_parents = 2,
1085		.ops = &clk_rcg2_ops,
1086	},
1087};
1088
1089static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
1090	F(144000, P_XO, 16, 3, 25),
1091	F(400000, P_XO, 12, 1, 4),
1092	F(20000000, P_GPLL0, 10, 1, 4),
1093	F(25000000, P_GPLL0, 16, 1, 2),
1094	F(50000000, P_GPLL0, 16, 0, 0),
1095	F(100000000, P_GPLL0, 8, 0, 0),
1096	F(177770000, P_GPLL0, 4.5, 0, 0),
1097	{ }
1098};
1099
1100static struct clk_rcg2 sdcc1_apps_clk_src = {
1101	.cmd_rcgr = 0x42004,
1102	.mnd_width = 8,
1103	.hid_width = 5,
1104	.parent_map = gcc_xo_gpll0_map,
1105	.freq_tbl = ftbl_gcc_sdcc1_apps_clk,
1106	.clkr.hw.init = &(struct clk_init_data){
1107		.name = "sdcc1_apps_clk_src",
1108		.parent_names = gcc_xo_gpll0,
1109		.num_parents = 2,
1110		.ops = &clk_rcg2_ops,
1111	},
1112};
1113
1114static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
1115	F(144000, P_XO, 16, 3, 25),
1116	F(400000, P_XO, 12, 1, 4),
1117	F(20000000, P_GPLL0, 10, 1, 4),
1118	F(25000000, P_GPLL0, 16, 1, 2),
1119	F(50000000, P_GPLL0, 16, 0, 0),
1120	F(100000000, P_GPLL0, 8, 0, 0),
1121	F(200000000, P_GPLL0, 4, 0, 0),
1122	{ }
1123};
1124
1125static struct clk_rcg2 sdcc2_apps_clk_src = {
1126	.cmd_rcgr = 0x43004,
1127	.mnd_width = 8,
1128	.hid_width = 5,
1129	.parent_map = gcc_xo_gpll0_map,
1130	.freq_tbl = ftbl_gcc_sdcc2_apps_clk,
1131	.clkr.hw.init = &(struct clk_init_data){
1132		.name = "sdcc2_apps_clk_src",
1133		.parent_names = gcc_xo_gpll0,
1134		.num_parents = 2,
1135		.ops = &clk_rcg2_ops,
1136	},
1137};
1138
1139static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
1140	F(155000000, P_GPLL2, 6, 0, 0),
1141	F(310000000, P_GPLL2, 3, 0, 0),
1142	F(400000000, P_GPLL0, 2, 0, 0),
1143	{ }
1144};
1145
1146static struct clk_rcg2 apss_tcu_clk_src = {
1147	.cmd_rcgr = 0x1207c,
1148	.hid_width = 5,
1149	.parent_map = gcc_xo_gpll0a_gpll1_gpll2_map,
1150	.freq_tbl = ftbl_gcc_apss_tcu_clk,
1151	.clkr.hw.init = &(struct clk_init_data){
1152		.name = "apss_tcu_clk_src",
1153		.parent_names = gcc_xo_gpll0a_gpll1_gpll2,
1154		.num_parents = 4,
1155		.ops = &clk_rcg2_ops,
1156	},
1157};
1158
1159static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
1160	F(19200000, P_XO, 1, 0, 0),
1161	F(100000000, P_GPLL0, 8, 0, 0),
1162	F(200000000, P_GPLL0, 4, 0, 0),
1163	F(266500000, P_BIMC, 4, 0, 0),
1164	F(400000000, P_GPLL0, 2, 0, 0),
1165	F(533000000, P_BIMC, 2, 0, 0),
1166	{ }
1167};
1168
1169static struct clk_rcg2 bimc_gpu_clk_src = {
1170	.cmd_rcgr = 0x31028,
1171	.hid_width = 5,
1172	.parent_map = gcc_xo_gpll0_bimc_map,
1173	.freq_tbl = ftbl_gcc_bimc_gpu_clk,
1174	.clkr.hw.init = &(struct clk_init_data){
1175		.name = "bimc_gpu_clk_src",
1176		.parent_names = gcc_xo_gpll0_bimc,
1177		.num_parents = 3,
1178		.flags = CLK_GET_RATE_NOCACHE,
1179		.ops = &clk_rcg2_shared_ops,
1180	},
1181};
1182
1183static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1184	F(80000000, P_GPLL0, 10, 0, 0),
1185	{ }
1186};
1187
1188static struct clk_rcg2 usb_hs_system_clk_src = {
1189	.cmd_rcgr = 0x41010,
1190	.hid_width = 5,
1191	.parent_map = gcc_xo_gpll0_map,
1192	.freq_tbl = ftbl_gcc_usb_hs_system_clk,
1193	.clkr.hw.init = &(struct clk_init_data){
1194		.name = "usb_hs_system_clk_src",
1195		.parent_names = gcc_xo_gpll0,
1196		.num_parents = 2,
1197		.ops = &clk_rcg2_ops,
1198	},
1199};
1200
1201static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
1202	F(3200000, P_XO, 6, 0, 0),
1203	F(6400000, P_XO, 3, 0, 0),
1204	F(9600000, P_XO, 2, 0, 0),
1205	F(19200000, P_XO, 1, 0, 0),
1206	F(40000000, P_GPLL0, 10, 1, 2),
1207	F(66670000, P_GPLL0, 12, 0, 0),
1208	F(80000000, P_GPLL0, 10, 0, 0),
1209	F(100000000, P_GPLL0, 8, 0, 0),
1210	{ }
1211};
1212
1213static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
1214	.cmd_rcgr = 0x1c010,
1215	.hid_width = 5,
1216	.mnd_width = 8,
1217	.parent_map = gcc_xo_gpll0_gpll1_sleep_map,
1218	.freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
1219	.clkr.hw.init = &(struct clk_init_data){
1220		.name = "ultaudio_ahbfabric_clk_src",
1221		.parent_names = gcc_xo_gpll0_gpll1_sleep,
1222		.num_parents = 4,
1223		.ops = &clk_rcg2_ops,
1224	},
1225};
1226
1227static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
1228	.halt_reg = 0x1c028,
1229	.clkr = {
1230		.enable_reg = 0x1c028,
1231		.enable_mask = BIT(0),
1232		.hw.init = &(struct clk_init_data){
1233			.name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
1234			.parent_names = (const char *[]){
1235				"ultaudio_ahbfabric_clk_src",
1236			},
1237			.num_parents = 1,
1238			.flags = CLK_SET_RATE_PARENT,
1239			.ops = &clk_branch2_ops,
1240		},
1241	},
1242};
1243
1244static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
1245	.halt_reg = 0x1c024,
1246	.clkr = {
1247		.enable_reg = 0x1c024,
1248		.enable_mask = BIT(0),
1249		.hw.init = &(struct clk_init_data){
1250			.name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
1251			.parent_names = (const char *[]){
1252				"ultaudio_ahbfabric_clk_src",
1253			},
1254			.num_parents = 1,
1255			.flags = CLK_SET_RATE_PARENT,
1256			.ops = &clk_branch2_ops,
1257		},
1258	},
1259};
1260
1261static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
1262	F(256000, P_XO, 5, 1, 15),
1263	F(512000, P_XO, 5, 2, 15),
1264	F(705600, P_GPLL1, 16, 1, 80),
1265	F(768000, P_XO, 5, 1, 5),
1266	F(800000, P_XO, 5, 5, 24),
1267	F(1024000, P_GPLL1, 14, 1, 63),
1268	F(1152000, P_XO, 1, 3, 50),
1269	F(1411200, P_GPLL1, 16, 1, 40),
1270	F(1536000, P_XO, 1, 2, 25),
1271	F(1600000, P_XO, 12, 0, 0),
1272	F(2048000, P_GPLL1, 9, 1, 49),
1273	F(2400000, P_XO, 8, 0, 0),
1274	F(2822400, P_GPLL1, 16, 1, 20),
1275	F(3072000, P_GPLL1, 14, 1, 21),
1276	F(4096000, P_GPLL1, 9, 2, 49),
1277	F(4800000, P_XO, 4, 0, 0),
1278	F(5644800, P_GPLL1, 16, 1, 10),
1279	F(6144000, P_GPLL1, 7, 1, 21),
1280	F(8192000, P_GPLL1, 9, 4, 49),
1281	F(9600000, P_XO, 2, 0, 0),
1282	F(11289600, P_GPLL1, 16, 1, 5),
1283	F(12288000, P_GPLL1, 7, 2, 21),
1284	{ }
1285};
1286
1287static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
1288	.cmd_rcgr = 0x1c054,
1289	.hid_width = 5,
1290	.mnd_width = 8,
1291	.parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map,
1292	.freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1293	.clkr.hw.init = &(struct clk_init_data){
1294		.name = "ultaudio_lpaif_pri_i2s_clk_src",
1295		.parent_names = gcc_xo_gpll1_epi2s_emclk_sleep,
1296		.num_parents = 5,
1297		.ops = &clk_rcg2_ops,
1298	},
1299};
1300
1301static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
1302	.halt_reg = 0x1c068,
1303	.clkr = {
1304		.enable_reg = 0x1c068,
1305		.enable_mask = BIT(0),
1306		.hw.init = &(struct clk_init_data){
1307			.name = "gcc_ultaudio_lpaif_pri_i2s_clk",
1308			.parent_names = (const char *[]){
1309				"ultaudio_lpaif_pri_i2s_clk_src",
1310			},
1311			.num_parents = 1,
1312			.flags = CLK_SET_RATE_PARENT,
1313			.ops = &clk_branch2_ops,
1314		},
1315	},
1316};
1317
1318static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
1319	.cmd_rcgr = 0x1c06c,
1320	.hid_width = 5,
1321	.mnd_width = 8,
1322	.parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map,
1323	.freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1324	.clkr.hw.init = &(struct clk_init_data){
1325		.name = "ultaudio_lpaif_sec_i2s_clk_src",
1326		.parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
1327		.num_parents = 5,
1328		.ops = &clk_rcg2_ops,
1329	},
1330};
1331
1332static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
1333	.halt_reg = 0x1c080,
1334	.clkr = {
1335		.enable_reg = 0x1c080,
1336		.enable_mask = BIT(0),
1337		.hw.init = &(struct clk_init_data){
1338			.name = "gcc_ultaudio_lpaif_sec_i2s_clk",
1339			.parent_names = (const char *[]){
1340				"ultaudio_lpaif_sec_i2s_clk_src",
1341			},
1342			.num_parents = 1,
1343			.flags = CLK_SET_RATE_PARENT,
1344			.ops = &clk_branch2_ops,
1345		},
1346	},
1347};
1348
1349static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
1350	.cmd_rcgr = 0x1c084,
1351	.hid_width = 5,
1352	.mnd_width = 8,
1353	.parent_map = gcc_xo_gpll1_emclk_sleep_map,
1354	.freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1355	.clkr.hw.init = &(struct clk_init_data){
1356		.name = "ultaudio_lpaif_aux_i2s_clk_src",
1357		.parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
1358		.num_parents = 5,
1359		.ops = &clk_rcg2_ops,
1360	},
1361};
1362
1363static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
1364	.halt_reg = 0x1c098,
1365	.clkr = {
1366		.enable_reg = 0x1c098,
1367		.enable_mask = BIT(0),
1368		.hw.init = &(struct clk_init_data){
1369			.name = "gcc_ultaudio_lpaif_aux_i2s_clk",
1370			.parent_names = (const char *[]){
1371				"ultaudio_lpaif_aux_i2s_clk_src",
1372			},
1373			.num_parents = 1,
1374			.flags = CLK_SET_RATE_PARENT,
1375			.ops = &clk_branch2_ops,
1376		},
1377	},
1378};
1379
1380static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = {
1381	F(19200000, P_XO, 1, 0, 0),
1382	{ }
1383};
1384
1385static struct clk_rcg2 ultaudio_xo_clk_src = {
1386	.cmd_rcgr = 0x1c034,
1387	.hid_width = 5,
1388	.parent_map = gcc_xo_sleep_map,
1389	.freq_tbl = ftbl_gcc_ultaudio_xo_clk,
1390	.clkr.hw.init = &(struct clk_init_data){
1391		.name = "ultaudio_xo_clk_src",
1392		.parent_names = gcc_xo_sleep,
1393		.num_parents = 2,
1394		.ops = &clk_rcg2_ops,
1395	},
1396};
1397
1398static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
1399	.halt_reg = 0x1c04c,
1400	.clkr = {
1401		.enable_reg = 0x1c04c,
1402		.enable_mask = BIT(0),
1403		.hw.init = &(struct clk_init_data){
1404			.name = "gcc_ultaudio_avsync_xo_clk",
1405			.parent_names = (const char *[]){
1406				"ultaudio_xo_clk_src",
1407			},
1408			.num_parents = 1,
1409			.flags = CLK_SET_RATE_PARENT,
1410			.ops = &clk_branch2_ops,
1411		},
1412	},
1413};
1414
1415static struct clk_branch gcc_ultaudio_stc_xo_clk = {
1416	.halt_reg = 0x1c050,
1417	.clkr = {
1418		.enable_reg = 0x1c050,
1419		.enable_mask = BIT(0),
1420		.hw.init = &(struct clk_init_data){
1421			.name = "gcc_ultaudio_stc_xo_clk",
1422			.parent_names = (const char *[]){
1423				"ultaudio_xo_clk_src",
1424			},
1425			.num_parents = 1,
1426			.flags = CLK_SET_RATE_PARENT,
1427			.ops = &clk_branch2_ops,
1428		},
1429	},
1430};
1431
1432static const struct freq_tbl ftbl_codec_clk[] = {
1433	F(19200000, P_XO, 1, 0, 0),
1434	F(11289600, P_EXT_MCLK, 1, 0, 0),
1435	{ }
1436};
1437
1438static struct clk_rcg2 codec_digcodec_clk_src = {
1439	.cmd_rcgr = 0x1c09c,
1440	.hid_width = 5,
1441	.parent_map = gcc_xo_gpll1_emclk_sleep_map,
1442	.freq_tbl = ftbl_codec_clk,
1443	.clkr.hw.init = &(struct clk_init_data){
1444		.name = "codec_digcodec_clk_src",
1445		.parent_names = gcc_xo_gpll1_emclk_sleep,
1446		.num_parents = 4,
1447		.ops = &clk_rcg2_ops,
1448	},
1449};
1450
1451static struct clk_branch gcc_codec_digcodec_clk = {
1452	.halt_reg = 0x1c0b0,
1453	.clkr = {
1454		.enable_reg = 0x1c0b0,
1455		.enable_mask = BIT(0),
1456		.hw.init = &(struct clk_init_data){
1457			.name = "gcc_ultaudio_codec_digcodec_clk",
1458			.parent_names = (const char *[]){
1459				"codec_digcodec_clk_src",
1460			},
1461			.num_parents = 1,
1462			.flags = CLK_SET_RATE_PARENT,
1463			.ops = &clk_branch2_ops,
1464		},
1465	},
1466};
1467
1468static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
1469	.halt_reg = 0x1c000,
1470	.clkr = {
1471		.enable_reg = 0x1c000,
1472		.enable_mask = BIT(0),
1473		.hw.init = &(struct clk_init_data){
1474			.name = "gcc_ultaudio_pcnoc_mport_clk",
1475			.parent_names = (const char *[]){
1476				"pcnoc_bfdcd_clk_src",
1477			},
1478			.num_parents = 1,
1479			.ops = &clk_branch2_ops,
1480		},
1481	},
1482};
1483
1484static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
1485	.halt_reg = 0x1c004,
1486	.clkr = {
1487		.enable_reg = 0x1c004,
1488		.enable_mask = BIT(0),
1489		.hw.init = &(struct clk_init_data){
1490			.name = "gcc_ultaudio_pcnoc_sway_clk",
1491			.parent_names = (const char *[]){
1492				"pcnoc_bfdcd_clk_src",
1493			},
1494			.num_parents = 1,
1495			.ops = &clk_branch2_ops,
1496		},
1497	},
1498};
1499
1500static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
1501	F(100000000, P_GPLL0, 8, 0, 0),
1502	F(160000000, P_GPLL0, 5, 0, 0),
1503	F(228570000, P_GPLL0, 3.5, 0, 0),
1504	{ }
1505};
1506
1507static struct clk_rcg2 vcodec0_clk_src = {
1508	.cmd_rcgr = 0x4C000,
1509	.mnd_width = 8,
1510	.hid_width = 5,
1511	.parent_map = gcc_xo_gpll0_map,
1512	.freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
1513	.clkr.hw.init = &(struct clk_init_data){
1514		.name = "vcodec0_clk_src",
1515		.parent_names = gcc_xo_gpll0,
1516		.num_parents = 2,
1517		.ops = &clk_rcg2_ops,
1518	},
1519};
1520
1521static struct clk_branch gcc_blsp1_ahb_clk = {
1522	.halt_reg = 0x01008,
1523	.halt_check = BRANCH_HALT_VOTED,
1524	.clkr = {
1525		.enable_reg = 0x45004,
1526		.enable_mask = BIT(10),
1527		.hw.init = &(struct clk_init_data){
1528			.name = "gcc_blsp1_ahb_clk",
1529			.parent_names = (const char *[]){
1530				"pcnoc_bfdcd_clk_src",
1531			},
1532			.num_parents = 1,
1533			.ops = &clk_branch2_ops,
1534		},
1535	},
1536};
1537
1538static struct clk_branch gcc_blsp1_sleep_clk = {
1539	.halt_reg = 0x01004,
1540	.clkr = {
1541		.enable_reg = 0x01004,
1542		.enable_mask = BIT(0),
1543		.hw.init = &(struct clk_init_data){
1544			.name = "gcc_blsp1_sleep_clk",
1545			.parent_names = (const char *[]){
1546				"sleep_clk_src",
1547			},
1548			.num_parents = 1,
1549			.flags = CLK_SET_RATE_PARENT,
1550			.ops = &clk_branch2_ops,
1551		},
1552	},
1553};
1554
1555static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1556	.halt_reg = 0x02008,
1557	.clkr = {
1558		.enable_reg = 0x02008,
1559		.enable_mask = BIT(0),
1560		.hw.init = &(struct clk_init_data){
1561			.name = "gcc_blsp1_qup1_i2c_apps_clk",
1562			.parent_names = (const char *[]){
1563				"blsp1_qup1_i2c_apps_clk_src",
1564			},
1565			.num_parents = 1,
1566			.flags = CLK_SET_RATE_PARENT,
1567			.ops = &clk_branch2_ops,
1568		},
1569	},
1570};
1571
1572static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1573	.halt_reg = 0x02004,
1574	.clkr = {
1575		.enable_reg = 0x02004,
1576		.enable_mask = BIT(0),
1577		.hw.init = &(struct clk_init_data){
1578			.name = "gcc_blsp1_qup1_spi_apps_clk",
1579			.parent_names = (const char *[]){
1580				"blsp1_qup1_spi_apps_clk_src",
1581			},
1582			.num_parents = 1,
1583			.flags = CLK_SET_RATE_PARENT,
1584			.ops = &clk_branch2_ops,
1585		},
1586	},
1587};
1588
1589static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1590	.halt_reg = 0x03010,
1591	.clkr = {
1592		.enable_reg = 0x03010,
1593		.enable_mask = BIT(0),
1594		.hw.init = &(struct clk_init_data){
1595			.name = "gcc_blsp1_qup2_i2c_apps_clk",
1596			.parent_names = (const char *[]){
1597				"blsp1_qup2_i2c_apps_clk_src",
1598			},
1599			.num_parents = 1,
1600			.flags = CLK_SET_RATE_PARENT,
1601			.ops = &clk_branch2_ops,
1602		},
1603	},
1604};
1605
1606static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1607	.halt_reg = 0x0300c,
1608	.clkr = {
1609		.enable_reg = 0x0300c,
1610		.enable_mask = BIT(0),
1611		.hw.init = &(struct clk_init_data){
1612			.name = "gcc_blsp1_qup2_spi_apps_clk",
1613			.parent_names = (const char *[]){
1614				"blsp1_qup2_spi_apps_clk_src",
1615			},
1616			.num_parents = 1,
1617			.flags = CLK_SET_RATE_PARENT,
1618			.ops = &clk_branch2_ops,
1619		},
1620	},
1621};
1622
1623static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1624	.halt_reg = 0x04020,
1625	.clkr = {
1626		.enable_reg = 0x04020,
1627		.enable_mask = BIT(0),
1628		.hw.init = &(struct clk_init_data){
1629			.name = "gcc_blsp1_qup3_i2c_apps_clk",
1630			.parent_names = (const char *[]){
1631				"blsp1_qup3_i2c_apps_clk_src",
1632			},
1633			.num_parents = 1,
1634			.flags = CLK_SET_RATE_PARENT,
1635			.ops = &clk_branch2_ops,
1636		},
1637	},
1638};
1639
1640static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1641	.halt_reg = 0x0401c,
1642	.clkr = {
1643		.enable_reg = 0x0401c,
1644		.enable_mask = BIT(0),
1645		.hw.init = &(struct clk_init_data){
1646			.name = "gcc_blsp1_qup3_spi_apps_clk",
1647			.parent_names = (const char *[]){
1648				"blsp1_qup3_spi_apps_clk_src",
1649			},
1650			.num_parents = 1,
1651			.flags = CLK_SET_RATE_PARENT,
1652			.ops = &clk_branch2_ops,
1653		},
1654	},
1655};
1656
1657static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1658	.halt_reg = 0x05020,
1659	.clkr = {
1660		.enable_reg = 0x05020,
1661		.enable_mask = BIT(0),
1662		.hw.init = &(struct clk_init_data){
1663			.name = "gcc_blsp1_qup4_i2c_apps_clk",
1664			.parent_names = (const char *[]){
1665				"blsp1_qup4_i2c_apps_clk_src",
1666			},
1667			.num_parents = 1,
1668			.flags = CLK_SET_RATE_PARENT,
1669			.ops = &clk_branch2_ops,
1670		},
1671	},
1672};
1673
1674static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1675	.halt_reg = 0x0501c,
1676	.clkr = {
1677		.enable_reg = 0x0501c,
1678		.enable_mask = BIT(0),
1679		.hw.init = &(struct clk_init_data){
1680			.name = "gcc_blsp1_qup4_spi_apps_clk",
1681			.parent_names = (const char *[]){
1682				"blsp1_qup4_spi_apps_clk_src",
1683			},
1684			.num_parents = 1,
1685			.flags = CLK_SET_RATE_PARENT,
1686			.ops = &clk_branch2_ops,
1687		},
1688	},
1689};
1690
1691static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1692	.halt_reg = 0x06020,
1693	.clkr = {
1694		.enable_reg = 0x06020,
1695		.enable_mask = BIT(0),
1696		.hw.init = &(struct clk_init_data){
1697			.name = "gcc_blsp1_qup5_i2c_apps_clk",
1698			.parent_names = (const char *[]){
1699				"blsp1_qup5_i2c_apps_clk_src",
1700			},
1701			.num_parents = 1,
1702			.flags = CLK_SET_RATE_PARENT,
1703			.ops = &clk_branch2_ops,
1704		},
1705	},
1706};
1707
1708static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1709	.halt_reg = 0x0601c,
1710	.clkr = {
1711		.enable_reg = 0x0601c,
1712		.enable_mask = BIT(0),
1713		.hw.init = &(struct clk_init_data){
1714			.name = "gcc_blsp1_qup5_spi_apps_clk",
1715			.parent_names = (const char *[]){
1716				"blsp1_qup5_spi_apps_clk_src",
1717			},
1718			.num_parents = 1,
1719			.flags = CLK_SET_RATE_PARENT,
1720			.ops = &clk_branch2_ops,
1721		},
1722	},
1723};
1724
1725static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1726	.halt_reg = 0x07020,
1727	.clkr = {
1728		.enable_reg = 0x07020,
1729		.enable_mask = BIT(0),
1730		.hw.init = &(struct clk_init_data){
1731			.name = "gcc_blsp1_qup6_i2c_apps_clk",
1732			.parent_names = (const char *[]){
1733				"blsp1_qup6_i2c_apps_clk_src",
1734			},
1735			.num_parents = 1,
1736			.flags = CLK_SET_RATE_PARENT,
1737			.ops = &clk_branch2_ops,
1738		},
1739	},
1740};
1741
1742static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1743	.halt_reg = 0x0701c,
1744	.clkr = {
1745		.enable_reg = 0x0701c,
1746		.enable_mask = BIT(0),
1747		.hw.init = &(struct clk_init_data){
1748			.name = "gcc_blsp1_qup6_spi_apps_clk",
1749			.parent_names = (const char *[]){
1750				"blsp1_qup6_spi_apps_clk_src",
1751			},
1752			.num_parents = 1,
1753			.flags = CLK_SET_RATE_PARENT,
1754			.ops = &clk_branch2_ops,
1755		},
1756	},
1757};
1758
1759static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1760	.halt_reg = 0x0203c,
1761	.clkr = {
1762		.enable_reg = 0x0203c,
1763		.enable_mask = BIT(0),
1764		.hw.init = &(struct clk_init_data){
1765			.name = "gcc_blsp1_uart1_apps_clk",
1766			.parent_names = (const char *[]){
1767				"blsp1_uart1_apps_clk_src",
1768			},
1769			.num_parents = 1,
1770			.flags = CLK_SET_RATE_PARENT,
1771			.ops = &clk_branch2_ops,
1772		},
1773	},
1774};
1775
1776static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1777	.halt_reg = 0x0302c,
1778	.clkr = {
1779		.enable_reg = 0x0302c,
1780		.enable_mask = BIT(0),
1781		.hw.init = &(struct clk_init_data){
1782			.name = "gcc_blsp1_uart2_apps_clk",
1783			.parent_names = (const char *[]){
1784				"blsp1_uart2_apps_clk_src",
1785			},
1786			.num_parents = 1,
1787			.flags = CLK_SET_RATE_PARENT,
1788			.ops = &clk_branch2_ops,
1789		},
1790	},
1791};
1792
1793static struct clk_branch gcc_boot_rom_ahb_clk = {
1794	.halt_reg = 0x1300c,
1795	.halt_check = BRANCH_HALT_VOTED,
1796	.clkr = {
1797		.enable_reg = 0x45004,
1798		.enable_mask = BIT(7),
1799		.hw.init = &(struct clk_init_data){
1800			.name = "gcc_boot_rom_ahb_clk",
1801			.parent_names = (const char *[]){
1802				"pcnoc_bfdcd_clk_src",
1803			},
1804			.num_parents = 1,
1805			.ops = &clk_branch2_ops,
1806		},
1807	},
1808};
1809
1810static struct clk_branch gcc_camss_cci_ahb_clk = {
1811	.halt_reg = 0x5101c,
1812	.clkr = {
1813		.enable_reg = 0x5101c,
1814		.enable_mask = BIT(0),
1815		.hw.init = &(struct clk_init_data){
1816			.name = "gcc_camss_cci_ahb_clk",
1817			.parent_names = (const char *[]){
1818				"camss_ahb_clk_src",
1819			},
1820			.num_parents = 1,
1821			.flags = CLK_SET_RATE_PARENT,
1822			.ops = &clk_branch2_ops,
1823		},
1824	},
1825};
1826
1827static struct clk_branch gcc_camss_cci_clk = {
1828	.halt_reg = 0x51018,
1829	.clkr = {
1830		.enable_reg = 0x51018,
1831		.enable_mask = BIT(0),
1832		.hw.init = &(struct clk_init_data){
1833			.name = "gcc_camss_cci_clk",
1834			.parent_names = (const char *[]){
1835				"cci_clk_src",
1836			},
1837			.num_parents = 1,
1838			.flags = CLK_SET_RATE_PARENT,
1839			.ops = &clk_branch2_ops,
1840		},
1841	},
1842};
1843
1844static struct clk_branch gcc_camss_csi0_ahb_clk = {
1845	.halt_reg = 0x4e040,
1846	.clkr = {
1847		.enable_reg = 0x4e040,
1848		.enable_mask = BIT(0),
1849		.hw.init = &(struct clk_init_data){
1850			.name = "gcc_camss_csi0_ahb_clk",
1851			.parent_names = (const char *[]){
1852				"camss_ahb_clk_src",
1853			},
1854			.num_parents = 1,
1855			.flags = CLK_SET_RATE_PARENT,
1856			.ops = &clk_branch2_ops,
1857		},
1858	},
1859};
1860
1861static struct clk_branch gcc_camss_csi0_clk = {
1862	.halt_reg = 0x4e03c,
1863	.clkr = {
1864		.enable_reg = 0x4e03c,
1865		.enable_mask = BIT(0),
1866		.hw.init = &(struct clk_init_data){
1867			.name = "gcc_camss_csi0_clk",
1868			.parent_names = (const char *[]){
1869				"csi0_clk_src",
1870			},
1871			.num_parents = 1,
1872			.flags = CLK_SET_RATE_PARENT,
1873			.ops = &clk_branch2_ops,
1874		},
1875	},
1876};
1877
1878static struct clk_branch gcc_camss_csi0phy_clk = {
1879	.halt_reg = 0x4e048,
1880	.clkr = {
1881		.enable_reg = 0x4e048,
1882		.enable_mask = BIT(0),
1883		.hw.init = &(struct clk_init_data){
1884			.name = "gcc_camss_csi0phy_clk",
1885			.parent_names = (const char *[]){
1886				"csi0_clk_src",
1887			},
1888			.num_parents = 1,
1889			.flags = CLK_SET_RATE_PARENT,
1890			.ops = &clk_branch2_ops,
1891		},
1892	},
1893};
1894
1895static struct clk_branch gcc_camss_csi0pix_clk = {
1896	.halt_reg = 0x4e058,
1897	.clkr = {
1898		.enable_reg = 0x4e058,
1899		.enable_mask = BIT(0),
1900		.hw.init = &(struct clk_init_data){
1901			.name = "gcc_camss_csi0pix_clk",
1902			.parent_names = (const char *[]){
1903				"csi0_clk_src",
1904			},
1905			.num_parents = 1,
1906			.flags = CLK_SET_RATE_PARENT,
1907			.ops = &clk_branch2_ops,
1908		},
1909	},
1910};
1911
1912static struct clk_branch gcc_camss_csi0rdi_clk = {
1913	.halt_reg = 0x4e050,
1914	.clkr = {
1915		.enable_reg = 0x4e050,
1916		.enable_mask = BIT(0),
1917		.hw.init = &(struct clk_init_data){
1918			.name = "gcc_camss_csi0rdi_clk",
1919			.parent_names = (const char *[]){
1920				"csi0_clk_src",
1921			},
1922			.num_parents = 1,
1923			.flags = CLK_SET_RATE_PARENT,
1924			.ops = &clk_branch2_ops,
1925		},
1926	},
1927};
1928
1929static struct clk_branch gcc_camss_csi1_ahb_clk = {
1930	.halt_reg = 0x4f040,
1931	.clkr = {
1932		.enable_reg = 0x4f040,
1933		.enable_mask = BIT(0),
1934		.hw.init = &(struct clk_init_data){
1935			.name = "gcc_camss_csi1_ahb_clk",
1936			.parent_names = (const char *[]){
1937				"camss_ahb_clk_src",
1938			},
1939			.num_parents = 1,
1940			.flags = CLK_SET_RATE_PARENT,
1941			.ops = &clk_branch2_ops,
1942		},
1943	},
1944};
1945
1946static struct clk_branch gcc_camss_csi1_clk = {
1947	.halt_reg = 0x4f03c,
1948	.clkr = {
1949		.enable_reg = 0x4f03c,
1950		.enable_mask = BIT(0),
1951		.hw.init = &(struct clk_init_data){
1952			.name = "gcc_camss_csi1_clk",
1953			.parent_names = (const char *[]){
1954				"csi1_clk_src",
1955			},
1956			.num_parents = 1,
1957			.flags = CLK_SET_RATE_PARENT,
1958			.ops = &clk_branch2_ops,
1959		},
1960	},
1961};
1962
1963static struct clk_branch gcc_camss_csi1phy_clk = {
1964	.halt_reg = 0x4f048,
1965	.clkr = {
1966		.enable_reg = 0x4f048,
1967		.enable_mask = BIT(0),
1968		.hw.init = &(struct clk_init_data){
1969			.name = "gcc_camss_csi1phy_clk",
1970			.parent_names = (const char *[]){
1971				"csi1_clk_src",
1972			},
1973			.num_parents = 1,
1974			.flags = CLK_SET_RATE_PARENT,
1975			.ops = &clk_branch2_ops,
1976		},
1977	},
1978};
1979
1980static struct clk_branch gcc_camss_csi1pix_clk = {
1981	.halt_reg = 0x4f058,
1982	.clkr = {
1983		.enable_reg = 0x4f058,
1984		.enable_mask = BIT(0),
1985		.hw.init = &(struct clk_init_data){
1986			.name = "gcc_camss_csi1pix_clk",
1987			.parent_names = (const char *[]){
1988				"csi1_clk_src",
1989			},
1990			.num_parents = 1,
1991			.flags = CLK_SET_RATE_PARENT,
1992			.ops = &clk_branch2_ops,
1993		},
1994	},
1995};
1996
1997static struct clk_branch gcc_camss_csi1rdi_clk = {
1998	.halt_reg = 0x4f050,
1999	.clkr = {
2000		.enable_reg = 0x4f050,
2001		.enable_mask = BIT(0),
2002		.hw.init = &(struct clk_init_data){
2003			.name = "gcc_camss_csi1rdi_clk",
2004			.parent_names = (const char *[]){
2005				"csi1_clk_src",
2006			},
2007			.num_parents = 1,
2008			.flags = CLK_SET_RATE_PARENT,
2009			.ops = &clk_branch2_ops,
2010		},
2011	},
2012};
2013
2014static struct clk_branch gcc_camss_csi_vfe0_clk = {
2015	.halt_reg = 0x58050,
2016	.clkr = {
2017		.enable_reg = 0x58050,
2018		.enable_mask = BIT(0),
2019		.hw.init = &(struct clk_init_data){
2020			.name = "gcc_camss_csi_vfe0_clk",
2021			.parent_names = (const char *[]){
2022				"vfe0_clk_src",
2023			},
2024			.num_parents = 1,
2025			.flags = CLK_SET_RATE_PARENT,
2026			.ops = &clk_branch2_ops,
2027		},
2028	},
2029};
2030
2031static struct clk_branch gcc_camss_gp0_clk = {
2032	.halt_reg = 0x54018,
2033	.clkr = {
2034		.enable_reg = 0x54018,
2035		.enable_mask = BIT(0),
2036		.hw.init = &(struct clk_init_data){
2037			.name = "gcc_camss_gp0_clk",
2038			.parent_names = (const char *[]){
2039				"camss_gp0_clk_src",
2040			},
2041			.num_parents = 1,
2042			.flags = CLK_SET_RATE_PARENT,
2043			.ops = &clk_branch2_ops,
2044		},
2045	},
2046};
2047
2048static struct clk_branch gcc_camss_gp1_clk = {
2049	.halt_reg = 0x55018,
2050	.clkr = {
2051		.enable_reg = 0x55018,
2052		.enable_mask = BIT(0),
2053		.hw.init = &(struct clk_init_data){
2054			.name = "gcc_camss_gp1_clk",
2055			.parent_names = (const char *[]){
2056				"camss_gp1_clk_src",
2057			},
2058			.num_parents = 1,
2059			.flags = CLK_SET_RATE_PARENT,
2060			.ops = &clk_branch2_ops,
2061		},
2062	},
2063};
2064
2065static struct clk_branch gcc_camss_ispif_ahb_clk = {
2066	.halt_reg = 0x50004,
2067	.clkr = {
2068		.enable_reg = 0x50004,
2069		.enable_mask = BIT(0),
2070		.hw.init = &(struct clk_init_data){
2071			.name = "gcc_camss_ispif_ahb_clk",
2072			.parent_names = (const char *[]){
2073				"camss_ahb_clk_src",
2074			},
2075			.num_parents = 1,
2076			.flags = CLK_SET_RATE_PARENT,
2077			.ops = &clk_branch2_ops,
2078		},
2079	},
2080};
2081
2082static struct clk_branch gcc_camss_jpeg0_clk = {
2083	.halt_reg = 0x57020,
2084	.clkr = {
2085		.enable_reg = 0x57020,
2086		.enable_mask = BIT(0),
2087		.hw.init = &(struct clk_init_data){
2088			.name = "gcc_camss_jpeg0_clk",
2089			.parent_names = (const char *[]){
2090				"jpeg0_clk_src",
2091			},
2092			.num_parents = 1,
2093			.flags = CLK_SET_RATE_PARENT,
2094			.ops = &clk_branch2_ops,
2095		},
2096	},
2097};
2098
2099static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2100	.halt_reg = 0x57024,
2101	.clkr = {
2102		.enable_reg = 0x57024,
2103		.enable_mask = BIT(0),
2104		.hw.init = &(struct clk_init_data){
2105			.name = "gcc_camss_jpeg_ahb_clk",
2106			.parent_names = (const char *[]){
2107				"camss_ahb_clk_src",
2108			},
2109			.num_parents = 1,
2110			.flags = CLK_SET_RATE_PARENT,
2111			.ops = &clk_branch2_ops,
2112		},
2113	},
2114};
2115
2116static struct clk_branch gcc_camss_jpeg_axi_clk = {
2117	.halt_reg = 0x57028,
2118	.clkr = {
2119		.enable_reg = 0x57028,
2120		.enable_mask = BIT(0),
2121		.hw.init = &(struct clk_init_data){
2122			.name = "gcc_camss_jpeg_axi_clk",
2123			.parent_names = (const char *[]){
2124				"system_noc_bfdcd_clk_src",
2125			},
2126			.num_parents = 1,
2127			.flags = CLK_SET_RATE_PARENT,
2128			.ops = &clk_branch2_ops,
2129		},
2130	},
2131};
2132
2133static struct clk_branch gcc_camss_mclk0_clk = {
2134	.halt_reg = 0x52018,
2135	.clkr = {
2136		.enable_reg = 0x52018,
2137		.enable_mask = BIT(0),
2138		.hw.init = &(struct clk_init_data){
2139			.name = "gcc_camss_mclk0_clk",
2140			.parent_names = (const char *[]){
2141				"mclk0_clk_src",
2142			},
2143			.num_parents = 1,
2144			.flags = CLK_SET_RATE_PARENT,
2145			.ops = &clk_branch2_ops,
2146		},
2147	},
2148};
2149
2150static struct clk_branch gcc_camss_mclk1_clk = {
2151	.halt_reg = 0x53018,
2152	.clkr = {
2153		.enable_reg = 0x53018,
2154		.enable_mask = BIT(0),
2155		.hw.init = &(struct clk_init_data){
2156			.name = "gcc_camss_mclk1_clk",
2157			.parent_names = (const char *[]){
2158				"mclk1_clk_src",
2159			},
2160			.num_parents = 1,
2161			.flags = CLK_SET_RATE_PARENT,
2162			.ops = &clk_branch2_ops,
2163		},
2164	},
2165};
2166
2167static struct clk_branch gcc_camss_micro_ahb_clk = {
2168	.halt_reg = 0x5600c,
2169	.clkr = {
2170		.enable_reg = 0x5600c,
2171		.enable_mask = BIT(0),
2172		.hw.init = &(struct clk_init_data){
2173			.name = "gcc_camss_micro_ahb_clk",
2174			.parent_names = (const char *[]){
2175				"camss_ahb_clk_src",
2176			},
2177			.num_parents = 1,
2178			.flags = CLK_SET_RATE_PARENT,
2179			.ops = &clk_branch2_ops,
2180		},
2181	},
2182};
2183
2184static struct clk_branch gcc_camss_csi0phytimer_clk = {
2185	.halt_reg = 0x4e01c,
2186	.clkr = {
2187		.enable_reg = 0x4e01c,
2188		.enable_mask = BIT(0),
2189		.hw.init = &(struct clk_init_data){
2190			.name = "gcc_camss_csi0phytimer_clk",
2191			.parent_names = (const char *[]){
2192				"csi0phytimer_clk_src",
2193			},
2194			.num_parents = 1,
2195			.flags = CLK_SET_RATE_PARENT,
2196			.ops = &clk_branch2_ops,
2197		},
2198	},
2199};
2200
2201static struct clk_branch gcc_camss_csi1phytimer_clk = {
2202	.halt_reg = 0x4f01c,
2203	.clkr = {
2204		.enable_reg = 0x4f01c,
2205		.enable_mask = BIT(0),
2206		.hw.init = &(struct clk_init_data){
2207			.name = "gcc_camss_csi1phytimer_clk",
2208			.parent_names = (const char *[]){
2209				"csi1phytimer_clk_src",
2210			},
2211			.num_parents = 1,
2212			.flags = CLK_SET_RATE_PARENT,
2213			.ops = &clk_branch2_ops,
2214		},
2215	},
2216};
2217
2218static struct clk_branch gcc_camss_ahb_clk = {
2219	.halt_reg = 0x5a014,
2220	.clkr = {
2221		.enable_reg = 0x5a014,
2222		.enable_mask = BIT(0),
2223		.hw.init = &(struct clk_init_data){
2224			.name = "gcc_camss_ahb_clk",
2225			.parent_names = (const char *[]){
2226				"camss_ahb_clk_src",
2227			},
2228			.num_parents = 1,
2229			.flags = CLK_SET_RATE_PARENT,
2230			.ops = &clk_branch2_ops,
2231		},
2232	},
2233};
2234
2235static struct clk_branch gcc_camss_top_ahb_clk = {
2236	.halt_reg = 0x56004,
2237	.clkr = {
2238		.enable_reg = 0x56004,
2239		.enable_mask = BIT(0),
2240		.hw.init = &(struct clk_init_data){
2241			.name = "gcc_camss_top_ahb_clk",
2242			.parent_names = (const char *[]){
2243				"pcnoc_bfdcd_clk_src",
2244			},
2245			.num_parents = 1,
2246			.flags = CLK_SET_RATE_PARENT,
2247			.ops = &clk_branch2_ops,
2248		},
2249	},
2250};
2251
2252static struct clk_branch gcc_camss_cpp_ahb_clk = {
2253	.halt_reg = 0x58040,
2254	.clkr = {
2255		.enable_reg = 0x58040,
2256		.enable_mask = BIT(0),
2257		.hw.init = &(struct clk_init_data){
2258			.name = "gcc_camss_cpp_ahb_clk",
2259			.parent_names = (const char *[]){
2260				"camss_ahb_clk_src",
2261			},
2262			.num_parents = 1,
2263			.flags = CLK_SET_RATE_PARENT,
2264			.ops = &clk_branch2_ops,
2265		},
2266	},
2267};
2268
2269static struct clk_branch gcc_camss_cpp_clk = {
2270	.halt_reg = 0x5803c,
2271	.clkr = {
2272		.enable_reg = 0x5803c,
2273		.enable_mask = BIT(0),
2274		.hw.init = &(struct clk_init_data){
2275			.name = "gcc_camss_cpp_clk",
2276			.parent_names = (const char *[]){
2277				"cpp_clk_src",
2278			},
2279			.num_parents = 1,
2280			.flags = CLK_SET_RATE_PARENT,
2281			.ops = &clk_branch2_ops,
2282		},
2283	},
2284};
2285
2286static struct clk_branch gcc_camss_vfe0_clk = {
2287	.halt_reg = 0x58038,
2288	.clkr = {
2289		.enable_reg = 0x58038,
2290		.enable_mask = BIT(0),
2291		.hw.init = &(struct clk_init_data){
2292			.name = "gcc_camss_vfe0_clk",
2293			.parent_names = (const char *[]){
2294				"vfe0_clk_src",
2295			},
2296			.num_parents = 1,
2297			.flags = CLK_SET_RATE_PARENT,
2298			.ops = &clk_branch2_ops,
2299		},
2300	},
2301};
2302
2303static struct clk_branch gcc_camss_vfe_ahb_clk = {
2304	.halt_reg = 0x58044,
2305	.clkr = {
2306		.enable_reg = 0x58044,
2307		.enable_mask = BIT(0),
2308		.hw.init = &(struct clk_init_data){
2309			.name = "gcc_camss_vfe_ahb_clk",
2310			.parent_names = (const char *[]){
2311				"camss_ahb_clk_src",
2312			},
2313			.num_parents = 1,
2314			.flags = CLK_SET_RATE_PARENT,
2315			.ops = &clk_branch2_ops,
2316		},
2317	},
2318};
2319
2320static struct clk_branch gcc_camss_vfe_axi_clk = {
2321	.halt_reg = 0x58048,
2322	.clkr = {
2323		.enable_reg = 0x58048,
2324		.enable_mask = BIT(0),
2325		.hw.init = &(struct clk_init_data){
2326			.name = "gcc_camss_vfe_axi_clk",
2327			.parent_names = (const char *[]){
2328				"system_noc_bfdcd_clk_src",
2329			},
2330			.num_parents = 1,
2331			.flags = CLK_SET_RATE_PARENT,
2332			.ops = &clk_branch2_ops,
2333		},
2334	},
2335};
2336
2337static struct clk_branch gcc_crypto_ahb_clk = {
2338	.halt_reg = 0x16024,
2339	.halt_check = BRANCH_HALT_VOTED,
2340	.clkr = {
2341		.enable_reg = 0x45004,
2342		.enable_mask = BIT(0),
2343		.hw.init = &(struct clk_init_data){
2344			.name = "gcc_crypto_ahb_clk",
2345			.parent_names = (const char *[]){
2346				"pcnoc_bfdcd_clk_src",
2347			},
2348			.num_parents = 1,
2349			.ops = &clk_branch2_ops,
2350		},
2351	},
2352};
2353
2354static struct clk_branch gcc_crypto_axi_clk = {
2355	.halt_reg = 0x16020,
2356	.halt_check = BRANCH_HALT_VOTED,
2357	.clkr = {
2358		.enable_reg = 0x45004,
2359		.enable_mask = BIT(1),
2360		.hw.init = &(struct clk_init_data){
2361			.name = "gcc_crypto_axi_clk",
2362			.parent_names = (const char *[]){
2363				"pcnoc_bfdcd_clk_src",
2364			},
2365			.num_parents = 1,
2366			.flags = CLK_SET_RATE_PARENT,
2367			.ops = &clk_branch2_ops,
2368		},
2369	},
2370};
2371
2372static struct clk_branch gcc_crypto_clk = {
2373	.halt_reg = 0x1601c,
2374	.halt_check = BRANCH_HALT_VOTED,
2375	.clkr = {
2376		.enable_reg = 0x45004,
2377		.enable_mask = BIT(2),
2378		.hw.init = &(struct clk_init_data){
2379			.name = "gcc_crypto_clk",
2380			.parent_names = (const char *[]){
2381				"crypto_clk_src",
2382			},
2383			.num_parents = 1,
2384			.ops = &clk_branch2_ops,
2385		},
2386	},
2387};
2388
2389static struct clk_branch gcc_oxili_gmem_clk = {
2390	.halt_reg = 0x59024,
2391	.clkr = {
2392		.enable_reg = 0x59024,
2393		.enable_mask = BIT(0),
2394		.hw.init = &(struct clk_init_data){
2395			.name = "gcc_oxili_gmem_clk",
2396			.parent_names = (const char *[]){
2397				"gfx3d_clk_src",
2398			},
2399			.num_parents = 1,
2400			.flags = CLK_SET_RATE_PARENT,
2401			.ops = &clk_branch2_ops,
2402		},
2403	},
2404};
2405
2406static struct clk_branch gcc_gp1_clk = {
2407	.halt_reg = 0x08000,
2408	.clkr = {
2409		.enable_reg = 0x08000,
2410		.enable_mask = BIT(0),
2411		.hw.init = &(struct clk_init_data){
2412			.name = "gcc_gp1_clk",
2413			.parent_names = (const char *[]){
2414				"gp1_clk_src",
2415			},
2416			.num_parents = 1,
2417			.flags = CLK_SET_RATE_PARENT,
2418			.ops = &clk_branch2_ops,
2419		},
2420	},
2421};
2422
2423static struct clk_branch gcc_gp2_clk = {
2424	.halt_reg = 0x09000,
2425	.clkr = {
2426		.enable_reg = 0x09000,
2427		.enable_mask = BIT(0),
2428		.hw.init = &(struct clk_init_data){
2429			.name = "gcc_gp2_clk",
2430			.parent_names = (const char *[]){
2431				"gp2_clk_src",
2432			},
2433			.num_parents = 1,
2434			.flags = CLK_SET_RATE_PARENT,
2435			.ops = &clk_branch2_ops,
2436		},
2437	},
2438};
2439
2440static struct clk_branch gcc_gp3_clk = {
2441	.halt_reg = 0x0a000,
2442	.clkr = {
2443		.enable_reg = 0x0a000,
2444		.enable_mask = BIT(0),
2445		.hw.init = &(struct clk_init_data){
2446			.name = "gcc_gp3_clk",
2447			.parent_names = (const char *[]){
2448				"gp3_clk_src",
2449			},
2450			.num_parents = 1,
2451			.flags = CLK_SET_RATE_PARENT,
2452			.ops = &clk_branch2_ops,
2453		},
2454	},
2455};
2456
2457static struct clk_branch gcc_mdss_ahb_clk = {
2458	.halt_reg = 0x4d07c,
2459	.clkr = {
2460		.enable_reg = 0x4d07c,
2461		.enable_mask = BIT(0),
2462		.hw.init = &(struct clk_init_data){
2463			.name = "gcc_mdss_ahb_clk",
2464			.parent_names = (const char *[]){
2465				"pcnoc_bfdcd_clk_src",
2466			},
2467			.num_parents = 1,
2468			.flags = CLK_SET_RATE_PARENT,
2469			.ops = &clk_branch2_ops,
2470		},
2471	},
2472};
2473
2474static struct clk_branch gcc_mdss_axi_clk = {
2475	.halt_reg = 0x4d080,
2476	.clkr = {
2477		.enable_reg = 0x4d080,
2478		.enable_mask = BIT(0),
2479		.hw.init = &(struct clk_init_data){
2480			.name = "gcc_mdss_axi_clk",
2481			.parent_names = (const char *[]){
2482				"system_noc_bfdcd_clk_src",
2483			},
2484			.num_parents = 1,
2485			.flags = CLK_SET_RATE_PARENT,
2486			.ops = &clk_branch2_ops,
2487		},
2488	},
2489};
2490
2491static struct clk_branch gcc_mdss_byte0_clk = {
2492	.halt_reg = 0x4d094,
2493	.clkr = {
2494		.enable_reg = 0x4d094,
2495		.enable_mask = BIT(0),
2496		.hw.init = &(struct clk_init_data){
2497			.name = "gcc_mdss_byte0_clk",
2498			.parent_names = (const char *[]){
2499				"byte0_clk_src",
2500			},
2501			.num_parents = 1,
2502			.flags = CLK_SET_RATE_PARENT,
2503			.ops = &clk_branch2_ops,
2504		},
2505	},
2506};
2507
2508static struct clk_branch gcc_mdss_esc0_clk = {
2509	.halt_reg = 0x4d098,
2510	.clkr = {
2511		.enable_reg = 0x4d098,
2512		.enable_mask = BIT(0),
2513		.hw.init = &(struct clk_init_data){
2514			.name = "gcc_mdss_esc0_clk",
2515			.parent_names = (const char *[]){
2516				"esc0_clk_src",
2517			},
2518			.num_parents = 1,
2519			.flags = CLK_SET_RATE_PARENT,
2520			.ops = &clk_branch2_ops,
2521		},
2522	},
2523};
2524
2525static struct clk_branch gcc_mdss_mdp_clk = {
2526	.halt_reg = 0x4D088,
2527	.clkr = {
2528		.enable_reg = 0x4D088,
2529		.enable_mask = BIT(0),
2530		.hw.init = &(struct clk_init_data){
2531			.name = "gcc_mdss_mdp_clk",
2532			.parent_names = (const char *[]){
2533				"mdp_clk_src",
2534			},
2535			.num_parents = 1,
2536			.flags = CLK_SET_RATE_PARENT,
2537			.ops = &clk_branch2_ops,
2538		},
2539	},
2540};
2541
2542static struct clk_branch gcc_mdss_pclk0_clk = {
2543	.halt_reg = 0x4d084,
2544	.clkr = {
2545		.enable_reg = 0x4d084,
2546		.enable_mask = BIT(0),
2547		.hw.init = &(struct clk_init_data){
2548			.name = "gcc_mdss_pclk0_clk",
2549			.parent_names = (const char *[]){
2550				"pclk0_clk_src",
2551			},
2552			.num_parents = 1,
2553			.flags = CLK_SET_RATE_PARENT,
2554			.ops = &clk_branch2_ops,
2555		},
2556	},
2557};
2558
2559static struct clk_branch gcc_mdss_vsync_clk = {
2560	.halt_reg = 0x4d090,
2561	.clkr = {
2562		.enable_reg = 0x4d090,
2563		.enable_mask = BIT(0),
2564		.hw.init = &(struct clk_init_data){
2565			.name = "gcc_mdss_vsync_clk",
2566			.parent_names = (const char *[]){
2567				"vsync_clk_src",
2568			},
2569			.num_parents = 1,
2570			.flags = CLK_SET_RATE_PARENT,
2571			.ops = &clk_branch2_ops,
2572		},
2573	},
2574};
2575
2576static struct clk_branch gcc_mss_cfg_ahb_clk = {
2577	.halt_reg = 0x49000,
2578	.clkr = {
2579		.enable_reg = 0x49000,
2580		.enable_mask = BIT(0),
2581		.hw.init = &(struct clk_init_data){
2582			.name = "gcc_mss_cfg_ahb_clk",
2583			.parent_names = (const char *[]){
2584				"pcnoc_bfdcd_clk_src",
2585			},
2586			.num_parents = 1,
2587			.flags = CLK_SET_RATE_PARENT,
2588			.ops = &clk_branch2_ops,
2589		},
2590	},
2591};
2592
2593static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
2594	.halt_reg = 0x49004,
2595	.clkr = {
2596		.enable_reg = 0x49004,
2597		.enable_mask = BIT(0),
2598		.hw.init = &(struct clk_init_data){
2599			.name = "gcc_mss_q6_bimc_axi_clk",
2600			.parent_names = (const char *[]){
2601				"bimc_ddr_clk_src",
2602			},
2603			.num_parents = 1,
2604			.flags = CLK_SET_RATE_PARENT,
2605			.ops = &clk_branch2_ops,
2606		},
2607	},
2608};
2609
2610static struct clk_branch gcc_oxili_ahb_clk = {
2611	.halt_reg = 0x59028,
2612	.clkr = {
2613		.enable_reg = 0x59028,
2614		.enable_mask = BIT(0),
2615		.hw.init = &(struct clk_init_data){
2616			.name = "gcc_oxili_ahb_clk",
2617			.parent_names = (const char *[]){
2618				"pcnoc_bfdcd_clk_src",
2619			},
2620			.num_parents = 1,
2621			.flags = CLK_SET_RATE_PARENT,
2622			.ops = &clk_branch2_ops,
2623		},
2624	},
2625};
2626
2627static struct clk_branch gcc_oxili_gfx3d_clk = {
2628	.halt_reg = 0x59020,
2629	.clkr = {
2630		.enable_reg = 0x59020,
2631		.enable_mask = BIT(0),
2632		.hw.init = &(struct clk_init_data){
2633			.name = "gcc_oxili_gfx3d_clk",
2634			.parent_names = (const char *[]){
2635				"gfx3d_clk_src",
2636			},
2637			.num_parents = 1,
2638			.flags = CLK_SET_RATE_PARENT,
2639			.ops = &clk_branch2_ops,
2640		},
2641	},
2642};
2643
2644static struct clk_branch gcc_pdm2_clk = {
2645	.halt_reg = 0x4400c,
2646	.clkr = {
2647		.enable_reg = 0x4400c,
2648		.enable_mask = BIT(0),
2649		.hw.init = &(struct clk_init_data){
2650			.name = "gcc_pdm2_clk",
2651			.parent_names = (const char *[]){
2652				"pdm2_clk_src",
2653			},
2654			.num_parents = 1,
2655			.flags = CLK_SET_RATE_PARENT,
2656			.ops = &clk_branch2_ops,
2657		},
2658	},
2659};
2660
2661static struct clk_branch gcc_pdm_ahb_clk = {
2662	.halt_reg = 0x44004,
2663	.clkr = {
2664		.enable_reg = 0x44004,
2665		.enable_mask = BIT(0),
2666		.hw.init = &(struct clk_init_data){
2667			.name = "gcc_pdm_ahb_clk",
2668			.parent_names = (const char *[]){
2669				"pcnoc_bfdcd_clk_src",
2670			},
2671			.num_parents = 1,
2672			.flags = CLK_SET_RATE_PARENT,
2673			.ops = &clk_branch2_ops,
2674		},
2675	},
2676};
2677
2678static struct clk_branch gcc_prng_ahb_clk = {
2679	.halt_reg = 0x13004,
2680	.halt_check = BRANCH_HALT_VOTED,
2681	.clkr = {
2682		.enable_reg = 0x45004,
2683		.enable_mask = BIT(8),
2684		.hw.init = &(struct clk_init_data){
2685			.name = "gcc_prng_ahb_clk",
2686			.parent_names = (const char *[]){
2687				"pcnoc_bfdcd_clk_src",
2688			},
2689			.num_parents = 1,
2690			.ops = &clk_branch2_ops,
2691		},
2692	},
2693};
2694
2695static struct clk_branch gcc_sdcc1_ahb_clk = {
2696	.halt_reg = 0x4201c,
2697	.clkr = {
2698		.enable_reg = 0x4201c,
2699		.enable_mask = BIT(0),
2700		.hw.init = &(struct clk_init_data){
2701			.name = "gcc_sdcc1_ahb_clk",
2702			.parent_names = (const char *[]){
2703				"pcnoc_bfdcd_clk_src",
2704			},
2705			.num_parents = 1,
2706			.flags = CLK_SET_RATE_PARENT,
2707			.ops = &clk_branch2_ops,
2708		},
2709	},
2710};
2711
2712static struct clk_branch gcc_sdcc1_apps_clk = {
2713	.halt_reg = 0x42018,
2714	.clkr = {
2715		.enable_reg = 0x42018,
2716		.enable_mask = BIT(0),
2717		.hw.init = &(struct clk_init_data){
2718			.name = "gcc_sdcc1_apps_clk",
2719			.parent_names = (const char *[]){
2720				"sdcc1_apps_clk_src",
2721			},
2722			.num_parents = 1,
2723			.flags = CLK_SET_RATE_PARENT,
2724			.ops = &clk_branch2_ops,
2725		},
2726	},
2727};
2728
2729static struct clk_branch gcc_sdcc2_ahb_clk = {
2730	.halt_reg = 0x4301c,
2731	.clkr = {
2732		.enable_reg = 0x4301c,
2733		.enable_mask = BIT(0),
2734		.hw.init = &(struct clk_init_data){
2735			.name = "gcc_sdcc2_ahb_clk",
2736			.parent_names = (const char *[]){
2737				"pcnoc_bfdcd_clk_src",
2738			},
2739			.num_parents = 1,
2740			.flags = CLK_SET_RATE_PARENT,
2741			.ops = &clk_branch2_ops,
2742		},
2743	},
2744};
2745
2746static struct clk_branch gcc_sdcc2_apps_clk = {
2747	.halt_reg = 0x43018,
2748	.clkr = {
2749		.enable_reg = 0x43018,
2750		.enable_mask = BIT(0),
2751		.hw.init = &(struct clk_init_data){
2752			.name = "gcc_sdcc2_apps_clk",
2753			.parent_names = (const char *[]){
2754				"sdcc2_apps_clk_src",
2755			},
2756			.num_parents = 1,
2757			.flags = CLK_SET_RATE_PARENT,
2758			.ops = &clk_branch2_ops,
2759		},
2760	},
2761};
2762
2763static struct clk_rcg2 bimc_ddr_clk_src = {
2764	.cmd_rcgr = 0x32004,
2765	.hid_width = 5,
2766	.parent_map = gcc_xo_gpll0_bimc_map,
2767	.clkr.hw.init = &(struct clk_init_data){
2768		.name = "bimc_ddr_clk_src",
2769		.parent_names = gcc_xo_gpll0_bimc,
2770		.num_parents = 3,
2771		.ops = &clk_rcg2_ops,
2772		.flags = CLK_GET_RATE_NOCACHE,
2773	},
2774};
2775
2776static struct clk_branch gcc_apss_tcu_clk = {
2777	.halt_reg = 0x12018,
2778	.clkr = {
2779		.enable_reg = 0x4500c,
2780		.enable_mask = BIT(1),
2781		.hw.init = &(struct clk_init_data){
2782			.name = "gcc_apss_tcu_clk",
2783			.parent_names = (const char *[]){
2784				"bimc_ddr_clk_src",
2785			},
2786			.num_parents = 1,
2787			.ops = &clk_branch2_ops,
2788		},
2789	},
2790};
2791
2792static struct clk_branch gcc_gfx_tcu_clk = {
2793	.halt_reg = 0x12020,
2794	.clkr = {
2795		.enable_reg = 0x4500c,
2796		.enable_mask = BIT(2),
2797		.hw.init = &(struct clk_init_data){
2798			.name = "gcc_gfx_tcu_clk",
2799			.parent_names = (const char *[]){
2800				"bimc_ddr_clk_src",
2801			},
2802			.num_parents = 1,
2803			.ops = &clk_branch2_ops,
2804		},
2805	},
2806};
2807
2808static struct clk_branch gcc_gtcu_ahb_clk = {
2809	.halt_reg = 0x12044,
2810	.clkr = {
2811		.enable_reg = 0x4500c,
2812		.enable_mask = BIT(13),
2813		.hw.init = &(struct clk_init_data){
2814			.name = "gcc_gtcu_ahb_clk",
2815			.parent_names = (const char *[]){
2816				"pcnoc_bfdcd_clk_src",
2817			},
2818			.num_parents = 1,
2819			.flags = CLK_SET_RATE_PARENT,
2820			.ops = &clk_branch2_ops,
2821		},
2822	},
2823};
2824
2825static struct clk_branch gcc_bimc_gfx_clk = {
2826	.halt_reg = 0x31024,
2827	.clkr = {
2828		.enable_reg = 0x31024,
2829		.enable_mask = BIT(0),
2830		.hw.init = &(struct clk_init_data){
2831			.name = "gcc_bimc_gfx_clk",
2832			.parent_names = (const char *[]){
2833				"bimc_gpu_clk_src",
2834			},
2835			.num_parents = 1,
2836			.flags = CLK_SET_RATE_PARENT,
2837			.ops = &clk_branch2_ops,
2838		},
2839	},
2840};
2841
2842static struct clk_branch gcc_bimc_gpu_clk = {
2843	.halt_reg = 0x31040,
2844	.clkr = {
2845		.enable_reg = 0x31040,
2846		.enable_mask = BIT(0),
2847		.hw.init = &(struct clk_init_data){
2848			.name = "gcc_bimc_gpu_clk",
2849			.parent_names = (const char *[]){
2850				"bimc_gpu_clk_src",
2851			},
2852			.num_parents = 1,
2853			.flags = CLK_SET_RATE_PARENT,
2854			.ops = &clk_branch2_ops,
2855		},
2856	},
2857};
2858
2859static struct clk_branch gcc_jpeg_tbu_clk = {
2860	.halt_reg = 0x12034,
2861	.clkr = {
2862		.enable_reg = 0x4500c,
2863		.enable_mask = BIT(10),
2864		.hw.init = &(struct clk_init_data){
2865			.name = "gcc_jpeg_tbu_clk",
2866			.parent_names = (const char *[]){
2867				"system_noc_bfdcd_clk_src",
2868			},
2869			.num_parents = 1,
2870			.flags = CLK_SET_RATE_PARENT,
2871			.ops = &clk_branch2_ops,
2872		},
2873	},
2874};
2875
2876static struct clk_branch gcc_mdp_tbu_clk = {
2877	.halt_reg = 0x1201c,
2878	.clkr = {
2879		.enable_reg = 0x4500c,
2880		.enable_mask = BIT(4),
2881		.hw.init = &(struct clk_init_data){
2882			.name = "gcc_mdp_tbu_clk",
2883			.parent_names = (const char *[]){
2884				"system_noc_bfdcd_clk_src",
2885			},
2886			.num_parents = 1,
2887			.flags = CLK_SET_RATE_PARENT,
2888			.ops = &clk_branch2_ops,
2889		},
2890	},
2891};
2892
2893static struct clk_branch gcc_smmu_cfg_clk = {
2894	.halt_reg = 0x12038,
2895	.clkr = {
2896		.enable_reg = 0x4500c,
2897		.enable_mask = BIT(12),
2898		.hw.init = &(struct clk_init_data){
2899			.name = "gcc_smmu_cfg_clk",
2900			.parent_names = (const char *[]){
2901				"pcnoc_bfdcd_clk_src",
2902			},
2903			.num_parents = 1,
2904			.flags = CLK_SET_RATE_PARENT,
2905			.ops = &clk_branch2_ops,
2906		},
2907	},
2908};
2909
2910static struct clk_branch gcc_venus_tbu_clk = {
2911	.halt_reg = 0x12014,
2912	.clkr = {
2913		.enable_reg = 0x4500c,
2914		.enable_mask = BIT(5),
2915		.hw.init = &(struct clk_init_data){
2916			.name = "gcc_venus_tbu_clk",
2917			.parent_names = (const char *[]){
2918				"system_noc_bfdcd_clk_src",
2919			},
2920			.num_parents = 1,
2921			.flags = CLK_SET_RATE_PARENT,
2922			.ops = &clk_branch2_ops,
2923		},
2924	},
2925};
2926
2927static struct clk_branch gcc_vfe_tbu_clk = {
2928	.halt_reg = 0x1203c,
2929	.clkr = {
2930		.enable_reg = 0x4500c,
2931		.enable_mask = BIT(9),
2932		.hw.init = &(struct clk_init_data){
2933			.name = "gcc_vfe_tbu_clk",
2934			.parent_names = (const char *[]){
2935				"system_noc_bfdcd_clk_src",
2936			},
2937			.num_parents = 1,
2938			.flags = CLK_SET_RATE_PARENT,
2939			.ops = &clk_branch2_ops,
2940		},
2941	},
2942};
2943
2944static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2945	.halt_reg = 0x4102c,
2946	.clkr = {
2947		.enable_reg = 0x4102c,
2948		.enable_mask = BIT(0),
2949		.hw.init = &(struct clk_init_data){
2950			.name = "gcc_usb2a_phy_sleep_clk",
2951			.parent_names = (const char *[]){
2952				"sleep_clk_src",
2953			},
2954			.num_parents = 1,
2955			.flags = CLK_SET_RATE_PARENT,
2956			.ops = &clk_branch2_ops,
2957		},
2958	},
2959};
2960
2961static struct clk_branch gcc_usb_hs_ahb_clk = {
2962	.halt_reg = 0x41008,
2963	.clkr = {
2964		.enable_reg = 0x41008,
2965		.enable_mask = BIT(0),
2966		.hw.init = &(struct clk_init_data){
2967			.name = "gcc_usb_hs_ahb_clk",
2968			.parent_names = (const char *[]){
2969				"pcnoc_bfdcd_clk_src",
2970			},
2971			.num_parents = 1,
2972			.flags = CLK_SET_RATE_PARENT,
2973			.ops = &clk_branch2_ops,
2974		},
2975	},
2976};
2977
2978static struct clk_branch gcc_usb_hs_system_clk = {
2979	.halt_reg = 0x41004,
2980	.clkr = {
2981		.enable_reg = 0x41004,
2982		.enable_mask = BIT(0),
2983		.hw.init = &(struct clk_init_data){
2984			.name = "gcc_usb_hs_system_clk",
2985			.parent_names = (const char *[]){
2986				"usb_hs_system_clk_src",
2987			},
2988			.num_parents = 1,
2989			.flags = CLK_SET_RATE_PARENT,
2990			.ops = &clk_branch2_ops,
2991		},
2992	},
2993};
2994
2995static struct clk_branch gcc_venus0_ahb_clk = {
2996	.halt_reg = 0x4c020,
2997	.clkr = {
2998		.enable_reg = 0x4c020,
2999		.enable_mask = BIT(0),
3000		.hw.init = &(struct clk_init_data){
3001			.name = "gcc_venus0_ahb_clk",
3002			.parent_names = (const char *[]){
3003				"pcnoc_bfdcd_clk_src",
3004			},
3005			.num_parents = 1,
3006			.flags = CLK_SET_RATE_PARENT,
3007			.ops = &clk_branch2_ops,
3008		},
3009	},
3010};
3011
3012static struct clk_branch gcc_venus0_axi_clk = {
3013	.halt_reg = 0x4c024,
3014	.clkr = {
3015		.enable_reg = 0x4c024,
3016		.enable_mask = BIT(0),
3017		.hw.init = &(struct clk_init_data){
3018			.name = "gcc_venus0_axi_clk",
3019			.parent_names = (const char *[]){
3020				"system_noc_bfdcd_clk_src",
3021			},
3022			.num_parents = 1,
3023			.flags = CLK_SET_RATE_PARENT,
3024			.ops = &clk_branch2_ops,
3025		},
3026	},
3027};
3028
3029static struct clk_branch gcc_venus0_vcodec0_clk = {
3030	.halt_reg = 0x4c01c,
3031	.clkr = {
3032		.enable_reg = 0x4c01c,
3033		.enable_mask = BIT(0),
3034		.hw.init = &(struct clk_init_data){
3035			.name = "gcc_venus0_vcodec0_clk",
3036			.parent_names = (const char *[]){
3037				"vcodec0_clk_src",
3038			},
3039			.num_parents = 1,
3040			.flags = CLK_SET_RATE_PARENT,
3041			.ops = &clk_branch2_ops,
3042		},
3043	},
3044};
3045
3046static struct gdsc venus_gdsc = {
3047	.gdscr = 0x4c018,
3048	.pd = {
3049		.name = "venus",
3050	},
3051	.pwrsts = PWRSTS_OFF_ON,
3052};
3053
3054static struct gdsc mdss_gdsc = {
3055	.gdscr = 0x4d078,
3056	.pd = {
3057		.name = "mdss",
3058	},
3059	.pwrsts = PWRSTS_OFF_ON,
3060};
3061
3062static struct gdsc jpeg_gdsc = {
3063	.gdscr = 0x5701c,
3064	.pd = {
3065		.name = "jpeg",
3066	},
3067	.pwrsts = PWRSTS_OFF_ON,
3068};
3069
3070static struct gdsc vfe_gdsc = {
3071	.gdscr = 0x58034,
3072	.pd = {
3073		.name = "vfe",
3074	},
3075	.pwrsts = PWRSTS_OFF_ON,
3076};
3077
3078static struct gdsc oxili_gdsc = {
3079	.gdscr = 0x5901c,
3080	.pd = {
3081		.name = "oxili",
3082	},
3083	.pwrsts = PWRSTS_OFF_ON,
3084};
3085
3086static struct clk_regmap *gcc_msm8916_clocks[] = {
3087	[GPLL0] = &gpll0.clkr,
3088	[GPLL0_VOTE] = &gpll0_vote,
3089	[BIMC_PLL] = &bimc_pll.clkr,
3090	[BIMC_PLL_VOTE] = &bimc_pll_vote,
3091	[GPLL1] = &gpll1.clkr,
3092	[GPLL1_VOTE] = &gpll1_vote,
3093	[GPLL2] = &gpll2.clkr,
3094	[GPLL2_VOTE] = &gpll2_vote,
3095	[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3096	[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3097	[CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
3098	[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3099	[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3100	[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3101	[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3102	[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3103	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3104	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3105	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3106	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3107	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3108	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3109	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3110	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3111	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3112	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3113	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3114	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3115	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3116	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3117	[CCI_CLK_SRC] = &cci_clk_src.clkr,
3118	[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3119	[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3120	[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3121	[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3122	[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3123	[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3124	[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3125	[CPP_CLK_SRC] = &cpp_clk_src.clkr,
3126	[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3127	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
3128	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
3129	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
3130	[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3131	[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3132	[MDP_CLK_SRC] = &mdp_clk_src.clkr,
3133	[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3134	[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3135	[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3136	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3137	[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3138	[APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
3139	[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3140	[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3141	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3142	[GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3143	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3144	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3145	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3146	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3147	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3148	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3149	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3150	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3151	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3152	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3153	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3154	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3155	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3156	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3157	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3158	[GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3159	[GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3160	[GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3161	[GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3162	[GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
3163	[GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3164	[GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3165	[GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3166	[GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3167	[GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3168	[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3169	[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3170	[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3171	[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3172	[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3173	[GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3174	[GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
3175	[GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3176	[GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3177	[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3178	[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3179	[GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3180	[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3181	[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3182	[GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
3183	[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3184	[GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3185	[GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3186	[GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3187	[GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
3188	[GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
3189	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3190	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3191	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3192	[GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
3193	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3194	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3195	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3196	[GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
3197	[GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
3198	[GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
3199	[GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
3200	[GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
3201	[GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
3202	[GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
3203	[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3204	[GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
3205	[GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
3206	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3207	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3208	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3209	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3210	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3211	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3212	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3213	[GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
3214	[GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3215	[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3216	[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3217	[GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3218	[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3219	[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3220	[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3221	[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3222	[GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
3223	[GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
3224	[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
3225	[BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
3226	[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
3227	[GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
3228	[BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
3229	[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3230	[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
3231	[ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr,
3232	[ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr,
3233	[ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr,
3234	[ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr,
3235	[ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr,
3236	[CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr,
3237	[GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr,
3238	[GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr,
3239	[GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr,
3240	[GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr,
3241	[GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] =	&gcc_ultaudio_ahbfabric_ixfabric_clk.clkr,
3242	[GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr,
3243	[GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr,
3244	[GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
3245	[GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
3246	[GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
3247	[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3248};
3249
3250static struct gdsc *gcc_msm8916_gdscs[] = {
3251	[VENUS_GDSC] = &venus_gdsc,
3252	[MDSS_GDSC] = &mdss_gdsc,
3253	[JPEG_GDSC] = &jpeg_gdsc,
3254	[VFE_GDSC] = &vfe_gdsc,
3255	[OXILI_GDSC] = &oxili_gdsc,
3256};
3257
3258static const struct qcom_reset_map gcc_msm8916_resets[] = {
3259	[GCC_BLSP1_BCR] = { 0x01000 },
3260	[GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3261	[GCC_BLSP1_UART1_BCR] = { 0x02038 },
3262	[GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3263	[GCC_BLSP1_UART2_BCR] = { 0x03028 },
3264	[GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3265	[GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3266	[GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3267	[GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3268	[GCC_IMEM_BCR] = { 0x0e000 },
3269	[GCC_SMMU_BCR] = { 0x12000 },
3270	[GCC_APSS_TCU_BCR] = { 0x12050 },
3271	[GCC_SMMU_XPU_BCR] = { 0x12054 },
3272	[GCC_PCNOC_TBU_BCR] = { 0x12058 },
3273	[GCC_PRNG_BCR] = { 0x13000 },
3274	[GCC_BOOT_ROM_BCR] = { 0x13008 },
3275	[GCC_CRYPTO_BCR] = { 0x16000 },
3276	[GCC_SEC_CTRL_BCR] = { 0x1a000 },
3277	[GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3278	[GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3279	[GCC_DEHR_BCR] = { 0x1f000 },
3280	[GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3281	[GCC_PCNOC_BCR] = { 0x27018 },
3282	[GCC_TCSR_BCR] = { 0x28000 },
3283	[GCC_QDSS_BCR] = { 0x29000 },
3284	[GCC_DCD_BCR] = { 0x2a000 },
3285	[GCC_MSG_RAM_BCR] = { 0x2b000 },
3286	[GCC_MPM_BCR] = { 0x2c000 },
3287	[GCC_SPMI_BCR] = { 0x2e000 },
3288	[GCC_SPDM_BCR] = { 0x2f000 },
3289	[GCC_MM_SPDM_BCR] = { 0x2f024 },
3290	[GCC_BIMC_BCR] = { 0x31000 },
3291	[GCC_RBCPR_BCR] = { 0x33000 },
3292	[GCC_TLMM_BCR] = { 0x34000 },
3293	[GCC_USB_HS_BCR] = { 0x41000 },
3294	[GCC_USB2A_PHY_BCR] = { 0x41028 },
3295	[GCC_SDCC1_BCR] = { 0x42000 },
3296	[GCC_SDCC2_BCR] = { 0x43000 },
3297	[GCC_PDM_BCR] = { 0x44000 },
3298	[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3299	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3300	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3301	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3302	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3303	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3304	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3305	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3306	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3307	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3308	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3309	[GCC_MMSS_BCR] = { 0x4b000 },
3310	[GCC_VENUS0_BCR] = { 0x4c014 },
3311	[GCC_MDSS_BCR] = { 0x4d074 },
3312	[GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3313	[GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3314	[GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3315	[GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3316	[GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3317	[GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3318	[GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3319	[GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3320	[GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3321	[GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3322	[GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3323	[GCC_CAMSS_CCI_BCR] = { 0x51014 },
3324	[GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3325	[GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3326	[GCC_CAMSS_GP0_BCR] = { 0x54014 },
3327	[GCC_CAMSS_GP1_BCR] = { 0x55014 },
3328	[GCC_CAMSS_TOP_BCR] = { 0x56000 },
3329	[GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3330	[GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3331	[GCC_CAMSS_VFE_BCR] = { 0x58030 },
3332	[GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3333	[GCC_OXILI_BCR] = { 0x59018 },
3334	[GCC_GMEM_BCR] = { 0x5902c },
3335	[GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3336	[GCC_MDP_TBU_BCR] = { 0x62000 },
3337	[GCC_GFX_TBU_BCR] = { 0x63000 },
3338	[GCC_GFX_TCU_BCR] = { 0x64000 },
3339	[GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3340	[GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3341	[GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3342	[GCC_GTCU_AHB_BCR] = { 0x68000 },
3343	[GCC_SMMU_CFG_BCR] = { 0x69000 },
3344	[GCC_VFE_TBU_BCR] = { 0x6a000 },
3345	[GCC_VENUS_TBU_BCR] = { 0x6b000 },
3346	[GCC_JPEG_TBU_BCR] = { 0x6c000 },
3347	[GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3348	[GCC_SMMU_CATS_BCR] = { 0x7c000 },
3349};
3350
3351static const struct regmap_config gcc_msm8916_regmap_config = {
3352	.reg_bits	= 32,
3353	.reg_stride	= 4,
3354	.val_bits	= 32,
3355	.max_register	= 0x80000,
3356	.fast_io	= true,
3357};
3358
3359static const struct qcom_cc_desc gcc_msm8916_desc = {
3360	.config = &gcc_msm8916_regmap_config,
3361	.clks = gcc_msm8916_clocks,
3362	.num_clks = ARRAY_SIZE(gcc_msm8916_clocks),
3363	.resets = gcc_msm8916_resets,
3364	.num_resets = ARRAY_SIZE(gcc_msm8916_resets),
3365	.gdscs = gcc_msm8916_gdscs,
3366	.num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs),
3367};
3368
3369static const struct of_device_id gcc_msm8916_match_table[] = {
3370	{ .compatible = "qcom,gcc-msm8916" },
3371	{ }
3372};
3373MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table);
3374
3375static int gcc_msm8916_probe(struct platform_device *pdev)
3376{
3377	int ret;
3378	struct device *dev = &pdev->dev;
3379
3380	ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
3381	if (ret)
3382		return ret;
3383
3384	ret = qcom_cc_register_sleep_clk(dev);
3385	if (ret)
3386		return ret;
3387
3388	return qcom_cc_probe(pdev, &gcc_msm8916_desc);
3389}
3390
3391static struct platform_driver gcc_msm8916_driver = {
3392	.probe		= gcc_msm8916_probe,
3393	.driver		= {
3394		.name	= "gcc-msm8916",
3395		.of_match_table = gcc_msm8916_match_table,
3396	},
3397};
3398
3399static int __init gcc_msm8916_init(void)
3400{
3401	return platform_driver_register(&gcc_msm8916_driver);
3402}
3403core_initcall(gcc_msm8916_init);
3404
3405static void __exit gcc_msm8916_exit(void)
3406{
3407	platform_driver_unregister(&gcc_msm8916_driver);
3408}
3409module_exit(gcc_msm8916_exit);
3410
3411MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver");
3412MODULE_LICENSE("GPL v2");
3413MODULE_ALIAS("platform:gcc-msm8916");