1/*
  2 * Copyright 2007, Olof Johansson, PA Semi
  3 *
  4 * Based on arch/powerpc/sysdev/mpic_u3msi.c:
  5 *
  6 * Copyright 2006, Segher Boessenkool, IBM Corporation.
  7 * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
  8 *
  9 * This program is free software; you can redistribute it and/or
 10 * modify it under the terms of the GNU General Public License
 11 * as published by the Free Software Foundation; version 2 of the
 12 * License.
 13 *
 14 */
 15
 16#undef DEBUG
 17
 18#include <linux/irq.h>
 19#include <linux/bootmem.h>
 20#include <linux/msi.h>
 21#include <asm/mpic.h>
 22#include <asm/prom.h>
 23#include <asm/hw_irq.h>
 24#include <asm/ppc-pci.h>
 25#include <asm/msi_bitmap.h>
 26
 27#include "mpic.h"
 28
 29/* Allocate 16 interrupts per device, to give an alignment of 16,
 30 * since that's the size of the grouping w.r.t. affinity. If someone
 31 * needs more than 32 MSI's down the road we'll have to rethink this,
 32 * but it should be OK for now.
 33 */
 34#define ALLOC_CHUNK 16
 35
 36#define PASEMI_MSI_ADDR 0xfc080000
 37
 38/* A bit ugly, can we get this from the pci_dev somehow? */
 39static struct mpic *msi_mpic;
 40
 41
 42static void mpic_pasemi_msi_mask_irq(struct irq_data *data)
 43{
 44	pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq);
 45	mask_msi_irq(data);
 46	mpic_mask_irq(data);
 47}
 48
 49static void mpic_pasemi_msi_unmask_irq(struct irq_data *data)
 50{
 51	pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq);
 52	mpic_unmask_irq(data);
 53	unmask_msi_irq(data);
 54}
 55
 56static struct irq_chip mpic_pasemi_msi_chip = {
 57	.irq_shutdown		= mpic_pasemi_msi_mask_irq,
 58	.irq_mask		= mpic_pasemi_msi_mask_irq,
 59	.irq_unmask		= mpic_pasemi_msi_unmask_irq,
 60	.irq_eoi		= mpic_end_irq,
 61	.irq_set_type		= mpic_set_irq_type,
 62	.irq_set_affinity	= mpic_set_affinity,
 63	.name			= "PASEMI-MSI",
 64};
 65
 66static int pasemi_msi_check_device(struct pci_dev *pdev, int nvec, int type)
 67{
 68	if (type == PCI_CAP_ID_MSIX)
 69		pr_debug("pasemi_msi: MSI-X untested, trying anyway\n");
 70
 71	return 0;
 72}
 73
 74static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev)
 75{
 76	struct msi_desc *entry;
 77
 78	pr_debug("pasemi_msi_teardown_msi_irqs, pdev %p\n", pdev);
 79
 80	list_for_each_entry(entry, &pdev->msi_list, list) {
 81		if (entry->irq == NO_IRQ)
 82			continue;
 83
 84		irq_set_msi_desc(entry->irq, NULL);
 85		msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap,
 86				       virq_to_hw(entry->irq), ALLOC_CHUNK);
 87		irq_dispose_mapping(entry->irq);
 88	}
 89
 90	return;
 91}
 92
 93static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
 94{
 95	unsigned int virq;
 96	struct msi_desc *entry;
 97	struct msi_msg msg;
 98	int hwirq;
 99
100	pr_debug("pasemi_msi_setup_msi_irqs, pdev %p nvec %d type %d\n",
101		 pdev, nvec, type);
102
103	msg.address_hi = 0;
104	msg.address_lo = PASEMI_MSI_ADDR;
105
106	list_for_each_entry(entry, &pdev->msi_list, list) {
107		/* Allocate 16 interrupts for now, since that's the grouping for
108		 * affinity. This can be changed later if it turns out 32 is too
109		 * few MSIs for someone, but restrictions will apply to how the
110		 * sources can be changed independently.
111		 */
112		hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap,
113						ALLOC_CHUNK);
114		if (hwirq < 0) {
115			pr_debug("pasemi_msi: failed allocating hwirq\n");
116			return hwirq;
117		}
118
119		virq = irq_create_mapping(msi_mpic->irqhost, hwirq);
120		if (virq == NO_IRQ) {
121			pr_debug("pasemi_msi: failed mapping hwirq 0x%x\n",
122				  hwirq);
123			msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq,
124					       ALLOC_CHUNK);
125			return -ENOSPC;
126		}
127
128		/* Vector on MSI is really an offset, the hardware adds
129		 * it to the value written at the magic address. So set
130		 * it to 0 to remain sane.
131		 */
132		mpic_set_vector(virq, 0);
133
134		irq_set_msi_desc(virq, entry);
135		irq_set_chip(virq, &mpic_pasemi_msi_chip);
136		irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
137
138		pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \
139			 "addr 0x%x\n", virq, hwirq, msg.address_lo);
140
141		/* Likewise, the device writes [0...511] into the target
142		 * register to generate MSI [512...1023]
143		 */
144		msg.data = hwirq-0x200;
145		write_msi_msg(virq, &msg);
146	}
147
148	return 0;
149}
150
151int mpic_pasemi_msi_init(struct mpic *mpic)
152{
153	int rc;
154
155	if (!mpic->irqhost->of_node ||
156	    !of_device_is_compatible(mpic->irqhost->of_node,
157				     "pasemi,pwrficient-openpic"))
158		return -ENODEV;
159
160	rc = mpic_msi_init_allocator(mpic);
161	if (rc) {
162		pr_debug("pasemi_msi: Error allocating bitmap!\n");
163		return rc;
164	}
165
166	pr_debug("pasemi_msi: Registering PA Semi MPIC MSI callbacks\n");
167
168	msi_mpic = mpic;
169	WARN_ON(ppc_md.setup_msi_irqs);
170	ppc_md.setup_msi_irqs = pasemi_msi_setup_msi_irqs;
171	ppc_md.teardown_msi_irqs = pasemi_msi_teardown_msi_irqs;
172	ppc_md.msi_check_device = pasemi_msi_check_device;
173
174	return 0;
175}