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1/*
2 * arch/powerpc/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 * Copyright 2010-2012 Freescale Semiconductor, Inc.
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive
13 * for more details.
14 */
15
16#undef DEBUG
17#undef DEBUG_IPI
18#undef DEBUG_IRQ
19#undef DEBUG_LOW
20
21#include <linux/types.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/irq.h>
25#include <linux/smp.h>
26#include <linux/interrupt.h>
27#include <linux/bootmem.h>
28#include <linux/spinlock.h>
29#include <linux/pci.h>
30#include <linux/slab.h>
31#include <linux/syscore_ops.h>
32#include <linux/ratelimit.h>
33
34#include <asm/ptrace.h>
35#include <asm/signal.h>
36#include <asm/io.h>
37#include <asm/pgtable.h>
38#include <asm/irq.h>
39#include <asm/machdep.h>
40#include <asm/mpic.h>
41#include <asm/smp.h>
42
43#include "mpic.h"
44
45#ifdef DEBUG
46#define DBG(fmt...) printk(fmt)
47#else
48#define DBG(fmt...)
49#endif
50
51struct bus_type mpic_subsys = {
52 .name = "mpic",
53 .dev_name = "mpic",
54};
55EXPORT_SYMBOL_GPL(mpic_subsys);
56
57static struct mpic *mpics;
58static struct mpic *mpic_primary;
59static DEFINE_RAW_SPINLOCK(mpic_lock);
60
61#ifdef CONFIG_PPC32 /* XXX for now */
62#ifdef CONFIG_IRQ_ALL_CPUS
63#define distribute_irqs (1)
64#else
65#define distribute_irqs (0)
66#endif
67#endif
68
69#ifdef CONFIG_MPIC_WEIRD
70static u32 mpic_infos[][MPIC_IDX_END] = {
71 [0] = { /* Original OpenPIC compatible MPIC */
72 MPIC_GREG_BASE,
73 MPIC_GREG_FEATURE_0,
74 MPIC_GREG_GLOBAL_CONF_0,
75 MPIC_GREG_VENDOR_ID,
76 MPIC_GREG_IPI_VECTOR_PRI_0,
77 MPIC_GREG_IPI_STRIDE,
78 MPIC_GREG_SPURIOUS,
79 MPIC_GREG_TIMER_FREQ,
80
81 MPIC_TIMER_BASE,
82 MPIC_TIMER_STRIDE,
83 MPIC_TIMER_CURRENT_CNT,
84 MPIC_TIMER_BASE_CNT,
85 MPIC_TIMER_VECTOR_PRI,
86 MPIC_TIMER_DESTINATION,
87
88 MPIC_CPU_BASE,
89 MPIC_CPU_STRIDE,
90 MPIC_CPU_IPI_DISPATCH_0,
91 MPIC_CPU_IPI_DISPATCH_STRIDE,
92 MPIC_CPU_CURRENT_TASK_PRI,
93 MPIC_CPU_WHOAMI,
94 MPIC_CPU_INTACK,
95 MPIC_CPU_EOI,
96 MPIC_CPU_MCACK,
97
98 MPIC_IRQ_BASE,
99 MPIC_IRQ_STRIDE,
100 MPIC_IRQ_VECTOR_PRI,
101 MPIC_VECPRI_VECTOR_MASK,
102 MPIC_VECPRI_POLARITY_POSITIVE,
103 MPIC_VECPRI_POLARITY_NEGATIVE,
104 MPIC_VECPRI_SENSE_LEVEL,
105 MPIC_VECPRI_SENSE_EDGE,
106 MPIC_VECPRI_POLARITY_MASK,
107 MPIC_VECPRI_SENSE_MASK,
108 MPIC_IRQ_DESTINATION
109 },
110 [1] = { /* Tsi108/109 PIC */
111 TSI108_GREG_BASE,
112 TSI108_GREG_FEATURE_0,
113 TSI108_GREG_GLOBAL_CONF_0,
114 TSI108_GREG_VENDOR_ID,
115 TSI108_GREG_IPI_VECTOR_PRI_0,
116 TSI108_GREG_IPI_STRIDE,
117 TSI108_GREG_SPURIOUS,
118 TSI108_GREG_TIMER_FREQ,
119
120 TSI108_TIMER_BASE,
121 TSI108_TIMER_STRIDE,
122 TSI108_TIMER_CURRENT_CNT,
123 TSI108_TIMER_BASE_CNT,
124 TSI108_TIMER_VECTOR_PRI,
125 TSI108_TIMER_DESTINATION,
126
127 TSI108_CPU_BASE,
128 TSI108_CPU_STRIDE,
129 TSI108_CPU_IPI_DISPATCH_0,
130 TSI108_CPU_IPI_DISPATCH_STRIDE,
131 TSI108_CPU_CURRENT_TASK_PRI,
132 TSI108_CPU_WHOAMI,
133 TSI108_CPU_INTACK,
134 TSI108_CPU_EOI,
135 TSI108_CPU_MCACK,
136
137 TSI108_IRQ_BASE,
138 TSI108_IRQ_STRIDE,
139 TSI108_IRQ_VECTOR_PRI,
140 TSI108_VECPRI_VECTOR_MASK,
141 TSI108_VECPRI_POLARITY_POSITIVE,
142 TSI108_VECPRI_POLARITY_NEGATIVE,
143 TSI108_VECPRI_SENSE_LEVEL,
144 TSI108_VECPRI_SENSE_EDGE,
145 TSI108_VECPRI_POLARITY_MASK,
146 TSI108_VECPRI_SENSE_MASK,
147 TSI108_IRQ_DESTINATION
148 },
149};
150
151#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
152
153#else /* CONFIG_MPIC_WEIRD */
154
155#define MPIC_INFO(name) MPIC_##name
156
157#endif /* CONFIG_MPIC_WEIRD */
158
159static inline unsigned int mpic_processor_id(struct mpic *mpic)
160{
161 unsigned int cpu = 0;
162
163 if (!(mpic->flags & MPIC_SECONDARY))
164 cpu = hard_smp_processor_id();
165
166 return cpu;
167}
168
169/*
170 * Register accessor functions
171 */
172
173
174static inline u32 _mpic_read(enum mpic_reg_type type,
175 struct mpic_reg_bank *rb,
176 unsigned int reg)
177{
178 switch(type) {
179#ifdef CONFIG_PPC_DCR
180 case mpic_access_dcr:
181 return dcr_read(rb->dhost, reg);
182#endif
183 case mpic_access_mmio_be:
184 return in_be32(rb->base + (reg >> 2));
185 case mpic_access_mmio_le:
186 default:
187 return in_le32(rb->base + (reg >> 2));
188 }
189}
190
191static inline void _mpic_write(enum mpic_reg_type type,
192 struct mpic_reg_bank *rb,
193 unsigned int reg, u32 value)
194{
195 switch(type) {
196#ifdef CONFIG_PPC_DCR
197 case mpic_access_dcr:
198 dcr_write(rb->dhost, reg, value);
199 break;
200#endif
201 case mpic_access_mmio_be:
202 out_be32(rb->base + (reg >> 2), value);
203 break;
204 case mpic_access_mmio_le:
205 default:
206 out_le32(rb->base + (reg >> 2), value);
207 break;
208 }
209}
210
211static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
212{
213 enum mpic_reg_type type = mpic->reg_type;
214 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
215 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
216
217 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
218 type = mpic_access_mmio_be;
219 return _mpic_read(type, &mpic->gregs, offset);
220}
221
222static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
223{
224 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
225 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
226
227 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
228}
229
230static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned int tm)
231{
232 return (tm >> 2) * MPIC_TIMER_GROUP_STRIDE +
233 (tm & 3) * MPIC_INFO(TIMER_STRIDE);
234}
235
236static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
237{
238 unsigned int offset = mpic_tm_offset(mpic, tm) +
239 MPIC_INFO(TIMER_VECTOR_PRI);
240
241 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
242}
243
244static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
245{
246 unsigned int offset = mpic_tm_offset(mpic, tm) +
247 MPIC_INFO(TIMER_VECTOR_PRI);
248
249 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
250}
251
252static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
253{
254 unsigned int cpu = mpic_processor_id(mpic);
255
256 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
257}
258
259static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
260{
261 unsigned int cpu = mpic_processor_id(mpic);
262
263 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
264}
265
266static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
267{
268 unsigned int isu = src_no >> mpic->isu_shift;
269 unsigned int idx = src_no & mpic->isu_mask;
270 unsigned int val;
271
272 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
273 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
274#ifdef CONFIG_MPIC_BROKEN_REGREAD
275 if (reg == 0)
276 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
277 mpic->isu_reg0_shadow[src_no];
278#endif
279 return val;
280}
281
282static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
283 unsigned int reg, u32 value)
284{
285 unsigned int isu = src_no >> mpic->isu_shift;
286 unsigned int idx = src_no & mpic->isu_mask;
287
288 _mpic_write(mpic->reg_type, &mpic->isus[isu],
289 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
290
291#ifdef CONFIG_MPIC_BROKEN_REGREAD
292 if (reg == 0)
293 mpic->isu_reg0_shadow[src_no] =
294 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
295#endif
296}
297
298#define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
299#define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
300#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
301#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
302#define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
303#define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
304#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
305#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
306#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
307#define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
308
309
310/*
311 * Low level utility functions
312 */
313
314
315static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
316 struct mpic_reg_bank *rb, unsigned int offset,
317 unsigned int size)
318{
319 rb->base = ioremap(phys_addr + offset, size);
320 BUG_ON(rb->base == NULL);
321}
322
323#ifdef CONFIG_PPC_DCR
324static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
325 unsigned int offset, unsigned int size)
326{
327 phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
328 rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
329 BUG_ON(!DCR_MAP_OK(rb->dhost));
330}
331
332static inline void mpic_map(struct mpic *mpic,
333 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
334 unsigned int offset, unsigned int size)
335{
336 if (mpic->flags & MPIC_USES_DCR)
337 _mpic_map_dcr(mpic, rb, offset, size);
338 else
339 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
340}
341#else /* CONFIG_PPC_DCR */
342#define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
343#endif /* !CONFIG_PPC_DCR */
344
345
346
347/* Check if we have one of those nice broken MPICs with a flipped endian on
348 * reads from IPI registers
349 */
350static void __init mpic_test_broken_ipi(struct mpic *mpic)
351{
352 u32 r;
353
354 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
355 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
356
357 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
358 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
359 mpic->flags |= MPIC_BROKEN_IPI;
360 }
361}
362
363#ifdef CONFIG_MPIC_U3_HT_IRQS
364
365/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
366 * to force the edge setting on the MPIC and do the ack workaround.
367 */
368static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
369{
370 if (source >= 128 || !mpic->fixups)
371 return 0;
372 return mpic->fixups[source].base != NULL;
373}
374
375
376static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
377{
378 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
379
380 if (fixup->applebase) {
381 unsigned int soff = (fixup->index >> 3) & ~3;
382 unsigned int mask = 1U << (fixup->index & 0x1f);
383 writel(mask, fixup->applebase + soff);
384 } else {
385 raw_spin_lock(&mpic->fixup_lock);
386 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
387 writel(fixup->data, fixup->base + 4);
388 raw_spin_unlock(&mpic->fixup_lock);
389 }
390}
391
392static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
393 bool level)
394{
395 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
396 unsigned long flags;
397 u32 tmp;
398
399 if (fixup->base == NULL)
400 return;
401
402 DBG("startup_ht_interrupt(0x%x) index: %d\n",
403 source, fixup->index);
404 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
405 /* Enable and configure */
406 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
407 tmp = readl(fixup->base + 4);
408 tmp &= ~(0x23U);
409 if (level)
410 tmp |= 0x22;
411 writel(tmp, fixup->base + 4);
412 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
413
414#ifdef CONFIG_PM
415 /* use the lowest bit inverted to the actual HW,
416 * set if this fixup was enabled, clear otherwise */
417 mpic->save_data[source].fixup_data = tmp | 1;
418#endif
419}
420
421static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
422{
423 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
424 unsigned long flags;
425 u32 tmp;
426
427 if (fixup->base == NULL)
428 return;
429
430 DBG("shutdown_ht_interrupt(0x%x)\n", source);
431
432 /* Disable */
433 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
434 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
435 tmp = readl(fixup->base + 4);
436 tmp |= 1;
437 writel(tmp, fixup->base + 4);
438 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
439
440#ifdef CONFIG_PM
441 /* use the lowest bit inverted to the actual HW,
442 * set if this fixup was enabled, clear otherwise */
443 mpic->save_data[source].fixup_data = tmp & ~1;
444#endif
445}
446
447#ifdef CONFIG_PCI_MSI
448static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
449 unsigned int devfn)
450{
451 u8 __iomem *base;
452 u8 pos, flags;
453 u64 addr = 0;
454
455 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
456 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
457 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
458 if (id == PCI_CAP_ID_HT) {
459 id = readb(devbase + pos + 3);
460 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
461 break;
462 }
463 }
464
465 if (pos == 0)
466 return;
467
468 base = devbase + pos;
469
470 flags = readb(base + HT_MSI_FLAGS);
471 if (!(flags & HT_MSI_FLAGS_FIXED)) {
472 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
473 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
474 }
475
476 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
477 PCI_SLOT(devfn), PCI_FUNC(devfn),
478 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
479
480 if (!(flags & HT_MSI_FLAGS_ENABLE))
481 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
482}
483#else
484static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
485 unsigned int devfn)
486{
487 return;
488}
489#endif
490
491static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
492 unsigned int devfn, u32 vdid)
493{
494 int i, irq, n;
495 u8 __iomem *base;
496 u32 tmp;
497 u8 pos;
498
499 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
500 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
501 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
502 if (id == PCI_CAP_ID_HT) {
503 id = readb(devbase + pos + 3);
504 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
505 break;
506 }
507 }
508 if (pos == 0)
509 return;
510
511 base = devbase + pos;
512 writeb(0x01, base + 2);
513 n = (readl(base + 4) >> 16) & 0xff;
514
515 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
516 " has %d irqs\n",
517 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
518
519 for (i = 0; i <= n; i++) {
520 writeb(0x10 + 2 * i, base + 2);
521 tmp = readl(base + 4);
522 irq = (tmp >> 16) & 0xff;
523 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
524 /* mask it , will be unmasked later */
525 tmp |= 0x1;
526 writel(tmp, base + 4);
527 mpic->fixups[irq].index = i;
528 mpic->fixups[irq].base = base;
529 /* Apple HT PIC has a non-standard way of doing EOIs */
530 if ((vdid & 0xffff) == 0x106b)
531 mpic->fixups[irq].applebase = devbase + 0x60;
532 else
533 mpic->fixups[irq].applebase = NULL;
534 writeb(0x11 + 2 * i, base + 2);
535 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
536 }
537}
538
539
540static void __init mpic_scan_ht_pics(struct mpic *mpic)
541{
542 unsigned int devfn;
543 u8 __iomem *cfgspace;
544
545 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
546
547 /* Allocate fixups array */
548 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
549 BUG_ON(mpic->fixups == NULL);
550
551 /* Init spinlock */
552 raw_spin_lock_init(&mpic->fixup_lock);
553
554 /* Map U3 config space. We assume all IO-APICs are on the primary bus
555 * so we only need to map 64kB.
556 */
557 cfgspace = ioremap(0xf2000000, 0x10000);
558 BUG_ON(cfgspace == NULL);
559
560 /* Now we scan all slots. We do a very quick scan, we read the header
561 * type, vendor ID and device ID only, that's plenty enough
562 */
563 for (devfn = 0; devfn < 0x100; devfn++) {
564 u8 __iomem *devbase = cfgspace + (devfn << 8);
565 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
566 u32 l = readl(devbase + PCI_VENDOR_ID);
567 u16 s;
568
569 DBG("devfn %x, l: %x\n", devfn, l);
570
571 /* If no device, skip */
572 if (l == 0xffffffff || l == 0x00000000 ||
573 l == 0x0000ffff || l == 0xffff0000)
574 goto next;
575 /* Check if is supports capability lists */
576 s = readw(devbase + PCI_STATUS);
577 if (!(s & PCI_STATUS_CAP_LIST))
578 goto next;
579
580 mpic_scan_ht_pic(mpic, devbase, devfn, l);
581 mpic_scan_ht_msi(mpic, devbase, devfn);
582
583 next:
584 /* next device, if function 0 */
585 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
586 devfn += 7;
587 }
588}
589
590#else /* CONFIG_MPIC_U3_HT_IRQS */
591
592static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
593{
594 return 0;
595}
596
597static void __init mpic_scan_ht_pics(struct mpic *mpic)
598{
599}
600
601#endif /* CONFIG_MPIC_U3_HT_IRQS */
602
603/* Find an mpic associated with a given linux interrupt */
604static struct mpic *mpic_find(unsigned int irq)
605{
606 if (irq < NUM_ISA_INTERRUPTS)
607 return NULL;
608
609 return irq_get_chip_data(irq);
610}
611
612/* Determine if the linux irq is an IPI */
613static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
614{
615 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
616}
617
618/* Determine if the linux irq is a timer */
619static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
620{
621 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
622}
623
624/* Convert a cpu mask from logical to physical cpu numbers. */
625static inline u32 mpic_physmask(u32 cpumask)
626{
627 int i;
628 u32 mask = 0;
629
630 for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
631 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
632 return mask;
633}
634
635#ifdef CONFIG_SMP
636/* Get the mpic structure from the IPI number */
637static inline struct mpic * mpic_from_ipi(struct irq_data *d)
638{
639 return irq_data_get_irq_chip_data(d);
640}
641#endif
642
643/* Get the mpic structure from the irq number */
644static inline struct mpic * mpic_from_irq(unsigned int irq)
645{
646 return irq_get_chip_data(irq);
647}
648
649/* Get the mpic structure from the irq data */
650static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
651{
652 return irq_data_get_irq_chip_data(d);
653}
654
655/* Send an EOI */
656static inline void mpic_eoi(struct mpic *mpic)
657{
658 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
659 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
660}
661
662/*
663 * Linux descriptor level callbacks
664 */
665
666
667void mpic_unmask_irq(struct irq_data *d)
668{
669 unsigned int loops = 100000;
670 struct mpic *mpic = mpic_from_irq_data(d);
671 unsigned int src = irqd_to_hwirq(d);
672
673 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
674
675 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
676 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
677 ~MPIC_VECPRI_MASK);
678 /* make sure mask gets to controller before we return to user */
679 do {
680 if (!loops--) {
681 printk(KERN_ERR "%s: timeout on hwirq %u\n",
682 __func__, src);
683 break;
684 }
685 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
686}
687
688void mpic_mask_irq(struct irq_data *d)
689{
690 unsigned int loops = 100000;
691 struct mpic *mpic = mpic_from_irq_data(d);
692 unsigned int src = irqd_to_hwirq(d);
693
694 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
695
696 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
697 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
698 MPIC_VECPRI_MASK);
699
700 /* make sure mask gets to controller before we return to user */
701 do {
702 if (!loops--) {
703 printk(KERN_ERR "%s: timeout on hwirq %u\n",
704 __func__, src);
705 break;
706 }
707 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
708}
709
710void mpic_end_irq(struct irq_data *d)
711{
712 struct mpic *mpic = mpic_from_irq_data(d);
713
714#ifdef DEBUG_IRQ
715 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
716#endif
717 /* We always EOI on end_irq() even for edge interrupts since that
718 * should only lower the priority, the MPIC should have properly
719 * latched another edge interrupt coming in anyway
720 */
721
722 mpic_eoi(mpic);
723}
724
725#ifdef CONFIG_MPIC_U3_HT_IRQS
726
727static void mpic_unmask_ht_irq(struct irq_data *d)
728{
729 struct mpic *mpic = mpic_from_irq_data(d);
730 unsigned int src = irqd_to_hwirq(d);
731
732 mpic_unmask_irq(d);
733
734 if (irqd_is_level_type(d))
735 mpic_ht_end_irq(mpic, src);
736}
737
738static unsigned int mpic_startup_ht_irq(struct irq_data *d)
739{
740 struct mpic *mpic = mpic_from_irq_data(d);
741 unsigned int src = irqd_to_hwirq(d);
742
743 mpic_unmask_irq(d);
744 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
745
746 return 0;
747}
748
749static void mpic_shutdown_ht_irq(struct irq_data *d)
750{
751 struct mpic *mpic = mpic_from_irq_data(d);
752 unsigned int src = irqd_to_hwirq(d);
753
754 mpic_shutdown_ht_interrupt(mpic, src);
755 mpic_mask_irq(d);
756}
757
758static void mpic_end_ht_irq(struct irq_data *d)
759{
760 struct mpic *mpic = mpic_from_irq_data(d);
761 unsigned int src = irqd_to_hwirq(d);
762
763#ifdef DEBUG_IRQ
764 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
765#endif
766 /* We always EOI on end_irq() even for edge interrupts since that
767 * should only lower the priority, the MPIC should have properly
768 * latched another edge interrupt coming in anyway
769 */
770
771 if (irqd_is_level_type(d))
772 mpic_ht_end_irq(mpic, src);
773 mpic_eoi(mpic);
774}
775#endif /* !CONFIG_MPIC_U3_HT_IRQS */
776
777#ifdef CONFIG_SMP
778
779static void mpic_unmask_ipi(struct irq_data *d)
780{
781 struct mpic *mpic = mpic_from_ipi(d);
782 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
783
784 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
785 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
786}
787
788static void mpic_mask_ipi(struct irq_data *d)
789{
790 /* NEVER disable an IPI... that's just plain wrong! */
791}
792
793static void mpic_end_ipi(struct irq_data *d)
794{
795 struct mpic *mpic = mpic_from_ipi(d);
796
797 /*
798 * IPIs are marked IRQ_PER_CPU. This has the side effect of
799 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
800 * applying to them. We EOI them late to avoid re-entering.
801 */
802 mpic_eoi(mpic);
803}
804
805#endif /* CONFIG_SMP */
806
807static void mpic_unmask_tm(struct irq_data *d)
808{
809 struct mpic *mpic = mpic_from_irq_data(d);
810 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
811
812 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
813 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
814 mpic_tm_read(src);
815}
816
817static void mpic_mask_tm(struct irq_data *d)
818{
819 struct mpic *mpic = mpic_from_irq_data(d);
820 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
821
822 mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
823 mpic_tm_read(src);
824}
825
826int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
827 bool force)
828{
829 struct mpic *mpic = mpic_from_irq_data(d);
830 unsigned int src = irqd_to_hwirq(d);
831
832 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
833 int cpuid = irq_choose_cpu(cpumask);
834
835 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
836 } else {
837 u32 mask = cpumask_bits(cpumask)[0];
838
839 mask &= cpumask_bits(cpu_online_mask)[0];
840
841 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
842 mpic_physmask(mask));
843 }
844
845 return IRQ_SET_MASK_OK;
846}
847
848static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
849{
850 /* Now convert sense value */
851 switch(type & IRQ_TYPE_SENSE_MASK) {
852 case IRQ_TYPE_EDGE_RISING:
853 return MPIC_INFO(VECPRI_SENSE_EDGE) |
854 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
855 case IRQ_TYPE_EDGE_FALLING:
856 case IRQ_TYPE_EDGE_BOTH:
857 return MPIC_INFO(VECPRI_SENSE_EDGE) |
858 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
859 case IRQ_TYPE_LEVEL_HIGH:
860 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
861 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
862 case IRQ_TYPE_LEVEL_LOW:
863 default:
864 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
865 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
866 }
867}
868
869int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
870{
871 struct mpic *mpic = mpic_from_irq_data(d);
872 unsigned int src = irqd_to_hwirq(d);
873 unsigned int vecpri, vold, vnew;
874
875 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
876 mpic, d->irq, src, flow_type);
877
878 if (src >= mpic->num_sources)
879 return -EINVAL;
880
881 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
882
883 /* We don't support "none" type */
884 if (flow_type == IRQ_TYPE_NONE)
885 flow_type = IRQ_TYPE_DEFAULT;
886
887 /* Default: read HW settings */
888 if (flow_type == IRQ_TYPE_DEFAULT) {
889 int vold_ps;
890
891 vold_ps = vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
892 MPIC_INFO(VECPRI_SENSE_MASK));
893
894 if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
895 MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
896 flow_type = IRQ_TYPE_EDGE_RISING;
897 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
898 MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
899 flow_type = IRQ_TYPE_EDGE_FALLING;
900 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
901 MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
902 flow_type = IRQ_TYPE_LEVEL_HIGH;
903 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
904 MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
905 flow_type = IRQ_TYPE_LEVEL_LOW;
906 else
907 WARN_ONCE(1, "mpic: unknown IRQ type %d\n", vold);
908 }
909
910 /* Apply to irq desc */
911 irqd_set_trigger_type(d, flow_type);
912
913 /* Apply to HW */
914 if (mpic_is_ht_interrupt(mpic, src))
915 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
916 MPIC_VECPRI_SENSE_EDGE;
917 else
918 vecpri = mpic_type_to_vecpri(mpic, flow_type);
919
920 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
921 MPIC_INFO(VECPRI_SENSE_MASK));
922 vnew |= vecpri;
923 if (vold != vnew)
924 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
925
926 return IRQ_SET_MASK_OK_NOCOPY;
927}
928
929static int mpic_irq_set_wake(struct irq_data *d, unsigned int on)
930{
931 struct irq_desc *desc = container_of(d, struct irq_desc, irq_data);
932 struct mpic *mpic = mpic_from_irq_data(d);
933
934 if (!(mpic->flags & MPIC_FSL))
935 return -ENXIO;
936
937 if (on)
938 desc->action->flags |= IRQF_NO_SUSPEND;
939 else
940 desc->action->flags &= ~IRQF_NO_SUSPEND;
941
942 return 0;
943}
944
945void mpic_set_vector(unsigned int virq, unsigned int vector)
946{
947 struct mpic *mpic = mpic_from_irq(virq);
948 unsigned int src = virq_to_hw(virq);
949 unsigned int vecpri;
950
951 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
952 mpic, virq, src, vector);
953
954 if (src >= mpic->num_sources)
955 return;
956
957 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
958 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
959 vecpri |= vector;
960 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
961}
962
963void mpic_set_destination(unsigned int virq, unsigned int cpuid)
964{
965 struct mpic *mpic = mpic_from_irq(virq);
966 unsigned int src = virq_to_hw(virq);
967
968 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
969 mpic, virq, src, cpuid);
970
971 if (src >= mpic->num_sources)
972 return;
973
974 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
975}
976
977static struct irq_chip mpic_irq_chip = {
978 .irq_mask = mpic_mask_irq,
979 .irq_unmask = mpic_unmask_irq,
980 .irq_eoi = mpic_end_irq,
981 .irq_set_type = mpic_set_irq_type,
982 .irq_set_wake = mpic_irq_set_wake,
983};
984
985#ifdef CONFIG_SMP
986static struct irq_chip mpic_ipi_chip = {
987 .irq_mask = mpic_mask_ipi,
988 .irq_unmask = mpic_unmask_ipi,
989 .irq_eoi = mpic_end_ipi,
990};
991#endif /* CONFIG_SMP */
992
993static struct irq_chip mpic_tm_chip = {
994 .irq_mask = mpic_mask_tm,
995 .irq_unmask = mpic_unmask_tm,
996 .irq_eoi = mpic_end_irq,
997 .irq_set_wake = mpic_irq_set_wake,
998};
999
1000#ifdef CONFIG_MPIC_U3_HT_IRQS
1001static struct irq_chip mpic_irq_ht_chip = {
1002 .irq_startup = mpic_startup_ht_irq,
1003 .irq_shutdown = mpic_shutdown_ht_irq,
1004 .irq_mask = mpic_mask_irq,
1005 .irq_unmask = mpic_unmask_ht_irq,
1006 .irq_eoi = mpic_end_ht_irq,
1007 .irq_set_type = mpic_set_irq_type,
1008};
1009#endif /* CONFIG_MPIC_U3_HT_IRQS */
1010
1011
1012static int mpic_host_match(struct irq_domain *h, struct device_node *node)
1013{
1014 /* Exact match, unless mpic node is NULL */
1015 return h->of_node == NULL || h->of_node == node;
1016}
1017
1018static int mpic_host_map(struct irq_domain *h, unsigned int virq,
1019 irq_hw_number_t hw)
1020{
1021 struct mpic *mpic = h->host_data;
1022 struct irq_chip *chip;
1023
1024 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
1025
1026 if (hw == mpic->spurious_vec)
1027 return -EINVAL;
1028 if (mpic->protected && test_bit(hw, mpic->protected)) {
1029 pr_warning("mpic: Mapping of source 0x%x failed, "
1030 "source protected by firmware !\n",\
1031 (unsigned int)hw);
1032 return -EPERM;
1033 }
1034
1035#ifdef CONFIG_SMP
1036 else if (hw >= mpic->ipi_vecs[0]) {
1037 WARN_ON(mpic->flags & MPIC_SECONDARY);
1038
1039 DBG("mpic: mapping as IPI\n");
1040 irq_set_chip_data(virq, mpic);
1041 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
1042 handle_percpu_irq);
1043 return 0;
1044 }
1045#endif /* CONFIG_SMP */
1046
1047 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1048 WARN_ON(mpic->flags & MPIC_SECONDARY);
1049
1050 DBG("mpic: mapping as timer\n");
1051 irq_set_chip_data(virq, mpic);
1052 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1053 handle_fasteoi_irq);
1054 return 0;
1055 }
1056
1057 if (mpic_map_error_int(mpic, virq, hw))
1058 return 0;
1059
1060 if (hw >= mpic->num_sources) {
1061 pr_warning("mpic: Mapping of source 0x%x failed, "
1062 "source out of range !\n",\
1063 (unsigned int)hw);
1064 return -EINVAL;
1065 }
1066
1067 mpic_msi_reserve_hwirq(mpic, hw);
1068
1069 /* Default chip */
1070 chip = &mpic->hc_irq;
1071
1072#ifdef CONFIG_MPIC_U3_HT_IRQS
1073 /* Check for HT interrupts, override vecpri */
1074 if (mpic_is_ht_interrupt(mpic, hw))
1075 chip = &mpic->hc_ht_irq;
1076#endif /* CONFIG_MPIC_U3_HT_IRQS */
1077
1078 DBG("mpic: mapping to irq chip @%p\n", chip);
1079
1080 irq_set_chip_data(virq, mpic);
1081 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1082
1083 /* Set default irq type */
1084 irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
1085
1086 /* If the MPIC was reset, then all vectors have already been
1087 * initialized. Otherwise, a per source lazy initialization
1088 * is done here.
1089 */
1090 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1091 int cpu;
1092
1093 preempt_disable();
1094 cpu = mpic_processor_id(mpic);
1095 preempt_enable();
1096
1097 mpic_set_vector(virq, hw);
1098 mpic_set_destination(virq, cpu);
1099 mpic_irq_set_priority(virq, 8);
1100 }
1101
1102 return 0;
1103}
1104
1105static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
1106 const u32 *intspec, unsigned int intsize,
1107 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1108
1109{
1110 struct mpic *mpic = h->host_data;
1111 static unsigned char map_mpic_senses[4] = {
1112 IRQ_TYPE_EDGE_RISING,
1113 IRQ_TYPE_LEVEL_LOW,
1114 IRQ_TYPE_LEVEL_HIGH,
1115 IRQ_TYPE_EDGE_FALLING,
1116 };
1117
1118 *out_hwirq = intspec[0];
1119 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1120 /*
1121 * Freescale MPIC with extended intspec:
1122 * First two cells are as usual. Third specifies
1123 * an "interrupt type". Fourth is type-specific data.
1124 *
1125 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1126 */
1127 switch (intspec[2]) {
1128 case 0:
1129 break;
1130 case 1:
1131 if (!(mpic->flags & MPIC_FSL_HAS_EIMR))
1132 break;
1133
1134 if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs))
1135 return -EINVAL;
1136
1137 *out_hwirq = mpic->err_int_vecs[intspec[3]];
1138
1139 break;
1140 case 2:
1141 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1142 return -EINVAL;
1143
1144 *out_hwirq = mpic->ipi_vecs[intspec[0]];
1145 break;
1146 case 3:
1147 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1148 return -EINVAL;
1149
1150 *out_hwirq = mpic->timer_vecs[intspec[0]];
1151 break;
1152 default:
1153 pr_debug("%s: unknown irq type %u\n",
1154 __func__, intspec[2]);
1155 return -EINVAL;
1156 }
1157
1158 *out_flags = map_mpic_senses[intspec[1] & 3];
1159 } else if (intsize > 1) {
1160 u32 mask = 0x3;
1161
1162 /* Apple invented a new race of encoding on machines with
1163 * an HT APIC. They encode, among others, the index within
1164 * the HT APIC. We don't care about it here since thankfully,
1165 * it appears that they have the APIC already properly
1166 * configured, and thus our current fixup code that reads the
1167 * APIC config works fine. However, we still need to mask out
1168 * bits in the specifier to make sure we only get bit 0 which
1169 * is the level/edge bit (the only sense bit exposed by Apple),
1170 * as their bit 1 means something else.
1171 */
1172 if (machine_is(powermac))
1173 mask = 0x1;
1174 *out_flags = map_mpic_senses[intspec[1] & mask];
1175 } else
1176 *out_flags = IRQ_TYPE_NONE;
1177
1178 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1179 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1180
1181 return 0;
1182}
1183
1184/* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
1185static void mpic_cascade(unsigned int irq, struct irq_desc *desc)
1186{
1187 struct irq_chip *chip = irq_desc_get_chip(desc);
1188 struct mpic *mpic = irq_desc_get_handler_data(desc);
1189 unsigned int virq;
1190
1191 BUG_ON(!(mpic->flags & MPIC_SECONDARY));
1192
1193 virq = mpic_get_one_irq(mpic);
1194 if (virq)
1195 generic_handle_irq(virq);
1196
1197 chip->irq_eoi(&desc->irq_data);
1198}
1199
1200static struct irq_domain_ops mpic_host_ops = {
1201 .match = mpic_host_match,
1202 .map = mpic_host_map,
1203 .xlate = mpic_host_xlate,
1204};
1205
1206static u32 fsl_mpic_get_version(struct mpic *mpic)
1207{
1208 u32 brr1;
1209
1210 if (!(mpic->flags & MPIC_FSL))
1211 return 0;
1212
1213 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
1214 MPIC_FSL_BRR1);
1215
1216 return brr1 & MPIC_FSL_BRR1_VER;
1217}
1218
1219/*
1220 * Exported functions
1221 */
1222
1223u32 fsl_mpic_primary_get_version(void)
1224{
1225 struct mpic *mpic = mpic_primary;
1226
1227 if (mpic)
1228 return fsl_mpic_get_version(mpic);
1229
1230 return 0;
1231}
1232
1233struct mpic * __init mpic_alloc(struct device_node *node,
1234 phys_addr_t phys_addr,
1235 unsigned int flags,
1236 unsigned int isu_size,
1237 unsigned int irq_count,
1238 const char *name)
1239{
1240 int i, psize, intvec_top;
1241 struct mpic *mpic;
1242 u32 greg_feature;
1243 const char *vers;
1244 const u32 *psrc;
1245 u32 last_irq;
1246 u32 fsl_version = 0;
1247
1248 /* Default MPIC search parameters */
1249 static const struct of_device_id __initconst mpic_device_id[] = {
1250 { .type = "open-pic", },
1251 { .compatible = "open-pic", },
1252 {},
1253 };
1254
1255 /*
1256 * If we were not passed a device-tree node, then perform the default
1257 * search for standardized a standardized OpenPIC.
1258 */
1259 if (node) {
1260 node = of_node_get(node);
1261 } else {
1262 node = of_find_matching_node(NULL, mpic_device_id);
1263 if (!node)
1264 return NULL;
1265 }
1266
1267 /* Pick the physical address from the device tree if unspecified */
1268 if (!phys_addr) {
1269 /* Check if it is DCR-based */
1270 if (of_get_property(node, "dcr-reg", NULL)) {
1271 flags |= MPIC_USES_DCR;
1272 } else {
1273 struct resource r;
1274 if (of_address_to_resource(node, 0, &r))
1275 goto err_of_node_put;
1276 phys_addr = r.start;
1277 }
1278 }
1279
1280 /* Read extra device-tree properties into the flags variable */
1281 if (of_get_property(node, "big-endian", NULL))
1282 flags |= MPIC_BIG_ENDIAN;
1283 if (of_get_property(node, "pic-no-reset", NULL))
1284 flags |= MPIC_NO_RESET;
1285 if (of_get_property(node, "single-cpu-affinity", NULL))
1286 flags |= MPIC_SINGLE_DEST_CPU;
1287 if (of_device_is_compatible(node, "fsl,mpic"))
1288 flags |= MPIC_FSL | MPIC_LARGE_VECTORS;
1289
1290 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1291 if (mpic == NULL)
1292 goto err_of_node_put;
1293
1294 mpic->name = name;
1295 mpic->node = node;
1296 mpic->paddr = phys_addr;
1297 mpic->flags = flags;
1298
1299 mpic->hc_irq = mpic_irq_chip;
1300 mpic->hc_irq.name = name;
1301 if (!(mpic->flags & MPIC_SECONDARY))
1302 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1303#ifdef CONFIG_MPIC_U3_HT_IRQS
1304 mpic->hc_ht_irq = mpic_irq_ht_chip;
1305 mpic->hc_ht_irq.name = name;
1306 if (!(mpic->flags & MPIC_SECONDARY))
1307 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1308#endif /* CONFIG_MPIC_U3_HT_IRQS */
1309
1310#ifdef CONFIG_SMP
1311 mpic->hc_ipi = mpic_ipi_chip;
1312 mpic->hc_ipi.name = name;
1313#endif /* CONFIG_SMP */
1314
1315 mpic->hc_tm = mpic_tm_chip;
1316 mpic->hc_tm.name = name;
1317
1318 mpic->num_sources = 0; /* so far */
1319
1320 if (mpic->flags & MPIC_LARGE_VECTORS)
1321 intvec_top = 2047;
1322 else
1323 intvec_top = 255;
1324
1325 mpic->timer_vecs[0] = intvec_top - 12;
1326 mpic->timer_vecs[1] = intvec_top - 11;
1327 mpic->timer_vecs[2] = intvec_top - 10;
1328 mpic->timer_vecs[3] = intvec_top - 9;
1329 mpic->timer_vecs[4] = intvec_top - 8;
1330 mpic->timer_vecs[5] = intvec_top - 7;
1331 mpic->timer_vecs[6] = intvec_top - 6;
1332 mpic->timer_vecs[7] = intvec_top - 5;
1333 mpic->ipi_vecs[0] = intvec_top - 4;
1334 mpic->ipi_vecs[1] = intvec_top - 3;
1335 mpic->ipi_vecs[2] = intvec_top - 2;
1336 mpic->ipi_vecs[3] = intvec_top - 1;
1337 mpic->spurious_vec = intvec_top;
1338
1339 /* Look for protected sources */
1340 psrc = of_get_property(mpic->node, "protected-sources", &psize);
1341 if (psrc) {
1342 /* Allocate a bitmap with one bit per interrupt */
1343 unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1);
1344 mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL);
1345 BUG_ON(mpic->protected == NULL);
1346 for (i = 0; i < psize/sizeof(u32); i++) {
1347 if (psrc[i] > intvec_top)
1348 continue;
1349 __set_bit(psrc[i], mpic->protected);
1350 }
1351 }
1352
1353#ifdef CONFIG_MPIC_WEIRD
1354 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
1355#endif
1356
1357 /* default register type */
1358 if (mpic->flags & MPIC_BIG_ENDIAN)
1359 mpic->reg_type = mpic_access_mmio_be;
1360 else
1361 mpic->reg_type = mpic_access_mmio_le;
1362
1363 /*
1364 * An MPIC with a "dcr-reg" property must be accessed that way, but
1365 * only if the kernel includes DCR support.
1366 */
1367#ifdef CONFIG_PPC_DCR
1368 if (mpic->flags & MPIC_USES_DCR)
1369 mpic->reg_type = mpic_access_dcr;
1370#else
1371 BUG_ON(mpic->flags & MPIC_USES_DCR);
1372#endif
1373
1374 /* Map the global registers */
1375 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1376 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1377
1378 if (mpic->flags & MPIC_FSL) {
1379 int ret;
1380
1381 /*
1382 * Yes, Freescale really did put global registers in the
1383 * magic per-cpu area -- and they don't even show up in the
1384 * non-magic per-cpu copies that this driver normally uses.
1385 */
1386 mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
1387 MPIC_CPU_THISBASE, 0x1000);
1388
1389 fsl_version = fsl_mpic_get_version(mpic);
1390
1391 /* Error interrupt mask register (EIMR) is required for
1392 * handling individual device error interrupts. EIMR
1393 * was added in MPIC version 4.1.
1394 *
1395 * Over here we reserve vector number space for error
1396 * interrupt vectors. This space is stolen from the
1397 * global vector number space, as in case of ipis
1398 * and timer interrupts.
1399 *
1400 * Available vector space = intvec_top - 12, where 12
1401 * is the number of vectors which have been consumed by
1402 * ipis and timer interrupts.
1403 */
1404 if (fsl_version >= 0x401) {
1405 ret = mpic_setup_error_int(mpic, intvec_top - 12);
1406 if (ret)
1407 return NULL;
1408 }
1409
1410 }
1411
1412 /*
1413 * EPR is only available starting with v4.0. To support
1414 * platforms that don't know the MPIC version at compile-time,
1415 * such as qemu-e500, turn off coreint if this MPIC doesn't
1416 * support it. Note that we never enable it if it wasn't
1417 * requested in the first place.
1418 *
1419 * This is done outside the MPIC_FSL check, so that we
1420 * also disable coreint if the MPIC node doesn't have
1421 * an "fsl,mpic" compatible at all. This will be the case
1422 * with device trees generated by older versions of QEMU.
1423 * fsl_version will be zero if MPIC_FSL is not set.
1424 */
1425 if (fsl_version < 0x400 && (flags & MPIC_ENABLE_COREINT)) {
1426 WARN_ON(ppc_md.get_irq != mpic_get_coreint_irq);
1427 ppc_md.get_irq = mpic_get_irq;
1428 }
1429
1430 /* Reset */
1431
1432 /* When using a device-node, reset requests are only honored if the MPIC
1433 * is allowed to reset.
1434 */
1435 if (!(mpic->flags & MPIC_NO_RESET)) {
1436 printk(KERN_DEBUG "mpic: Resetting\n");
1437 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1438 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1439 | MPIC_GREG_GCONF_RESET);
1440 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1441 & MPIC_GREG_GCONF_RESET)
1442 mb();
1443 }
1444
1445 /* CoreInt */
1446 if (mpic->flags & MPIC_ENABLE_COREINT)
1447 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1448 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1449 | MPIC_GREG_GCONF_COREINT);
1450
1451 if (mpic->flags & MPIC_ENABLE_MCK)
1452 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1453 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1454 | MPIC_GREG_GCONF_MCK);
1455
1456 /*
1457 * The MPIC driver will crash if there are more cores than we
1458 * can initialize, so we may as well catch that problem here.
1459 */
1460 BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS);
1461
1462 /* Map the per-CPU registers */
1463 for_each_possible_cpu(i) {
1464 unsigned int cpu = get_hard_smp_processor_id(i);
1465
1466 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
1467 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
1468 0x1000);
1469 }
1470
1471 /*
1472 * Read feature register. For non-ISU MPICs, num sources as well. On
1473 * ISU MPICs, sources are counted as ISUs are added
1474 */
1475 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1476
1477 /*
1478 * By default, the last source number comes from the MPIC, but the
1479 * device-tree and board support code can override it on buggy hw.
1480 * If we get passed an isu_size (multi-isu MPIC) then we use that
1481 * as a default instead of the value read from the HW.
1482 */
1483 last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1484 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT;
1485 if (isu_size)
1486 last_irq = isu_size * MPIC_MAX_ISU - 1;
1487 of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
1488 if (irq_count)
1489 last_irq = irq_count - 1;
1490
1491 /* Initialize main ISU if none provided */
1492 if (!isu_size) {
1493 isu_size = last_irq + 1;
1494 mpic->num_sources = isu_size;
1495 mpic_map(mpic, mpic->paddr, &mpic->isus[0],
1496 MPIC_INFO(IRQ_BASE),
1497 MPIC_INFO(IRQ_STRIDE) * isu_size);
1498 }
1499
1500 mpic->isu_size = isu_size;
1501 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1502 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1503
1504 mpic->irqhost = irq_domain_add_linear(mpic->node,
1505 intvec_top,
1506 &mpic_host_ops, mpic);
1507
1508 /*
1509 * FIXME: The code leaks the MPIC object and mappings here; this
1510 * is very unlikely to fail but it ought to be fixed anyways.
1511 */
1512 if (mpic->irqhost == NULL)
1513 return NULL;
1514
1515 /* Display version */
1516 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1517 case 1:
1518 vers = "1.0";
1519 break;
1520 case 2:
1521 vers = "1.2";
1522 break;
1523 case 3:
1524 vers = "1.3";
1525 break;
1526 default:
1527 vers = "<unknown>";
1528 break;
1529 }
1530 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1531 " max %d CPUs\n",
1532 name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
1533 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1534 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1535
1536 mpic->next = mpics;
1537 mpics = mpic;
1538
1539 if (!(mpic->flags & MPIC_SECONDARY)) {
1540 mpic_primary = mpic;
1541 irq_set_default_host(mpic->irqhost);
1542 }
1543
1544 return mpic;
1545
1546err_of_node_put:
1547 of_node_put(node);
1548 return NULL;
1549}
1550
1551void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1552 phys_addr_t paddr)
1553{
1554 unsigned int isu_first = isu_num * mpic->isu_size;
1555
1556 BUG_ON(isu_num >= MPIC_MAX_ISU);
1557
1558 mpic_map(mpic,
1559 paddr, &mpic->isus[isu_num], 0,
1560 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1561
1562 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1563 mpic->num_sources = isu_first + mpic->isu_size;
1564}
1565
1566void __init mpic_init(struct mpic *mpic)
1567{
1568 int i, cpu;
1569 int num_timers = 4;
1570
1571 BUG_ON(mpic->num_sources == 0);
1572
1573 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1574
1575 /* Set current processor priority to max */
1576 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1577
1578 if (mpic->flags & MPIC_FSL) {
1579 u32 version = fsl_mpic_get_version(mpic);
1580
1581 /*
1582 * Timer group B is present at the latest in MPIC 3.1 (e.g.
1583 * mpc8536). It is not present in MPIC 2.0 (e.g. mpc8544).
1584 * I don't know about the status of intermediate versions (or
1585 * whether they even exist).
1586 */
1587 if (version >= 0x0301)
1588 num_timers = 8;
1589 }
1590
1591 /* FSL mpic error interrupt intialization */
1592 if (mpic->flags & MPIC_FSL_HAS_EIMR)
1593 mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
1594
1595 /* Initialize timers to our reserved vectors and mask them for now */
1596 for (i = 0; i < num_timers; i++) {
1597 unsigned int offset = mpic_tm_offset(mpic, i);
1598
1599 mpic_write(mpic->tmregs,
1600 offset + MPIC_INFO(TIMER_DESTINATION),
1601 1 << hard_smp_processor_id());
1602 mpic_write(mpic->tmregs,
1603 offset + MPIC_INFO(TIMER_VECTOR_PRI),
1604 MPIC_VECPRI_MASK |
1605 (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1606 (mpic->timer_vecs[0] + i));
1607 }
1608
1609 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1610 mpic_test_broken_ipi(mpic);
1611 for (i = 0; i < 4; i++) {
1612 mpic_ipi_write(i,
1613 MPIC_VECPRI_MASK |
1614 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1615 (mpic->ipi_vecs[0] + i));
1616 }
1617
1618 /* Do the HT PIC fixups on U3 broken mpic */
1619 DBG("MPIC flags: %x\n", mpic->flags);
1620 if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
1621 mpic_scan_ht_pics(mpic);
1622 mpic_u3msi_init(mpic);
1623 }
1624
1625 mpic_pasemi_msi_init(mpic);
1626
1627 cpu = mpic_processor_id(mpic);
1628
1629 if (!(mpic->flags & MPIC_NO_RESET)) {
1630 for (i = 0; i < mpic->num_sources; i++) {
1631 /* start with vector = source number, and masked */
1632 u32 vecpri = MPIC_VECPRI_MASK | i |
1633 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1634
1635 /* check if protected */
1636 if (mpic->protected && test_bit(i, mpic->protected))
1637 continue;
1638 /* init hw */
1639 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1640 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1641 }
1642 }
1643
1644 /* Init spurious vector */
1645 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1646
1647 /* Disable 8259 passthrough, if supported */
1648 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1649 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1650 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1651 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1652
1653 if (mpic->flags & MPIC_NO_BIAS)
1654 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1655 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1656 | MPIC_GREG_GCONF_NO_BIAS);
1657
1658 /* Set current processor priority to 0 */
1659 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1660
1661#ifdef CONFIG_PM
1662 /* allocate memory to save mpic state */
1663 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1664 GFP_KERNEL);
1665 BUG_ON(mpic->save_data == NULL);
1666#endif
1667
1668 /* Check if this MPIC is chained from a parent interrupt controller */
1669 if (mpic->flags & MPIC_SECONDARY) {
1670 int virq = irq_of_parse_and_map(mpic->node, 0);
1671 if (virq != NO_IRQ) {
1672 printk(KERN_INFO "%s: hooking up to IRQ %d\n",
1673 mpic->node->full_name, virq);
1674 irq_set_handler_data(virq, mpic);
1675 irq_set_chained_handler(virq, &mpic_cascade);
1676 }
1677 }
1678}
1679
1680void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1681{
1682 u32 v;
1683
1684 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1685 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1686 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1687 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1688}
1689
1690void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1691{
1692 unsigned long flags;
1693 u32 v;
1694
1695 raw_spin_lock_irqsave(&mpic_lock, flags);
1696 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1697 if (enable)
1698 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1699 else
1700 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1701 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1702 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1703}
1704
1705void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1706{
1707 struct mpic *mpic = mpic_find(irq);
1708 unsigned int src = virq_to_hw(irq);
1709 unsigned long flags;
1710 u32 reg;
1711
1712 if (!mpic)
1713 return;
1714
1715 raw_spin_lock_irqsave(&mpic_lock, flags);
1716 if (mpic_is_ipi(mpic, src)) {
1717 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1718 ~MPIC_VECPRI_PRIORITY_MASK;
1719 mpic_ipi_write(src - mpic->ipi_vecs[0],
1720 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1721 } else if (mpic_is_tm(mpic, src)) {
1722 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1723 ~MPIC_VECPRI_PRIORITY_MASK;
1724 mpic_tm_write(src - mpic->timer_vecs[0],
1725 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1726 } else {
1727 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1728 & ~MPIC_VECPRI_PRIORITY_MASK;
1729 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1730 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1731 }
1732 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1733}
1734
1735void mpic_setup_this_cpu(void)
1736{
1737#ifdef CONFIG_SMP
1738 struct mpic *mpic = mpic_primary;
1739 unsigned long flags;
1740 u32 msk = 1 << hard_smp_processor_id();
1741 unsigned int i;
1742
1743 BUG_ON(mpic == NULL);
1744
1745 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1746
1747 raw_spin_lock_irqsave(&mpic_lock, flags);
1748
1749 /* let the mpic know we want intrs. default affinity is 0xffffffff
1750 * until changed via /proc. That's how it's done on x86. If we want
1751 * it differently, then we should make sure we also change the default
1752 * values of irq_desc[].affinity in irq.c.
1753 */
1754 if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) {
1755 for (i = 0; i < mpic->num_sources ; i++)
1756 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1757 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1758 }
1759
1760 /* Set current processor priority to 0 */
1761 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1762
1763 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1764#endif /* CONFIG_SMP */
1765}
1766
1767int mpic_cpu_get_priority(void)
1768{
1769 struct mpic *mpic = mpic_primary;
1770
1771 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1772}
1773
1774void mpic_cpu_set_priority(int prio)
1775{
1776 struct mpic *mpic = mpic_primary;
1777
1778 prio &= MPIC_CPU_TASKPRI_MASK;
1779 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1780}
1781
1782void mpic_teardown_this_cpu(int secondary)
1783{
1784 struct mpic *mpic = mpic_primary;
1785 unsigned long flags;
1786 u32 msk = 1 << hard_smp_processor_id();
1787 unsigned int i;
1788
1789 BUG_ON(mpic == NULL);
1790
1791 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1792 raw_spin_lock_irqsave(&mpic_lock, flags);
1793
1794 /* let the mpic know we don't want intrs. */
1795 for (i = 0; i < mpic->num_sources ; i++)
1796 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1797 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1798
1799 /* Set current processor priority to max */
1800 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1801 /* We need to EOI the IPI since not all platforms reset the MPIC
1802 * on boot and new interrupts wouldn't get delivered otherwise.
1803 */
1804 mpic_eoi(mpic);
1805
1806 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1807}
1808
1809
1810static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1811{
1812 u32 src;
1813
1814 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1815#ifdef DEBUG_LOW
1816 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1817#endif
1818 if (unlikely(src == mpic->spurious_vec)) {
1819 if (mpic->flags & MPIC_SPV_EOI)
1820 mpic_eoi(mpic);
1821 return NO_IRQ;
1822 }
1823 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1824 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1825 mpic->name, (int)src);
1826 mpic_eoi(mpic);
1827 return NO_IRQ;
1828 }
1829
1830 return irq_linear_revmap(mpic->irqhost, src);
1831}
1832
1833unsigned int mpic_get_one_irq(struct mpic *mpic)
1834{
1835 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1836}
1837
1838unsigned int mpic_get_irq(void)
1839{
1840 struct mpic *mpic = mpic_primary;
1841
1842 BUG_ON(mpic == NULL);
1843
1844 return mpic_get_one_irq(mpic);
1845}
1846
1847unsigned int mpic_get_coreint_irq(void)
1848{
1849#ifdef CONFIG_BOOKE
1850 struct mpic *mpic = mpic_primary;
1851 u32 src;
1852
1853 BUG_ON(mpic == NULL);
1854
1855 src = mfspr(SPRN_EPR);
1856
1857 if (unlikely(src == mpic->spurious_vec)) {
1858 if (mpic->flags & MPIC_SPV_EOI)
1859 mpic_eoi(mpic);
1860 return NO_IRQ;
1861 }
1862 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1863 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1864 mpic->name, (int)src);
1865 return NO_IRQ;
1866 }
1867
1868 return irq_linear_revmap(mpic->irqhost, src);
1869#else
1870 return NO_IRQ;
1871#endif
1872}
1873
1874unsigned int mpic_get_mcirq(void)
1875{
1876 struct mpic *mpic = mpic_primary;
1877
1878 BUG_ON(mpic == NULL);
1879
1880 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1881}
1882
1883#ifdef CONFIG_SMP
1884void mpic_request_ipis(void)
1885{
1886 struct mpic *mpic = mpic_primary;
1887 int i;
1888 BUG_ON(mpic == NULL);
1889
1890 printk(KERN_INFO "mpic: requesting IPIs...\n");
1891
1892 for (i = 0; i < 4; i++) {
1893 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1894 mpic->ipi_vecs[0] + i);
1895 if (vipi == NO_IRQ) {
1896 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1897 continue;
1898 }
1899 smp_request_message_ipi(vipi, i);
1900 }
1901}
1902
1903void smp_mpic_message_pass(int cpu, int msg)
1904{
1905 struct mpic *mpic = mpic_primary;
1906 u32 physmask;
1907
1908 BUG_ON(mpic == NULL);
1909
1910 /* make sure we're sending something that translates to an IPI */
1911 if ((unsigned int)msg > 3) {
1912 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1913 smp_processor_id(), msg);
1914 return;
1915 }
1916
1917#ifdef DEBUG_IPI
1918 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1919#endif
1920
1921 physmask = 1 << get_hard_smp_processor_id(cpu);
1922
1923 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1924 msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1925}
1926
1927int __init smp_mpic_probe(void)
1928{
1929 int nr_cpus;
1930
1931 DBG("smp_mpic_probe()...\n");
1932
1933 nr_cpus = cpumask_weight(cpu_possible_mask);
1934
1935 DBG("nr_cpus: %d\n", nr_cpus);
1936
1937 if (nr_cpus > 1)
1938 mpic_request_ipis();
1939
1940 return nr_cpus;
1941}
1942
1943void smp_mpic_setup_cpu(int cpu)
1944{
1945 mpic_setup_this_cpu();
1946}
1947
1948void mpic_reset_core(int cpu)
1949{
1950 struct mpic *mpic = mpic_primary;
1951 u32 pir;
1952 int cpuid = get_hard_smp_processor_id(cpu);
1953 int i;
1954
1955 /* Set target bit for core reset */
1956 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1957 pir |= (1 << cpuid);
1958 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1959 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1960
1961 /* Restore target bit after reset complete */
1962 pir &= ~(1 << cpuid);
1963 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1964 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1965
1966 /* Perform 15 EOI on each reset core to clear pending interrupts.
1967 * This is required for FSL CoreNet based devices */
1968 if (mpic->flags & MPIC_FSL) {
1969 for (i = 0; i < 15; i++) {
1970 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1971 MPIC_CPU_EOI, 0);
1972 }
1973 }
1974}
1975#endif /* CONFIG_SMP */
1976
1977#ifdef CONFIG_PM
1978static void mpic_suspend_one(struct mpic *mpic)
1979{
1980 int i;
1981
1982 for (i = 0; i < mpic->num_sources; i++) {
1983 mpic->save_data[i].vecprio =
1984 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1985 mpic->save_data[i].dest =
1986 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1987 }
1988}
1989
1990static int mpic_suspend(void)
1991{
1992 struct mpic *mpic = mpics;
1993
1994 while (mpic) {
1995 mpic_suspend_one(mpic);
1996 mpic = mpic->next;
1997 }
1998
1999 return 0;
2000}
2001
2002static void mpic_resume_one(struct mpic *mpic)
2003{
2004 int i;
2005
2006 for (i = 0; i < mpic->num_sources; i++) {
2007 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
2008 mpic->save_data[i].vecprio);
2009 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
2010 mpic->save_data[i].dest);
2011
2012#ifdef CONFIG_MPIC_U3_HT_IRQS
2013 if (mpic->fixups) {
2014 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
2015
2016 if (fixup->base) {
2017 /* we use the lowest bit in an inverted meaning */
2018 if ((mpic->save_data[i].fixup_data & 1) == 0)
2019 continue;
2020
2021 /* Enable and configure */
2022 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
2023
2024 writel(mpic->save_data[i].fixup_data & ~1,
2025 fixup->base + 4);
2026 }
2027 }
2028#endif
2029 } /* end for loop */
2030}
2031
2032static void mpic_resume(void)
2033{
2034 struct mpic *mpic = mpics;
2035
2036 while (mpic) {
2037 mpic_resume_one(mpic);
2038 mpic = mpic->next;
2039 }
2040}
2041
2042static struct syscore_ops mpic_syscore_ops = {
2043 .resume = mpic_resume,
2044 .suspend = mpic_suspend,
2045};
2046
2047static int mpic_init_sys(void)
2048{
2049 register_syscore_ops(&mpic_syscore_ops);
2050 subsys_system_register(&mpic_subsys, NULL);
2051
2052 return 0;
2053}
2054
2055device_initcall(mpic_init_sys);
2056#endif
1/*
2 * arch/powerpc/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation being IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 * Copyright 2010-2012 Freescale Semiconductor, Inc.
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive
13 * for more details.
14 */
15
16#undef DEBUG
17#undef DEBUG_IPI
18#undef DEBUG_IRQ
19#undef DEBUG_LOW
20
21#include <linux/types.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/irq.h>
25#include <linux/smp.h>
26#include <linux/interrupt.h>
27#include <linux/spinlock.h>
28#include <linux/pci.h>
29#include <linux/slab.h>
30#include <linux/syscore_ops.h>
31#include <linux/ratelimit.h>
32
33#include <asm/ptrace.h>
34#include <asm/signal.h>
35#include <asm/io.h>
36#include <asm/pgtable.h>
37#include <asm/irq.h>
38#include <asm/machdep.h>
39#include <asm/mpic.h>
40#include <asm/smp.h>
41
42#include "mpic.h"
43
44#ifdef DEBUG
45#define DBG(fmt...) printk(fmt)
46#else
47#define DBG(fmt...)
48#endif
49
50struct bus_type mpic_subsys = {
51 .name = "mpic",
52 .dev_name = "mpic",
53};
54EXPORT_SYMBOL_GPL(mpic_subsys);
55
56static struct mpic *mpics;
57static struct mpic *mpic_primary;
58static DEFINE_RAW_SPINLOCK(mpic_lock);
59
60#ifdef CONFIG_PPC32 /* XXX for now */
61#ifdef CONFIG_IRQ_ALL_CPUS
62#define distribute_irqs (1)
63#else
64#define distribute_irqs (0)
65#endif
66#endif
67
68#ifdef CONFIG_MPIC_WEIRD
69static u32 mpic_infos[][MPIC_IDX_END] = {
70 [0] = { /* Original OpenPIC compatible MPIC */
71 MPIC_GREG_BASE,
72 MPIC_GREG_FEATURE_0,
73 MPIC_GREG_GLOBAL_CONF_0,
74 MPIC_GREG_VENDOR_ID,
75 MPIC_GREG_IPI_VECTOR_PRI_0,
76 MPIC_GREG_IPI_STRIDE,
77 MPIC_GREG_SPURIOUS,
78 MPIC_GREG_TIMER_FREQ,
79
80 MPIC_TIMER_BASE,
81 MPIC_TIMER_STRIDE,
82 MPIC_TIMER_CURRENT_CNT,
83 MPIC_TIMER_BASE_CNT,
84 MPIC_TIMER_VECTOR_PRI,
85 MPIC_TIMER_DESTINATION,
86
87 MPIC_CPU_BASE,
88 MPIC_CPU_STRIDE,
89 MPIC_CPU_IPI_DISPATCH_0,
90 MPIC_CPU_IPI_DISPATCH_STRIDE,
91 MPIC_CPU_CURRENT_TASK_PRI,
92 MPIC_CPU_WHOAMI,
93 MPIC_CPU_INTACK,
94 MPIC_CPU_EOI,
95 MPIC_CPU_MCACK,
96
97 MPIC_IRQ_BASE,
98 MPIC_IRQ_STRIDE,
99 MPIC_IRQ_VECTOR_PRI,
100 MPIC_VECPRI_VECTOR_MASK,
101 MPIC_VECPRI_POLARITY_POSITIVE,
102 MPIC_VECPRI_POLARITY_NEGATIVE,
103 MPIC_VECPRI_SENSE_LEVEL,
104 MPIC_VECPRI_SENSE_EDGE,
105 MPIC_VECPRI_POLARITY_MASK,
106 MPIC_VECPRI_SENSE_MASK,
107 MPIC_IRQ_DESTINATION
108 },
109 [1] = { /* Tsi108/109 PIC */
110 TSI108_GREG_BASE,
111 TSI108_GREG_FEATURE_0,
112 TSI108_GREG_GLOBAL_CONF_0,
113 TSI108_GREG_VENDOR_ID,
114 TSI108_GREG_IPI_VECTOR_PRI_0,
115 TSI108_GREG_IPI_STRIDE,
116 TSI108_GREG_SPURIOUS,
117 TSI108_GREG_TIMER_FREQ,
118
119 TSI108_TIMER_BASE,
120 TSI108_TIMER_STRIDE,
121 TSI108_TIMER_CURRENT_CNT,
122 TSI108_TIMER_BASE_CNT,
123 TSI108_TIMER_VECTOR_PRI,
124 TSI108_TIMER_DESTINATION,
125
126 TSI108_CPU_BASE,
127 TSI108_CPU_STRIDE,
128 TSI108_CPU_IPI_DISPATCH_0,
129 TSI108_CPU_IPI_DISPATCH_STRIDE,
130 TSI108_CPU_CURRENT_TASK_PRI,
131 TSI108_CPU_WHOAMI,
132 TSI108_CPU_INTACK,
133 TSI108_CPU_EOI,
134 TSI108_CPU_MCACK,
135
136 TSI108_IRQ_BASE,
137 TSI108_IRQ_STRIDE,
138 TSI108_IRQ_VECTOR_PRI,
139 TSI108_VECPRI_VECTOR_MASK,
140 TSI108_VECPRI_POLARITY_POSITIVE,
141 TSI108_VECPRI_POLARITY_NEGATIVE,
142 TSI108_VECPRI_SENSE_LEVEL,
143 TSI108_VECPRI_SENSE_EDGE,
144 TSI108_VECPRI_POLARITY_MASK,
145 TSI108_VECPRI_SENSE_MASK,
146 TSI108_IRQ_DESTINATION
147 },
148};
149
150#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
151
152#else /* CONFIG_MPIC_WEIRD */
153
154#define MPIC_INFO(name) MPIC_##name
155
156#endif /* CONFIG_MPIC_WEIRD */
157
158static inline unsigned int mpic_processor_id(struct mpic *mpic)
159{
160 unsigned int cpu = 0;
161
162 if (!(mpic->flags & MPIC_SECONDARY))
163 cpu = hard_smp_processor_id();
164
165 return cpu;
166}
167
168/*
169 * Register accessor functions
170 */
171
172
173static inline u32 _mpic_read(enum mpic_reg_type type,
174 struct mpic_reg_bank *rb,
175 unsigned int reg)
176{
177 switch(type) {
178#ifdef CONFIG_PPC_DCR
179 case mpic_access_dcr:
180 return dcr_read(rb->dhost, reg);
181#endif
182 case mpic_access_mmio_be:
183 return in_be32(rb->base + (reg >> 2));
184 case mpic_access_mmio_le:
185 default:
186 return in_le32(rb->base + (reg >> 2));
187 }
188}
189
190static inline void _mpic_write(enum mpic_reg_type type,
191 struct mpic_reg_bank *rb,
192 unsigned int reg, u32 value)
193{
194 switch(type) {
195#ifdef CONFIG_PPC_DCR
196 case mpic_access_dcr:
197 dcr_write(rb->dhost, reg, value);
198 break;
199#endif
200 case mpic_access_mmio_be:
201 out_be32(rb->base + (reg >> 2), value);
202 break;
203 case mpic_access_mmio_le:
204 default:
205 out_le32(rb->base + (reg >> 2), value);
206 break;
207 }
208}
209
210static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
211{
212 enum mpic_reg_type type = mpic->reg_type;
213 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
214 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
215
216 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
217 type = mpic_access_mmio_be;
218 return _mpic_read(type, &mpic->gregs, offset);
219}
220
221static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
222{
223 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
224 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
225
226 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
227}
228
229static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned int tm)
230{
231 return (tm >> 2) * MPIC_TIMER_GROUP_STRIDE +
232 (tm & 3) * MPIC_INFO(TIMER_STRIDE);
233}
234
235static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
236{
237 unsigned int offset = mpic_tm_offset(mpic, tm) +
238 MPIC_INFO(TIMER_VECTOR_PRI);
239
240 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
241}
242
243static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
244{
245 unsigned int offset = mpic_tm_offset(mpic, tm) +
246 MPIC_INFO(TIMER_VECTOR_PRI);
247
248 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
249}
250
251static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
252{
253 unsigned int cpu = mpic_processor_id(mpic);
254
255 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
256}
257
258static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
259{
260 unsigned int cpu = mpic_processor_id(mpic);
261
262 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
263}
264
265static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
266{
267 unsigned int isu = src_no >> mpic->isu_shift;
268 unsigned int idx = src_no & mpic->isu_mask;
269 unsigned int val;
270
271 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
272 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
273#ifdef CONFIG_MPIC_BROKEN_REGREAD
274 if (reg == 0)
275 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
276 mpic->isu_reg0_shadow[src_no];
277#endif
278 return val;
279}
280
281static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
282 unsigned int reg, u32 value)
283{
284 unsigned int isu = src_no >> mpic->isu_shift;
285 unsigned int idx = src_no & mpic->isu_mask;
286
287 _mpic_write(mpic->reg_type, &mpic->isus[isu],
288 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
289
290#ifdef CONFIG_MPIC_BROKEN_REGREAD
291 if (reg == 0)
292 mpic->isu_reg0_shadow[src_no] =
293 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
294#endif
295}
296
297#define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
298#define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
299#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
300#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
301#define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
302#define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
303#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
304#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
305#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
306#define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
307
308
309/*
310 * Low level utility functions
311 */
312
313
314static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
315 struct mpic_reg_bank *rb, unsigned int offset,
316 unsigned int size)
317{
318 rb->base = ioremap(phys_addr + offset, size);
319 BUG_ON(rb->base == NULL);
320}
321
322#ifdef CONFIG_PPC_DCR
323static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
324 unsigned int offset, unsigned int size)
325{
326 phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
327 rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
328 BUG_ON(!DCR_MAP_OK(rb->dhost));
329}
330
331static inline void mpic_map(struct mpic *mpic,
332 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
333 unsigned int offset, unsigned int size)
334{
335 if (mpic->flags & MPIC_USES_DCR)
336 _mpic_map_dcr(mpic, rb, offset, size);
337 else
338 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
339}
340#else /* CONFIG_PPC_DCR */
341#define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
342#endif /* !CONFIG_PPC_DCR */
343
344
345
346/* Check if we have one of those nice broken MPICs with a flipped endian on
347 * reads from IPI registers
348 */
349static void __init mpic_test_broken_ipi(struct mpic *mpic)
350{
351 u32 r;
352
353 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
354 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
355
356 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
357 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
358 mpic->flags |= MPIC_BROKEN_IPI;
359 }
360}
361
362#ifdef CONFIG_MPIC_U3_HT_IRQS
363
364/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
365 * to force the edge setting on the MPIC and do the ack workaround.
366 */
367static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
368{
369 if (source >= 128 || !mpic->fixups)
370 return 0;
371 return mpic->fixups[source].base != NULL;
372}
373
374
375static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
376{
377 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
378
379 if (fixup->applebase) {
380 unsigned int soff = (fixup->index >> 3) & ~3;
381 unsigned int mask = 1U << (fixup->index & 0x1f);
382 writel(mask, fixup->applebase + soff);
383 } else {
384 raw_spin_lock(&mpic->fixup_lock);
385 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
386 writel(fixup->data, fixup->base + 4);
387 raw_spin_unlock(&mpic->fixup_lock);
388 }
389}
390
391static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
392 bool level)
393{
394 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
395 unsigned long flags;
396 u32 tmp;
397
398 if (fixup->base == NULL)
399 return;
400
401 DBG("startup_ht_interrupt(0x%x) index: %d\n",
402 source, fixup->index);
403 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
404 /* Enable and configure */
405 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
406 tmp = readl(fixup->base + 4);
407 tmp &= ~(0x23U);
408 if (level)
409 tmp |= 0x22;
410 writel(tmp, fixup->base + 4);
411 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
412
413#ifdef CONFIG_PM
414 /* use the lowest bit inverted to the actual HW,
415 * set if this fixup was enabled, clear otherwise */
416 mpic->save_data[source].fixup_data = tmp | 1;
417#endif
418}
419
420static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
421{
422 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
423 unsigned long flags;
424 u32 tmp;
425
426 if (fixup->base == NULL)
427 return;
428
429 DBG("shutdown_ht_interrupt(0x%x)\n", source);
430
431 /* Disable */
432 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
433 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
434 tmp = readl(fixup->base + 4);
435 tmp |= 1;
436 writel(tmp, fixup->base + 4);
437 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
438
439#ifdef CONFIG_PM
440 /* use the lowest bit inverted to the actual HW,
441 * set if this fixup was enabled, clear otherwise */
442 mpic->save_data[source].fixup_data = tmp & ~1;
443#endif
444}
445
446#ifdef CONFIG_PCI_MSI
447static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
448 unsigned int devfn)
449{
450 u8 __iomem *base;
451 u8 pos, flags;
452 u64 addr = 0;
453
454 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
455 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
456 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
457 if (id == PCI_CAP_ID_HT) {
458 id = readb(devbase + pos + 3);
459 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
460 break;
461 }
462 }
463
464 if (pos == 0)
465 return;
466
467 base = devbase + pos;
468
469 flags = readb(base + HT_MSI_FLAGS);
470 if (!(flags & HT_MSI_FLAGS_FIXED)) {
471 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
472 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
473 }
474
475 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
476 PCI_SLOT(devfn), PCI_FUNC(devfn),
477 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
478
479 if (!(flags & HT_MSI_FLAGS_ENABLE))
480 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
481}
482#else
483static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
484 unsigned int devfn)
485{
486 return;
487}
488#endif
489
490static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
491 unsigned int devfn, u32 vdid)
492{
493 int i, irq, n;
494 u8 __iomem *base;
495 u32 tmp;
496 u8 pos;
497
498 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
499 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
500 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
501 if (id == PCI_CAP_ID_HT) {
502 id = readb(devbase + pos + 3);
503 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
504 break;
505 }
506 }
507 if (pos == 0)
508 return;
509
510 base = devbase + pos;
511 writeb(0x01, base + 2);
512 n = (readl(base + 4) >> 16) & 0xff;
513
514 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
515 " has %d irqs\n",
516 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
517
518 for (i = 0; i <= n; i++) {
519 writeb(0x10 + 2 * i, base + 2);
520 tmp = readl(base + 4);
521 irq = (tmp >> 16) & 0xff;
522 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
523 /* mask it , will be unmasked later */
524 tmp |= 0x1;
525 writel(tmp, base + 4);
526 mpic->fixups[irq].index = i;
527 mpic->fixups[irq].base = base;
528 /* Apple HT PIC has a non-standard way of doing EOIs */
529 if ((vdid & 0xffff) == 0x106b)
530 mpic->fixups[irq].applebase = devbase + 0x60;
531 else
532 mpic->fixups[irq].applebase = NULL;
533 writeb(0x11 + 2 * i, base + 2);
534 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
535 }
536}
537
538
539static void __init mpic_scan_ht_pics(struct mpic *mpic)
540{
541 unsigned int devfn;
542 u8 __iomem *cfgspace;
543
544 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
545
546 /* Allocate fixups array */
547 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
548 BUG_ON(mpic->fixups == NULL);
549
550 /* Init spinlock */
551 raw_spin_lock_init(&mpic->fixup_lock);
552
553 /* Map U3 config space. We assume all IO-APICs are on the primary bus
554 * so we only need to map 64kB.
555 */
556 cfgspace = ioremap(0xf2000000, 0x10000);
557 BUG_ON(cfgspace == NULL);
558
559 /* Now we scan all slots. We do a very quick scan, we read the header
560 * type, vendor ID and device ID only, that's plenty enough
561 */
562 for (devfn = 0; devfn < 0x100; devfn++) {
563 u8 __iomem *devbase = cfgspace + (devfn << 8);
564 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
565 u32 l = readl(devbase + PCI_VENDOR_ID);
566 u16 s;
567
568 DBG("devfn %x, l: %x\n", devfn, l);
569
570 /* If no device, skip */
571 if (l == 0xffffffff || l == 0x00000000 ||
572 l == 0x0000ffff || l == 0xffff0000)
573 goto next;
574 /* Check if is supports capability lists */
575 s = readw(devbase + PCI_STATUS);
576 if (!(s & PCI_STATUS_CAP_LIST))
577 goto next;
578
579 mpic_scan_ht_pic(mpic, devbase, devfn, l);
580 mpic_scan_ht_msi(mpic, devbase, devfn);
581
582 next:
583 /* next device, if function 0 */
584 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
585 devfn += 7;
586 }
587}
588
589#else /* CONFIG_MPIC_U3_HT_IRQS */
590
591static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
592{
593 return 0;
594}
595
596static void __init mpic_scan_ht_pics(struct mpic *mpic)
597{
598}
599
600#endif /* CONFIG_MPIC_U3_HT_IRQS */
601
602/* Find an mpic associated with a given linux interrupt */
603static struct mpic *mpic_find(unsigned int irq)
604{
605 if (irq < NUM_ISA_INTERRUPTS)
606 return NULL;
607
608 return irq_get_chip_data(irq);
609}
610
611/* Determine if the linux irq is an IPI */
612static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
613{
614 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
615}
616
617/* Determine if the linux irq is a timer */
618static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
619{
620 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
621}
622
623/* Convert a cpu mask from logical to physical cpu numbers. */
624static inline u32 mpic_physmask(u32 cpumask)
625{
626 int i;
627 u32 mask = 0;
628
629 for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
630 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
631 return mask;
632}
633
634#ifdef CONFIG_SMP
635/* Get the mpic structure from the IPI number */
636static inline struct mpic * mpic_from_ipi(struct irq_data *d)
637{
638 return irq_data_get_irq_chip_data(d);
639}
640#endif
641
642/* Get the mpic structure from the irq number */
643static inline struct mpic * mpic_from_irq(unsigned int irq)
644{
645 return irq_get_chip_data(irq);
646}
647
648/* Get the mpic structure from the irq data */
649static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
650{
651 return irq_data_get_irq_chip_data(d);
652}
653
654/* Send an EOI */
655static inline void mpic_eoi(struct mpic *mpic)
656{
657 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
658}
659
660/*
661 * Linux descriptor level callbacks
662 */
663
664
665void mpic_unmask_irq(struct irq_data *d)
666{
667 unsigned int loops = 100000;
668 struct mpic *mpic = mpic_from_irq_data(d);
669 unsigned int src = irqd_to_hwirq(d);
670
671 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
672
673 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
674 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
675 ~MPIC_VECPRI_MASK);
676 /* make sure mask gets to controller before we return to user */
677 do {
678 if (!loops--) {
679 printk(KERN_ERR "%s: timeout on hwirq %u\n",
680 __func__, src);
681 break;
682 }
683 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
684}
685
686void mpic_mask_irq(struct irq_data *d)
687{
688 unsigned int loops = 100000;
689 struct mpic *mpic = mpic_from_irq_data(d);
690 unsigned int src = irqd_to_hwirq(d);
691
692 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
693
694 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
695 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
696 MPIC_VECPRI_MASK);
697
698 /* make sure mask gets to controller before we return to user */
699 do {
700 if (!loops--) {
701 printk(KERN_ERR "%s: timeout on hwirq %u\n",
702 __func__, src);
703 break;
704 }
705 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
706}
707
708void mpic_end_irq(struct irq_data *d)
709{
710 struct mpic *mpic = mpic_from_irq_data(d);
711
712#ifdef DEBUG_IRQ
713 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
714#endif
715 /* We always EOI on end_irq() even for edge interrupts since that
716 * should only lower the priority, the MPIC should have properly
717 * latched another edge interrupt coming in anyway
718 */
719
720 mpic_eoi(mpic);
721}
722
723#ifdef CONFIG_MPIC_U3_HT_IRQS
724
725static void mpic_unmask_ht_irq(struct irq_data *d)
726{
727 struct mpic *mpic = mpic_from_irq_data(d);
728 unsigned int src = irqd_to_hwirq(d);
729
730 mpic_unmask_irq(d);
731
732 if (irqd_is_level_type(d))
733 mpic_ht_end_irq(mpic, src);
734}
735
736static unsigned int mpic_startup_ht_irq(struct irq_data *d)
737{
738 struct mpic *mpic = mpic_from_irq_data(d);
739 unsigned int src = irqd_to_hwirq(d);
740
741 mpic_unmask_irq(d);
742 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
743
744 return 0;
745}
746
747static void mpic_shutdown_ht_irq(struct irq_data *d)
748{
749 struct mpic *mpic = mpic_from_irq_data(d);
750 unsigned int src = irqd_to_hwirq(d);
751
752 mpic_shutdown_ht_interrupt(mpic, src);
753 mpic_mask_irq(d);
754}
755
756static void mpic_end_ht_irq(struct irq_data *d)
757{
758 struct mpic *mpic = mpic_from_irq_data(d);
759 unsigned int src = irqd_to_hwirq(d);
760
761#ifdef DEBUG_IRQ
762 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
763#endif
764 /* We always EOI on end_irq() even for edge interrupts since that
765 * should only lower the priority, the MPIC should have properly
766 * latched another edge interrupt coming in anyway
767 */
768
769 if (irqd_is_level_type(d))
770 mpic_ht_end_irq(mpic, src);
771 mpic_eoi(mpic);
772}
773#endif /* !CONFIG_MPIC_U3_HT_IRQS */
774
775#ifdef CONFIG_SMP
776
777static void mpic_unmask_ipi(struct irq_data *d)
778{
779 struct mpic *mpic = mpic_from_ipi(d);
780 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
781
782 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
783 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
784}
785
786static void mpic_mask_ipi(struct irq_data *d)
787{
788 /* NEVER disable an IPI... that's just plain wrong! */
789}
790
791static void mpic_end_ipi(struct irq_data *d)
792{
793 struct mpic *mpic = mpic_from_ipi(d);
794
795 /*
796 * IPIs are marked IRQ_PER_CPU. This has the side effect of
797 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
798 * applying to them. We EOI them late to avoid re-entering.
799 */
800 mpic_eoi(mpic);
801}
802
803#endif /* CONFIG_SMP */
804
805static void mpic_unmask_tm(struct irq_data *d)
806{
807 struct mpic *mpic = mpic_from_irq_data(d);
808 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
809
810 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
811 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
812 mpic_tm_read(src);
813}
814
815static void mpic_mask_tm(struct irq_data *d)
816{
817 struct mpic *mpic = mpic_from_irq_data(d);
818 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
819
820 mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
821 mpic_tm_read(src);
822}
823
824int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
825 bool force)
826{
827 struct mpic *mpic = mpic_from_irq_data(d);
828 unsigned int src = irqd_to_hwirq(d);
829
830 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
831 int cpuid = irq_choose_cpu(cpumask);
832
833 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
834 } else {
835 u32 mask = cpumask_bits(cpumask)[0];
836
837 mask &= cpumask_bits(cpu_online_mask)[0];
838
839 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
840 mpic_physmask(mask));
841 }
842
843 return IRQ_SET_MASK_OK;
844}
845
846static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
847{
848 /* Now convert sense value */
849 switch(type & IRQ_TYPE_SENSE_MASK) {
850 case IRQ_TYPE_EDGE_RISING:
851 return MPIC_INFO(VECPRI_SENSE_EDGE) |
852 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
853 case IRQ_TYPE_EDGE_FALLING:
854 case IRQ_TYPE_EDGE_BOTH:
855 return MPIC_INFO(VECPRI_SENSE_EDGE) |
856 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
857 case IRQ_TYPE_LEVEL_HIGH:
858 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
859 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
860 case IRQ_TYPE_LEVEL_LOW:
861 default:
862 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
863 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
864 }
865}
866
867int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
868{
869 struct mpic *mpic = mpic_from_irq_data(d);
870 unsigned int src = irqd_to_hwirq(d);
871 unsigned int vecpri, vold, vnew;
872
873 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
874 mpic, d->irq, src, flow_type);
875
876 if (src >= mpic->num_sources)
877 return -EINVAL;
878
879 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
880
881 /* We don't support "none" type */
882 if (flow_type == IRQ_TYPE_NONE)
883 flow_type = IRQ_TYPE_DEFAULT;
884
885 /* Default: read HW settings */
886 if (flow_type == IRQ_TYPE_DEFAULT) {
887 int vold_ps;
888
889 vold_ps = vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
890 MPIC_INFO(VECPRI_SENSE_MASK));
891
892 if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
893 MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
894 flow_type = IRQ_TYPE_EDGE_RISING;
895 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
896 MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
897 flow_type = IRQ_TYPE_EDGE_FALLING;
898 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
899 MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
900 flow_type = IRQ_TYPE_LEVEL_HIGH;
901 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
902 MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
903 flow_type = IRQ_TYPE_LEVEL_LOW;
904 else
905 WARN_ONCE(1, "mpic: unknown IRQ type %d\n", vold);
906 }
907
908 /* Apply to irq desc */
909 irqd_set_trigger_type(d, flow_type);
910
911 /* Apply to HW */
912 if (mpic_is_ht_interrupt(mpic, src))
913 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
914 MPIC_VECPRI_SENSE_EDGE;
915 else
916 vecpri = mpic_type_to_vecpri(mpic, flow_type);
917
918 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
919 MPIC_INFO(VECPRI_SENSE_MASK));
920 vnew |= vecpri;
921 if (vold != vnew)
922 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
923
924 return IRQ_SET_MASK_OK_NOCOPY;
925}
926
927void mpic_set_vector(unsigned int virq, unsigned int vector)
928{
929 struct mpic *mpic = mpic_from_irq(virq);
930 unsigned int src = virq_to_hw(virq);
931 unsigned int vecpri;
932
933 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
934 mpic, virq, src, vector);
935
936 if (src >= mpic->num_sources)
937 return;
938
939 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
940 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
941 vecpri |= vector;
942 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
943}
944
945static void mpic_set_destination(unsigned int virq, unsigned int cpuid)
946{
947 struct mpic *mpic = mpic_from_irq(virq);
948 unsigned int src = virq_to_hw(virq);
949
950 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
951 mpic, virq, src, cpuid);
952
953 if (src >= mpic->num_sources)
954 return;
955
956 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
957}
958
959static struct irq_chip mpic_irq_chip = {
960 .irq_mask = mpic_mask_irq,
961 .irq_unmask = mpic_unmask_irq,
962 .irq_eoi = mpic_end_irq,
963 .irq_set_type = mpic_set_irq_type,
964};
965
966#ifdef CONFIG_SMP
967static struct irq_chip mpic_ipi_chip = {
968 .irq_mask = mpic_mask_ipi,
969 .irq_unmask = mpic_unmask_ipi,
970 .irq_eoi = mpic_end_ipi,
971};
972#endif /* CONFIG_SMP */
973
974static struct irq_chip mpic_tm_chip = {
975 .irq_mask = mpic_mask_tm,
976 .irq_unmask = mpic_unmask_tm,
977 .irq_eoi = mpic_end_irq,
978};
979
980#ifdef CONFIG_MPIC_U3_HT_IRQS
981static struct irq_chip mpic_irq_ht_chip = {
982 .irq_startup = mpic_startup_ht_irq,
983 .irq_shutdown = mpic_shutdown_ht_irq,
984 .irq_mask = mpic_mask_irq,
985 .irq_unmask = mpic_unmask_ht_irq,
986 .irq_eoi = mpic_end_ht_irq,
987 .irq_set_type = mpic_set_irq_type,
988};
989#endif /* CONFIG_MPIC_U3_HT_IRQS */
990
991
992static int mpic_host_match(struct irq_domain *h, struct device_node *node,
993 enum irq_domain_bus_token bus_token)
994{
995 /* Exact match, unless mpic node is NULL */
996 struct device_node *of_node = irq_domain_get_of_node(h);
997 return of_node == NULL || of_node == node;
998}
999
1000static int mpic_host_map(struct irq_domain *h, unsigned int virq,
1001 irq_hw_number_t hw)
1002{
1003 struct mpic *mpic = h->host_data;
1004 struct irq_chip *chip;
1005
1006 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
1007
1008 if (hw == mpic->spurious_vec)
1009 return -EINVAL;
1010 if (mpic->protected && test_bit(hw, mpic->protected)) {
1011 pr_warning("mpic: Mapping of source 0x%x failed, "
1012 "source protected by firmware !\n",\
1013 (unsigned int)hw);
1014 return -EPERM;
1015 }
1016
1017#ifdef CONFIG_SMP
1018 else if (hw >= mpic->ipi_vecs[0]) {
1019 WARN_ON(mpic->flags & MPIC_SECONDARY);
1020
1021 DBG("mpic: mapping as IPI\n");
1022 irq_set_chip_data(virq, mpic);
1023 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
1024 handle_percpu_irq);
1025 return 0;
1026 }
1027#endif /* CONFIG_SMP */
1028
1029 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1030 WARN_ON(mpic->flags & MPIC_SECONDARY);
1031
1032 DBG("mpic: mapping as timer\n");
1033 irq_set_chip_data(virq, mpic);
1034 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1035 handle_fasteoi_irq);
1036 return 0;
1037 }
1038
1039 if (mpic_map_error_int(mpic, virq, hw))
1040 return 0;
1041
1042 if (hw >= mpic->num_sources) {
1043 pr_warning("mpic: Mapping of source 0x%x failed, "
1044 "source out of range !\n",\
1045 (unsigned int)hw);
1046 return -EINVAL;
1047 }
1048
1049 mpic_msi_reserve_hwirq(mpic, hw);
1050
1051 /* Default chip */
1052 chip = &mpic->hc_irq;
1053
1054#ifdef CONFIG_MPIC_U3_HT_IRQS
1055 /* Check for HT interrupts, override vecpri */
1056 if (mpic_is_ht_interrupt(mpic, hw))
1057 chip = &mpic->hc_ht_irq;
1058#endif /* CONFIG_MPIC_U3_HT_IRQS */
1059
1060 DBG("mpic: mapping to irq chip @%p\n", chip);
1061
1062 irq_set_chip_data(virq, mpic);
1063 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1064
1065 /* Set default irq type */
1066 irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
1067
1068 /* If the MPIC was reset, then all vectors have already been
1069 * initialized. Otherwise, a per source lazy initialization
1070 * is done here.
1071 */
1072 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1073 int cpu;
1074
1075 preempt_disable();
1076 cpu = mpic_processor_id(mpic);
1077 preempt_enable();
1078
1079 mpic_set_vector(virq, hw);
1080 mpic_set_destination(virq, cpu);
1081 mpic_irq_set_priority(virq, 8);
1082 }
1083
1084 return 0;
1085}
1086
1087static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
1088 const u32 *intspec, unsigned int intsize,
1089 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1090
1091{
1092 struct mpic *mpic = h->host_data;
1093 static unsigned char map_mpic_senses[4] = {
1094 IRQ_TYPE_EDGE_RISING,
1095 IRQ_TYPE_LEVEL_LOW,
1096 IRQ_TYPE_LEVEL_HIGH,
1097 IRQ_TYPE_EDGE_FALLING,
1098 };
1099
1100 *out_hwirq = intspec[0];
1101 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1102 /*
1103 * Freescale MPIC with extended intspec:
1104 * First two cells are as usual. Third specifies
1105 * an "interrupt type". Fourth is type-specific data.
1106 *
1107 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1108 */
1109 switch (intspec[2]) {
1110 case 0:
1111 break;
1112 case 1:
1113 if (!(mpic->flags & MPIC_FSL_HAS_EIMR))
1114 break;
1115
1116 if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs))
1117 return -EINVAL;
1118
1119 *out_hwirq = mpic->err_int_vecs[intspec[3]];
1120
1121 break;
1122 case 2:
1123 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1124 return -EINVAL;
1125
1126 *out_hwirq = mpic->ipi_vecs[intspec[0]];
1127 break;
1128 case 3:
1129 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1130 return -EINVAL;
1131
1132 *out_hwirq = mpic->timer_vecs[intspec[0]];
1133 break;
1134 default:
1135 pr_debug("%s: unknown irq type %u\n",
1136 __func__, intspec[2]);
1137 return -EINVAL;
1138 }
1139
1140 *out_flags = map_mpic_senses[intspec[1] & 3];
1141 } else if (intsize > 1) {
1142 u32 mask = 0x3;
1143
1144 /* Apple invented a new race of encoding on machines with
1145 * an HT APIC. They encode, among others, the index within
1146 * the HT APIC. We don't care about it here since thankfully,
1147 * it appears that they have the APIC already properly
1148 * configured, and thus our current fixup code that reads the
1149 * APIC config works fine. However, we still need to mask out
1150 * bits in the specifier to make sure we only get bit 0 which
1151 * is the level/edge bit (the only sense bit exposed by Apple),
1152 * as their bit 1 means something else.
1153 */
1154 if (machine_is(powermac))
1155 mask = 0x1;
1156 *out_flags = map_mpic_senses[intspec[1] & mask];
1157 } else
1158 *out_flags = IRQ_TYPE_NONE;
1159
1160 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1161 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1162
1163 return 0;
1164}
1165
1166/* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
1167static void mpic_cascade(struct irq_desc *desc)
1168{
1169 struct irq_chip *chip = irq_desc_get_chip(desc);
1170 struct mpic *mpic = irq_desc_get_handler_data(desc);
1171 unsigned int virq;
1172
1173 BUG_ON(!(mpic->flags & MPIC_SECONDARY));
1174
1175 virq = mpic_get_one_irq(mpic);
1176 if (virq)
1177 generic_handle_irq(virq);
1178
1179 chip->irq_eoi(&desc->irq_data);
1180}
1181
1182static const struct irq_domain_ops mpic_host_ops = {
1183 .match = mpic_host_match,
1184 .map = mpic_host_map,
1185 .xlate = mpic_host_xlate,
1186};
1187
1188static u32 fsl_mpic_get_version(struct mpic *mpic)
1189{
1190 u32 brr1;
1191
1192 if (!(mpic->flags & MPIC_FSL))
1193 return 0;
1194
1195 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
1196 MPIC_FSL_BRR1);
1197
1198 return brr1 & MPIC_FSL_BRR1_VER;
1199}
1200
1201/*
1202 * Exported functions
1203 */
1204
1205u32 fsl_mpic_primary_get_version(void)
1206{
1207 struct mpic *mpic = mpic_primary;
1208
1209 if (mpic)
1210 return fsl_mpic_get_version(mpic);
1211
1212 return 0;
1213}
1214
1215struct mpic * __init mpic_alloc(struct device_node *node,
1216 phys_addr_t phys_addr,
1217 unsigned int flags,
1218 unsigned int isu_size,
1219 unsigned int irq_count,
1220 const char *name)
1221{
1222 int i, psize, intvec_top;
1223 struct mpic *mpic;
1224 u32 greg_feature;
1225 const char *vers;
1226 const u32 *psrc;
1227 u32 last_irq;
1228 u32 fsl_version = 0;
1229
1230 /* Default MPIC search parameters */
1231 static const struct of_device_id __initconst mpic_device_id[] = {
1232 { .type = "open-pic", },
1233 { .compatible = "open-pic", },
1234 {},
1235 };
1236
1237 /*
1238 * If we were not passed a device-tree node, then perform the default
1239 * search for standardized a standardized OpenPIC.
1240 */
1241 if (node) {
1242 node = of_node_get(node);
1243 } else {
1244 node = of_find_matching_node(NULL, mpic_device_id);
1245 if (!node)
1246 return NULL;
1247 }
1248
1249 /* Pick the physical address from the device tree if unspecified */
1250 if (!phys_addr) {
1251 /* Check if it is DCR-based */
1252 if (of_get_property(node, "dcr-reg", NULL)) {
1253 flags |= MPIC_USES_DCR;
1254 } else {
1255 struct resource r;
1256 if (of_address_to_resource(node, 0, &r))
1257 goto err_of_node_put;
1258 phys_addr = r.start;
1259 }
1260 }
1261
1262 /* Read extra device-tree properties into the flags variable */
1263 if (of_get_property(node, "big-endian", NULL))
1264 flags |= MPIC_BIG_ENDIAN;
1265 if (of_get_property(node, "pic-no-reset", NULL))
1266 flags |= MPIC_NO_RESET;
1267 if (of_get_property(node, "single-cpu-affinity", NULL))
1268 flags |= MPIC_SINGLE_DEST_CPU;
1269 if (of_device_is_compatible(node, "fsl,mpic")) {
1270 flags |= MPIC_FSL | MPIC_LARGE_VECTORS;
1271 mpic_irq_chip.flags |= IRQCHIP_SKIP_SET_WAKE;
1272 mpic_tm_chip.flags |= IRQCHIP_SKIP_SET_WAKE;
1273 }
1274
1275 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1276 if (mpic == NULL)
1277 goto err_of_node_put;
1278
1279 mpic->name = name;
1280 mpic->node = node;
1281 mpic->paddr = phys_addr;
1282 mpic->flags = flags;
1283
1284 mpic->hc_irq = mpic_irq_chip;
1285 mpic->hc_irq.name = name;
1286 if (!(mpic->flags & MPIC_SECONDARY))
1287 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1288#ifdef CONFIG_MPIC_U3_HT_IRQS
1289 mpic->hc_ht_irq = mpic_irq_ht_chip;
1290 mpic->hc_ht_irq.name = name;
1291 if (!(mpic->flags & MPIC_SECONDARY))
1292 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1293#endif /* CONFIG_MPIC_U3_HT_IRQS */
1294
1295#ifdef CONFIG_SMP
1296 mpic->hc_ipi = mpic_ipi_chip;
1297 mpic->hc_ipi.name = name;
1298#endif /* CONFIG_SMP */
1299
1300 mpic->hc_tm = mpic_tm_chip;
1301 mpic->hc_tm.name = name;
1302
1303 mpic->num_sources = 0; /* so far */
1304
1305 if (mpic->flags & MPIC_LARGE_VECTORS)
1306 intvec_top = 2047;
1307 else
1308 intvec_top = 255;
1309
1310 mpic->timer_vecs[0] = intvec_top - 12;
1311 mpic->timer_vecs[1] = intvec_top - 11;
1312 mpic->timer_vecs[2] = intvec_top - 10;
1313 mpic->timer_vecs[3] = intvec_top - 9;
1314 mpic->timer_vecs[4] = intvec_top - 8;
1315 mpic->timer_vecs[5] = intvec_top - 7;
1316 mpic->timer_vecs[6] = intvec_top - 6;
1317 mpic->timer_vecs[7] = intvec_top - 5;
1318 mpic->ipi_vecs[0] = intvec_top - 4;
1319 mpic->ipi_vecs[1] = intvec_top - 3;
1320 mpic->ipi_vecs[2] = intvec_top - 2;
1321 mpic->ipi_vecs[3] = intvec_top - 1;
1322 mpic->spurious_vec = intvec_top;
1323
1324 /* Look for protected sources */
1325 psrc = of_get_property(mpic->node, "protected-sources", &psize);
1326 if (psrc) {
1327 /* Allocate a bitmap with one bit per interrupt */
1328 unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1);
1329 mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL);
1330 BUG_ON(mpic->protected == NULL);
1331 for (i = 0; i < psize/sizeof(u32); i++) {
1332 if (psrc[i] > intvec_top)
1333 continue;
1334 __set_bit(psrc[i], mpic->protected);
1335 }
1336 }
1337
1338#ifdef CONFIG_MPIC_WEIRD
1339 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
1340#endif
1341
1342 /* default register type */
1343 if (mpic->flags & MPIC_BIG_ENDIAN)
1344 mpic->reg_type = mpic_access_mmio_be;
1345 else
1346 mpic->reg_type = mpic_access_mmio_le;
1347
1348 /*
1349 * An MPIC with a "dcr-reg" property must be accessed that way, but
1350 * only if the kernel includes DCR support.
1351 */
1352#ifdef CONFIG_PPC_DCR
1353 if (mpic->flags & MPIC_USES_DCR)
1354 mpic->reg_type = mpic_access_dcr;
1355#else
1356 BUG_ON(mpic->flags & MPIC_USES_DCR);
1357#endif
1358
1359 /* Map the global registers */
1360 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1361 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1362
1363 if (mpic->flags & MPIC_FSL) {
1364 int ret;
1365
1366 /*
1367 * Yes, Freescale really did put global registers in the
1368 * magic per-cpu area -- and they don't even show up in the
1369 * non-magic per-cpu copies that this driver normally uses.
1370 */
1371 mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
1372 MPIC_CPU_THISBASE, 0x1000);
1373
1374 fsl_version = fsl_mpic_get_version(mpic);
1375
1376 /* Error interrupt mask register (EIMR) is required for
1377 * handling individual device error interrupts. EIMR
1378 * was added in MPIC version 4.1.
1379 *
1380 * Over here we reserve vector number space for error
1381 * interrupt vectors. This space is stolen from the
1382 * global vector number space, as in case of ipis
1383 * and timer interrupts.
1384 *
1385 * Available vector space = intvec_top - 12, where 12
1386 * is the number of vectors which have been consumed by
1387 * ipis and timer interrupts.
1388 */
1389 if (fsl_version >= 0x401) {
1390 ret = mpic_setup_error_int(mpic, intvec_top - 12);
1391 if (ret)
1392 return NULL;
1393 }
1394
1395 }
1396
1397 /*
1398 * EPR is only available starting with v4.0. To support
1399 * platforms that don't know the MPIC version at compile-time,
1400 * such as qemu-e500, turn off coreint if this MPIC doesn't
1401 * support it. Note that we never enable it if it wasn't
1402 * requested in the first place.
1403 *
1404 * This is done outside the MPIC_FSL check, so that we
1405 * also disable coreint if the MPIC node doesn't have
1406 * an "fsl,mpic" compatible at all. This will be the case
1407 * with device trees generated by older versions of QEMU.
1408 * fsl_version will be zero if MPIC_FSL is not set.
1409 */
1410 if (fsl_version < 0x400 && (flags & MPIC_ENABLE_COREINT)) {
1411 WARN_ON(ppc_md.get_irq != mpic_get_coreint_irq);
1412 ppc_md.get_irq = mpic_get_irq;
1413 }
1414
1415 /* Reset */
1416
1417 /* When using a device-node, reset requests are only honored if the MPIC
1418 * is allowed to reset.
1419 */
1420 if (!(mpic->flags & MPIC_NO_RESET)) {
1421 printk(KERN_DEBUG "mpic: Resetting\n");
1422 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1423 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1424 | MPIC_GREG_GCONF_RESET);
1425 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1426 & MPIC_GREG_GCONF_RESET)
1427 mb();
1428 }
1429
1430 /* CoreInt */
1431 if (mpic->flags & MPIC_ENABLE_COREINT)
1432 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1433 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1434 | MPIC_GREG_GCONF_COREINT);
1435
1436 if (mpic->flags & MPIC_ENABLE_MCK)
1437 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1438 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1439 | MPIC_GREG_GCONF_MCK);
1440
1441 /*
1442 * The MPIC driver will crash if there are more cores than we
1443 * can initialize, so we may as well catch that problem here.
1444 */
1445 BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS);
1446
1447 /* Map the per-CPU registers */
1448 for_each_possible_cpu(i) {
1449 unsigned int cpu = get_hard_smp_processor_id(i);
1450
1451 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
1452 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
1453 0x1000);
1454 }
1455
1456 /*
1457 * Read feature register. For non-ISU MPICs, num sources as well. On
1458 * ISU MPICs, sources are counted as ISUs are added
1459 */
1460 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1461
1462 /*
1463 * By default, the last source number comes from the MPIC, but the
1464 * device-tree and board support code can override it on buggy hw.
1465 * If we get passed an isu_size (multi-isu MPIC) then we use that
1466 * as a default instead of the value read from the HW.
1467 */
1468 last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1469 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT;
1470 if (isu_size)
1471 last_irq = isu_size * MPIC_MAX_ISU - 1;
1472 of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
1473 if (irq_count)
1474 last_irq = irq_count - 1;
1475
1476 /* Initialize main ISU if none provided */
1477 if (!isu_size) {
1478 isu_size = last_irq + 1;
1479 mpic->num_sources = isu_size;
1480 mpic_map(mpic, mpic->paddr, &mpic->isus[0],
1481 MPIC_INFO(IRQ_BASE),
1482 MPIC_INFO(IRQ_STRIDE) * isu_size);
1483 }
1484
1485 mpic->isu_size = isu_size;
1486 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1487 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1488
1489 mpic->irqhost = irq_domain_add_linear(mpic->node,
1490 intvec_top,
1491 &mpic_host_ops, mpic);
1492
1493 /*
1494 * FIXME: The code leaks the MPIC object and mappings here; this
1495 * is very unlikely to fail but it ought to be fixed anyways.
1496 */
1497 if (mpic->irqhost == NULL)
1498 return NULL;
1499
1500 /* Display version */
1501 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1502 case 1:
1503 vers = "1.0";
1504 break;
1505 case 2:
1506 vers = "1.2";
1507 break;
1508 case 3:
1509 vers = "1.3";
1510 break;
1511 default:
1512 vers = "<unknown>";
1513 break;
1514 }
1515 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1516 " max %d CPUs\n",
1517 name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
1518 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1519 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1520
1521 mpic->next = mpics;
1522 mpics = mpic;
1523
1524 if (!(mpic->flags & MPIC_SECONDARY)) {
1525 mpic_primary = mpic;
1526 irq_set_default_host(mpic->irqhost);
1527 }
1528
1529 return mpic;
1530
1531err_of_node_put:
1532 of_node_put(node);
1533 return NULL;
1534}
1535
1536void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1537 phys_addr_t paddr)
1538{
1539 unsigned int isu_first = isu_num * mpic->isu_size;
1540
1541 BUG_ON(isu_num >= MPIC_MAX_ISU);
1542
1543 mpic_map(mpic,
1544 paddr, &mpic->isus[isu_num], 0,
1545 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1546
1547 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1548 mpic->num_sources = isu_first + mpic->isu_size;
1549}
1550
1551void __init mpic_init(struct mpic *mpic)
1552{
1553 int i, cpu;
1554 int num_timers = 4;
1555
1556 BUG_ON(mpic->num_sources == 0);
1557
1558 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1559
1560 /* Set current processor priority to max */
1561 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1562
1563 if (mpic->flags & MPIC_FSL) {
1564 u32 version = fsl_mpic_get_version(mpic);
1565
1566 /*
1567 * Timer group B is present at the latest in MPIC 3.1 (e.g.
1568 * mpc8536). It is not present in MPIC 2.0 (e.g. mpc8544).
1569 * I don't know about the status of intermediate versions (or
1570 * whether they even exist).
1571 */
1572 if (version >= 0x0301)
1573 num_timers = 8;
1574 }
1575
1576 /* Initialize timers to our reserved vectors and mask them for now */
1577 for (i = 0; i < num_timers; i++) {
1578 unsigned int offset = mpic_tm_offset(mpic, i);
1579
1580 mpic_write(mpic->tmregs,
1581 offset + MPIC_INFO(TIMER_DESTINATION),
1582 1 << hard_smp_processor_id());
1583 mpic_write(mpic->tmregs,
1584 offset + MPIC_INFO(TIMER_VECTOR_PRI),
1585 MPIC_VECPRI_MASK |
1586 (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1587 (mpic->timer_vecs[0] + i));
1588 }
1589
1590 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1591 mpic_test_broken_ipi(mpic);
1592 for (i = 0; i < 4; i++) {
1593 mpic_ipi_write(i,
1594 MPIC_VECPRI_MASK |
1595 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1596 (mpic->ipi_vecs[0] + i));
1597 }
1598
1599 /* Do the HT PIC fixups on U3 broken mpic */
1600 DBG("MPIC flags: %x\n", mpic->flags);
1601 if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
1602 mpic_scan_ht_pics(mpic);
1603 mpic_u3msi_init(mpic);
1604 }
1605
1606 mpic_pasemi_msi_init(mpic);
1607
1608 cpu = mpic_processor_id(mpic);
1609
1610 if (!(mpic->flags & MPIC_NO_RESET)) {
1611 for (i = 0; i < mpic->num_sources; i++) {
1612 /* start with vector = source number, and masked */
1613 u32 vecpri = MPIC_VECPRI_MASK | i |
1614 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1615
1616 /* check if protected */
1617 if (mpic->protected && test_bit(i, mpic->protected))
1618 continue;
1619 /* init hw */
1620 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1621 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1622 }
1623 }
1624
1625 /* Init spurious vector */
1626 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1627
1628 /* Disable 8259 passthrough, if supported */
1629 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1630 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1631 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1632 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1633
1634 if (mpic->flags & MPIC_NO_BIAS)
1635 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1636 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1637 | MPIC_GREG_GCONF_NO_BIAS);
1638
1639 /* Set current processor priority to 0 */
1640 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1641
1642#ifdef CONFIG_PM
1643 /* allocate memory to save mpic state */
1644 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1645 GFP_KERNEL);
1646 BUG_ON(mpic->save_data == NULL);
1647#endif
1648
1649 /* Check if this MPIC is chained from a parent interrupt controller */
1650 if (mpic->flags & MPIC_SECONDARY) {
1651 int virq = irq_of_parse_and_map(mpic->node, 0);
1652 if (virq != NO_IRQ) {
1653 printk(KERN_INFO "%s: hooking up to IRQ %d\n",
1654 mpic->node->full_name, virq);
1655 irq_set_handler_data(virq, mpic);
1656 irq_set_chained_handler(virq, &mpic_cascade);
1657 }
1658 }
1659
1660 /* FSL mpic error interrupt initialization */
1661 if (mpic->flags & MPIC_FSL_HAS_EIMR)
1662 mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
1663}
1664
1665void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1666{
1667 struct mpic *mpic = mpic_find(irq);
1668 unsigned int src = virq_to_hw(irq);
1669 unsigned long flags;
1670 u32 reg;
1671
1672 if (!mpic)
1673 return;
1674
1675 raw_spin_lock_irqsave(&mpic_lock, flags);
1676 if (mpic_is_ipi(mpic, src)) {
1677 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1678 ~MPIC_VECPRI_PRIORITY_MASK;
1679 mpic_ipi_write(src - mpic->ipi_vecs[0],
1680 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1681 } else if (mpic_is_tm(mpic, src)) {
1682 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1683 ~MPIC_VECPRI_PRIORITY_MASK;
1684 mpic_tm_write(src - mpic->timer_vecs[0],
1685 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1686 } else {
1687 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1688 & ~MPIC_VECPRI_PRIORITY_MASK;
1689 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1690 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1691 }
1692 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1693}
1694
1695void mpic_setup_this_cpu(void)
1696{
1697#ifdef CONFIG_SMP
1698 struct mpic *mpic = mpic_primary;
1699 unsigned long flags;
1700 u32 msk = 1 << hard_smp_processor_id();
1701 unsigned int i;
1702
1703 BUG_ON(mpic == NULL);
1704
1705 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1706
1707 raw_spin_lock_irqsave(&mpic_lock, flags);
1708
1709 /* let the mpic know we want intrs. default affinity is 0xffffffff
1710 * until changed via /proc. That's how it's done on x86. If we want
1711 * it differently, then we should make sure we also change the default
1712 * values of irq_desc[].affinity in irq.c.
1713 */
1714 if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) {
1715 for (i = 0; i < mpic->num_sources ; i++)
1716 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1717 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1718 }
1719
1720 /* Set current processor priority to 0 */
1721 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1722
1723 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1724#endif /* CONFIG_SMP */
1725}
1726
1727int mpic_cpu_get_priority(void)
1728{
1729 struct mpic *mpic = mpic_primary;
1730
1731 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1732}
1733
1734void mpic_cpu_set_priority(int prio)
1735{
1736 struct mpic *mpic = mpic_primary;
1737
1738 prio &= MPIC_CPU_TASKPRI_MASK;
1739 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1740}
1741
1742void mpic_teardown_this_cpu(int secondary)
1743{
1744 struct mpic *mpic = mpic_primary;
1745 unsigned long flags;
1746 u32 msk = 1 << hard_smp_processor_id();
1747 unsigned int i;
1748
1749 BUG_ON(mpic == NULL);
1750
1751 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1752 raw_spin_lock_irqsave(&mpic_lock, flags);
1753
1754 /* let the mpic know we don't want intrs. */
1755 for (i = 0; i < mpic->num_sources ; i++)
1756 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1757 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1758
1759 /* Set current processor priority to max */
1760 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1761 /* We need to EOI the IPI since not all platforms reset the MPIC
1762 * on boot and new interrupts wouldn't get delivered otherwise.
1763 */
1764 mpic_eoi(mpic);
1765
1766 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1767}
1768
1769
1770static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1771{
1772 u32 src;
1773
1774 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1775#ifdef DEBUG_LOW
1776 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1777#endif
1778 if (unlikely(src == mpic->spurious_vec)) {
1779 if (mpic->flags & MPIC_SPV_EOI)
1780 mpic_eoi(mpic);
1781 return NO_IRQ;
1782 }
1783 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1784 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1785 mpic->name, (int)src);
1786 mpic_eoi(mpic);
1787 return NO_IRQ;
1788 }
1789
1790 return irq_linear_revmap(mpic->irqhost, src);
1791}
1792
1793unsigned int mpic_get_one_irq(struct mpic *mpic)
1794{
1795 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1796}
1797
1798unsigned int mpic_get_irq(void)
1799{
1800 struct mpic *mpic = mpic_primary;
1801
1802 BUG_ON(mpic == NULL);
1803
1804 return mpic_get_one_irq(mpic);
1805}
1806
1807unsigned int mpic_get_coreint_irq(void)
1808{
1809#ifdef CONFIG_BOOKE
1810 struct mpic *mpic = mpic_primary;
1811 u32 src;
1812
1813 BUG_ON(mpic == NULL);
1814
1815 src = mfspr(SPRN_EPR);
1816
1817 if (unlikely(src == mpic->spurious_vec)) {
1818 if (mpic->flags & MPIC_SPV_EOI)
1819 mpic_eoi(mpic);
1820 return NO_IRQ;
1821 }
1822 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1823 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1824 mpic->name, (int)src);
1825 return NO_IRQ;
1826 }
1827
1828 return irq_linear_revmap(mpic->irqhost, src);
1829#else
1830 return NO_IRQ;
1831#endif
1832}
1833
1834unsigned int mpic_get_mcirq(void)
1835{
1836 struct mpic *mpic = mpic_primary;
1837
1838 BUG_ON(mpic == NULL);
1839
1840 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1841}
1842
1843#ifdef CONFIG_SMP
1844void mpic_request_ipis(void)
1845{
1846 struct mpic *mpic = mpic_primary;
1847 int i;
1848 BUG_ON(mpic == NULL);
1849
1850 printk(KERN_INFO "mpic: requesting IPIs...\n");
1851
1852 for (i = 0; i < 4; i++) {
1853 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1854 mpic->ipi_vecs[0] + i);
1855 if (vipi == NO_IRQ) {
1856 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1857 continue;
1858 }
1859 smp_request_message_ipi(vipi, i);
1860 }
1861}
1862
1863void smp_mpic_message_pass(int cpu, int msg)
1864{
1865 struct mpic *mpic = mpic_primary;
1866 u32 physmask;
1867
1868 BUG_ON(mpic == NULL);
1869
1870 /* make sure we're sending something that translates to an IPI */
1871 if ((unsigned int)msg > 3) {
1872 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1873 smp_processor_id(), msg);
1874 return;
1875 }
1876
1877#ifdef DEBUG_IPI
1878 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1879#endif
1880
1881 physmask = 1 << get_hard_smp_processor_id(cpu);
1882
1883 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1884 msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1885}
1886
1887void __init smp_mpic_probe(void)
1888{
1889 int nr_cpus;
1890
1891 DBG("smp_mpic_probe()...\n");
1892
1893 nr_cpus = num_possible_cpus();
1894
1895 DBG("nr_cpus: %d\n", nr_cpus);
1896
1897 if (nr_cpus > 1)
1898 mpic_request_ipis();
1899}
1900
1901void smp_mpic_setup_cpu(int cpu)
1902{
1903 mpic_setup_this_cpu();
1904}
1905
1906void mpic_reset_core(int cpu)
1907{
1908 struct mpic *mpic = mpic_primary;
1909 u32 pir;
1910 int cpuid = get_hard_smp_processor_id(cpu);
1911 int i;
1912
1913 /* Set target bit for core reset */
1914 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1915 pir |= (1 << cpuid);
1916 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1917 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1918
1919 /* Restore target bit after reset complete */
1920 pir &= ~(1 << cpuid);
1921 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1922 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1923
1924 /* Perform 15 EOI on each reset core to clear pending interrupts.
1925 * This is required for FSL CoreNet based devices */
1926 if (mpic->flags & MPIC_FSL) {
1927 for (i = 0; i < 15; i++) {
1928 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1929 MPIC_CPU_EOI, 0);
1930 }
1931 }
1932}
1933#endif /* CONFIG_SMP */
1934
1935#ifdef CONFIG_PM
1936static void mpic_suspend_one(struct mpic *mpic)
1937{
1938 int i;
1939
1940 for (i = 0; i < mpic->num_sources; i++) {
1941 mpic->save_data[i].vecprio =
1942 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1943 mpic->save_data[i].dest =
1944 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1945 }
1946}
1947
1948static int mpic_suspend(void)
1949{
1950 struct mpic *mpic = mpics;
1951
1952 while (mpic) {
1953 mpic_suspend_one(mpic);
1954 mpic = mpic->next;
1955 }
1956
1957 return 0;
1958}
1959
1960static void mpic_resume_one(struct mpic *mpic)
1961{
1962 int i;
1963
1964 for (i = 0; i < mpic->num_sources; i++) {
1965 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1966 mpic->save_data[i].vecprio);
1967 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1968 mpic->save_data[i].dest);
1969
1970#ifdef CONFIG_MPIC_U3_HT_IRQS
1971 if (mpic->fixups) {
1972 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1973
1974 if (fixup->base) {
1975 /* we use the lowest bit in an inverted meaning */
1976 if ((mpic->save_data[i].fixup_data & 1) == 0)
1977 continue;
1978
1979 /* Enable and configure */
1980 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1981
1982 writel(mpic->save_data[i].fixup_data & ~1,
1983 fixup->base + 4);
1984 }
1985 }
1986#endif
1987 } /* end for loop */
1988}
1989
1990static void mpic_resume(void)
1991{
1992 struct mpic *mpic = mpics;
1993
1994 while (mpic) {
1995 mpic_resume_one(mpic);
1996 mpic = mpic->next;
1997 }
1998}
1999
2000static struct syscore_ops mpic_syscore_ops = {
2001 .resume = mpic_resume,
2002 .suspend = mpic_suspend,
2003};
2004
2005static int mpic_init_sys(void)
2006{
2007 register_syscore_ops(&mpic_syscore_ops);
2008 subsys_system_register(&mpic_subsys, NULL);
2009
2010 return 0;
2011}
2012
2013device_initcall(mpic_init_sys);
2014#endif