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1/*
2 * arch/powerpc/sysdev/ipic.c
3 *
4 * IPIC routines implementations.
5 *
6 * Copyright 2005 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/reboot.h>
17#include <linux/slab.h>
18#include <linux/stddef.h>
19#include <linux/sched.h>
20#include <linux/signal.h>
21#include <linux/syscore_ops.h>
22#include <linux/device.h>
23#include <linux/bootmem.h>
24#include <linux/spinlock.h>
25#include <linux/fsl_devices.h>
26#include <asm/irq.h>
27#include <asm/io.h>
28#include <asm/prom.h>
29#include <asm/ipic.h>
30
31#include "ipic.h"
32
33static struct ipic * primary_ipic;
34static struct irq_chip ipic_level_irq_chip, ipic_edge_irq_chip;
35static DEFINE_RAW_SPINLOCK(ipic_lock);
36
37static struct ipic_info ipic_info[] = {
38 [1] = {
39 .mask = IPIC_SIMSR_H,
40 .prio = IPIC_SIPRR_C,
41 .force = IPIC_SIFCR_H,
42 .bit = 16,
43 .prio_mask = 0,
44 },
45 [2] = {
46 .mask = IPIC_SIMSR_H,
47 .prio = IPIC_SIPRR_C,
48 .force = IPIC_SIFCR_H,
49 .bit = 17,
50 .prio_mask = 1,
51 },
52 [3] = {
53 .mask = IPIC_SIMSR_H,
54 .prio = IPIC_SIPRR_C,
55 .force = IPIC_SIFCR_H,
56 .bit = 18,
57 .prio_mask = 2,
58 },
59 [4] = {
60 .mask = IPIC_SIMSR_H,
61 .prio = IPIC_SIPRR_C,
62 .force = IPIC_SIFCR_H,
63 .bit = 19,
64 .prio_mask = 3,
65 },
66 [5] = {
67 .mask = IPIC_SIMSR_H,
68 .prio = IPIC_SIPRR_C,
69 .force = IPIC_SIFCR_H,
70 .bit = 20,
71 .prio_mask = 4,
72 },
73 [6] = {
74 .mask = IPIC_SIMSR_H,
75 .prio = IPIC_SIPRR_C,
76 .force = IPIC_SIFCR_H,
77 .bit = 21,
78 .prio_mask = 5,
79 },
80 [7] = {
81 .mask = IPIC_SIMSR_H,
82 .prio = IPIC_SIPRR_C,
83 .force = IPIC_SIFCR_H,
84 .bit = 22,
85 .prio_mask = 6,
86 },
87 [8] = {
88 .mask = IPIC_SIMSR_H,
89 .prio = IPIC_SIPRR_C,
90 .force = IPIC_SIFCR_H,
91 .bit = 23,
92 .prio_mask = 7,
93 },
94 [9] = {
95 .mask = IPIC_SIMSR_H,
96 .prio = IPIC_SIPRR_D,
97 .force = IPIC_SIFCR_H,
98 .bit = 24,
99 .prio_mask = 0,
100 },
101 [10] = {
102 .mask = IPIC_SIMSR_H,
103 .prio = IPIC_SIPRR_D,
104 .force = IPIC_SIFCR_H,
105 .bit = 25,
106 .prio_mask = 1,
107 },
108 [11] = {
109 .mask = IPIC_SIMSR_H,
110 .prio = IPIC_SIPRR_D,
111 .force = IPIC_SIFCR_H,
112 .bit = 26,
113 .prio_mask = 2,
114 },
115 [12] = {
116 .mask = IPIC_SIMSR_H,
117 .prio = IPIC_SIPRR_D,
118 .force = IPIC_SIFCR_H,
119 .bit = 27,
120 .prio_mask = 3,
121 },
122 [13] = {
123 .mask = IPIC_SIMSR_H,
124 .prio = IPIC_SIPRR_D,
125 .force = IPIC_SIFCR_H,
126 .bit = 28,
127 .prio_mask = 4,
128 },
129 [14] = {
130 .mask = IPIC_SIMSR_H,
131 .prio = IPIC_SIPRR_D,
132 .force = IPIC_SIFCR_H,
133 .bit = 29,
134 .prio_mask = 5,
135 },
136 [15] = {
137 .mask = IPIC_SIMSR_H,
138 .prio = IPIC_SIPRR_D,
139 .force = IPIC_SIFCR_H,
140 .bit = 30,
141 .prio_mask = 6,
142 },
143 [16] = {
144 .mask = IPIC_SIMSR_H,
145 .prio = IPIC_SIPRR_D,
146 .force = IPIC_SIFCR_H,
147 .bit = 31,
148 .prio_mask = 7,
149 },
150 [17] = {
151 .ack = IPIC_SEPNR,
152 .mask = IPIC_SEMSR,
153 .prio = IPIC_SMPRR_A,
154 .force = IPIC_SEFCR,
155 .bit = 1,
156 .prio_mask = 5,
157 },
158 [18] = {
159 .ack = IPIC_SEPNR,
160 .mask = IPIC_SEMSR,
161 .prio = IPIC_SMPRR_A,
162 .force = IPIC_SEFCR,
163 .bit = 2,
164 .prio_mask = 6,
165 },
166 [19] = {
167 .ack = IPIC_SEPNR,
168 .mask = IPIC_SEMSR,
169 .prio = IPIC_SMPRR_A,
170 .force = IPIC_SEFCR,
171 .bit = 3,
172 .prio_mask = 7,
173 },
174 [20] = {
175 .ack = IPIC_SEPNR,
176 .mask = IPIC_SEMSR,
177 .prio = IPIC_SMPRR_B,
178 .force = IPIC_SEFCR,
179 .bit = 4,
180 .prio_mask = 4,
181 },
182 [21] = {
183 .ack = IPIC_SEPNR,
184 .mask = IPIC_SEMSR,
185 .prio = IPIC_SMPRR_B,
186 .force = IPIC_SEFCR,
187 .bit = 5,
188 .prio_mask = 5,
189 },
190 [22] = {
191 .ack = IPIC_SEPNR,
192 .mask = IPIC_SEMSR,
193 .prio = IPIC_SMPRR_B,
194 .force = IPIC_SEFCR,
195 .bit = 6,
196 .prio_mask = 6,
197 },
198 [23] = {
199 .ack = IPIC_SEPNR,
200 .mask = IPIC_SEMSR,
201 .prio = IPIC_SMPRR_B,
202 .force = IPIC_SEFCR,
203 .bit = 7,
204 .prio_mask = 7,
205 },
206 [32] = {
207 .mask = IPIC_SIMSR_H,
208 .prio = IPIC_SIPRR_A,
209 .force = IPIC_SIFCR_H,
210 .bit = 0,
211 .prio_mask = 0,
212 },
213 [33] = {
214 .mask = IPIC_SIMSR_H,
215 .prio = IPIC_SIPRR_A,
216 .force = IPIC_SIFCR_H,
217 .bit = 1,
218 .prio_mask = 1,
219 },
220 [34] = {
221 .mask = IPIC_SIMSR_H,
222 .prio = IPIC_SIPRR_A,
223 .force = IPIC_SIFCR_H,
224 .bit = 2,
225 .prio_mask = 2,
226 },
227 [35] = {
228 .mask = IPIC_SIMSR_H,
229 .prio = IPIC_SIPRR_A,
230 .force = IPIC_SIFCR_H,
231 .bit = 3,
232 .prio_mask = 3,
233 },
234 [36] = {
235 .mask = IPIC_SIMSR_H,
236 .prio = IPIC_SIPRR_A,
237 .force = IPIC_SIFCR_H,
238 .bit = 4,
239 .prio_mask = 4,
240 },
241 [37] = {
242 .mask = IPIC_SIMSR_H,
243 .prio = IPIC_SIPRR_A,
244 .force = IPIC_SIFCR_H,
245 .bit = 5,
246 .prio_mask = 5,
247 },
248 [38] = {
249 .mask = IPIC_SIMSR_H,
250 .prio = IPIC_SIPRR_A,
251 .force = IPIC_SIFCR_H,
252 .bit = 6,
253 .prio_mask = 6,
254 },
255 [39] = {
256 .mask = IPIC_SIMSR_H,
257 .prio = IPIC_SIPRR_A,
258 .force = IPIC_SIFCR_H,
259 .bit = 7,
260 .prio_mask = 7,
261 },
262 [40] = {
263 .mask = IPIC_SIMSR_H,
264 .prio = IPIC_SIPRR_B,
265 .force = IPIC_SIFCR_H,
266 .bit = 8,
267 .prio_mask = 0,
268 },
269 [41] = {
270 .mask = IPIC_SIMSR_H,
271 .prio = IPIC_SIPRR_B,
272 .force = IPIC_SIFCR_H,
273 .bit = 9,
274 .prio_mask = 1,
275 },
276 [42] = {
277 .mask = IPIC_SIMSR_H,
278 .prio = IPIC_SIPRR_B,
279 .force = IPIC_SIFCR_H,
280 .bit = 10,
281 .prio_mask = 2,
282 },
283 [43] = {
284 .mask = IPIC_SIMSR_H,
285 .prio = IPIC_SIPRR_B,
286 .force = IPIC_SIFCR_H,
287 .bit = 11,
288 .prio_mask = 3,
289 },
290 [44] = {
291 .mask = IPIC_SIMSR_H,
292 .prio = IPIC_SIPRR_B,
293 .force = IPIC_SIFCR_H,
294 .bit = 12,
295 .prio_mask = 4,
296 },
297 [45] = {
298 .mask = IPIC_SIMSR_H,
299 .prio = IPIC_SIPRR_B,
300 .force = IPIC_SIFCR_H,
301 .bit = 13,
302 .prio_mask = 5,
303 },
304 [46] = {
305 .mask = IPIC_SIMSR_H,
306 .prio = IPIC_SIPRR_B,
307 .force = IPIC_SIFCR_H,
308 .bit = 14,
309 .prio_mask = 6,
310 },
311 [47] = {
312 .mask = IPIC_SIMSR_H,
313 .prio = IPIC_SIPRR_B,
314 .force = IPIC_SIFCR_H,
315 .bit = 15,
316 .prio_mask = 7,
317 },
318 [48] = {
319 .mask = IPIC_SEMSR,
320 .prio = IPIC_SMPRR_A,
321 .force = IPIC_SEFCR,
322 .bit = 0,
323 .prio_mask = 4,
324 },
325 [64] = {
326 .mask = IPIC_SIMSR_L,
327 .prio = IPIC_SMPRR_A,
328 .force = IPIC_SIFCR_L,
329 .bit = 0,
330 .prio_mask = 0,
331 },
332 [65] = {
333 .mask = IPIC_SIMSR_L,
334 .prio = IPIC_SMPRR_A,
335 .force = IPIC_SIFCR_L,
336 .bit = 1,
337 .prio_mask = 1,
338 },
339 [66] = {
340 .mask = IPIC_SIMSR_L,
341 .prio = IPIC_SMPRR_A,
342 .force = IPIC_SIFCR_L,
343 .bit = 2,
344 .prio_mask = 2,
345 },
346 [67] = {
347 .mask = IPIC_SIMSR_L,
348 .prio = IPIC_SMPRR_A,
349 .force = IPIC_SIFCR_L,
350 .bit = 3,
351 .prio_mask = 3,
352 },
353 [68] = {
354 .mask = IPIC_SIMSR_L,
355 .prio = IPIC_SMPRR_B,
356 .force = IPIC_SIFCR_L,
357 .bit = 4,
358 .prio_mask = 0,
359 },
360 [69] = {
361 .mask = IPIC_SIMSR_L,
362 .prio = IPIC_SMPRR_B,
363 .force = IPIC_SIFCR_L,
364 .bit = 5,
365 .prio_mask = 1,
366 },
367 [70] = {
368 .mask = IPIC_SIMSR_L,
369 .prio = IPIC_SMPRR_B,
370 .force = IPIC_SIFCR_L,
371 .bit = 6,
372 .prio_mask = 2,
373 },
374 [71] = {
375 .mask = IPIC_SIMSR_L,
376 .prio = IPIC_SMPRR_B,
377 .force = IPIC_SIFCR_L,
378 .bit = 7,
379 .prio_mask = 3,
380 },
381 [72] = {
382 .mask = IPIC_SIMSR_L,
383 .prio = 0,
384 .force = IPIC_SIFCR_L,
385 .bit = 8,
386 },
387 [73] = {
388 .mask = IPIC_SIMSR_L,
389 .prio = 0,
390 .force = IPIC_SIFCR_L,
391 .bit = 9,
392 },
393 [74] = {
394 .mask = IPIC_SIMSR_L,
395 .prio = 0,
396 .force = IPIC_SIFCR_L,
397 .bit = 10,
398 },
399 [75] = {
400 .mask = IPIC_SIMSR_L,
401 .prio = 0,
402 .force = IPIC_SIFCR_L,
403 .bit = 11,
404 },
405 [76] = {
406 .mask = IPIC_SIMSR_L,
407 .prio = 0,
408 .force = IPIC_SIFCR_L,
409 .bit = 12,
410 },
411 [77] = {
412 .mask = IPIC_SIMSR_L,
413 .prio = 0,
414 .force = IPIC_SIFCR_L,
415 .bit = 13,
416 },
417 [78] = {
418 .mask = IPIC_SIMSR_L,
419 .prio = 0,
420 .force = IPIC_SIFCR_L,
421 .bit = 14,
422 },
423 [79] = {
424 .mask = IPIC_SIMSR_L,
425 .prio = 0,
426 .force = IPIC_SIFCR_L,
427 .bit = 15,
428 },
429 [80] = {
430 .mask = IPIC_SIMSR_L,
431 .prio = 0,
432 .force = IPIC_SIFCR_L,
433 .bit = 16,
434 },
435 [81] = {
436 .mask = IPIC_SIMSR_L,
437 .prio = 0,
438 .force = IPIC_SIFCR_L,
439 .bit = 17,
440 },
441 [82] = {
442 .mask = IPIC_SIMSR_L,
443 .prio = 0,
444 .force = IPIC_SIFCR_L,
445 .bit = 18,
446 },
447 [83] = {
448 .mask = IPIC_SIMSR_L,
449 .prio = 0,
450 .force = IPIC_SIFCR_L,
451 .bit = 19,
452 },
453 [84] = {
454 .mask = IPIC_SIMSR_L,
455 .prio = 0,
456 .force = IPIC_SIFCR_L,
457 .bit = 20,
458 },
459 [85] = {
460 .mask = IPIC_SIMSR_L,
461 .prio = 0,
462 .force = IPIC_SIFCR_L,
463 .bit = 21,
464 },
465 [86] = {
466 .mask = IPIC_SIMSR_L,
467 .prio = 0,
468 .force = IPIC_SIFCR_L,
469 .bit = 22,
470 },
471 [87] = {
472 .mask = IPIC_SIMSR_L,
473 .prio = 0,
474 .force = IPIC_SIFCR_L,
475 .bit = 23,
476 },
477 [88] = {
478 .mask = IPIC_SIMSR_L,
479 .prio = 0,
480 .force = IPIC_SIFCR_L,
481 .bit = 24,
482 },
483 [89] = {
484 .mask = IPIC_SIMSR_L,
485 .prio = 0,
486 .force = IPIC_SIFCR_L,
487 .bit = 25,
488 },
489 [90] = {
490 .mask = IPIC_SIMSR_L,
491 .prio = 0,
492 .force = IPIC_SIFCR_L,
493 .bit = 26,
494 },
495 [91] = {
496 .mask = IPIC_SIMSR_L,
497 .prio = 0,
498 .force = IPIC_SIFCR_L,
499 .bit = 27,
500 },
501 [94] = {
502 .mask = IPIC_SIMSR_L,
503 .prio = 0,
504 .force = IPIC_SIFCR_L,
505 .bit = 30,
506 },
507};
508
509static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
510{
511 return in_be32(base + (reg >> 2));
512}
513
514static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
515{
516 out_be32(base + (reg >> 2), value);
517}
518
519static inline struct ipic * ipic_from_irq(unsigned int virq)
520{
521 return primary_ipic;
522}
523
524static void ipic_unmask_irq(struct irq_data *d)
525{
526 struct ipic *ipic = ipic_from_irq(d->irq);
527 unsigned int src = irqd_to_hwirq(d);
528 unsigned long flags;
529 u32 temp;
530
531 raw_spin_lock_irqsave(&ipic_lock, flags);
532
533 temp = ipic_read(ipic->regs, ipic_info[src].mask);
534 temp |= (1 << (31 - ipic_info[src].bit));
535 ipic_write(ipic->regs, ipic_info[src].mask, temp);
536
537 raw_spin_unlock_irqrestore(&ipic_lock, flags);
538}
539
540static void ipic_mask_irq(struct irq_data *d)
541{
542 struct ipic *ipic = ipic_from_irq(d->irq);
543 unsigned int src = irqd_to_hwirq(d);
544 unsigned long flags;
545 u32 temp;
546
547 raw_spin_lock_irqsave(&ipic_lock, flags);
548
549 temp = ipic_read(ipic->regs, ipic_info[src].mask);
550 temp &= ~(1 << (31 - ipic_info[src].bit));
551 ipic_write(ipic->regs, ipic_info[src].mask, temp);
552
553 /* mb() can't guarantee that masking is finished. But it does finish
554 * for nearly all cases. */
555 mb();
556
557 raw_spin_unlock_irqrestore(&ipic_lock, flags);
558}
559
560static void ipic_ack_irq(struct irq_data *d)
561{
562 struct ipic *ipic = ipic_from_irq(d->irq);
563 unsigned int src = irqd_to_hwirq(d);
564 unsigned long flags;
565 u32 temp;
566
567 raw_spin_lock_irqsave(&ipic_lock, flags);
568
569 temp = 1 << (31 - ipic_info[src].bit);
570 ipic_write(ipic->regs, ipic_info[src].ack, temp);
571
572 /* mb() can't guarantee that ack is finished. But it does finish
573 * for nearly all cases. */
574 mb();
575
576 raw_spin_unlock_irqrestore(&ipic_lock, flags);
577}
578
579static void ipic_mask_irq_and_ack(struct irq_data *d)
580{
581 struct ipic *ipic = ipic_from_irq(d->irq);
582 unsigned int src = irqd_to_hwirq(d);
583 unsigned long flags;
584 u32 temp;
585
586 raw_spin_lock_irqsave(&ipic_lock, flags);
587
588 temp = ipic_read(ipic->regs, ipic_info[src].mask);
589 temp &= ~(1 << (31 - ipic_info[src].bit));
590 ipic_write(ipic->regs, ipic_info[src].mask, temp);
591
592 temp = 1 << (31 - ipic_info[src].bit);
593 ipic_write(ipic->regs, ipic_info[src].ack, temp);
594
595 /* mb() can't guarantee that ack is finished. But it does finish
596 * for nearly all cases. */
597 mb();
598
599 raw_spin_unlock_irqrestore(&ipic_lock, flags);
600}
601
602static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type)
603{
604 struct ipic *ipic = ipic_from_irq(d->irq);
605 unsigned int src = irqd_to_hwirq(d);
606 unsigned int vold, vnew, edibit;
607
608 if (flow_type == IRQ_TYPE_NONE)
609 flow_type = IRQ_TYPE_LEVEL_LOW;
610
611 /* ipic supports only low assertion and high-to-low change senses
612 */
613 if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {
614 printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
615 flow_type);
616 return -EINVAL;
617 }
618 /* ipic supports only edge mode on external interrupts */
619 if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !ipic_info[src].ack) {
620 printk(KERN_ERR "ipic: edge sense not supported on internal "
621 "interrupts\n");
622 return -EINVAL;
623
624 }
625
626 irqd_set_trigger_type(d, flow_type);
627 if (flow_type & IRQ_TYPE_LEVEL_LOW) {
628 __irq_set_handler_locked(d->irq, handle_level_irq);
629 d->chip = &ipic_level_irq_chip;
630 } else {
631 __irq_set_handler_locked(d->irq, handle_edge_irq);
632 d->chip = &ipic_edge_irq_chip;
633 }
634
635 /* only EXT IRQ senses are programmable on ipic
636 * internal IRQ senses are LEVEL_LOW
637 */
638 if (src == IPIC_IRQ_EXT0)
639 edibit = 15;
640 else
641 if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7)
642 edibit = (14 - (src - IPIC_IRQ_EXT1));
643 else
644 return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
645
646 vold = ipic_read(ipic->regs, IPIC_SECNR);
647 if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) {
648 vnew = vold | (1 << edibit);
649 } else {
650 vnew = vold & ~(1 << edibit);
651 }
652 if (vold != vnew)
653 ipic_write(ipic->regs, IPIC_SECNR, vnew);
654 return IRQ_SET_MASK_OK_NOCOPY;
655}
656
657/* level interrupts and edge interrupts have different ack operations */
658static struct irq_chip ipic_level_irq_chip = {
659 .name = "IPIC",
660 .irq_unmask = ipic_unmask_irq,
661 .irq_mask = ipic_mask_irq,
662 .irq_mask_ack = ipic_mask_irq,
663 .irq_set_type = ipic_set_irq_type,
664};
665
666static struct irq_chip ipic_edge_irq_chip = {
667 .name = "IPIC",
668 .irq_unmask = ipic_unmask_irq,
669 .irq_mask = ipic_mask_irq,
670 .irq_mask_ack = ipic_mask_irq_and_ack,
671 .irq_ack = ipic_ack_irq,
672 .irq_set_type = ipic_set_irq_type,
673};
674
675static int ipic_host_match(struct irq_domain *h, struct device_node *node)
676{
677 /* Exact match, unless ipic node is NULL */
678 return h->of_node == NULL || h->of_node == node;
679}
680
681static int ipic_host_map(struct irq_domain *h, unsigned int virq,
682 irq_hw_number_t hw)
683{
684 struct ipic *ipic = h->host_data;
685
686 irq_set_chip_data(virq, ipic);
687 irq_set_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq);
688
689 /* Set default irq type */
690 irq_set_irq_type(virq, IRQ_TYPE_NONE);
691
692 return 0;
693}
694
695static struct irq_domain_ops ipic_host_ops = {
696 .match = ipic_host_match,
697 .map = ipic_host_map,
698 .xlate = irq_domain_xlate_onetwocell,
699};
700
701struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
702{
703 struct ipic *ipic;
704 struct resource res;
705 u32 temp = 0, ret;
706
707 ret = of_address_to_resource(node, 0, &res);
708 if (ret)
709 return NULL;
710
711 ipic = kzalloc(sizeof(*ipic), GFP_KERNEL);
712 if (ipic == NULL)
713 return NULL;
714
715 ipic->irqhost = irq_domain_add_linear(node, NR_IPIC_INTS,
716 &ipic_host_ops, ipic);
717 if (ipic->irqhost == NULL) {
718 kfree(ipic);
719 return NULL;
720 }
721
722 ipic->regs = ioremap(res.start, resource_size(&res));
723
724 /* init hw */
725 ipic_write(ipic->regs, IPIC_SICNR, 0x0);
726
727 /* default priority scheme is grouped. If spread mode is required
728 * configure SICFR accordingly */
729 if (flags & IPIC_SPREADMODE_GRP_A)
730 temp |= SICFR_IPSA;
731 if (flags & IPIC_SPREADMODE_GRP_B)
732 temp |= SICFR_IPSB;
733 if (flags & IPIC_SPREADMODE_GRP_C)
734 temp |= SICFR_IPSC;
735 if (flags & IPIC_SPREADMODE_GRP_D)
736 temp |= SICFR_IPSD;
737 if (flags & IPIC_SPREADMODE_MIX_A)
738 temp |= SICFR_MPSA;
739 if (flags & IPIC_SPREADMODE_MIX_B)
740 temp |= SICFR_MPSB;
741
742 ipic_write(ipic->regs, IPIC_SICFR, temp);
743
744 /* handle MCP route */
745 temp = 0;
746 if (flags & IPIC_DISABLE_MCP_OUT)
747 temp = SERCR_MCPR;
748 ipic_write(ipic->regs, IPIC_SERCR, temp);
749
750 /* handle routing of IRQ0 to MCP */
751 temp = ipic_read(ipic->regs, IPIC_SEMSR);
752
753 if (flags & IPIC_IRQ0_MCP)
754 temp |= SEMSR_SIRQ0;
755 else
756 temp &= ~SEMSR_SIRQ0;
757
758 ipic_write(ipic->regs, IPIC_SEMSR, temp);
759
760 primary_ipic = ipic;
761 irq_set_default_host(primary_ipic->irqhost);
762
763 ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
764 ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
765
766 printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
767 primary_ipic->regs);
768
769 return ipic;
770}
771
772int ipic_set_priority(unsigned int virq, unsigned int priority)
773{
774 struct ipic *ipic = ipic_from_irq(virq);
775 unsigned int src = virq_to_hw(virq);
776 u32 temp;
777
778 if (priority > 7)
779 return -EINVAL;
780 if (src > 127)
781 return -EINVAL;
782 if (ipic_info[src].prio == 0)
783 return -EINVAL;
784
785 temp = ipic_read(ipic->regs, ipic_info[src].prio);
786
787 if (priority < 4) {
788 temp &= ~(0x7 << (20 + (3 - priority) * 3));
789 temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
790 } else {
791 temp &= ~(0x7 << (4 + (7 - priority) * 3));
792 temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
793 }
794
795 ipic_write(ipic->regs, ipic_info[src].prio, temp);
796
797 return 0;
798}
799
800void ipic_set_highest_priority(unsigned int virq)
801{
802 struct ipic *ipic = ipic_from_irq(virq);
803 unsigned int src = virq_to_hw(virq);
804 u32 temp;
805
806 temp = ipic_read(ipic->regs, IPIC_SICFR);
807
808 /* clear and set HPI */
809 temp &= 0x7f000000;
810 temp |= (src & 0x7f) << 24;
811
812 ipic_write(ipic->regs, IPIC_SICFR, temp);
813}
814
815void ipic_set_default_priority(void)
816{
817 ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);
818 ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);
819 ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT);
820 ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT);
821 ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT);
822 ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT);
823}
824
825void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
826{
827 struct ipic *ipic = primary_ipic;
828 u32 temp;
829
830 temp = ipic_read(ipic->regs, IPIC_SERMR);
831 temp |= (1 << (31 - mcp_irq));
832 ipic_write(ipic->regs, IPIC_SERMR, temp);
833}
834
835void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq)
836{
837 struct ipic *ipic = primary_ipic;
838 u32 temp;
839
840 temp = ipic_read(ipic->regs, IPIC_SERMR);
841 temp &= (1 << (31 - mcp_irq));
842 ipic_write(ipic->regs, IPIC_SERMR, temp);
843}
844
845u32 ipic_get_mcp_status(void)
846{
847 return ipic_read(primary_ipic->regs, IPIC_SERMR);
848}
849
850void ipic_clear_mcp_status(u32 mask)
851{
852 ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
853}
854
855/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
856unsigned int ipic_get_irq(void)
857{
858 int irq;
859
860 BUG_ON(primary_ipic == NULL);
861
862#define IPIC_SIVCR_VECTOR_MASK 0x7f
863 irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;
864
865 if (irq == 0) /* 0 --> no irq is pending */
866 return NO_IRQ;
867
868 return irq_linear_revmap(primary_ipic->irqhost, irq);
869}
870
871#ifdef CONFIG_SUSPEND
872static struct {
873 u32 sicfr;
874 u32 siprr[2];
875 u32 simsr[2];
876 u32 sicnr;
877 u32 smprr[2];
878 u32 semsr;
879 u32 secnr;
880 u32 sermr;
881 u32 sercr;
882} ipic_saved_state;
883
884static int ipic_suspend(void)
885{
886 struct ipic *ipic = primary_ipic;
887
888 ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR);
889 ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A);
890 ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D);
891 ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H);
892 ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L);
893 ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR);
894 ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A);
895 ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B);
896 ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR);
897 ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR);
898 ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR);
899 ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR);
900
901 if (fsl_deep_sleep()) {
902 /* In deep sleep, make sure there can be no
903 * pending interrupts, as this can cause
904 * problems on 831x.
905 */
906 ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
907 ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
908 ipic_write(ipic->regs, IPIC_SEMSR, 0);
909 ipic_write(ipic->regs, IPIC_SERMR, 0);
910 }
911
912 return 0;
913}
914
915static void ipic_resume(void)
916{
917 struct ipic *ipic = primary_ipic;
918
919 ipic_write(ipic->regs, IPIC_SICFR, ipic_saved_state.sicfr);
920 ipic_write(ipic->regs, IPIC_SIPRR_A, ipic_saved_state.siprr[0]);
921 ipic_write(ipic->regs, IPIC_SIPRR_D, ipic_saved_state.siprr[1]);
922 ipic_write(ipic->regs, IPIC_SIMSR_H, ipic_saved_state.simsr[0]);
923 ipic_write(ipic->regs, IPIC_SIMSR_L, ipic_saved_state.simsr[1]);
924 ipic_write(ipic->regs, IPIC_SICNR, ipic_saved_state.sicnr);
925 ipic_write(ipic->regs, IPIC_SMPRR_A, ipic_saved_state.smprr[0]);
926 ipic_write(ipic->regs, IPIC_SMPRR_B, ipic_saved_state.smprr[1]);
927 ipic_write(ipic->regs, IPIC_SEMSR, ipic_saved_state.semsr);
928 ipic_write(ipic->regs, IPIC_SECNR, ipic_saved_state.secnr);
929 ipic_write(ipic->regs, IPIC_SERMR, ipic_saved_state.sermr);
930 ipic_write(ipic->regs, IPIC_SERCR, ipic_saved_state.sercr);
931}
932#else
933#define ipic_suspend NULL
934#define ipic_resume NULL
935#endif
936
937static struct syscore_ops ipic_syscore_ops = {
938 .suspend = ipic_suspend,
939 .resume = ipic_resume,
940};
941
942static int __init init_ipic_syscore(void)
943{
944 if (!primary_ipic || !primary_ipic->regs)
945 return -ENODEV;
946
947 printk(KERN_DEBUG "Registering ipic system core operations\n");
948 register_syscore_ops(&ipic_syscore_ops);
949
950 return 0;
951}
952
953subsys_initcall(init_ipic_syscore);
1/*
2 * arch/powerpc/sysdev/ipic.c
3 *
4 * IPIC routines implementations.
5 *
6 * Copyright 2005 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/reboot.h>
17#include <linux/slab.h>
18#include <linux/stddef.h>
19#include <linux/sched.h>
20#include <linux/signal.h>
21#include <linux/syscore_ops.h>
22#include <linux/device.h>
23#include <linux/spinlock.h>
24#include <linux/fsl_devices.h>
25#include <asm/irq.h>
26#include <asm/io.h>
27#include <asm/prom.h>
28#include <asm/ipic.h>
29
30#include "ipic.h"
31
32static struct ipic * primary_ipic;
33static struct irq_chip ipic_level_irq_chip, ipic_edge_irq_chip;
34static DEFINE_RAW_SPINLOCK(ipic_lock);
35
36static struct ipic_info ipic_info[] = {
37 [1] = {
38 .mask = IPIC_SIMSR_H,
39 .prio = IPIC_SIPRR_C,
40 .force = IPIC_SIFCR_H,
41 .bit = 16,
42 .prio_mask = 0,
43 },
44 [2] = {
45 .mask = IPIC_SIMSR_H,
46 .prio = IPIC_SIPRR_C,
47 .force = IPIC_SIFCR_H,
48 .bit = 17,
49 .prio_mask = 1,
50 },
51 [3] = {
52 .mask = IPIC_SIMSR_H,
53 .prio = IPIC_SIPRR_C,
54 .force = IPIC_SIFCR_H,
55 .bit = 18,
56 .prio_mask = 2,
57 },
58 [4] = {
59 .mask = IPIC_SIMSR_H,
60 .prio = IPIC_SIPRR_C,
61 .force = IPIC_SIFCR_H,
62 .bit = 19,
63 .prio_mask = 3,
64 },
65 [5] = {
66 .mask = IPIC_SIMSR_H,
67 .prio = IPIC_SIPRR_C,
68 .force = IPIC_SIFCR_H,
69 .bit = 20,
70 .prio_mask = 4,
71 },
72 [6] = {
73 .mask = IPIC_SIMSR_H,
74 .prio = IPIC_SIPRR_C,
75 .force = IPIC_SIFCR_H,
76 .bit = 21,
77 .prio_mask = 5,
78 },
79 [7] = {
80 .mask = IPIC_SIMSR_H,
81 .prio = IPIC_SIPRR_C,
82 .force = IPIC_SIFCR_H,
83 .bit = 22,
84 .prio_mask = 6,
85 },
86 [8] = {
87 .mask = IPIC_SIMSR_H,
88 .prio = IPIC_SIPRR_C,
89 .force = IPIC_SIFCR_H,
90 .bit = 23,
91 .prio_mask = 7,
92 },
93 [9] = {
94 .mask = IPIC_SIMSR_H,
95 .prio = IPIC_SIPRR_D,
96 .force = IPIC_SIFCR_H,
97 .bit = 24,
98 .prio_mask = 0,
99 },
100 [10] = {
101 .mask = IPIC_SIMSR_H,
102 .prio = IPIC_SIPRR_D,
103 .force = IPIC_SIFCR_H,
104 .bit = 25,
105 .prio_mask = 1,
106 },
107 [11] = {
108 .mask = IPIC_SIMSR_H,
109 .prio = IPIC_SIPRR_D,
110 .force = IPIC_SIFCR_H,
111 .bit = 26,
112 .prio_mask = 2,
113 },
114 [12] = {
115 .mask = IPIC_SIMSR_H,
116 .prio = IPIC_SIPRR_D,
117 .force = IPIC_SIFCR_H,
118 .bit = 27,
119 .prio_mask = 3,
120 },
121 [13] = {
122 .mask = IPIC_SIMSR_H,
123 .prio = IPIC_SIPRR_D,
124 .force = IPIC_SIFCR_H,
125 .bit = 28,
126 .prio_mask = 4,
127 },
128 [14] = {
129 .mask = IPIC_SIMSR_H,
130 .prio = IPIC_SIPRR_D,
131 .force = IPIC_SIFCR_H,
132 .bit = 29,
133 .prio_mask = 5,
134 },
135 [15] = {
136 .mask = IPIC_SIMSR_H,
137 .prio = IPIC_SIPRR_D,
138 .force = IPIC_SIFCR_H,
139 .bit = 30,
140 .prio_mask = 6,
141 },
142 [16] = {
143 .mask = IPIC_SIMSR_H,
144 .prio = IPIC_SIPRR_D,
145 .force = IPIC_SIFCR_H,
146 .bit = 31,
147 .prio_mask = 7,
148 },
149 [17] = {
150 .ack = IPIC_SEPNR,
151 .mask = IPIC_SEMSR,
152 .prio = IPIC_SMPRR_A,
153 .force = IPIC_SEFCR,
154 .bit = 1,
155 .prio_mask = 5,
156 },
157 [18] = {
158 .ack = IPIC_SEPNR,
159 .mask = IPIC_SEMSR,
160 .prio = IPIC_SMPRR_A,
161 .force = IPIC_SEFCR,
162 .bit = 2,
163 .prio_mask = 6,
164 },
165 [19] = {
166 .ack = IPIC_SEPNR,
167 .mask = IPIC_SEMSR,
168 .prio = IPIC_SMPRR_A,
169 .force = IPIC_SEFCR,
170 .bit = 3,
171 .prio_mask = 7,
172 },
173 [20] = {
174 .ack = IPIC_SEPNR,
175 .mask = IPIC_SEMSR,
176 .prio = IPIC_SMPRR_B,
177 .force = IPIC_SEFCR,
178 .bit = 4,
179 .prio_mask = 4,
180 },
181 [21] = {
182 .ack = IPIC_SEPNR,
183 .mask = IPIC_SEMSR,
184 .prio = IPIC_SMPRR_B,
185 .force = IPIC_SEFCR,
186 .bit = 5,
187 .prio_mask = 5,
188 },
189 [22] = {
190 .ack = IPIC_SEPNR,
191 .mask = IPIC_SEMSR,
192 .prio = IPIC_SMPRR_B,
193 .force = IPIC_SEFCR,
194 .bit = 6,
195 .prio_mask = 6,
196 },
197 [23] = {
198 .ack = IPIC_SEPNR,
199 .mask = IPIC_SEMSR,
200 .prio = IPIC_SMPRR_B,
201 .force = IPIC_SEFCR,
202 .bit = 7,
203 .prio_mask = 7,
204 },
205 [32] = {
206 .mask = IPIC_SIMSR_H,
207 .prio = IPIC_SIPRR_A,
208 .force = IPIC_SIFCR_H,
209 .bit = 0,
210 .prio_mask = 0,
211 },
212 [33] = {
213 .mask = IPIC_SIMSR_H,
214 .prio = IPIC_SIPRR_A,
215 .force = IPIC_SIFCR_H,
216 .bit = 1,
217 .prio_mask = 1,
218 },
219 [34] = {
220 .mask = IPIC_SIMSR_H,
221 .prio = IPIC_SIPRR_A,
222 .force = IPIC_SIFCR_H,
223 .bit = 2,
224 .prio_mask = 2,
225 },
226 [35] = {
227 .mask = IPIC_SIMSR_H,
228 .prio = IPIC_SIPRR_A,
229 .force = IPIC_SIFCR_H,
230 .bit = 3,
231 .prio_mask = 3,
232 },
233 [36] = {
234 .mask = IPIC_SIMSR_H,
235 .prio = IPIC_SIPRR_A,
236 .force = IPIC_SIFCR_H,
237 .bit = 4,
238 .prio_mask = 4,
239 },
240 [37] = {
241 .mask = IPIC_SIMSR_H,
242 .prio = IPIC_SIPRR_A,
243 .force = IPIC_SIFCR_H,
244 .bit = 5,
245 .prio_mask = 5,
246 },
247 [38] = {
248 .mask = IPIC_SIMSR_H,
249 .prio = IPIC_SIPRR_A,
250 .force = IPIC_SIFCR_H,
251 .bit = 6,
252 .prio_mask = 6,
253 },
254 [39] = {
255 .mask = IPIC_SIMSR_H,
256 .prio = IPIC_SIPRR_A,
257 .force = IPIC_SIFCR_H,
258 .bit = 7,
259 .prio_mask = 7,
260 },
261 [40] = {
262 .mask = IPIC_SIMSR_H,
263 .prio = IPIC_SIPRR_B,
264 .force = IPIC_SIFCR_H,
265 .bit = 8,
266 .prio_mask = 0,
267 },
268 [41] = {
269 .mask = IPIC_SIMSR_H,
270 .prio = IPIC_SIPRR_B,
271 .force = IPIC_SIFCR_H,
272 .bit = 9,
273 .prio_mask = 1,
274 },
275 [42] = {
276 .mask = IPIC_SIMSR_H,
277 .prio = IPIC_SIPRR_B,
278 .force = IPIC_SIFCR_H,
279 .bit = 10,
280 .prio_mask = 2,
281 },
282 [43] = {
283 .mask = IPIC_SIMSR_H,
284 .prio = IPIC_SIPRR_B,
285 .force = IPIC_SIFCR_H,
286 .bit = 11,
287 .prio_mask = 3,
288 },
289 [44] = {
290 .mask = IPIC_SIMSR_H,
291 .prio = IPIC_SIPRR_B,
292 .force = IPIC_SIFCR_H,
293 .bit = 12,
294 .prio_mask = 4,
295 },
296 [45] = {
297 .mask = IPIC_SIMSR_H,
298 .prio = IPIC_SIPRR_B,
299 .force = IPIC_SIFCR_H,
300 .bit = 13,
301 .prio_mask = 5,
302 },
303 [46] = {
304 .mask = IPIC_SIMSR_H,
305 .prio = IPIC_SIPRR_B,
306 .force = IPIC_SIFCR_H,
307 .bit = 14,
308 .prio_mask = 6,
309 },
310 [47] = {
311 .mask = IPIC_SIMSR_H,
312 .prio = IPIC_SIPRR_B,
313 .force = IPIC_SIFCR_H,
314 .bit = 15,
315 .prio_mask = 7,
316 },
317 [48] = {
318 .mask = IPIC_SEMSR,
319 .prio = IPIC_SMPRR_A,
320 .force = IPIC_SEFCR,
321 .bit = 0,
322 .prio_mask = 4,
323 },
324 [64] = {
325 .mask = IPIC_SIMSR_L,
326 .prio = IPIC_SMPRR_A,
327 .force = IPIC_SIFCR_L,
328 .bit = 0,
329 .prio_mask = 0,
330 },
331 [65] = {
332 .mask = IPIC_SIMSR_L,
333 .prio = IPIC_SMPRR_A,
334 .force = IPIC_SIFCR_L,
335 .bit = 1,
336 .prio_mask = 1,
337 },
338 [66] = {
339 .mask = IPIC_SIMSR_L,
340 .prio = IPIC_SMPRR_A,
341 .force = IPIC_SIFCR_L,
342 .bit = 2,
343 .prio_mask = 2,
344 },
345 [67] = {
346 .mask = IPIC_SIMSR_L,
347 .prio = IPIC_SMPRR_A,
348 .force = IPIC_SIFCR_L,
349 .bit = 3,
350 .prio_mask = 3,
351 },
352 [68] = {
353 .mask = IPIC_SIMSR_L,
354 .prio = IPIC_SMPRR_B,
355 .force = IPIC_SIFCR_L,
356 .bit = 4,
357 .prio_mask = 0,
358 },
359 [69] = {
360 .mask = IPIC_SIMSR_L,
361 .prio = IPIC_SMPRR_B,
362 .force = IPIC_SIFCR_L,
363 .bit = 5,
364 .prio_mask = 1,
365 },
366 [70] = {
367 .mask = IPIC_SIMSR_L,
368 .prio = IPIC_SMPRR_B,
369 .force = IPIC_SIFCR_L,
370 .bit = 6,
371 .prio_mask = 2,
372 },
373 [71] = {
374 .mask = IPIC_SIMSR_L,
375 .prio = IPIC_SMPRR_B,
376 .force = IPIC_SIFCR_L,
377 .bit = 7,
378 .prio_mask = 3,
379 },
380 [72] = {
381 .mask = IPIC_SIMSR_L,
382 .prio = 0,
383 .force = IPIC_SIFCR_L,
384 .bit = 8,
385 },
386 [73] = {
387 .mask = IPIC_SIMSR_L,
388 .prio = 0,
389 .force = IPIC_SIFCR_L,
390 .bit = 9,
391 },
392 [74] = {
393 .mask = IPIC_SIMSR_L,
394 .prio = 0,
395 .force = IPIC_SIFCR_L,
396 .bit = 10,
397 },
398 [75] = {
399 .mask = IPIC_SIMSR_L,
400 .prio = 0,
401 .force = IPIC_SIFCR_L,
402 .bit = 11,
403 },
404 [76] = {
405 .mask = IPIC_SIMSR_L,
406 .prio = 0,
407 .force = IPIC_SIFCR_L,
408 .bit = 12,
409 },
410 [77] = {
411 .mask = IPIC_SIMSR_L,
412 .prio = 0,
413 .force = IPIC_SIFCR_L,
414 .bit = 13,
415 },
416 [78] = {
417 .mask = IPIC_SIMSR_L,
418 .prio = 0,
419 .force = IPIC_SIFCR_L,
420 .bit = 14,
421 },
422 [79] = {
423 .mask = IPIC_SIMSR_L,
424 .prio = 0,
425 .force = IPIC_SIFCR_L,
426 .bit = 15,
427 },
428 [80] = {
429 .mask = IPIC_SIMSR_L,
430 .prio = 0,
431 .force = IPIC_SIFCR_L,
432 .bit = 16,
433 },
434 [81] = {
435 .mask = IPIC_SIMSR_L,
436 .prio = 0,
437 .force = IPIC_SIFCR_L,
438 .bit = 17,
439 },
440 [82] = {
441 .mask = IPIC_SIMSR_L,
442 .prio = 0,
443 .force = IPIC_SIFCR_L,
444 .bit = 18,
445 },
446 [83] = {
447 .mask = IPIC_SIMSR_L,
448 .prio = 0,
449 .force = IPIC_SIFCR_L,
450 .bit = 19,
451 },
452 [84] = {
453 .mask = IPIC_SIMSR_L,
454 .prio = 0,
455 .force = IPIC_SIFCR_L,
456 .bit = 20,
457 },
458 [85] = {
459 .mask = IPIC_SIMSR_L,
460 .prio = 0,
461 .force = IPIC_SIFCR_L,
462 .bit = 21,
463 },
464 [86] = {
465 .mask = IPIC_SIMSR_L,
466 .prio = 0,
467 .force = IPIC_SIFCR_L,
468 .bit = 22,
469 },
470 [87] = {
471 .mask = IPIC_SIMSR_L,
472 .prio = 0,
473 .force = IPIC_SIFCR_L,
474 .bit = 23,
475 },
476 [88] = {
477 .mask = IPIC_SIMSR_L,
478 .prio = 0,
479 .force = IPIC_SIFCR_L,
480 .bit = 24,
481 },
482 [89] = {
483 .mask = IPIC_SIMSR_L,
484 .prio = 0,
485 .force = IPIC_SIFCR_L,
486 .bit = 25,
487 },
488 [90] = {
489 .mask = IPIC_SIMSR_L,
490 .prio = 0,
491 .force = IPIC_SIFCR_L,
492 .bit = 26,
493 },
494 [91] = {
495 .mask = IPIC_SIMSR_L,
496 .prio = 0,
497 .force = IPIC_SIFCR_L,
498 .bit = 27,
499 },
500 [94] = {
501 .mask = IPIC_SIMSR_L,
502 .prio = 0,
503 .force = IPIC_SIFCR_L,
504 .bit = 30,
505 },
506};
507
508static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
509{
510 return in_be32(base + (reg >> 2));
511}
512
513static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
514{
515 out_be32(base + (reg >> 2), value);
516}
517
518static inline struct ipic * ipic_from_irq(unsigned int virq)
519{
520 return primary_ipic;
521}
522
523static void ipic_unmask_irq(struct irq_data *d)
524{
525 struct ipic *ipic = ipic_from_irq(d->irq);
526 unsigned int src = irqd_to_hwirq(d);
527 unsigned long flags;
528 u32 temp;
529
530 raw_spin_lock_irqsave(&ipic_lock, flags);
531
532 temp = ipic_read(ipic->regs, ipic_info[src].mask);
533 temp |= (1 << (31 - ipic_info[src].bit));
534 ipic_write(ipic->regs, ipic_info[src].mask, temp);
535
536 raw_spin_unlock_irqrestore(&ipic_lock, flags);
537}
538
539static void ipic_mask_irq(struct irq_data *d)
540{
541 struct ipic *ipic = ipic_from_irq(d->irq);
542 unsigned int src = irqd_to_hwirq(d);
543 unsigned long flags;
544 u32 temp;
545
546 raw_spin_lock_irqsave(&ipic_lock, flags);
547
548 temp = ipic_read(ipic->regs, ipic_info[src].mask);
549 temp &= ~(1 << (31 - ipic_info[src].bit));
550 ipic_write(ipic->regs, ipic_info[src].mask, temp);
551
552 /* mb() can't guarantee that masking is finished. But it does finish
553 * for nearly all cases. */
554 mb();
555
556 raw_spin_unlock_irqrestore(&ipic_lock, flags);
557}
558
559static void ipic_ack_irq(struct irq_data *d)
560{
561 struct ipic *ipic = ipic_from_irq(d->irq);
562 unsigned int src = irqd_to_hwirq(d);
563 unsigned long flags;
564 u32 temp;
565
566 raw_spin_lock_irqsave(&ipic_lock, flags);
567
568 temp = 1 << (31 - ipic_info[src].bit);
569 ipic_write(ipic->regs, ipic_info[src].ack, temp);
570
571 /* mb() can't guarantee that ack is finished. But it does finish
572 * for nearly all cases. */
573 mb();
574
575 raw_spin_unlock_irqrestore(&ipic_lock, flags);
576}
577
578static void ipic_mask_irq_and_ack(struct irq_data *d)
579{
580 struct ipic *ipic = ipic_from_irq(d->irq);
581 unsigned int src = irqd_to_hwirq(d);
582 unsigned long flags;
583 u32 temp;
584
585 raw_spin_lock_irqsave(&ipic_lock, flags);
586
587 temp = ipic_read(ipic->regs, ipic_info[src].mask);
588 temp &= ~(1 << (31 - ipic_info[src].bit));
589 ipic_write(ipic->regs, ipic_info[src].mask, temp);
590
591 temp = 1 << (31 - ipic_info[src].bit);
592 ipic_write(ipic->regs, ipic_info[src].ack, temp);
593
594 /* mb() can't guarantee that ack is finished. But it does finish
595 * for nearly all cases. */
596 mb();
597
598 raw_spin_unlock_irqrestore(&ipic_lock, flags);
599}
600
601static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type)
602{
603 struct ipic *ipic = ipic_from_irq(d->irq);
604 unsigned int src = irqd_to_hwirq(d);
605 unsigned int vold, vnew, edibit;
606
607 if (flow_type == IRQ_TYPE_NONE)
608 flow_type = IRQ_TYPE_LEVEL_LOW;
609
610 /* ipic supports only low assertion and high-to-low change senses
611 */
612 if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {
613 printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
614 flow_type);
615 return -EINVAL;
616 }
617 /* ipic supports only edge mode on external interrupts */
618 if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !ipic_info[src].ack) {
619 printk(KERN_ERR "ipic: edge sense not supported on internal "
620 "interrupts\n");
621 return -EINVAL;
622
623 }
624
625 irqd_set_trigger_type(d, flow_type);
626 if (flow_type & IRQ_TYPE_LEVEL_LOW) {
627 irq_set_handler_locked(d, handle_level_irq);
628 d->chip = &ipic_level_irq_chip;
629 } else {
630 irq_set_handler_locked(d, handle_edge_irq);
631 d->chip = &ipic_edge_irq_chip;
632 }
633
634 /* only EXT IRQ senses are programmable on ipic
635 * internal IRQ senses are LEVEL_LOW
636 */
637 if (src == IPIC_IRQ_EXT0)
638 edibit = 15;
639 else
640 if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7)
641 edibit = (14 - (src - IPIC_IRQ_EXT1));
642 else
643 return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
644
645 vold = ipic_read(ipic->regs, IPIC_SECNR);
646 if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) {
647 vnew = vold | (1 << edibit);
648 } else {
649 vnew = vold & ~(1 << edibit);
650 }
651 if (vold != vnew)
652 ipic_write(ipic->regs, IPIC_SECNR, vnew);
653 return IRQ_SET_MASK_OK_NOCOPY;
654}
655
656/* level interrupts and edge interrupts have different ack operations */
657static struct irq_chip ipic_level_irq_chip = {
658 .name = "IPIC",
659 .irq_unmask = ipic_unmask_irq,
660 .irq_mask = ipic_mask_irq,
661 .irq_mask_ack = ipic_mask_irq,
662 .irq_set_type = ipic_set_irq_type,
663};
664
665static struct irq_chip ipic_edge_irq_chip = {
666 .name = "IPIC",
667 .irq_unmask = ipic_unmask_irq,
668 .irq_mask = ipic_mask_irq,
669 .irq_mask_ack = ipic_mask_irq_and_ack,
670 .irq_ack = ipic_ack_irq,
671 .irq_set_type = ipic_set_irq_type,
672};
673
674static int ipic_host_match(struct irq_domain *h, struct device_node *node,
675 enum irq_domain_bus_token bus_token)
676{
677 /* Exact match, unless ipic node is NULL */
678 struct device_node *of_node = irq_domain_get_of_node(h);
679 return of_node == NULL || of_node == node;
680}
681
682static int ipic_host_map(struct irq_domain *h, unsigned int virq,
683 irq_hw_number_t hw)
684{
685 struct ipic *ipic = h->host_data;
686
687 irq_set_chip_data(virq, ipic);
688 irq_set_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq);
689
690 /* Set default irq type */
691 irq_set_irq_type(virq, IRQ_TYPE_NONE);
692
693 return 0;
694}
695
696static const struct irq_domain_ops ipic_host_ops = {
697 .match = ipic_host_match,
698 .map = ipic_host_map,
699 .xlate = irq_domain_xlate_onetwocell,
700};
701
702struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
703{
704 struct ipic *ipic;
705 struct resource res;
706 u32 temp = 0, ret;
707
708 ret = of_address_to_resource(node, 0, &res);
709 if (ret)
710 return NULL;
711
712 ipic = kzalloc(sizeof(*ipic), GFP_KERNEL);
713 if (ipic == NULL)
714 return NULL;
715
716 ipic->irqhost = irq_domain_add_linear(node, NR_IPIC_INTS,
717 &ipic_host_ops, ipic);
718 if (ipic->irqhost == NULL) {
719 kfree(ipic);
720 return NULL;
721 }
722
723 ipic->regs = ioremap(res.start, resource_size(&res));
724
725 /* init hw */
726 ipic_write(ipic->regs, IPIC_SICNR, 0x0);
727
728 /* default priority scheme is grouped. If spread mode is required
729 * configure SICFR accordingly */
730 if (flags & IPIC_SPREADMODE_GRP_A)
731 temp |= SICFR_IPSA;
732 if (flags & IPIC_SPREADMODE_GRP_B)
733 temp |= SICFR_IPSB;
734 if (flags & IPIC_SPREADMODE_GRP_C)
735 temp |= SICFR_IPSC;
736 if (flags & IPIC_SPREADMODE_GRP_D)
737 temp |= SICFR_IPSD;
738 if (flags & IPIC_SPREADMODE_MIX_A)
739 temp |= SICFR_MPSA;
740 if (flags & IPIC_SPREADMODE_MIX_B)
741 temp |= SICFR_MPSB;
742
743 ipic_write(ipic->regs, IPIC_SICFR, temp);
744
745 /* handle MCP route */
746 temp = 0;
747 if (flags & IPIC_DISABLE_MCP_OUT)
748 temp = SERCR_MCPR;
749 ipic_write(ipic->regs, IPIC_SERCR, temp);
750
751 /* handle routing of IRQ0 to MCP */
752 temp = ipic_read(ipic->regs, IPIC_SEMSR);
753
754 if (flags & IPIC_IRQ0_MCP)
755 temp |= SEMSR_SIRQ0;
756 else
757 temp &= ~SEMSR_SIRQ0;
758
759 ipic_write(ipic->regs, IPIC_SEMSR, temp);
760
761 primary_ipic = ipic;
762 irq_set_default_host(primary_ipic->irqhost);
763
764 ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
765 ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
766
767 printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
768 primary_ipic->regs);
769
770 return ipic;
771}
772
773int ipic_set_priority(unsigned int virq, unsigned int priority)
774{
775 struct ipic *ipic = ipic_from_irq(virq);
776 unsigned int src = virq_to_hw(virq);
777 u32 temp;
778
779 if (priority > 7)
780 return -EINVAL;
781 if (src > 127)
782 return -EINVAL;
783 if (ipic_info[src].prio == 0)
784 return -EINVAL;
785
786 temp = ipic_read(ipic->regs, ipic_info[src].prio);
787
788 if (priority < 4) {
789 temp &= ~(0x7 << (20 + (3 - priority) * 3));
790 temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
791 } else {
792 temp &= ~(0x7 << (4 + (7 - priority) * 3));
793 temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
794 }
795
796 ipic_write(ipic->regs, ipic_info[src].prio, temp);
797
798 return 0;
799}
800
801void ipic_set_highest_priority(unsigned int virq)
802{
803 struct ipic *ipic = ipic_from_irq(virq);
804 unsigned int src = virq_to_hw(virq);
805 u32 temp;
806
807 temp = ipic_read(ipic->regs, IPIC_SICFR);
808
809 /* clear and set HPI */
810 temp &= 0x7f000000;
811 temp |= (src & 0x7f) << 24;
812
813 ipic_write(ipic->regs, IPIC_SICFR, temp);
814}
815
816void ipic_set_default_priority(void)
817{
818 ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);
819 ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);
820 ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT);
821 ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT);
822 ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT);
823 ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT);
824}
825
826void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
827{
828 struct ipic *ipic = primary_ipic;
829 u32 temp;
830
831 temp = ipic_read(ipic->regs, IPIC_SERMR);
832 temp |= (1 << (31 - mcp_irq));
833 ipic_write(ipic->regs, IPIC_SERMR, temp);
834}
835
836void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq)
837{
838 struct ipic *ipic = primary_ipic;
839 u32 temp;
840
841 temp = ipic_read(ipic->regs, IPIC_SERMR);
842 temp &= (1 << (31 - mcp_irq));
843 ipic_write(ipic->regs, IPIC_SERMR, temp);
844}
845
846u32 ipic_get_mcp_status(void)
847{
848 return ipic_read(primary_ipic->regs, IPIC_SERMR);
849}
850
851void ipic_clear_mcp_status(u32 mask)
852{
853 ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
854}
855
856/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
857unsigned int ipic_get_irq(void)
858{
859 int irq;
860
861 BUG_ON(primary_ipic == NULL);
862
863#define IPIC_SIVCR_VECTOR_MASK 0x7f
864 irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;
865
866 if (irq == 0) /* 0 --> no irq is pending */
867 return NO_IRQ;
868
869 return irq_linear_revmap(primary_ipic->irqhost, irq);
870}
871
872#ifdef CONFIG_SUSPEND
873static struct {
874 u32 sicfr;
875 u32 siprr[2];
876 u32 simsr[2];
877 u32 sicnr;
878 u32 smprr[2];
879 u32 semsr;
880 u32 secnr;
881 u32 sermr;
882 u32 sercr;
883} ipic_saved_state;
884
885static int ipic_suspend(void)
886{
887 struct ipic *ipic = primary_ipic;
888
889 ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR);
890 ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A);
891 ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D);
892 ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H);
893 ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L);
894 ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR);
895 ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A);
896 ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B);
897 ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR);
898 ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR);
899 ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR);
900 ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR);
901
902 if (fsl_deep_sleep()) {
903 /* In deep sleep, make sure there can be no
904 * pending interrupts, as this can cause
905 * problems on 831x.
906 */
907 ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
908 ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
909 ipic_write(ipic->regs, IPIC_SEMSR, 0);
910 ipic_write(ipic->regs, IPIC_SERMR, 0);
911 }
912
913 return 0;
914}
915
916static void ipic_resume(void)
917{
918 struct ipic *ipic = primary_ipic;
919
920 ipic_write(ipic->regs, IPIC_SICFR, ipic_saved_state.sicfr);
921 ipic_write(ipic->regs, IPIC_SIPRR_A, ipic_saved_state.siprr[0]);
922 ipic_write(ipic->regs, IPIC_SIPRR_D, ipic_saved_state.siprr[1]);
923 ipic_write(ipic->regs, IPIC_SIMSR_H, ipic_saved_state.simsr[0]);
924 ipic_write(ipic->regs, IPIC_SIMSR_L, ipic_saved_state.simsr[1]);
925 ipic_write(ipic->regs, IPIC_SICNR, ipic_saved_state.sicnr);
926 ipic_write(ipic->regs, IPIC_SMPRR_A, ipic_saved_state.smprr[0]);
927 ipic_write(ipic->regs, IPIC_SMPRR_B, ipic_saved_state.smprr[1]);
928 ipic_write(ipic->regs, IPIC_SEMSR, ipic_saved_state.semsr);
929 ipic_write(ipic->regs, IPIC_SECNR, ipic_saved_state.secnr);
930 ipic_write(ipic->regs, IPIC_SERMR, ipic_saved_state.sermr);
931 ipic_write(ipic->regs, IPIC_SERCR, ipic_saved_state.sercr);
932}
933#else
934#define ipic_suspend NULL
935#define ipic_resume NULL
936#endif
937
938static struct syscore_ops ipic_syscore_ops = {
939 .suspend = ipic_suspend,
940 .resume = ipic_resume,
941};
942
943static int __init init_ipic_syscore(void)
944{
945 if (!primary_ipic || !primary_ipic->regs)
946 return -ENODEV;
947
948 printk(KERN_DEBUG "Registering ipic system core operations\n");
949 register_syscore_ops(&ipic_syscore_ops);
950
951 return 0;
952}
953
954subsys_initcall(init_ipic_syscore);