Loading...
Note: File does not exist in v3.15.
1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15#include <linux/delay.h>
16#include <linux/highmem.h>
17#include <linux/module.h>
18#include <linux/pci.h>
19#include <linux/dma-mapping.h>
20#include <linux/slab.h>
21#include <linux/device.h>
22#include <linux/mmc/host.h>
23#include <linux/mmc/mmc.h>
24#include <linux/scatterlist.h>
25#include <linux/io.h>
26#include <linux/gpio.h>
27#include <linux/pm_runtime.h>
28#include <linux/mmc/slot-gpio.h>
29#include <linux/mmc/sdhci-pci-data.h>
30
31#include "sdhci.h"
32#include "sdhci-pci.h"
33#include "sdhci-pci-o2micro.h"
34
35/*****************************************************************************\
36 * *
37 * Hardware specific quirk handling *
38 * *
39\*****************************************************************************/
40
41static int ricoh_probe(struct sdhci_pci_chip *chip)
42{
43 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
44 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
45 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
46 return 0;
47}
48
49static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
50{
51 slot->host->caps =
52 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
53 & SDHCI_TIMEOUT_CLK_MASK) |
54
55 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
56 & SDHCI_CLOCK_BASE_MASK) |
57
58 SDHCI_TIMEOUT_CLK_UNIT |
59 SDHCI_CAN_VDD_330 |
60 SDHCI_CAN_DO_HISPD |
61 SDHCI_CAN_DO_SDMA;
62 return 0;
63}
64
65static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
66{
67 /* Apply a delay to allow controller to settle */
68 /* Otherwise it becomes confused if card state changed
69 during suspend */
70 msleep(500);
71 return 0;
72}
73
74static const struct sdhci_pci_fixes sdhci_ricoh = {
75 .probe = ricoh_probe,
76 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
77 SDHCI_QUIRK_FORCE_DMA |
78 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
79};
80
81static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
82 .probe_slot = ricoh_mmc_probe_slot,
83 .resume = ricoh_mmc_resume,
84 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
85 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
86 SDHCI_QUIRK_NO_CARD_NO_RESET |
87 SDHCI_QUIRK_MISSING_CAPS
88};
89
90static const struct sdhci_pci_fixes sdhci_ene_712 = {
91 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
92 SDHCI_QUIRK_BROKEN_DMA,
93};
94
95static const struct sdhci_pci_fixes sdhci_ene_714 = {
96 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
97 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
98 SDHCI_QUIRK_BROKEN_DMA,
99};
100
101static const struct sdhci_pci_fixes sdhci_cafe = {
102 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
103 SDHCI_QUIRK_NO_BUSY_IRQ |
104 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
105 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
106};
107
108static const struct sdhci_pci_fixes sdhci_intel_qrk = {
109 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
110};
111
112static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
113{
114 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
115 return 0;
116}
117
118/*
119 * ADMA operation is disabled for Moorestown platform due to
120 * hardware bugs.
121 */
122static int mrst_hc_probe(struct sdhci_pci_chip *chip)
123{
124 /*
125 * slots number is fixed here for MRST as SDIO3/5 are never used and
126 * have hardware bugs.
127 */
128 chip->num_slots = 1;
129 return 0;
130}
131
132static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
133{
134 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
135 return 0;
136}
137
138#ifdef CONFIG_PM
139
140static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
141{
142 struct sdhci_pci_slot *slot = dev_id;
143 struct sdhci_host *host = slot->host;
144
145 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
146 return IRQ_HANDLED;
147}
148
149static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
150{
151 int err, irq, gpio = slot->cd_gpio;
152
153 slot->cd_gpio = -EINVAL;
154 slot->cd_irq = -EINVAL;
155
156 if (!gpio_is_valid(gpio))
157 return;
158
159 err = gpio_request(gpio, "sd_cd");
160 if (err < 0)
161 goto out;
162
163 err = gpio_direction_input(gpio);
164 if (err < 0)
165 goto out_free;
166
167 irq = gpio_to_irq(gpio);
168 if (irq < 0)
169 goto out_free;
170
171 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
172 IRQF_TRIGGER_FALLING, "sd_cd", slot);
173 if (err)
174 goto out_free;
175
176 slot->cd_gpio = gpio;
177 slot->cd_irq = irq;
178
179 return;
180
181out_free:
182 gpio_free(gpio);
183out:
184 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
185}
186
187static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
188{
189 if (slot->cd_irq >= 0)
190 free_irq(slot->cd_irq, slot);
191 if (gpio_is_valid(slot->cd_gpio))
192 gpio_free(slot->cd_gpio);
193}
194
195#else
196
197static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
198{
199}
200
201static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
202{
203}
204
205#endif
206
207static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
208{
209 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
210 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
211 MMC_CAP2_HC_ERASE_SZ;
212 return 0;
213}
214
215static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
216{
217 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
218 return 0;
219}
220
221static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
222 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
223 .probe_slot = mrst_hc_probe_slot,
224};
225
226static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
227 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
228 .probe = mrst_hc_probe,
229};
230
231static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
232 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
233 .allow_runtime_pm = true,
234 .own_cd_for_runtime_pm = true,
235};
236
237static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
238 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
239 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
240 .allow_runtime_pm = true,
241 .probe_slot = mfd_sdio_probe_slot,
242};
243
244static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
245 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
246 .allow_runtime_pm = true,
247 .probe_slot = mfd_emmc_probe_slot,
248};
249
250static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
251 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
252 .probe_slot = pch_hc_probe_slot,
253};
254
255static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
256{
257 u8 reg;
258
259 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
260 reg |= 0x10;
261 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
262 /* For eMMC, minimum is 1us but give it 9us for good measure */
263 udelay(9);
264 reg &= ~0x10;
265 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
266 /* For eMMC, minimum is 200us but give it 300us for good measure */
267 usleep_range(300, 1000);
268}
269
270static int spt_select_drive_strength(struct sdhci_host *host,
271 struct mmc_card *card,
272 unsigned int max_dtr,
273 int host_drv, int card_drv, int *drv_type)
274{
275 int drive_strength;
276
277 if (sdhci_pci_spt_drive_strength > 0)
278 drive_strength = sdhci_pci_spt_drive_strength & 0xf;
279 else
280 drive_strength = 0; /* Default 50-ohm */
281
282 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0)
283 drive_strength = 0; /* Default 50-ohm */
284
285 return drive_strength;
286}
287
288/* Try to read the drive strength from the card */
289static void spt_read_drive_strength(struct sdhci_host *host)
290{
291 u32 val, i, t;
292 u16 m;
293
294 if (sdhci_pci_spt_drive_strength)
295 return;
296
297 sdhci_pci_spt_drive_strength = -1;
298
299 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7;
300 if (m != 3 && m != 5)
301 return;
302 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
303 if (val & 0x3)
304 return;
305 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE);
306 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
307 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE);
308 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
309 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE);
310 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT);
311 sdhci_writel(host, 0, SDHCI_ARGUMENT);
312 sdhci_writew(host, 0x83b, SDHCI_COMMAND);
313 for (i = 0; i < 1000; i++) {
314 val = sdhci_readl(host, SDHCI_INT_STATUS);
315 if (val & 0xffff8000)
316 return;
317 if (val & 0x20)
318 break;
319 udelay(1);
320 }
321 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
322 if (!(val & 0x800))
323 return;
324 for (i = 0; i < 47; i++)
325 val = sdhci_readl(host, SDHCI_BUFFER);
326 t = val & 0xf00;
327 if (t != 0x200 && t != 0x300)
328 return;
329
330 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf);
331}
332
333static int bxt_get_cd(struct mmc_host *mmc)
334{
335 int gpio_cd = mmc_gpio_get_cd(mmc);
336 struct sdhci_host *host = mmc_priv(mmc);
337 unsigned long flags;
338 int ret = 0;
339
340 if (!gpio_cd)
341 return 0;
342
343 pm_runtime_get_sync(mmc->parent);
344
345 spin_lock_irqsave(&host->lock, flags);
346
347 if (host->flags & SDHCI_DEVICE_DEAD)
348 goto out;
349
350 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
351out:
352 spin_unlock_irqrestore(&host->lock, flags);
353
354 pm_runtime_mark_last_busy(mmc->parent);
355 pm_runtime_put_autosuspend(mmc->parent);
356
357 return ret;
358}
359
360static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
361{
362 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
363 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
364 MMC_CAP_BUS_WIDTH_TEST |
365 MMC_CAP_WAIT_WHILE_BUSY;
366 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
367 slot->hw_reset = sdhci_pci_int_hw_reset;
368 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
369 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
370 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) {
371 spt_read_drive_strength(slot->host);
372 slot->select_drive_strength = spt_select_drive_strength;
373 }
374 return 0;
375}
376
377static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
378{
379 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
380 MMC_CAP_BUS_WIDTH_TEST |
381 MMC_CAP_WAIT_WHILE_BUSY;
382 return 0;
383}
384
385static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
386{
387 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST |
388 MMC_CAP_WAIT_WHILE_BUSY;
389 slot->cd_con_id = NULL;
390 slot->cd_idx = 0;
391 slot->cd_override_level = true;
392 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
393 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
394 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD)
395 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
396
397 return 0;
398}
399
400static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
401 .allow_runtime_pm = true,
402 .probe_slot = byt_emmc_probe_slot,
403 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
404 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
405 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
406 SDHCI_QUIRK2_STOP_WITH_TC,
407};
408
409static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
410 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
411 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
412 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
413 .allow_runtime_pm = true,
414 .probe_slot = byt_sdio_probe_slot,
415};
416
417static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
418 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
419 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
420 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
421 SDHCI_QUIRK2_STOP_WITH_TC,
422 .allow_runtime_pm = true,
423 .own_cd_for_runtime_pm = true,
424 .probe_slot = byt_sd_probe_slot,
425};
426
427/* Define Host controllers for Intel Merrifield platform */
428#define INTEL_MRFL_EMMC_0 0
429#define INTEL_MRFL_EMMC_1 1
430
431static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
432{
433 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
434 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
435 /* SD support is not ready yet */
436 return -ENODEV;
437
438 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
439 MMC_CAP_1_8V_DDR;
440
441 return 0;
442}
443
444static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
445 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
446 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
447 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
448 .allow_runtime_pm = true,
449 .probe_slot = intel_mrfl_mmc_probe_slot,
450};
451
452/* O2Micro extra registers */
453#define O2_SD_LOCK_WP 0xD3
454#define O2_SD_MULTI_VCC3V 0xEE
455#define O2_SD_CLKREQ 0xEC
456#define O2_SD_CAPS 0xE0
457#define O2_SD_ADMA1 0xE2
458#define O2_SD_ADMA2 0xE7
459#define O2_SD_INF_MOD 0xF1
460
461static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
462{
463 u8 scratch;
464 int ret;
465
466 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
467 if (ret)
468 return ret;
469
470 /*
471 * Turn PMOS on [bit 0], set over current detection to 2.4 V
472 * [bit 1:2] and enable over current debouncing [bit 6].
473 */
474 if (on)
475 scratch |= 0x47;
476 else
477 scratch &= ~0x47;
478
479 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
480}
481
482static int jmicron_probe(struct sdhci_pci_chip *chip)
483{
484 int ret;
485 u16 mmcdev = 0;
486
487 if (chip->pdev->revision == 0) {
488 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
489 SDHCI_QUIRK_32BIT_DMA_SIZE |
490 SDHCI_QUIRK_32BIT_ADMA_SIZE |
491 SDHCI_QUIRK_RESET_AFTER_REQUEST |
492 SDHCI_QUIRK_BROKEN_SMALL_PIO;
493 }
494
495 /*
496 * JMicron chips can have two interfaces to the same hardware
497 * in order to work around limitations in Microsoft's driver.
498 * We need to make sure we only bind to one of them.
499 *
500 * This code assumes two things:
501 *
502 * 1. The PCI code adds subfunctions in order.
503 *
504 * 2. The MMC interface has a lower subfunction number
505 * than the SD interface.
506 */
507 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
508 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
509 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
510 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
511
512 if (mmcdev) {
513 struct pci_dev *sd_dev;
514
515 sd_dev = NULL;
516 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
517 mmcdev, sd_dev)) != NULL) {
518 if ((PCI_SLOT(chip->pdev->devfn) ==
519 PCI_SLOT(sd_dev->devfn)) &&
520 (chip->pdev->bus == sd_dev->bus))
521 break;
522 }
523
524 if (sd_dev) {
525 pci_dev_put(sd_dev);
526 dev_info(&chip->pdev->dev, "Refusing to bind to "
527 "secondary interface.\n");
528 return -ENODEV;
529 }
530 }
531
532 /*
533 * JMicron chips need a bit of a nudge to enable the power
534 * output pins.
535 */
536 ret = jmicron_pmos(chip, 1);
537 if (ret) {
538 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
539 return ret;
540 }
541
542 /* quirk for unsable RO-detection on JM388 chips */
543 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
544 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
545 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
546
547 return 0;
548}
549
550static void jmicron_enable_mmc(struct sdhci_host *host, int on)
551{
552 u8 scratch;
553
554 scratch = readb(host->ioaddr + 0xC0);
555
556 if (on)
557 scratch |= 0x01;
558 else
559 scratch &= ~0x01;
560
561 writeb(scratch, host->ioaddr + 0xC0);
562}
563
564static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
565{
566 if (slot->chip->pdev->revision == 0) {
567 u16 version;
568
569 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
570 version = (version & SDHCI_VENDOR_VER_MASK) >>
571 SDHCI_VENDOR_VER_SHIFT;
572
573 /*
574 * Older versions of the chip have lots of nasty glitches
575 * in the ADMA engine. It's best just to avoid it
576 * completely.
577 */
578 if (version < 0xAC)
579 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
580 }
581
582 /* JM388 MMC doesn't support 1.8V while SD supports it */
583 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
584 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
585 MMC_VDD_29_30 | MMC_VDD_30_31 |
586 MMC_VDD_165_195; /* allow 1.8V */
587 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
588 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
589 }
590
591 /*
592 * The secondary interface requires a bit set to get the
593 * interrupts.
594 */
595 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
596 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
597 jmicron_enable_mmc(slot->host, 1);
598
599 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
600
601 return 0;
602}
603
604static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
605{
606 if (dead)
607 return;
608
609 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
610 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
611 jmicron_enable_mmc(slot->host, 0);
612}
613
614static int jmicron_suspend(struct sdhci_pci_chip *chip)
615{
616 int i;
617
618 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
619 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
620 for (i = 0; i < chip->num_slots; i++)
621 jmicron_enable_mmc(chip->slots[i]->host, 0);
622 }
623
624 return 0;
625}
626
627static int jmicron_resume(struct sdhci_pci_chip *chip)
628{
629 int ret, i;
630
631 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
632 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
633 for (i = 0; i < chip->num_slots; i++)
634 jmicron_enable_mmc(chip->slots[i]->host, 1);
635 }
636
637 ret = jmicron_pmos(chip, 1);
638 if (ret) {
639 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
640 return ret;
641 }
642
643 return 0;
644}
645
646static const struct sdhci_pci_fixes sdhci_o2 = {
647 .probe = sdhci_pci_o2_probe,
648 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
649 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
650 .probe_slot = sdhci_pci_o2_probe_slot,
651 .resume = sdhci_pci_o2_resume,
652};
653
654static const struct sdhci_pci_fixes sdhci_jmicron = {
655 .probe = jmicron_probe,
656
657 .probe_slot = jmicron_probe_slot,
658 .remove_slot = jmicron_remove_slot,
659
660 .suspend = jmicron_suspend,
661 .resume = jmicron_resume,
662};
663
664/* SysKonnect CardBus2SDIO extra registers */
665#define SYSKT_CTRL 0x200
666#define SYSKT_RDFIFO_STAT 0x204
667#define SYSKT_WRFIFO_STAT 0x208
668#define SYSKT_POWER_DATA 0x20c
669#define SYSKT_POWER_330 0xef
670#define SYSKT_POWER_300 0xf8
671#define SYSKT_POWER_184 0xcc
672#define SYSKT_POWER_CMD 0x20d
673#define SYSKT_POWER_START (1 << 7)
674#define SYSKT_POWER_STATUS 0x20e
675#define SYSKT_POWER_STATUS_OK (1 << 0)
676#define SYSKT_BOARD_REV 0x210
677#define SYSKT_CHIP_REV 0x211
678#define SYSKT_CONF_DATA 0x212
679#define SYSKT_CONF_DATA_1V8 (1 << 2)
680#define SYSKT_CONF_DATA_2V5 (1 << 1)
681#define SYSKT_CONF_DATA_3V3 (1 << 0)
682
683static int syskt_probe(struct sdhci_pci_chip *chip)
684{
685 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
686 chip->pdev->class &= ~0x0000FF;
687 chip->pdev->class |= PCI_SDHCI_IFDMA;
688 }
689 return 0;
690}
691
692static int syskt_probe_slot(struct sdhci_pci_slot *slot)
693{
694 int tm, ps;
695
696 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
697 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
698 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
699 "board rev %d.%d, chip rev %d.%d\n",
700 board_rev >> 4, board_rev & 0xf,
701 chip_rev >> 4, chip_rev & 0xf);
702 if (chip_rev >= 0x20)
703 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
704
705 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
706 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
707 udelay(50);
708 tm = 10; /* Wait max 1 ms */
709 do {
710 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
711 if (ps & SYSKT_POWER_STATUS_OK)
712 break;
713 udelay(100);
714 } while (--tm);
715 if (!tm) {
716 dev_err(&slot->chip->pdev->dev,
717 "power regulator never stabilized");
718 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
719 return -ENODEV;
720 }
721
722 return 0;
723}
724
725static const struct sdhci_pci_fixes sdhci_syskt = {
726 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
727 .probe = syskt_probe,
728 .probe_slot = syskt_probe_slot,
729};
730
731static int via_probe(struct sdhci_pci_chip *chip)
732{
733 if (chip->pdev->revision == 0x10)
734 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
735
736 return 0;
737}
738
739static const struct sdhci_pci_fixes sdhci_via = {
740 .probe = via_probe,
741};
742
743static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
744{
745 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
746 return 0;
747}
748
749static const struct sdhci_pci_fixes sdhci_rtsx = {
750 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
751 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
752 SDHCI_QUIRK2_BROKEN_DDR50,
753 .probe_slot = rtsx_probe_slot,
754};
755
756/*AMD chipset generation*/
757enum amd_chipset_gen {
758 AMD_CHIPSET_BEFORE_ML,
759 AMD_CHIPSET_CZ,
760 AMD_CHIPSET_NL,
761 AMD_CHIPSET_UNKNOWN,
762};
763
764static int amd_probe(struct sdhci_pci_chip *chip)
765{
766 struct pci_dev *smbus_dev;
767 enum amd_chipset_gen gen;
768
769 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
770 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
771 if (smbus_dev) {
772 gen = AMD_CHIPSET_BEFORE_ML;
773 } else {
774 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
775 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
776 if (smbus_dev) {
777 if (smbus_dev->revision < 0x51)
778 gen = AMD_CHIPSET_CZ;
779 else
780 gen = AMD_CHIPSET_NL;
781 } else {
782 gen = AMD_CHIPSET_UNKNOWN;
783 }
784 }
785
786 if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) {
787 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
788 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
789 }
790
791 return 0;
792}
793
794static const struct sdhci_pci_fixes sdhci_amd = {
795 .probe = amd_probe,
796};
797
798static const struct pci_device_id pci_ids[] = {
799 {
800 .vendor = PCI_VENDOR_ID_RICOH,
801 .device = PCI_DEVICE_ID_RICOH_R5C822,
802 .subvendor = PCI_ANY_ID,
803 .subdevice = PCI_ANY_ID,
804 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
805 },
806
807 {
808 .vendor = PCI_VENDOR_ID_RICOH,
809 .device = 0x843,
810 .subvendor = PCI_ANY_ID,
811 .subdevice = PCI_ANY_ID,
812 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
813 },
814
815 {
816 .vendor = PCI_VENDOR_ID_RICOH,
817 .device = 0xe822,
818 .subvendor = PCI_ANY_ID,
819 .subdevice = PCI_ANY_ID,
820 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
821 },
822
823 {
824 .vendor = PCI_VENDOR_ID_RICOH,
825 .device = 0xe823,
826 .subvendor = PCI_ANY_ID,
827 .subdevice = PCI_ANY_ID,
828 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
829 },
830
831 {
832 .vendor = PCI_VENDOR_ID_ENE,
833 .device = PCI_DEVICE_ID_ENE_CB712_SD,
834 .subvendor = PCI_ANY_ID,
835 .subdevice = PCI_ANY_ID,
836 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
837 },
838
839 {
840 .vendor = PCI_VENDOR_ID_ENE,
841 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
842 .subvendor = PCI_ANY_ID,
843 .subdevice = PCI_ANY_ID,
844 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
845 },
846
847 {
848 .vendor = PCI_VENDOR_ID_ENE,
849 .device = PCI_DEVICE_ID_ENE_CB714_SD,
850 .subvendor = PCI_ANY_ID,
851 .subdevice = PCI_ANY_ID,
852 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
853 },
854
855 {
856 .vendor = PCI_VENDOR_ID_ENE,
857 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
858 .subvendor = PCI_ANY_ID,
859 .subdevice = PCI_ANY_ID,
860 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
861 },
862
863 {
864 .vendor = PCI_VENDOR_ID_MARVELL,
865 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
866 .subvendor = PCI_ANY_ID,
867 .subdevice = PCI_ANY_ID,
868 .driver_data = (kernel_ulong_t)&sdhci_cafe,
869 },
870
871 {
872 .vendor = PCI_VENDOR_ID_JMICRON,
873 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
874 .subvendor = PCI_ANY_ID,
875 .subdevice = PCI_ANY_ID,
876 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
877 },
878
879 {
880 .vendor = PCI_VENDOR_ID_JMICRON,
881 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
882 .subvendor = PCI_ANY_ID,
883 .subdevice = PCI_ANY_ID,
884 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
885 },
886
887 {
888 .vendor = PCI_VENDOR_ID_JMICRON,
889 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
890 .subvendor = PCI_ANY_ID,
891 .subdevice = PCI_ANY_ID,
892 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
893 },
894
895 {
896 .vendor = PCI_VENDOR_ID_JMICRON,
897 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
898 .subvendor = PCI_ANY_ID,
899 .subdevice = PCI_ANY_ID,
900 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
901 },
902
903 {
904 .vendor = PCI_VENDOR_ID_SYSKONNECT,
905 .device = 0x8000,
906 .subvendor = PCI_ANY_ID,
907 .subdevice = PCI_ANY_ID,
908 .driver_data = (kernel_ulong_t)&sdhci_syskt,
909 },
910
911 {
912 .vendor = PCI_VENDOR_ID_VIA,
913 .device = 0x95d0,
914 .subvendor = PCI_ANY_ID,
915 .subdevice = PCI_ANY_ID,
916 .driver_data = (kernel_ulong_t)&sdhci_via,
917 },
918
919 {
920 .vendor = PCI_VENDOR_ID_REALTEK,
921 .device = 0x5250,
922 .subvendor = PCI_ANY_ID,
923 .subdevice = PCI_ANY_ID,
924 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
925 },
926
927 {
928 .vendor = PCI_VENDOR_ID_INTEL,
929 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
930 .subvendor = PCI_ANY_ID,
931 .subdevice = PCI_ANY_ID,
932 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
933 },
934
935 {
936 .vendor = PCI_VENDOR_ID_INTEL,
937 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
938 .subvendor = PCI_ANY_ID,
939 .subdevice = PCI_ANY_ID,
940 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
941 },
942
943 {
944 .vendor = PCI_VENDOR_ID_INTEL,
945 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
946 .subvendor = PCI_ANY_ID,
947 .subdevice = PCI_ANY_ID,
948 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
949 },
950
951 {
952 .vendor = PCI_VENDOR_ID_INTEL,
953 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
954 .subvendor = PCI_ANY_ID,
955 .subdevice = PCI_ANY_ID,
956 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
957 },
958
959 {
960 .vendor = PCI_VENDOR_ID_INTEL,
961 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
962 .subvendor = PCI_ANY_ID,
963 .subdevice = PCI_ANY_ID,
964 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
965 },
966
967 {
968 .vendor = PCI_VENDOR_ID_INTEL,
969 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
970 .subvendor = PCI_ANY_ID,
971 .subdevice = PCI_ANY_ID,
972 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
973 },
974
975 {
976 .vendor = PCI_VENDOR_ID_INTEL,
977 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
978 .subvendor = PCI_ANY_ID,
979 .subdevice = PCI_ANY_ID,
980 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
981 },
982
983 {
984 .vendor = PCI_VENDOR_ID_INTEL,
985 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
986 .subvendor = PCI_ANY_ID,
987 .subdevice = PCI_ANY_ID,
988 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
989 },
990
991 {
992 .vendor = PCI_VENDOR_ID_INTEL,
993 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
994 .subvendor = PCI_ANY_ID,
995 .subdevice = PCI_ANY_ID,
996 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
997 },
998
999 {
1000 .vendor = PCI_VENDOR_ID_INTEL,
1001 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
1002 .subvendor = PCI_ANY_ID,
1003 .subdevice = PCI_ANY_ID,
1004 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
1005 },
1006
1007 {
1008 .vendor = PCI_VENDOR_ID_INTEL,
1009 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
1010 .subvendor = PCI_ANY_ID,
1011 .subdevice = PCI_ANY_ID,
1012 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
1013 },
1014
1015 {
1016 .vendor = PCI_VENDOR_ID_INTEL,
1017 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
1018 .subvendor = PCI_ANY_ID,
1019 .subdevice = PCI_ANY_ID,
1020 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1021 },
1022
1023 {
1024 .vendor = PCI_VENDOR_ID_INTEL,
1025 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
1026 .subvendor = PCI_ANY_ID,
1027 .subdevice = PCI_ANY_ID,
1028 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1029 },
1030
1031 {
1032 .vendor = PCI_VENDOR_ID_INTEL,
1033 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
1034 .subvendor = PCI_ANY_ID,
1035 .subdevice = PCI_ANY_ID,
1036 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1037 },
1038
1039 {
1040 .vendor = PCI_VENDOR_ID_INTEL,
1041 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
1042 .subvendor = PCI_ANY_ID,
1043 .subdevice = PCI_ANY_ID,
1044 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1045 },
1046
1047 {
1048 .vendor = PCI_VENDOR_ID_INTEL,
1049 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
1050 .subvendor = PCI_ANY_ID,
1051 .subdevice = PCI_ANY_ID,
1052 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1053 },
1054
1055 {
1056 .vendor = PCI_VENDOR_ID_INTEL,
1057 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
1058 .subvendor = PCI_ANY_ID,
1059 .subdevice = PCI_ANY_ID,
1060 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1061 },
1062
1063 {
1064 .vendor = PCI_VENDOR_ID_INTEL,
1065 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
1066 .subvendor = PCI_ANY_ID,
1067 .subdevice = PCI_ANY_ID,
1068 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1069 },
1070
1071 {
1072 .vendor = PCI_VENDOR_ID_INTEL,
1073 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
1074 .subvendor = PCI_ANY_ID,
1075 .subdevice = PCI_ANY_ID,
1076 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
1077 },
1078
1079 {
1080 .vendor = PCI_VENDOR_ID_INTEL,
1081 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
1082 .subvendor = PCI_ANY_ID,
1083 .subdevice = PCI_ANY_ID,
1084 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1085 },
1086
1087 {
1088 .vendor = PCI_VENDOR_ID_INTEL,
1089 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
1090 .subvendor = PCI_ANY_ID,
1091 .subdevice = PCI_ANY_ID,
1092 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1093 },
1094
1095 {
1096 .vendor = PCI_VENDOR_ID_INTEL,
1097 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
1098 .subvendor = PCI_ANY_ID,
1099 .subdevice = PCI_ANY_ID,
1100 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1101 },
1102
1103 {
1104 .vendor = PCI_VENDOR_ID_INTEL,
1105 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
1106 .subvendor = PCI_ANY_ID,
1107 .subdevice = PCI_ANY_ID,
1108 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1109 },
1110
1111 {
1112 .vendor = PCI_VENDOR_ID_INTEL,
1113 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC,
1114 .subvendor = PCI_ANY_ID,
1115 .subdevice = PCI_ANY_ID,
1116 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
1117 },
1118
1119 {
1120 .vendor = PCI_VENDOR_ID_INTEL,
1121 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC,
1122 .subvendor = PCI_ANY_ID,
1123 .subdevice = PCI_ANY_ID,
1124 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1125 },
1126
1127 {
1128 .vendor = PCI_VENDOR_ID_INTEL,
1129 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO,
1130 .subvendor = PCI_ANY_ID,
1131 .subdevice = PCI_ANY_ID,
1132 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1133 },
1134
1135 {
1136 .vendor = PCI_VENDOR_ID_INTEL,
1137 .device = PCI_DEVICE_ID_INTEL_SPT_SD,
1138 .subvendor = PCI_ANY_ID,
1139 .subdevice = PCI_ANY_ID,
1140 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1141 },
1142
1143 {
1144 .vendor = PCI_VENDOR_ID_INTEL,
1145 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC,
1146 .subvendor = PCI_ANY_ID,
1147 .subdevice = PCI_ANY_ID,
1148 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1149 },
1150
1151 {
1152 .vendor = PCI_VENDOR_ID_INTEL,
1153 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC,
1154 .subvendor = PCI_ANY_ID,
1155 .subdevice = PCI_ANY_ID,
1156 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1157 },
1158
1159 {
1160 .vendor = PCI_VENDOR_ID_INTEL,
1161 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO,
1162 .subvendor = PCI_ANY_ID,
1163 .subdevice = PCI_ANY_ID,
1164 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1165 },
1166
1167 {
1168 .vendor = PCI_VENDOR_ID_INTEL,
1169 .device = PCI_DEVICE_ID_INTEL_BXT_SD,
1170 .subvendor = PCI_ANY_ID,
1171 .subdevice = PCI_ANY_ID,
1172 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1173 },
1174
1175 {
1176 .vendor = PCI_VENDOR_ID_INTEL,
1177 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC,
1178 .subvendor = PCI_ANY_ID,
1179 .subdevice = PCI_ANY_ID,
1180 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1181 },
1182
1183 {
1184 .vendor = PCI_VENDOR_ID_INTEL,
1185 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO,
1186 .subvendor = PCI_ANY_ID,
1187 .subdevice = PCI_ANY_ID,
1188 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1189 },
1190
1191 {
1192 .vendor = PCI_VENDOR_ID_INTEL,
1193 .device = PCI_DEVICE_ID_INTEL_BXTM_SD,
1194 .subvendor = PCI_ANY_ID,
1195 .subdevice = PCI_ANY_ID,
1196 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1197 },
1198
1199 {
1200 .vendor = PCI_VENDOR_ID_INTEL,
1201 .device = PCI_DEVICE_ID_INTEL_APL_EMMC,
1202 .subvendor = PCI_ANY_ID,
1203 .subdevice = PCI_ANY_ID,
1204 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1205 },
1206
1207 {
1208 .vendor = PCI_VENDOR_ID_INTEL,
1209 .device = PCI_DEVICE_ID_INTEL_APL_SDIO,
1210 .subvendor = PCI_ANY_ID,
1211 .subdevice = PCI_ANY_ID,
1212 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1213 },
1214
1215 {
1216 .vendor = PCI_VENDOR_ID_INTEL,
1217 .device = PCI_DEVICE_ID_INTEL_APL_SD,
1218 .subvendor = PCI_ANY_ID,
1219 .subdevice = PCI_ANY_ID,
1220 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1221 },
1222
1223 {
1224 .vendor = PCI_VENDOR_ID_O2,
1225 .device = PCI_DEVICE_ID_O2_8120,
1226 .subvendor = PCI_ANY_ID,
1227 .subdevice = PCI_ANY_ID,
1228 .driver_data = (kernel_ulong_t)&sdhci_o2,
1229 },
1230
1231 {
1232 .vendor = PCI_VENDOR_ID_O2,
1233 .device = PCI_DEVICE_ID_O2_8220,
1234 .subvendor = PCI_ANY_ID,
1235 .subdevice = PCI_ANY_ID,
1236 .driver_data = (kernel_ulong_t)&sdhci_o2,
1237 },
1238
1239 {
1240 .vendor = PCI_VENDOR_ID_O2,
1241 .device = PCI_DEVICE_ID_O2_8221,
1242 .subvendor = PCI_ANY_ID,
1243 .subdevice = PCI_ANY_ID,
1244 .driver_data = (kernel_ulong_t)&sdhci_o2,
1245 },
1246
1247 {
1248 .vendor = PCI_VENDOR_ID_O2,
1249 .device = PCI_DEVICE_ID_O2_8320,
1250 .subvendor = PCI_ANY_ID,
1251 .subdevice = PCI_ANY_ID,
1252 .driver_data = (kernel_ulong_t)&sdhci_o2,
1253 },
1254
1255 {
1256 .vendor = PCI_VENDOR_ID_O2,
1257 .device = PCI_DEVICE_ID_O2_8321,
1258 .subvendor = PCI_ANY_ID,
1259 .subdevice = PCI_ANY_ID,
1260 .driver_data = (kernel_ulong_t)&sdhci_o2,
1261 },
1262
1263 {
1264 .vendor = PCI_VENDOR_ID_O2,
1265 .device = PCI_DEVICE_ID_O2_FUJIN2,
1266 .subvendor = PCI_ANY_ID,
1267 .subdevice = PCI_ANY_ID,
1268 .driver_data = (kernel_ulong_t)&sdhci_o2,
1269 },
1270
1271 {
1272 .vendor = PCI_VENDOR_ID_O2,
1273 .device = PCI_DEVICE_ID_O2_SDS0,
1274 .subvendor = PCI_ANY_ID,
1275 .subdevice = PCI_ANY_ID,
1276 .driver_data = (kernel_ulong_t)&sdhci_o2,
1277 },
1278
1279 {
1280 .vendor = PCI_VENDOR_ID_O2,
1281 .device = PCI_DEVICE_ID_O2_SDS1,
1282 .subvendor = PCI_ANY_ID,
1283 .subdevice = PCI_ANY_ID,
1284 .driver_data = (kernel_ulong_t)&sdhci_o2,
1285 },
1286
1287 {
1288 .vendor = PCI_VENDOR_ID_O2,
1289 .device = PCI_DEVICE_ID_O2_SEABIRD0,
1290 .subvendor = PCI_ANY_ID,
1291 .subdevice = PCI_ANY_ID,
1292 .driver_data = (kernel_ulong_t)&sdhci_o2,
1293 },
1294
1295 {
1296 .vendor = PCI_VENDOR_ID_O2,
1297 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1298 .subvendor = PCI_ANY_ID,
1299 .subdevice = PCI_ANY_ID,
1300 .driver_data = (kernel_ulong_t)&sdhci_o2,
1301 },
1302 {
1303 .vendor = PCI_VENDOR_ID_AMD,
1304 .device = PCI_ANY_ID,
1305 .class = PCI_CLASS_SYSTEM_SDHCI << 8,
1306 .class_mask = 0xFFFF00,
1307 .subvendor = PCI_ANY_ID,
1308 .subdevice = PCI_ANY_ID,
1309 .driver_data = (kernel_ulong_t)&sdhci_amd,
1310 },
1311 { /* Generic SD host controller */
1312 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1313 },
1314
1315 { /* end: all zeroes */ },
1316};
1317
1318MODULE_DEVICE_TABLE(pci, pci_ids);
1319
1320/*****************************************************************************\
1321 * *
1322 * SDHCI core callbacks *
1323 * *
1324\*****************************************************************************/
1325
1326static int sdhci_pci_enable_dma(struct sdhci_host *host)
1327{
1328 struct sdhci_pci_slot *slot;
1329 struct pci_dev *pdev;
1330
1331 slot = sdhci_priv(host);
1332 pdev = slot->chip->pdev;
1333
1334 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1335 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1336 (host->flags & SDHCI_USE_SDMA)) {
1337 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1338 "doesn't fully claim to support it.\n");
1339 }
1340
1341 pci_set_master(pdev);
1342
1343 return 0;
1344}
1345
1346static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
1347{
1348 u8 ctrl;
1349
1350 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1351
1352 switch (width) {
1353 case MMC_BUS_WIDTH_8:
1354 ctrl |= SDHCI_CTRL_8BITBUS;
1355 ctrl &= ~SDHCI_CTRL_4BITBUS;
1356 break;
1357 case MMC_BUS_WIDTH_4:
1358 ctrl |= SDHCI_CTRL_4BITBUS;
1359 ctrl &= ~SDHCI_CTRL_8BITBUS;
1360 break;
1361 default:
1362 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1363 break;
1364 }
1365
1366 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1367}
1368
1369static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1370{
1371 struct sdhci_pci_slot *slot = sdhci_priv(host);
1372 int rst_n_gpio = slot->rst_n_gpio;
1373
1374 if (!gpio_is_valid(rst_n_gpio))
1375 return;
1376 gpio_set_value_cansleep(rst_n_gpio, 0);
1377 /* For eMMC, minimum is 1us but give it 10us for good measure */
1378 udelay(10);
1379 gpio_set_value_cansleep(rst_n_gpio, 1);
1380 /* For eMMC, minimum is 200us but give it 300us for good measure */
1381 usleep_range(300, 1000);
1382}
1383
1384static void sdhci_pci_hw_reset(struct sdhci_host *host)
1385{
1386 struct sdhci_pci_slot *slot = sdhci_priv(host);
1387
1388 if (slot->hw_reset)
1389 slot->hw_reset(host);
1390}
1391
1392static int sdhci_pci_select_drive_strength(struct sdhci_host *host,
1393 struct mmc_card *card,
1394 unsigned int max_dtr, int host_drv,
1395 int card_drv, int *drv_type)
1396{
1397 struct sdhci_pci_slot *slot = sdhci_priv(host);
1398
1399 if (!slot->select_drive_strength)
1400 return 0;
1401
1402 return slot->select_drive_strength(host, card, max_dtr, host_drv,
1403 card_drv, drv_type);
1404}
1405
1406static const struct sdhci_ops sdhci_pci_ops = {
1407 .set_clock = sdhci_set_clock,
1408 .enable_dma = sdhci_pci_enable_dma,
1409 .set_bus_width = sdhci_pci_set_bus_width,
1410 .reset = sdhci_reset,
1411 .set_uhs_signaling = sdhci_set_uhs_signaling,
1412 .hw_reset = sdhci_pci_hw_reset,
1413 .select_drive_strength = sdhci_pci_select_drive_strength,
1414};
1415
1416/*****************************************************************************\
1417 * *
1418 * Suspend/resume *
1419 * *
1420\*****************************************************************************/
1421
1422#ifdef CONFIG_PM
1423
1424static int sdhci_pci_suspend(struct device *dev)
1425{
1426 struct pci_dev *pdev = to_pci_dev(dev);
1427 struct sdhci_pci_chip *chip;
1428 struct sdhci_pci_slot *slot;
1429 mmc_pm_flag_t slot_pm_flags;
1430 mmc_pm_flag_t pm_flags = 0;
1431 int i, ret;
1432
1433 chip = pci_get_drvdata(pdev);
1434 if (!chip)
1435 return 0;
1436
1437 for (i = 0; i < chip->num_slots; i++) {
1438 slot = chip->slots[i];
1439 if (!slot)
1440 continue;
1441
1442 ret = sdhci_suspend_host(slot->host);
1443
1444 if (ret)
1445 goto err_pci_suspend;
1446
1447 slot_pm_flags = slot->host->mmc->pm_flags;
1448 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1449 sdhci_enable_irq_wakeups(slot->host);
1450
1451 pm_flags |= slot_pm_flags;
1452 }
1453
1454 if (chip->fixes && chip->fixes->suspend) {
1455 ret = chip->fixes->suspend(chip);
1456 if (ret)
1457 goto err_pci_suspend;
1458 }
1459
1460 if (pm_flags & MMC_PM_KEEP_POWER) {
1461 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1462 device_init_wakeup(dev, true);
1463 else
1464 device_init_wakeup(dev, false);
1465 } else
1466 device_init_wakeup(dev, false);
1467
1468 return 0;
1469
1470err_pci_suspend:
1471 while (--i >= 0)
1472 sdhci_resume_host(chip->slots[i]->host);
1473 return ret;
1474}
1475
1476static int sdhci_pci_resume(struct device *dev)
1477{
1478 struct pci_dev *pdev = to_pci_dev(dev);
1479 struct sdhci_pci_chip *chip;
1480 struct sdhci_pci_slot *slot;
1481 int i, ret;
1482
1483 chip = pci_get_drvdata(pdev);
1484 if (!chip)
1485 return 0;
1486
1487 if (chip->fixes && chip->fixes->resume) {
1488 ret = chip->fixes->resume(chip);
1489 if (ret)
1490 return ret;
1491 }
1492
1493 for (i = 0; i < chip->num_slots; i++) {
1494 slot = chip->slots[i];
1495 if (!slot)
1496 continue;
1497
1498 ret = sdhci_resume_host(slot->host);
1499 if (ret)
1500 return ret;
1501 }
1502
1503 return 0;
1504}
1505
1506static int sdhci_pci_runtime_suspend(struct device *dev)
1507{
1508 struct pci_dev *pdev = to_pci_dev(dev);
1509 struct sdhci_pci_chip *chip;
1510 struct sdhci_pci_slot *slot;
1511 int i, ret;
1512
1513 chip = pci_get_drvdata(pdev);
1514 if (!chip)
1515 return 0;
1516
1517 for (i = 0; i < chip->num_slots; i++) {
1518 slot = chip->slots[i];
1519 if (!slot)
1520 continue;
1521
1522 ret = sdhci_runtime_suspend_host(slot->host);
1523
1524 if (ret)
1525 goto err_pci_runtime_suspend;
1526 }
1527
1528 if (chip->fixes && chip->fixes->suspend) {
1529 ret = chip->fixes->suspend(chip);
1530 if (ret)
1531 goto err_pci_runtime_suspend;
1532 }
1533
1534 return 0;
1535
1536err_pci_runtime_suspend:
1537 while (--i >= 0)
1538 sdhci_runtime_resume_host(chip->slots[i]->host);
1539 return ret;
1540}
1541
1542static int sdhci_pci_runtime_resume(struct device *dev)
1543{
1544 struct pci_dev *pdev = to_pci_dev(dev);
1545 struct sdhci_pci_chip *chip;
1546 struct sdhci_pci_slot *slot;
1547 int i, ret;
1548
1549 chip = pci_get_drvdata(pdev);
1550 if (!chip)
1551 return 0;
1552
1553 if (chip->fixes && chip->fixes->resume) {
1554 ret = chip->fixes->resume(chip);
1555 if (ret)
1556 return ret;
1557 }
1558
1559 for (i = 0; i < chip->num_slots; i++) {
1560 slot = chip->slots[i];
1561 if (!slot)
1562 continue;
1563
1564 ret = sdhci_runtime_resume_host(slot->host);
1565 if (ret)
1566 return ret;
1567 }
1568
1569 return 0;
1570}
1571
1572#else /* CONFIG_PM */
1573
1574#define sdhci_pci_suspend NULL
1575#define sdhci_pci_resume NULL
1576
1577#endif /* CONFIG_PM */
1578
1579static const struct dev_pm_ops sdhci_pci_pm_ops = {
1580 .suspend = sdhci_pci_suspend,
1581 .resume = sdhci_pci_resume,
1582 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1583 sdhci_pci_runtime_resume, NULL)
1584};
1585
1586/*****************************************************************************\
1587 * *
1588 * Device probing/removal *
1589 * *
1590\*****************************************************************************/
1591
1592static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1593 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1594 int slotno)
1595{
1596 struct sdhci_pci_slot *slot;
1597 struct sdhci_host *host;
1598 int ret, bar = first_bar + slotno;
1599
1600 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1601 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1602 return ERR_PTR(-ENODEV);
1603 }
1604
1605 if (pci_resource_len(pdev, bar) < 0x100) {
1606 dev_err(&pdev->dev, "Invalid iomem size. You may "
1607 "experience problems.\n");
1608 }
1609
1610 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1611 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1612 return ERR_PTR(-ENODEV);
1613 }
1614
1615 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1616 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1617 return ERR_PTR(-ENODEV);
1618 }
1619
1620 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1621 if (IS_ERR(host)) {
1622 dev_err(&pdev->dev, "cannot allocate host\n");
1623 return ERR_CAST(host);
1624 }
1625
1626 slot = sdhci_priv(host);
1627
1628 slot->chip = chip;
1629 slot->host = host;
1630 slot->pci_bar = bar;
1631 slot->rst_n_gpio = -EINVAL;
1632 slot->cd_gpio = -EINVAL;
1633 slot->cd_idx = -1;
1634
1635 /* Retrieve platform data if there is any */
1636 if (*sdhci_pci_get_data)
1637 slot->data = sdhci_pci_get_data(pdev, slotno);
1638
1639 if (slot->data) {
1640 if (slot->data->setup) {
1641 ret = slot->data->setup(slot->data);
1642 if (ret) {
1643 dev_err(&pdev->dev, "platform setup failed\n");
1644 goto free;
1645 }
1646 }
1647 slot->rst_n_gpio = slot->data->rst_n_gpio;
1648 slot->cd_gpio = slot->data->cd_gpio;
1649 }
1650
1651 host->hw_name = "PCI";
1652 host->ops = &sdhci_pci_ops;
1653 host->quirks = chip->quirks;
1654 host->quirks2 = chip->quirks2;
1655
1656 host->irq = pdev->irq;
1657
1658 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1659 if (ret) {
1660 dev_err(&pdev->dev, "cannot request region\n");
1661 goto cleanup;
1662 }
1663
1664 host->ioaddr = pci_ioremap_bar(pdev, bar);
1665 if (!host->ioaddr) {
1666 dev_err(&pdev->dev, "failed to remap registers\n");
1667 ret = -ENOMEM;
1668 goto release;
1669 }
1670
1671 if (chip->fixes && chip->fixes->probe_slot) {
1672 ret = chip->fixes->probe_slot(slot);
1673 if (ret)
1674 goto unmap;
1675 }
1676
1677 if (gpio_is_valid(slot->rst_n_gpio)) {
1678 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1679 gpio_direction_output(slot->rst_n_gpio, 1);
1680 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1681 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1682 } else {
1683 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1684 slot->rst_n_gpio = -EINVAL;
1685 }
1686 }
1687
1688 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1689 host->mmc->slotno = slotno;
1690 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1691
1692 if (slot->cd_idx >= 0 &&
1693 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1694 slot->cd_override_level, 0, NULL)) {
1695 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1696 slot->cd_idx = -1;
1697 }
1698
1699 ret = sdhci_add_host(host);
1700 if (ret)
1701 goto remove;
1702
1703 sdhci_pci_add_own_cd(slot);
1704
1705 /*
1706 * Check if the chip needs a separate GPIO for card detect to wake up
1707 * from runtime suspend. If it is not there, don't allow runtime PM.
1708 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1709 */
1710 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1711 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1712 chip->allow_runtime_pm = false;
1713
1714 return slot;
1715
1716remove:
1717 if (gpio_is_valid(slot->rst_n_gpio))
1718 gpio_free(slot->rst_n_gpio);
1719
1720 if (chip->fixes && chip->fixes->remove_slot)
1721 chip->fixes->remove_slot(slot, 0);
1722
1723unmap:
1724 iounmap(host->ioaddr);
1725
1726release:
1727 pci_release_region(pdev, bar);
1728
1729cleanup:
1730 if (slot->data && slot->data->cleanup)
1731 slot->data->cleanup(slot->data);
1732
1733free:
1734 sdhci_free_host(host);
1735
1736 return ERR_PTR(ret);
1737}
1738
1739static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1740{
1741 int dead;
1742 u32 scratch;
1743
1744 sdhci_pci_remove_own_cd(slot);
1745
1746 dead = 0;
1747 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1748 if (scratch == (u32)-1)
1749 dead = 1;
1750
1751 sdhci_remove_host(slot->host, dead);
1752
1753 if (gpio_is_valid(slot->rst_n_gpio))
1754 gpio_free(slot->rst_n_gpio);
1755
1756 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1757 slot->chip->fixes->remove_slot(slot, dead);
1758
1759 if (slot->data && slot->data->cleanup)
1760 slot->data->cleanup(slot->data);
1761
1762 pci_release_region(slot->chip->pdev, slot->pci_bar);
1763
1764 sdhci_free_host(slot->host);
1765}
1766
1767static void sdhci_pci_runtime_pm_allow(struct device *dev)
1768{
1769 pm_runtime_put_noidle(dev);
1770 pm_runtime_allow(dev);
1771 pm_runtime_set_autosuspend_delay(dev, 50);
1772 pm_runtime_use_autosuspend(dev);
1773 pm_suspend_ignore_children(dev, 1);
1774}
1775
1776static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1777{
1778 pm_runtime_forbid(dev);
1779 pm_runtime_get_noresume(dev);
1780}
1781
1782static int sdhci_pci_probe(struct pci_dev *pdev,
1783 const struct pci_device_id *ent)
1784{
1785 struct sdhci_pci_chip *chip;
1786 struct sdhci_pci_slot *slot;
1787
1788 u8 slots, first_bar;
1789 int ret, i;
1790
1791 BUG_ON(pdev == NULL);
1792 BUG_ON(ent == NULL);
1793
1794 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1795 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1796
1797 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1798 if (ret)
1799 return ret;
1800
1801 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1802 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1803 if (slots == 0)
1804 return -ENODEV;
1805
1806 BUG_ON(slots > MAX_SLOTS);
1807
1808 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1809 if (ret)
1810 return ret;
1811
1812 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1813
1814 if (first_bar > 5) {
1815 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1816 return -ENODEV;
1817 }
1818
1819 ret = pci_enable_device(pdev);
1820 if (ret)
1821 return ret;
1822
1823 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1824 if (!chip) {
1825 ret = -ENOMEM;
1826 goto err;
1827 }
1828
1829 chip->pdev = pdev;
1830 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1831 if (chip->fixes) {
1832 chip->quirks = chip->fixes->quirks;
1833 chip->quirks2 = chip->fixes->quirks2;
1834 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1835 }
1836 chip->num_slots = slots;
1837
1838 pci_set_drvdata(pdev, chip);
1839
1840 if (chip->fixes && chip->fixes->probe) {
1841 ret = chip->fixes->probe(chip);
1842 if (ret)
1843 goto free;
1844 }
1845
1846 slots = chip->num_slots; /* Quirk may have changed this */
1847
1848 for (i = 0; i < slots; i++) {
1849 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1850 if (IS_ERR(slot)) {
1851 for (i--; i >= 0; i--)
1852 sdhci_pci_remove_slot(chip->slots[i]);
1853 ret = PTR_ERR(slot);
1854 goto free;
1855 }
1856
1857 chip->slots[i] = slot;
1858 }
1859
1860 if (chip->allow_runtime_pm)
1861 sdhci_pci_runtime_pm_allow(&pdev->dev);
1862
1863 return 0;
1864
1865free:
1866 pci_set_drvdata(pdev, NULL);
1867 kfree(chip);
1868
1869err:
1870 pci_disable_device(pdev);
1871 return ret;
1872}
1873
1874static void sdhci_pci_remove(struct pci_dev *pdev)
1875{
1876 int i;
1877 struct sdhci_pci_chip *chip;
1878
1879 chip = pci_get_drvdata(pdev);
1880
1881 if (chip) {
1882 if (chip->allow_runtime_pm)
1883 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1884
1885 for (i = 0; i < chip->num_slots; i++)
1886 sdhci_pci_remove_slot(chip->slots[i]);
1887
1888 pci_set_drvdata(pdev, NULL);
1889 kfree(chip);
1890 }
1891
1892 pci_disable_device(pdev);
1893}
1894
1895static struct pci_driver sdhci_driver = {
1896 .name = "sdhci-pci",
1897 .id_table = pci_ids,
1898 .probe = sdhci_pci_probe,
1899 .remove = sdhci_pci_remove,
1900 .driver = {
1901 .pm = &sdhci_pci_pm_ops
1902 },
1903};
1904
1905module_pci_driver(sdhci_driver);
1906
1907MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1908MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1909MODULE_LICENSE("GPL");