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1/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <linux/init.h>
17#include <linux/slab.h>
18#include <linux/module.h>
19#include <linux/string.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmaengine.h>
24#include <linux/amba/bus.h>
25#include <linux/amba/pl330.h>
26#include <linux/scatterlist.h>
27#include <linux/of.h>
28#include <linux/of_dma.h>
29#include <linux/err.h>
30
31#include "dmaengine.h"
32#define PL330_MAX_CHAN 8
33#define PL330_MAX_IRQS 32
34#define PL330_MAX_PERI 32
35
36enum pl330_srccachectrl {
37 SCCTRL0, /* Noncacheable and nonbufferable */
38 SCCTRL1, /* Bufferable only */
39 SCCTRL2, /* Cacheable, but do not allocate */
40 SCCTRL3, /* Cacheable and bufferable, but do not allocate */
41 SINVALID1,
42 SINVALID2,
43 SCCTRL6, /* Cacheable write-through, allocate on reads only */
44 SCCTRL7, /* Cacheable write-back, allocate on reads only */
45};
46
47enum pl330_dstcachectrl {
48 DCCTRL0, /* Noncacheable and nonbufferable */
49 DCCTRL1, /* Bufferable only */
50 DCCTRL2, /* Cacheable, but do not allocate */
51 DCCTRL3, /* Cacheable and bufferable, but do not allocate */
52 DINVALID1, /* AWCACHE = 0x1000 */
53 DINVALID2,
54 DCCTRL6, /* Cacheable write-through, allocate on writes only */
55 DCCTRL7, /* Cacheable write-back, allocate on writes only */
56};
57
58enum pl330_byteswap {
59 SWAP_NO,
60 SWAP_2,
61 SWAP_4,
62 SWAP_8,
63 SWAP_16,
64};
65
66enum pl330_reqtype {
67 MEMTOMEM,
68 MEMTODEV,
69 DEVTOMEM,
70 DEVTODEV,
71};
72
73/* Register and Bit field Definitions */
74#define DS 0x0
75#define DS_ST_STOP 0x0
76#define DS_ST_EXEC 0x1
77#define DS_ST_CMISS 0x2
78#define DS_ST_UPDTPC 0x3
79#define DS_ST_WFE 0x4
80#define DS_ST_ATBRR 0x5
81#define DS_ST_QBUSY 0x6
82#define DS_ST_WFP 0x7
83#define DS_ST_KILL 0x8
84#define DS_ST_CMPLT 0x9
85#define DS_ST_FLTCMP 0xe
86#define DS_ST_FAULT 0xf
87
88#define DPC 0x4
89#define INTEN 0x20
90#define ES 0x24
91#define INTSTATUS 0x28
92#define INTCLR 0x2c
93#define FSM 0x30
94#define FSC 0x34
95#define FTM 0x38
96
97#define _FTC 0x40
98#define FTC(n) (_FTC + (n)*0x4)
99
100#define _CS 0x100
101#define CS(n) (_CS + (n)*0x8)
102#define CS_CNS (1 << 21)
103
104#define _CPC 0x104
105#define CPC(n) (_CPC + (n)*0x8)
106
107#define _SA 0x400
108#define SA(n) (_SA + (n)*0x20)
109
110#define _DA 0x404
111#define DA(n) (_DA + (n)*0x20)
112
113#define _CC 0x408
114#define CC(n) (_CC + (n)*0x20)
115
116#define CC_SRCINC (1 << 0)
117#define CC_DSTINC (1 << 14)
118#define CC_SRCPRI (1 << 8)
119#define CC_DSTPRI (1 << 22)
120#define CC_SRCNS (1 << 9)
121#define CC_DSTNS (1 << 23)
122#define CC_SRCIA (1 << 10)
123#define CC_DSTIA (1 << 24)
124#define CC_SRCBRSTLEN_SHFT 4
125#define CC_DSTBRSTLEN_SHFT 18
126#define CC_SRCBRSTSIZE_SHFT 1
127#define CC_DSTBRSTSIZE_SHFT 15
128#define CC_SRCCCTRL_SHFT 11
129#define CC_SRCCCTRL_MASK 0x7
130#define CC_DSTCCTRL_SHFT 25
131#define CC_DRCCCTRL_MASK 0x7
132#define CC_SWAP_SHFT 28
133
134#define _LC0 0x40c
135#define LC0(n) (_LC0 + (n)*0x20)
136
137#define _LC1 0x410
138#define LC1(n) (_LC1 + (n)*0x20)
139
140#define DBGSTATUS 0xd00
141#define DBG_BUSY (1 << 0)
142
143#define DBGCMD 0xd04
144#define DBGINST0 0xd08
145#define DBGINST1 0xd0c
146
147#define CR0 0xe00
148#define CR1 0xe04
149#define CR2 0xe08
150#define CR3 0xe0c
151#define CR4 0xe10
152#define CRD 0xe14
153
154#define PERIPH_ID 0xfe0
155#define PERIPH_REV_SHIFT 20
156#define PERIPH_REV_MASK 0xf
157#define PERIPH_REV_R0P0 0
158#define PERIPH_REV_R1P0 1
159#define PERIPH_REV_R1P1 2
160
161#define CR0_PERIPH_REQ_SET (1 << 0)
162#define CR0_BOOT_EN_SET (1 << 1)
163#define CR0_BOOT_MAN_NS (1 << 2)
164#define CR0_NUM_CHANS_SHIFT 4
165#define CR0_NUM_CHANS_MASK 0x7
166#define CR0_NUM_PERIPH_SHIFT 12
167#define CR0_NUM_PERIPH_MASK 0x1f
168#define CR0_NUM_EVENTS_SHIFT 17
169#define CR0_NUM_EVENTS_MASK 0x1f
170
171#define CR1_ICACHE_LEN_SHIFT 0
172#define CR1_ICACHE_LEN_MASK 0x7
173#define CR1_NUM_ICACHELINES_SHIFT 4
174#define CR1_NUM_ICACHELINES_MASK 0xf
175
176#define CRD_DATA_WIDTH_SHIFT 0
177#define CRD_DATA_WIDTH_MASK 0x7
178#define CRD_WR_CAP_SHIFT 4
179#define CRD_WR_CAP_MASK 0x7
180#define CRD_WR_Q_DEP_SHIFT 8
181#define CRD_WR_Q_DEP_MASK 0xf
182#define CRD_RD_CAP_SHIFT 12
183#define CRD_RD_CAP_MASK 0x7
184#define CRD_RD_Q_DEP_SHIFT 16
185#define CRD_RD_Q_DEP_MASK 0xf
186#define CRD_DATA_BUFF_SHIFT 20
187#define CRD_DATA_BUFF_MASK 0x3ff
188
189#define PART 0x330
190#define DESIGNER 0x41
191#define REVISION 0x0
192#define INTEG_CFG 0x0
193#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
194
195#define PL330_STATE_STOPPED (1 << 0)
196#define PL330_STATE_EXECUTING (1 << 1)
197#define PL330_STATE_WFE (1 << 2)
198#define PL330_STATE_FAULTING (1 << 3)
199#define PL330_STATE_COMPLETING (1 << 4)
200#define PL330_STATE_WFP (1 << 5)
201#define PL330_STATE_KILLING (1 << 6)
202#define PL330_STATE_FAULT_COMPLETING (1 << 7)
203#define PL330_STATE_CACHEMISS (1 << 8)
204#define PL330_STATE_UPDTPC (1 << 9)
205#define PL330_STATE_ATBARRIER (1 << 10)
206#define PL330_STATE_QUEUEBUSY (1 << 11)
207#define PL330_STATE_INVALID (1 << 15)
208
209#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
210 | PL330_STATE_WFE | PL330_STATE_FAULTING)
211
212#define CMD_DMAADDH 0x54
213#define CMD_DMAEND 0x00
214#define CMD_DMAFLUSHP 0x35
215#define CMD_DMAGO 0xa0
216#define CMD_DMALD 0x04
217#define CMD_DMALDP 0x25
218#define CMD_DMALP 0x20
219#define CMD_DMALPEND 0x28
220#define CMD_DMAKILL 0x01
221#define CMD_DMAMOV 0xbc
222#define CMD_DMANOP 0x18
223#define CMD_DMARMB 0x12
224#define CMD_DMASEV 0x34
225#define CMD_DMAST 0x08
226#define CMD_DMASTP 0x29
227#define CMD_DMASTZ 0x0c
228#define CMD_DMAWFE 0x36
229#define CMD_DMAWFP 0x30
230#define CMD_DMAWMB 0x13
231
232#define SZ_DMAADDH 3
233#define SZ_DMAEND 1
234#define SZ_DMAFLUSHP 2
235#define SZ_DMALD 1
236#define SZ_DMALDP 2
237#define SZ_DMALP 2
238#define SZ_DMALPEND 2
239#define SZ_DMAKILL 1
240#define SZ_DMAMOV 6
241#define SZ_DMANOP 1
242#define SZ_DMARMB 1
243#define SZ_DMASEV 2
244#define SZ_DMAST 1
245#define SZ_DMASTP 2
246#define SZ_DMASTZ 1
247#define SZ_DMAWFE 2
248#define SZ_DMAWFP 2
249#define SZ_DMAWMB 1
250#define SZ_DMAGO 6
251
252#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
253#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
254
255#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
256#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
257
258/*
259 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
260 * at 1byte/burst for P<->M and M<->M respectively.
261 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
262 * should be enough for P<->M and M<->M respectively.
263 */
264#define MCODE_BUFF_PER_REQ 256
265
266/* If the _pl330_req is available to the client */
267#define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND)
268
269/* Use this _only_ to wait on transient states */
270#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
271
272#ifdef PL330_DEBUG_MCGEN
273static unsigned cmd_line;
274#define PL330_DBGCMD_DUMP(off, x...) do { \
275 printk("%x:", cmd_line); \
276 printk(x); \
277 cmd_line += off; \
278 } while (0)
279#define PL330_DBGMC_START(addr) (cmd_line = addr)
280#else
281#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
282#define PL330_DBGMC_START(addr) do {} while (0)
283#endif
284
285/* The number of default descriptors */
286
287#define NR_DEFAULT_DESC 16
288
289/* Populated by the PL330 core driver for DMA API driver's info */
290struct pl330_config {
291 u32 periph_id;
292#define DMAC_MODE_NS (1 << 0)
293 unsigned int mode;
294 unsigned int data_bus_width:10; /* In number of bits */
295 unsigned int data_buf_dep:10;
296 unsigned int num_chan:4;
297 unsigned int num_peri:6;
298 u32 peri_ns;
299 unsigned int num_events:6;
300 u32 irq_ns;
301};
302
303/* Handle to the DMAC provided to the PL330 core */
304struct pl330_info {
305 /* Owning device */
306 struct device *dev;
307 /* Size of MicroCode buffers for each channel. */
308 unsigned mcbufsz;
309 /* ioremap'ed address of PL330 registers. */
310 void __iomem *base;
311 /* Client can freely use it. */
312 void *client_data;
313 /* PL330 core data, Client must not touch it. */
314 void *pl330_data;
315 /* Populated by the PL330 core driver during pl330_add */
316 struct pl330_config pcfg;
317 /*
318 * If the DMAC has some reset mechanism, then the
319 * client may want to provide pointer to the method.
320 */
321 void (*dmac_reset)(struct pl330_info *pi);
322};
323
324/**
325 * Request Configuration.
326 * The PL330 core does not modify this and uses the last
327 * working configuration if the request doesn't provide any.
328 *
329 * The Client may want to provide this info only for the
330 * first request and a request with new settings.
331 */
332struct pl330_reqcfg {
333 /* Address Incrementing */
334 unsigned dst_inc:1;
335 unsigned src_inc:1;
336
337 /*
338 * For now, the SRC & DST protection levels
339 * and burst size/length are assumed same.
340 */
341 bool nonsecure;
342 bool privileged;
343 bool insnaccess;
344 unsigned brst_len:5;
345 unsigned brst_size:3; /* in power of 2 */
346
347 enum pl330_dstcachectrl dcctl;
348 enum pl330_srccachectrl scctl;
349 enum pl330_byteswap swap;
350 struct pl330_config *pcfg;
351};
352
353/*
354 * One cycle of DMAC operation.
355 * There may be more than one xfer in a request.
356 */
357struct pl330_xfer {
358 u32 src_addr;
359 u32 dst_addr;
360 /* Size to xfer */
361 u32 bytes;
362 /*
363 * Pointer to next xfer in the list.
364 * The last xfer in the req must point to NULL.
365 */
366 struct pl330_xfer *next;
367};
368
369/* The xfer callbacks are made with one of these arguments. */
370enum pl330_op_err {
371 /* The all xfers in the request were success. */
372 PL330_ERR_NONE,
373 /* If req aborted due to global error. */
374 PL330_ERR_ABORT,
375 /* If req failed due to problem with Channel. */
376 PL330_ERR_FAIL,
377};
378
379/* A request defining Scatter-Gather List ending with NULL xfer. */
380struct pl330_req {
381 enum pl330_reqtype rqtype;
382 /* Index of peripheral for the xfer. */
383 unsigned peri:5;
384 /* Unique token for this xfer, set by the client. */
385 void *token;
386 /* Callback to be called after xfer. */
387 void (*xfer_cb)(void *token, enum pl330_op_err err);
388 /* If NULL, req will be done at last set parameters. */
389 struct pl330_reqcfg *cfg;
390 /* Pointer to first xfer in the request. */
391 struct pl330_xfer *x;
392 /* Hook to attach to DMAC's list of reqs with due callback */
393 struct list_head rqd;
394};
395
396/*
397 * To know the status of the channel and DMAC, the client
398 * provides a pointer to this structure. The PL330 core
399 * fills it with current information.
400 */
401struct pl330_chanstatus {
402 /*
403 * If the DMAC engine halted due to some error,
404 * the client should remove-add DMAC.
405 */
406 bool dmac_halted;
407 /*
408 * If channel is halted due to some error,
409 * the client should ABORT/FLUSH and START the channel.
410 */
411 bool faulting;
412 /* Location of last load */
413 u32 src_addr;
414 /* Location of last store */
415 u32 dst_addr;
416 /*
417 * Pointer to the currently active req, NULL if channel is
418 * inactive, even though the requests may be present.
419 */
420 struct pl330_req *top_req;
421 /* Pointer to req waiting second in the queue if any. */
422 struct pl330_req *wait_req;
423};
424
425enum pl330_chan_op {
426 /* Start the channel */
427 PL330_OP_START,
428 /* Abort the active xfer */
429 PL330_OP_ABORT,
430 /* Stop xfer and flush queue */
431 PL330_OP_FLUSH,
432};
433
434struct _xfer_spec {
435 u32 ccr;
436 struct pl330_req *r;
437 struct pl330_xfer *x;
438};
439
440enum dmamov_dst {
441 SAR = 0,
442 CCR,
443 DAR,
444};
445
446enum pl330_dst {
447 SRC = 0,
448 DST,
449};
450
451enum pl330_cond {
452 SINGLE,
453 BURST,
454 ALWAYS,
455};
456
457struct _pl330_req {
458 u32 mc_bus;
459 void *mc_cpu;
460 /* Number of bytes taken to setup MC for the req */
461 u32 mc_len;
462 struct pl330_req *r;
463};
464
465/* ToBeDone for tasklet */
466struct _pl330_tbd {
467 bool reset_dmac;
468 bool reset_mngr;
469 u8 reset_chan;
470};
471
472/* A DMAC Thread */
473struct pl330_thread {
474 u8 id;
475 int ev;
476 /* If the channel is not yet acquired by any client */
477 bool free;
478 /* Parent DMAC */
479 struct pl330_dmac *dmac;
480 /* Only two at a time */
481 struct _pl330_req req[2];
482 /* Index of the last enqueued request */
483 unsigned lstenq;
484 /* Index of the last submitted request or -1 if the DMA is stopped */
485 int req_running;
486};
487
488enum pl330_dmac_state {
489 UNINIT,
490 INIT,
491 DYING,
492};
493
494/* A DMAC */
495struct pl330_dmac {
496 spinlock_t lock;
497 /* Holds list of reqs with due callbacks */
498 struct list_head req_done;
499 /* Pointer to platform specific stuff */
500 struct pl330_info *pinfo;
501 /* Maximum possible events/irqs */
502 int events[32];
503 /* BUS address of MicroCode buffer */
504 dma_addr_t mcode_bus;
505 /* CPU address of MicroCode buffer */
506 void *mcode_cpu;
507 /* List of all Channel threads */
508 struct pl330_thread *channels;
509 /* Pointer to the MANAGER thread */
510 struct pl330_thread *manager;
511 /* To handle bad news in interrupt */
512 struct tasklet_struct tasks;
513 struct _pl330_tbd dmac_tbd;
514 /* State of DMAC operation */
515 enum pl330_dmac_state state;
516};
517
518enum desc_status {
519 /* In the DMAC pool */
520 FREE,
521 /*
522 * Allocated to some channel during prep_xxx
523 * Also may be sitting on the work_list.
524 */
525 PREP,
526 /*
527 * Sitting on the work_list and already submitted
528 * to the PL330 core. Not more than two descriptors
529 * of a channel can be BUSY at any time.
530 */
531 BUSY,
532 /*
533 * Sitting on the channel work_list but xfer done
534 * by PL330 core
535 */
536 DONE,
537};
538
539struct dma_pl330_chan {
540 /* Schedule desc completion */
541 struct tasklet_struct task;
542
543 /* DMA-Engine Channel */
544 struct dma_chan chan;
545
546 /* List of submitted descriptors */
547 struct list_head submitted_list;
548 /* List of issued descriptors */
549 struct list_head work_list;
550 /* List of completed descriptors */
551 struct list_head completed_list;
552
553 /* Pointer to the DMAC that manages this channel,
554 * NULL if the channel is available to be acquired.
555 * As the parent, this DMAC also provides descriptors
556 * to the channel.
557 */
558 struct dma_pl330_dmac *dmac;
559
560 /* To protect channel manipulation */
561 spinlock_t lock;
562
563 /* Token of a hardware channel thread of PL330 DMAC
564 * NULL if the channel is available to be acquired.
565 */
566 void *pl330_chid;
567
568 /* For D-to-M and M-to-D channels */
569 int burst_sz; /* the peripheral fifo width */
570 int burst_len; /* the number of burst */
571 dma_addr_t fifo_addr;
572
573 /* for cyclic capability */
574 bool cyclic;
575};
576
577struct dma_pl330_dmac {
578 struct pl330_info pif;
579
580 /* DMA-Engine Device */
581 struct dma_device ddma;
582
583 /* Holds info about sg limitations */
584 struct device_dma_parameters dma_parms;
585
586 /* Pool of descriptors available for the DMAC's channels */
587 struct list_head desc_pool;
588 /* To protect desc_pool manipulation */
589 spinlock_t pool_lock;
590
591 /* Peripheral channels connected to this DMAC */
592 unsigned int num_peripherals;
593 struct dma_pl330_chan *peripherals; /* keep at end */
594};
595
596struct dma_pl330_desc {
597 /* To attach to a queue as child */
598 struct list_head node;
599
600 /* Descriptor for the DMA Engine API */
601 struct dma_async_tx_descriptor txd;
602
603 /* Xfer for PL330 core */
604 struct pl330_xfer px;
605
606 struct pl330_reqcfg rqcfg;
607 struct pl330_req req;
608
609 enum desc_status status;
610
611 /* The channel which currently holds this desc */
612 struct dma_pl330_chan *pchan;
613};
614
615static inline void _callback(struct pl330_req *r, enum pl330_op_err err)
616{
617 if (r && r->xfer_cb)
618 r->xfer_cb(r->token, err);
619}
620
621static inline bool _queue_empty(struct pl330_thread *thrd)
622{
623 return (IS_FREE(&thrd->req[0]) && IS_FREE(&thrd->req[1]))
624 ? true : false;
625}
626
627static inline bool _queue_full(struct pl330_thread *thrd)
628{
629 return (IS_FREE(&thrd->req[0]) || IS_FREE(&thrd->req[1]))
630 ? false : true;
631}
632
633static inline bool is_manager(struct pl330_thread *thrd)
634{
635 struct pl330_dmac *pl330 = thrd->dmac;
636
637 /* MANAGER is indexed at the end */
638 if (thrd->id == pl330->pinfo->pcfg.num_chan)
639 return true;
640 else
641 return false;
642}
643
644/* If manager of the thread is in Non-Secure mode */
645static inline bool _manager_ns(struct pl330_thread *thrd)
646{
647 struct pl330_dmac *pl330 = thrd->dmac;
648
649 return (pl330->pinfo->pcfg.mode & DMAC_MODE_NS) ? true : false;
650}
651
652static inline u32 get_revision(u32 periph_id)
653{
654 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
655}
656
657static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
658 enum pl330_dst da, u16 val)
659{
660 if (dry_run)
661 return SZ_DMAADDH;
662
663 buf[0] = CMD_DMAADDH;
664 buf[0] |= (da << 1);
665 *((u16 *)&buf[1]) = val;
666
667 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
668 da == 1 ? "DA" : "SA", val);
669
670 return SZ_DMAADDH;
671}
672
673static inline u32 _emit_END(unsigned dry_run, u8 buf[])
674{
675 if (dry_run)
676 return SZ_DMAEND;
677
678 buf[0] = CMD_DMAEND;
679
680 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
681
682 return SZ_DMAEND;
683}
684
685static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
686{
687 if (dry_run)
688 return SZ_DMAFLUSHP;
689
690 buf[0] = CMD_DMAFLUSHP;
691
692 peri &= 0x1f;
693 peri <<= 3;
694 buf[1] = peri;
695
696 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
697
698 return SZ_DMAFLUSHP;
699}
700
701static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
702{
703 if (dry_run)
704 return SZ_DMALD;
705
706 buf[0] = CMD_DMALD;
707
708 if (cond == SINGLE)
709 buf[0] |= (0 << 1) | (1 << 0);
710 else if (cond == BURST)
711 buf[0] |= (1 << 1) | (1 << 0);
712
713 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
714 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
715
716 return SZ_DMALD;
717}
718
719static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
720 enum pl330_cond cond, u8 peri)
721{
722 if (dry_run)
723 return SZ_DMALDP;
724
725 buf[0] = CMD_DMALDP;
726
727 if (cond == BURST)
728 buf[0] |= (1 << 1);
729
730 peri &= 0x1f;
731 peri <<= 3;
732 buf[1] = peri;
733
734 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
735 cond == SINGLE ? 'S' : 'B', peri >> 3);
736
737 return SZ_DMALDP;
738}
739
740static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
741 unsigned loop, u8 cnt)
742{
743 if (dry_run)
744 return SZ_DMALP;
745
746 buf[0] = CMD_DMALP;
747
748 if (loop)
749 buf[0] |= (1 << 1);
750
751 cnt--; /* DMAC increments by 1 internally */
752 buf[1] = cnt;
753
754 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
755
756 return SZ_DMALP;
757}
758
759struct _arg_LPEND {
760 enum pl330_cond cond;
761 bool forever;
762 unsigned loop;
763 u8 bjump;
764};
765
766static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
767 const struct _arg_LPEND *arg)
768{
769 enum pl330_cond cond = arg->cond;
770 bool forever = arg->forever;
771 unsigned loop = arg->loop;
772 u8 bjump = arg->bjump;
773
774 if (dry_run)
775 return SZ_DMALPEND;
776
777 buf[0] = CMD_DMALPEND;
778
779 if (loop)
780 buf[0] |= (1 << 2);
781
782 if (!forever)
783 buf[0] |= (1 << 4);
784
785 if (cond == SINGLE)
786 buf[0] |= (0 << 1) | (1 << 0);
787 else if (cond == BURST)
788 buf[0] |= (1 << 1) | (1 << 0);
789
790 buf[1] = bjump;
791
792 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
793 forever ? "FE" : "END",
794 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
795 loop ? '1' : '0',
796 bjump);
797
798 return SZ_DMALPEND;
799}
800
801static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
802{
803 if (dry_run)
804 return SZ_DMAKILL;
805
806 buf[0] = CMD_DMAKILL;
807
808 return SZ_DMAKILL;
809}
810
811static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
812 enum dmamov_dst dst, u32 val)
813{
814 if (dry_run)
815 return SZ_DMAMOV;
816
817 buf[0] = CMD_DMAMOV;
818 buf[1] = dst;
819 *((u32 *)&buf[2]) = val;
820
821 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
822 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
823
824 return SZ_DMAMOV;
825}
826
827static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
828{
829 if (dry_run)
830 return SZ_DMANOP;
831
832 buf[0] = CMD_DMANOP;
833
834 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
835
836 return SZ_DMANOP;
837}
838
839static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
840{
841 if (dry_run)
842 return SZ_DMARMB;
843
844 buf[0] = CMD_DMARMB;
845
846 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
847
848 return SZ_DMARMB;
849}
850
851static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
852{
853 if (dry_run)
854 return SZ_DMASEV;
855
856 buf[0] = CMD_DMASEV;
857
858 ev &= 0x1f;
859 ev <<= 3;
860 buf[1] = ev;
861
862 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
863
864 return SZ_DMASEV;
865}
866
867static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
868{
869 if (dry_run)
870 return SZ_DMAST;
871
872 buf[0] = CMD_DMAST;
873
874 if (cond == SINGLE)
875 buf[0] |= (0 << 1) | (1 << 0);
876 else if (cond == BURST)
877 buf[0] |= (1 << 1) | (1 << 0);
878
879 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
880 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
881
882 return SZ_DMAST;
883}
884
885static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
886 enum pl330_cond cond, u8 peri)
887{
888 if (dry_run)
889 return SZ_DMASTP;
890
891 buf[0] = CMD_DMASTP;
892
893 if (cond == BURST)
894 buf[0] |= (1 << 1);
895
896 peri &= 0x1f;
897 peri <<= 3;
898 buf[1] = peri;
899
900 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
901 cond == SINGLE ? 'S' : 'B', peri >> 3);
902
903 return SZ_DMASTP;
904}
905
906static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
907{
908 if (dry_run)
909 return SZ_DMASTZ;
910
911 buf[0] = CMD_DMASTZ;
912
913 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
914
915 return SZ_DMASTZ;
916}
917
918static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
919 unsigned invalidate)
920{
921 if (dry_run)
922 return SZ_DMAWFE;
923
924 buf[0] = CMD_DMAWFE;
925
926 ev &= 0x1f;
927 ev <<= 3;
928 buf[1] = ev;
929
930 if (invalidate)
931 buf[1] |= (1 << 1);
932
933 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
934 ev >> 3, invalidate ? ", I" : "");
935
936 return SZ_DMAWFE;
937}
938
939static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
940 enum pl330_cond cond, u8 peri)
941{
942 if (dry_run)
943 return SZ_DMAWFP;
944
945 buf[0] = CMD_DMAWFP;
946
947 if (cond == SINGLE)
948 buf[0] |= (0 << 1) | (0 << 0);
949 else if (cond == BURST)
950 buf[0] |= (1 << 1) | (0 << 0);
951 else
952 buf[0] |= (0 << 1) | (1 << 0);
953
954 peri &= 0x1f;
955 peri <<= 3;
956 buf[1] = peri;
957
958 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
959 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
960
961 return SZ_DMAWFP;
962}
963
964static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
965{
966 if (dry_run)
967 return SZ_DMAWMB;
968
969 buf[0] = CMD_DMAWMB;
970
971 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
972
973 return SZ_DMAWMB;
974}
975
976struct _arg_GO {
977 u8 chan;
978 u32 addr;
979 unsigned ns;
980};
981
982static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
983 const struct _arg_GO *arg)
984{
985 u8 chan = arg->chan;
986 u32 addr = arg->addr;
987 unsigned ns = arg->ns;
988
989 if (dry_run)
990 return SZ_DMAGO;
991
992 buf[0] = CMD_DMAGO;
993 buf[0] |= (ns << 1);
994
995 buf[1] = chan & 0x7;
996
997 *((u32 *)&buf[2]) = addr;
998
999 return SZ_DMAGO;
1000}
1001
1002#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
1003
1004/* Returns Time-Out */
1005static bool _until_dmac_idle(struct pl330_thread *thrd)
1006{
1007 void __iomem *regs = thrd->dmac->pinfo->base;
1008 unsigned long loops = msecs_to_loops(5);
1009
1010 do {
1011 /* Until Manager is Idle */
1012 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
1013 break;
1014
1015 cpu_relax();
1016 } while (--loops);
1017
1018 if (!loops)
1019 return true;
1020
1021 return false;
1022}
1023
1024static inline void _execute_DBGINSN(struct pl330_thread *thrd,
1025 u8 insn[], bool as_manager)
1026{
1027 void __iomem *regs = thrd->dmac->pinfo->base;
1028 u32 val;
1029
1030 val = (insn[0] << 16) | (insn[1] << 24);
1031 if (!as_manager) {
1032 val |= (1 << 0);
1033 val |= (thrd->id << 8); /* Channel Number */
1034 }
1035 writel(val, regs + DBGINST0);
1036
1037 val = *((u32 *)&insn[2]);
1038 writel(val, regs + DBGINST1);
1039
1040 /* If timed out due to halted state-machine */
1041 if (_until_dmac_idle(thrd)) {
1042 dev_err(thrd->dmac->pinfo->dev, "DMAC halted!\n");
1043 return;
1044 }
1045
1046 /* Get going */
1047 writel(0, regs + DBGCMD);
1048}
1049
1050/*
1051 * Mark a _pl330_req as free.
1052 * We do it by writing DMAEND as the first instruction
1053 * because no valid request is going to have DMAEND as
1054 * its first instruction to execute.
1055 */
1056static void mark_free(struct pl330_thread *thrd, int idx)
1057{
1058 struct _pl330_req *req = &thrd->req[idx];
1059
1060 _emit_END(0, req->mc_cpu);
1061 req->mc_len = 0;
1062
1063 thrd->req_running = -1;
1064}
1065
1066static inline u32 _state(struct pl330_thread *thrd)
1067{
1068 void __iomem *regs = thrd->dmac->pinfo->base;
1069 u32 val;
1070
1071 if (is_manager(thrd))
1072 val = readl(regs + DS) & 0xf;
1073 else
1074 val = readl(regs + CS(thrd->id)) & 0xf;
1075
1076 switch (val) {
1077 case DS_ST_STOP:
1078 return PL330_STATE_STOPPED;
1079 case DS_ST_EXEC:
1080 return PL330_STATE_EXECUTING;
1081 case DS_ST_CMISS:
1082 return PL330_STATE_CACHEMISS;
1083 case DS_ST_UPDTPC:
1084 return PL330_STATE_UPDTPC;
1085 case DS_ST_WFE:
1086 return PL330_STATE_WFE;
1087 case DS_ST_FAULT:
1088 return PL330_STATE_FAULTING;
1089 case DS_ST_ATBRR:
1090 if (is_manager(thrd))
1091 return PL330_STATE_INVALID;
1092 else
1093 return PL330_STATE_ATBARRIER;
1094 case DS_ST_QBUSY:
1095 if (is_manager(thrd))
1096 return PL330_STATE_INVALID;
1097 else
1098 return PL330_STATE_QUEUEBUSY;
1099 case DS_ST_WFP:
1100 if (is_manager(thrd))
1101 return PL330_STATE_INVALID;
1102 else
1103 return PL330_STATE_WFP;
1104 case DS_ST_KILL:
1105 if (is_manager(thrd))
1106 return PL330_STATE_INVALID;
1107 else
1108 return PL330_STATE_KILLING;
1109 case DS_ST_CMPLT:
1110 if (is_manager(thrd))
1111 return PL330_STATE_INVALID;
1112 else
1113 return PL330_STATE_COMPLETING;
1114 case DS_ST_FLTCMP:
1115 if (is_manager(thrd))
1116 return PL330_STATE_INVALID;
1117 else
1118 return PL330_STATE_FAULT_COMPLETING;
1119 default:
1120 return PL330_STATE_INVALID;
1121 }
1122}
1123
1124static void _stop(struct pl330_thread *thrd)
1125{
1126 void __iomem *regs = thrd->dmac->pinfo->base;
1127 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1128
1129 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1130 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1131
1132 /* Return if nothing needs to be done */
1133 if (_state(thrd) == PL330_STATE_COMPLETING
1134 || _state(thrd) == PL330_STATE_KILLING
1135 || _state(thrd) == PL330_STATE_STOPPED)
1136 return;
1137
1138 _emit_KILL(0, insn);
1139
1140 /* Stop generating interrupts for SEV */
1141 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1142
1143 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1144}
1145
1146/* Start doing req 'idx' of thread 'thrd' */
1147static bool _trigger(struct pl330_thread *thrd)
1148{
1149 void __iomem *regs = thrd->dmac->pinfo->base;
1150 struct _pl330_req *req;
1151 struct pl330_req *r;
1152 struct _arg_GO go;
1153 unsigned ns;
1154 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1155 int idx;
1156
1157 /* Return if already ACTIVE */
1158 if (_state(thrd) != PL330_STATE_STOPPED)
1159 return true;
1160
1161 idx = 1 - thrd->lstenq;
1162 if (!IS_FREE(&thrd->req[idx]))
1163 req = &thrd->req[idx];
1164 else {
1165 idx = thrd->lstenq;
1166 if (!IS_FREE(&thrd->req[idx]))
1167 req = &thrd->req[idx];
1168 else
1169 req = NULL;
1170 }
1171
1172 /* Return if no request */
1173 if (!req || !req->r)
1174 return true;
1175
1176 r = req->r;
1177
1178 if (r->cfg)
1179 ns = r->cfg->nonsecure ? 1 : 0;
1180 else if (readl(regs + CS(thrd->id)) & CS_CNS)
1181 ns = 1;
1182 else
1183 ns = 0;
1184
1185 /* See 'Abort Sources' point-4 at Page 2-25 */
1186 if (_manager_ns(thrd) && !ns)
1187 dev_info(thrd->dmac->pinfo->dev, "%s:%d Recipe for ABORT!\n",
1188 __func__, __LINE__);
1189
1190 go.chan = thrd->id;
1191 go.addr = req->mc_bus;
1192 go.ns = ns;
1193 _emit_GO(0, insn, &go);
1194
1195 /* Set to generate interrupts for SEV */
1196 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1197
1198 /* Only manager can execute GO */
1199 _execute_DBGINSN(thrd, insn, true);
1200
1201 thrd->req_running = idx;
1202
1203 return true;
1204}
1205
1206static bool _start(struct pl330_thread *thrd)
1207{
1208 switch (_state(thrd)) {
1209 case PL330_STATE_FAULT_COMPLETING:
1210 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1211
1212 if (_state(thrd) == PL330_STATE_KILLING)
1213 UNTIL(thrd, PL330_STATE_STOPPED)
1214
1215 case PL330_STATE_FAULTING:
1216 _stop(thrd);
1217
1218 case PL330_STATE_KILLING:
1219 case PL330_STATE_COMPLETING:
1220 UNTIL(thrd, PL330_STATE_STOPPED)
1221
1222 case PL330_STATE_STOPPED:
1223 return _trigger(thrd);
1224
1225 case PL330_STATE_WFP:
1226 case PL330_STATE_QUEUEBUSY:
1227 case PL330_STATE_ATBARRIER:
1228 case PL330_STATE_UPDTPC:
1229 case PL330_STATE_CACHEMISS:
1230 case PL330_STATE_EXECUTING:
1231 return true;
1232
1233 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1234 default:
1235 return false;
1236 }
1237}
1238
1239static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1240 const struct _xfer_spec *pxs, int cyc)
1241{
1242 int off = 0;
1243 struct pl330_config *pcfg = pxs->r->cfg->pcfg;
1244
1245 /* check lock-up free version */
1246 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1247 while (cyc--) {
1248 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1249 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1250 }
1251 } else {
1252 while (cyc--) {
1253 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1254 off += _emit_RMB(dry_run, &buf[off]);
1255 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1256 off += _emit_WMB(dry_run, &buf[off]);
1257 }
1258 }
1259
1260 return off;
1261}
1262
1263static inline int _ldst_devtomem(unsigned dry_run, u8 buf[],
1264 const struct _xfer_spec *pxs, int cyc)
1265{
1266 int off = 0;
1267
1268 while (cyc--) {
1269 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1270 off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1271 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1272 off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
1273 }
1274
1275 return off;
1276}
1277
1278static inline int _ldst_memtodev(unsigned dry_run, u8 buf[],
1279 const struct _xfer_spec *pxs, int cyc)
1280{
1281 int off = 0;
1282
1283 while (cyc--) {
1284 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1285 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1286 off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1287 off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
1288 }
1289
1290 return off;
1291}
1292
1293static int _bursts(unsigned dry_run, u8 buf[],
1294 const struct _xfer_spec *pxs, int cyc)
1295{
1296 int off = 0;
1297
1298 switch (pxs->r->rqtype) {
1299 case MEMTODEV:
1300 off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc);
1301 break;
1302 case DEVTOMEM:
1303 off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc);
1304 break;
1305 case MEMTOMEM:
1306 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1307 break;
1308 default:
1309 off += 0x40000000; /* Scare off the Client */
1310 break;
1311 }
1312
1313 return off;
1314}
1315
1316/* Returns bytes consumed and updates bursts */
1317static inline int _loop(unsigned dry_run, u8 buf[],
1318 unsigned long *bursts, const struct _xfer_spec *pxs)
1319{
1320 int cyc, cycmax, szlp, szlpend, szbrst, off;
1321 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1322 struct _arg_LPEND lpend;
1323
1324 /* Max iterations possible in DMALP is 256 */
1325 if (*bursts >= 256*256) {
1326 lcnt1 = 256;
1327 lcnt0 = 256;
1328 cyc = *bursts / lcnt1 / lcnt0;
1329 } else if (*bursts > 256) {
1330 lcnt1 = 256;
1331 lcnt0 = *bursts / lcnt1;
1332 cyc = 1;
1333 } else {
1334 lcnt1 = *bursts;
1335 lcnt0 = 0;
1336 cyc = 1;
1337 }
1338
1339 szlp = _emit_LP(1, buf, 0, 0);
1340 szbrst = _bursts(1, buf, pxs, 1);
1341
1342 lpend.cond = ALWAYS;
1343 lpend.forever = false;
1344 lpend.loop = 0;
1345 lpend.bjump = 0;
1346 szlpend = _emit_LPEND(1, buf, &lpend);
1347
1348 if (lcnt0) {
1349 szlp *= 2;
1350 szlpend *= 2;
1351 }
1352
1353 /*
1354 * Max bursts that we can unroll due to limit on the
1355 * size of backward jump that can be encoded in DMALPEND
1356 * which is 8-bits and hence 255
1357 */
1358 cycmax = (255 - (szlp + szlpend)) / szbrst;
1359
1360 cyc = (cycmax < cyc) ? cycmax : cyc;
1361
1362 off = 0;
1363
1364 if (lcnt0) {
1365 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1366 ljmp0 = off;
1367 }
1368
1369 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1370 ljmp1 = off;
1371
1372 off += _bursts(dry_run, &buf[off], pxs, cyc);
1373
1374 lpend.cond = ALWAYS;
1375 lpend.forever = false;
1376 lpend.loop = 1;
1377 lpend.bjump = off - ljmp1;
1378 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1379
1380 if (lcnt0) {
1381 lpend.cond = ALWAYS;
1382 lpend.forever = false;
1383 lpend.loop = 0;
1384 lpend.bjump = off - ljmp0;
1385 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1386 }
1387
1388 *bursts = lcnt1 * cyc;
1389 if (lcnt0)
1390 *bursts *= lcnt0;
1391
1392 return off;
1393}
1394
1395static inline int _setup_loops(unsigned dry_run, u8 buf[],
1396 const struct _xfer_spec *pxs)
1397{
1398 struct pl330_xfer *x = pxs->x;
1399 u32 ccr = pxs->ccr;
1400 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1401 int off = 0;
1402
1403 while (bursts) {
1404 c = bursts;
1405 off += _loop(dry_run, &buf[off], &c, pxs);
1406 bursts -= c;
1407 }
1408
1409 return off;
1410}
1411
1412static inline int _setup_xfer(unsigned dry_run, u8 buf[],
1413 const struct _xfer_spec *pxs)
1414{
1415 struct pl330_xfer *x = pxs->x;
1416 int off = 0;
1417
1418 /* DMAMOV SAR, x->src_addr */
1419 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1420 /* DMAMOV DAR, x->dst_addr */
1421 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1422
1423 /* Setup Loop(s) */
1424 off += _setup_loops(dry_run, &buf[off], pxs);
1425
1426 return off;
1427}
1428
1429/*
1430 * A req is a sequence of one or more xfer units.
1431 * Returns the number of bytes taken to setup the MC for the req.
1432 */
1433static int _setup_req(unsigned dry_run, struct pl330_thread *thrd,
1434 unsigned index, struct _xfer_spec *pxs)
1435{
1436 struct _pl330_req *req = &thrd->req[index];
1437 struct pl330_xfer *x;
1438 u8 *buf = req->mc_cpu;
1439 int off = 0;
1440
1441 PL330_DBGMC_START(req->mc_bus);
1442
1443 /* DMAMOV CCR, ccr */
1444 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1445
1446 x = pxs->r->x;
1447 do {
1448 /* Error if xfer length is not aligned at burst size */
1449 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1450 return -EINVAL;
1451
1452 pxs->x = x;
1453 off += _setup_xfer(dry_run, &buf[off], pxs);
1454
1455 x = x->next;
1456 } while (x);
1457
1458 /* DMASEV peripheral/event */
1459 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1460 /* DMAEND */
1461 off += _emit_END(dry_run, &buf[off]);
1462
1463 return off;
1464}
1465
1466static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1467{
1468 u32 ccr = 0;
1469
1470 if (rqc->src_inc)
1471 ccr |= CC_SRCINC;
1472
1473 if (rqc->dst_inc)
1474 ccr |= CC_DSTINC;
1475
1476 /* We set same protection levels for Src and DST for now */
1477 if (rqc->privileged)
1478 ccr |= CC_SRCPRI | CC_DSTPRI;
1479 if (rqc->nonsecure)
1480 ccr |= CC_SRCNS | CC_DSTNS;
1481 if (rqc->insnaccess)
1482 ccr |= CC_SRCIA | CC_DSTIA;
1483
1484 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1485 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1486
1487 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1488 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1489
1490 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1491 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1492
1493 ccr |= (rqc->swap << CC_SWAP_SHFT);
1494
1495 return ccr;
1496}
1497
1498static inline bool _is_valid(u32 ccr)
1499{
1500 enum pl330_dstcachectrl dcctl;
1501 enum pl330_srccachectrl scctl;
1502
1503 dcctl = (ccr >> CC_DSTCCTRL_SHFT) & CC_DRCCCTRL_MASK;
1504 scctl = (ccr >> CC_SRCCCTRL_SHFT) & CC_SRCCCTRL_MASK;
1505
1506 if (dcctl == DINVALID1 || dcctl == DINVALID2
1507 || scctl == SINVALID1 || scctl == SINVALID2)
1508 return false;
1509 else
1510 return true;
1511}
1512
1513/*
1514 * Submit a list of xfers after which the client wants notification.
1515 * Client is not notified after each xfer unit, just once after all
1516 * xfer units are done or some error occurs.
1517 */
1518static int pl330_submit_req(void *ch_id, struct pl330_req *r)
1519{
1520 struct pl330_thread *thrd = ch_id;
1521 struct pl330_dmac *pl330;
1522 struct pl330_info *pi;
1523 struct _xfer_spec xs;
1524 unsigned long flags;
1525 void __iomem *regs;
1526 unsigned idx;
1527 u32 ccr;
1528 int ret = 0;
1529
1530 /* No Req or Unacquired Channel or DMAC */
1531 if (!r || !thrd || thrd->free)
1532 return -EINVAL;
1533
1534 pl330 = thrd->dmac;
1535 pi = pl330->pinfo;
1536 regs = pi->base;
1537
1538 if (pl330->state == DYING
1539 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1540 dev_info(thrd->dmac->pinfo->dev, "%s:%d\n",
1541 __func__, __LINE__);
1542 return -EAGAIN;
1543 }
1544
1545 /* If request for non-existing peripheral */
1546 if (r->rqtype != MEMTOMEM && r->peri >= pi->pcfg.num_peri) {
1547 dev_info(thrd->dmac->pinfo->dev,
1548 "%s:%d Invalid peripheral(%u)!\n",
1549 __func__, __LINE__, r->peri);
1550 return -EINVAL;
1551 }
1552
1553 spin_lock_irqsave(&pl330->lock, flags);
1554
1555 if (_queue_full(thrd)) {
1556 ret = -EAGAIN;
1557 goto xfer_exit;
1558 }
1559
1560
1561 /* Use last settings, if not provided */
1562 if (r->cfg) {
1563 /* Prefer Secure Channel */
1564 if (!_manager_ns(thrd))
1565 r->cfg->nonsecure = 0;
1566 else
1567 r->cfg->nonsecure = 1;
1568
1569 ccr = _prepare_ccr(r->cfg);
1570 } else {
1571 ccr = readl(regs + CC(thrd->id));
1572 }
1573
1574 /* If this req doesn't have valid xfer settings */
1575 if (!_is_valid(ccr)) {
1576 ret = -EINVAL;
1577 dev_info(thrd->dmac->pinfo->dev, "%s:%d Invalid CCR(%x)!\n",
1578 __func__, __LINE__, ccr);
1579 goto xfer_exit;
1580 }
1581
1582 idx = IS_FREE(&thrd->req[0]) ? 0 : 1;
1583
1584 xs.ccr = ccr;
1585 xs.r = r;
1586
1587 /* First dry run to check if req is acceptable */
1588 ret = _setup_req(1, thrd, idx, &xs);
1589 if (ret < 0)
1590 goto xfer_exit;
1591
1592 if (ret > pi->mcbufsz / 2) {
1593 dev_info(thrd->dmac->pinfo->dev,
1594 "%s:%d Trying increasing mcbufsz\n",
1595 __func__, __LINE__);
1596 ret = -ENOMEM;
1597 goto xfer_exit;
1598 }
1599
1600 /* Hook the request */
1601 thrd->lstenq = idx;
1602 thrd->req[idx].mc_len = _setup_req(0, thrd, idx, &xs);
1603 thrd->req[idx].r = r;
1604
1605 ret = 0;
1606
1607xfer_exit:
1608 spin_unlock_irqrestore(&pl330->lock, flags);
1609
1610 return ret;
1611}
1612
1613static void pl330_dotask(unsigned long data)
1614{
1615 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1616 struct pl330_info *pi = pl330->pinfo;
1617 unsigned long flags;
1618 int i;
1619
1620 spin_lock_irqsave(&pl330->lock, flags);
1621
1622 /* The DMAC itself gone nuts */
1623 if (pl330->dmac_tbd.reset_dmac) {
1624 pl330->state = DYING;
1625 /* Reset the manager too */
1626 pl330->dmac_tbd.reset_mngr = true;
1627 /* Clear the reset flag */
1628 pl330->dmac_tbd.reset_dmac = false;
1629 }
1630
1631 if (pl330->dmac_tbd.reset_mngr) {
1632 _stop(pl330->manager);
1633 /* Reset all channels */
1634 pl330->dmac_tbd.reset_chan = (1 << pi->pcfg.num_chan) - 1;
1635 /* Clear the reset flag */
1636 pl330->dmac_tbd.reset_mngr = false;
1637 }
1638
1639 for (i = 0; i < pi->pcfg.num_chan; i++) {
1640
1641 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1642 struct pl330_thread *thrd = &pl330->channels[i];
1643 void __iomem *regs = pi->base;
1644 enum pl330_op_err err;
1645
1646 _stop(thrd);
1647
1648 if (readl(regs + FSC) & (1 << thrd->id))
1649 err = PL330_ERR_FAIL;
1650 else
1651 err = PL330_ERR_ABORT;
1652
1653 spin_unlock_irqrestore(&pl330->lock, flags);
1654
1655 _callback(thrd->req[1 - thrd->lstenq].r, err);
1656 _callback(thrd->req[thrd->lstenq].r, err);
1657
1658 spin_lock_irqsave(&pl330->lock, flags);
1659
1660 thrd->req[0].r = NULL;
1661 thrd->req[1].r = NULL;
1662 mark_free(thrd, 0);
1663 mark_free(thrd, 1);
1664
1665 /* Clear the reset flag */
1666 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1667 }
1668 }
1669
1670 spin_unlock_irqrestore(&pl330->lock, flags);
1671
1672 return;
1673}
1674
1675/* Returns 1 if state was updated, 0 otherwise */
1676static int pl330_update(const struct pl330_info *pi)
1677{
1678 struct pl330_req *rqdone, *tmp;
1679 struct pl330_dmac *pl330;
1680 unsigned long flags;
1681 void __iomem *regs;
1682 u32 val;
1683 int id, ev, ret = 0;
1684
1685 if (!pi || !pi->pl330_data)
1686 return 0;
1687
1688 regs = pi->base;
1689 pl330 = pi->pl330_data;
1690
1691 spin_lock_irqsave(&pl330->lock, flags);
1692
1693 val = readl(regs + FSM) & 0x1;
1694 if (val)
1695 pl330->dmac_tbd.reset_mngr = true;
1696 else
1697 pl330->dmac_tbd.reset_mngr = false;
1698
1699 val = readl(regs + FSC) & ((1 << pi->pcfg.num_chan) - 1);
1700 pl330->dmac_tbd.reset_chan |= val;
1701 if (val) {
1702 int i = 0;
1703 while (i < pi->pcfg.num_chan) {
1704 if (val & (1 << i)) {
1705 dev_info(pi->dev,
1706 "Reset Channel-%d\t CS-%x FTC-%x\n",
1707 i, readl(regs + CS(i)),
1708 readl(regs + FTC(i)));
1709 _stop(&pl330->channels[i]);
1710 }
1711 i++;
1712 }
1713 }
1714
1715 /* Check which event happened i.e, thread notified */
1716 val = readl(regs + ES);
1717 if (pi->pcfg.num_events < 32
1718 && val & ~((1 << pi->pcfg.num_events) - 1)) {
1719 pl330->dmac_tbd.reset_dmac = true;
1720 dev_err(pi->dev, "%s:%d Unexpected!\n", __func__, __LINE__);
1721 ret = 1;
1722 goto updt_exit;
1723 }
1724
1725 for (ev = 0; ev < pi->pcfg.num_events; ev++) {
1726 if (val & (1 << ev)) { /* Event occurred */
1727 struct pl330_thread *thrd;
1728 u32 inten = readl(regs + INTEN);
1729 int active;
1730
1731 /* Clear the event */
1732 if (inten & (1 << ev))
1733 writel(1 << ev, regs + INTCLR);
1734
1735 ret = 1;
1736
1737 id = pl330->events[ev];
1738
1739 thrd = &pl330->channels[id];
1740
1741 active = thrd->req_running;
1742 if (active == -1) /* Aborted */
1743 continue;
1744
1745 /* Detach the req */
1746 rqdone = thrd->req[active].r;
1747 thrd->req[active].r = NULL;
1748
1749 mark_free(thrd, active);
1750
1751 /* Get going again ASAP */
1752 _start(thrd);
1753
1754 /* For now, just make a list of callbacks to be done */
1755 list_add_tail(&rqdone->rqd, &pl330->req_done);
1756 }
1757 }
1758
1759 /* Now that we are in no hurry, do the callbacks */
1760 list_for_each_entry_safe(rqdone, tmp, &pl330->req_done, rqd) {
1761 list_del(&rqdone->rqd);
1762
1763 spin_unlock_irqrestore(&pl330->lock, flags);
1764 _callback(rqdone, PL330_ERR_NONE);
1765 spin_lock_irqsave(&pl330->lock, flags);
1766 }
1767
1768updt_exit:
1769 spin_unlock_irqrestore(&pl330->lock, flags);
1770
1771 if (pl330->dmac_tbd.reset_dmac
1772 || pl330->dmac_tbd.reset_mngr
1773 || pl330->dmac_tbd.reset_chan) {
1774 ret = 1;
1775 tasklet_schedule(&pl330->tasks);
1776 }
1777
1778 return ret;
1779}
1780
1781static int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op)
1782{
1783 struct pl330_thread *thrd = ch_id;
1784 struct pl330_dmac *pl330;
1785 unsigned long flags;
1786 int ret = 0, active;
1787
1788 if (!thrd || thrd->free || thrd->dmac->state == DYING)
1789 return -EINVAL;
1790
1791 pl330 = thrd->dmac;
1792 active = thrd->req_running;
1793
1794 spin_lock_irqsave(&pl330->lock, flags);
1795
1796 switch (op) {
1797 case PL330_OP_FLUSH:
1798 /* Make sure the channel is stopped */
1799 _stop(thrd);
1800
1801 thrd->req[0].r = NULL;
1802 thrd->req[1].r = NULL;
1803 mark_free(thrd, 0);
1804 mark_free(thrd, 1);
1805 break;
1806
1807 case PL330_OP_ABORT:
1808 /* Make sure the channel is stopped */
1809 _stop(thrd);
1810
1811 /* ABORT is only for the active req */
1812 if (active == -1)
1813 break;
1814
1815 thrd->req[active].r = NULL;
1816 mark_free(thrd, active);
1817
1818 /* Start the next */
1819 case PL330_OP_START:
1820 if ((active == -1) && !_start(thrd))
1821 ret = -EIO;
1822 break;
1823
1824 default:
1825 ret = -EINVAL;
1826 }
1827
1828 spin_unlock_irqrestore(&pl330->lock, flags);
1829 return ret;
1830}
1831
1832/* Reserve an event */
1833static inline int _alloc_event(struct pl330_thread *thrd)
1834{
1835 struct pl330_dmac *pl330 = thrd->dmac;
1836 struct pl330_info *pi = pl330->pinfo;
1837 int ev;
1838
1839 for (ev = 0; ev < pi->pcfg.num_events; ev++)
1840 if (pl330->events[ev] == -1) {
1841 pl330->events[ev] = thrd->id;
1842 return ev;
1843 }
1844
1845 return -1;
1846}
1847
1848static bool _chan_ns(const struct pl330_info *pi, int i)
1849{
1850 return pi->pcfg.irq_ns & (1 << i);
1851}
1852
1853/* Upon success, returns IdentityToken for the
1854 * allocated channel, NULL otherwise.
1855 */
1856static void *pl330_request_channel(const struct pl330_info *pi)
1857{
1858 struct pl330_thread *thrd = NULL;
1859 struct pl330_dmac *pl330;
1860 unsigned long flags;
1861 int chans, i;
1862
1863 if (!pi || !pi->pl330_data)
1864 return NULL;
1865
1866 pl330 = pi->pl330_data;
1867
1868 if (pl330->state == DYING)
1869 return NULL;
1870
1871 chans = pi->pcfg.num_chan;
1872
1873 spin_lock_irqsave(&pl330->lock, flags);
1874
1875 for (i = 0; i < chans; i++) {
1876 thrd = &pl330->channels[i];
1877 if ((thrd->free) && (!_manager_ns(thrd) ||
1878 _chan_ns(pi, i))) {
1879 thrd->ev = _alloc_event(thrd);
1880 if (thrd->ev >= 0) {
1881 thrd->free = false;
1882 thrd->lstenq = 1;
1883 thrd->req[0].r = NULL;
1884 mark_free(thrd, 0);
1885 thrd->req[1].r = NULL;
1886 mark_free(thrd, 1);
1887 break;
1888 }
1889 }
1890 thrd = NULL;
1891 }
1892
1893 spin_unlock_irqrestore(&pl330->lock, flags);
1894
1895 return thrd;
1896}
1897
1898/* Release an event */
1899static inline void _free_event(struct pl330_thread *thrd, int ev)
1900{
1901 struct pl330_dmac *pl330 = thrd->dmac;
1902 struct pl330_info *pi = pl330->pinfo;
1903
1904 /* If the event is valid and was held by the thread */
1905 if (ev >= 0 && ev < pi->pcfg.num_events
1906 && pl330->events[ev] == thrd->id)
1907 pl330->events[ev] = -1;
1908}
1909
1910static void pl330_release_channel(void *ch_id)
1911{
1912 struct pl330_thread *thrd = ch_id;
1913 struct pl330_dmac *pl330;
1914 unsigned long flags;
1915
1916 if (!thrd || thrd->free)
1917 return;
1918
1919 _stop(thrd);
1920
1921 _callback(thrd->req[1 - thrd->lstenq].r, PL330_ERR_ABORT);
1922 _callback(thrd->req[thrd->lstenq].r, PL330_ERR_ABORT);
1923
1924 pl330 = thrd->dmac;
1925
1926 spin_lock_irqsave(&pl330->lock, flags);
1927 _free_event(thrd, thrd->ev);
1928 thrd->free = true;
1929 spin_unlock_irqrestore(&pl330->lock, flags);
1930}
1931
1932/* Initialize the structure for PL330 configuration, that can be used
1933 * by the client driver the make best use of the DMAC
1934 */
1935static void read_dmac_config(struct pl330_info *pi)
1936{
1937 void __iomem *regs = pi->base;
1938 u32 val;
1939
1940 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1941 val &= CRD_DATA_WIDTH_MASK;
1942 pi->pcfg.data_bus_width = 8 * (1 << val);
1943
1944 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1945 val &= CRD_DATA_BUFF_MASK;
1946 pi->pcfg.data_buf_dep = val + 1;
1947
1948 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1949 val &= CR0_NUM_CHANS_MASK;
1950 val += 1;
1951 pi->pcfg.num_chan = val;
1952
1953 val = readl(regs + CR0);
1954 if (val & CR0_PERIPH_REQ_SET) {
1955 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1956 val += 1;
1957 pi->pcfg.num_peri = val;
1958 pi->pcfg.peri_ns = readl(regs + CR4);
1959 } else {
1960 pi->pcfg.num_peri = 0;
1961 }
1962
1963 val = readl(regs + CR0);
1964 if (val & CR0_BOOT_MAN_NS)
1965 pi->pcfg.mode |= DMAC_MODE_NS;
1966 else
1967 pi->pcfg.mode &= ~DMAC_MODE_NS;
1968
1969 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1970 val &= CR0_NUM_EVENTS_MASK;
1971 val += 1;
1972 pi->pcfg.num_events = val;
1973
1974 pi->pcfg.irq_ns = readl(regs + CR3);
1975}
1976
1977static inline void _reset_thread(struct pl330_thread *thrd)
1978{
1979 struct pl330_dmac *pl330 = thrd->dmac;
1980 struct pl330_info *pi = pl330->pinfo;
1981
1982 thrd->req[0].mc_cpu = pl330->mcode_cpu
1983 + (thrd->id * pi->mcbufsz);
1984 thrd->req[0].mc_bus = pl330->mcode_bus
1985 + (thrd->id * pi->mcbufsz);
1986 thrd->req[0].r = NULL;
1987 mark_free(thrd, 0);
1988
1989 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1990 + pi->mcbufsz / 2;
1991 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1992 + pi->mcbufsz / 2;
1993 thrd->req[1].r = NULL;
1994 mark_free(thrd, 1);
1995}
1996
1997static int dmac_alloc_threads(struct pl330_dmac *pl330)
1998{
1999 struct pl330_info *pi = pl330->pinfo;
2000 int chans = pi->pcfg.num_chan;
2001 struct pl330_thread *thrd;
2002 int i;
2003
2004 /* Allocate 1 Manager and 'chans' Channel threads */
2005 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
2006 GFP_KERNEL);
2007 if (!pl330->channels)
2008 return -ENOMEM;
2009
2010 /* Init Channel threads */
2011 for (i = 0; i < chans; i++) {
2012 thrd = &pl330->channels[i];
2013 thrd->id = i;
2014 thrd->dmac = pl330;
2015 _reset_thread(thrd);
2016 thrd->free = true;
2017 }
2018
2019 /* MANAGER is indexed at the end */
2020 thrd = &pl330->channels[chans];
2021 thrd->id = chans;
2022 thrd->dmac = pl330;
2023 thrd->free = false;
2024 pl330->manager = thrd;
2025
2026 return 0;
2027}
2028
2029static int dmac_alloc_resources(struct pl330_dmac *pl330)
2030{
2031 struct pl330_info *pi = pl330->pinfo;
2032 int chans = pi->pcfg.num_chan;
2033 int ret;
2034
2035 /*
2036 * Alloc MicroCode buffer for 'chans' Channel threads.
2037 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
2038 */
2039 pl330->mcode_cpu = dma_alloc_coherent(pi->dev,
2040 chans * pi->mcbufsz,
2041 &pl330->mcode_bus, GFP_KERNEL);
2042 if (!pl330->mcode_cpu) {
2043 dev_err(pi->dev, "%s:%d Can't allocate memory!\n",
2044 __func__, __LINE__);
2045 return -ENOMEM;
2046 }
2047
2048 ret = dmac_alloc_threads(pl330);
2049 if (ret) {
2050 dev_err(pi->dev, "%s:%d Can't to create channels for DMAC!\n",
2051 __func__, __LINE__);
2052 dma_free_coherent(pi->dev,
2053 chans * pi->mcbufsz,
2054 pl330->mcode_cpu, pl330->mcode_bus);
2055 return ret;
2056 }
2057
2058 return 0;
2059}
2060
2061static int pl330_add(struct pl330_info *pi)
2062{
2063 struct pl330_dmac *pl330;
2064 void __iomem *regs;
2065 int i, ret;
2066
2067 if (!pi || !pi->dev)
2068 return -EINVAL;
2069
2070 /* If already added */
2071 if (pi->pl330_data)
2072 return -EINVAL;
2073
2074 /*
2075 * If the SoC can perform reset on the DMAC, then do it
2076 * before reading its configuration.
2077 */
2078 if (pi->dmac_reset)
2079 pi->dmac_reset(pi);
2080
2081 regs = pi->base;
2082
2083 /* Check if we can handle this DMAC */
2084 if ((pi->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
2085 dev_err(pi->dev, "PERIPH_ID 0x%x !\n", pi->pcfg.periph_id);
2086 return -EINVAL;
2087 }
2088
2089 /* Read the configuration of the DMAC */
2090 read_dmac_config(pi);
2091
2092 if (pi->pcfg.num_events == 0) {
2093 dev_err(pi->dev, "%s:%d Can't work without events!\n",
2094 __func__, __LINE__);
2095 return -EINVAL;
2096 }
2097
2098 pl330 = kzalloc(sizeof(*pl330), GFP_KERNEL);
2099 if (!pl330) {
2100 dev_err(pi->dev, "%s:%d Can't allocate memory!\n",
2101 __func__, __LINE__);
2102 return -ENOMEM;
2103 }
2104
2105 /* Assign the info structure and private data */
2106 pl330->pinfo = pi;
2107 pi->pl330_data = pl330;
2108
2109 spin_lock_init(&pl330->lock);
2110
2111 INIT_LIST_HEAD(&pl330->req_done);
2112
2113 /* Use default MC buffer size if not provided */
2114 if (!pi->mcbufsz)
2115 pi->mcbufsz = MCODE_BUFF_PER_REQ * 2;
2116
2117 /* Mark all events as free */
2118 for (i = 0; i < pi->pcfg.num_events; i++)
2119 pl330->events[i] = -1;
2120
2121 /* Allocate resources needed by the DMAC */
2122 ret = dmac_alloc_resources(pl330);
2123 if (ret) {
2124 dev_err(pi->dev, "Unable to create channels for DMAC\n");
2125 kfree(pl330);
2126 return ret;
2127 }
2128
2129 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
2130
2131 pl330->state = INIT;
2132
2133 return 0;
2134}
2135
2136static int dmac_free_threads(struct pl330_dmac *pl330)
2137{
2138 struct pl330_info *pi = pl330->pinfo;
2139 int chans = pi->pcfg.num_chan;
2140 struct pl330_thread *thrd;
2141 int i;
2142
2143 /* Release Channel threads */
2144 for (i = 0; i < chans; i++) {
2145 thrd = &pl330->channels[i];
2146 pl330_release_channel((void *)thrd);
2147 }
2148
2149 /* Free memory */
2150 kfree(pl330->channels);
2151
2152 return 0;
2153}
2154
2155static void dmac_free_resources(struct pl330_dmac *pl330)
2156{
2157 struct pl330_info *pi = pl330->pinfo;
2158 int chans = pi->pcfg.num_chan;
2159
2160 dmac_free_threads(pl330);
2161
2162 dma_free_coherent(pi->dev, chans * pi->mcbufsz,
2163 pl330->mcode_cpu, pl330->mcode_bus);
2164}
2165
2166static void pl330_del(struct pl330_info *pi)
2167{
2168 struct pl330_dmac *pl330;
2169
2170 if (!pi || !pi->pl330_data)
2171 return;
2172
2173 pl330 = pi->pl330_data;
2174
2175 pl330->state = UNINIT;
2176
2177 tasklet_kill(&pl330->tasks);
2178
2179 /* Free DMAC resources */
2180 dmac_free_resources(pl330);
2181
2182 kfree(pl330);
2183 pi->pl330_data = NULL;
2184}
2185
2186/* forward declaration */
2187static struct amba_driver pl330_driver;
2188
2189static inline struct dma_pl330_chan *
2190to_pchan(struct dma_chan *ch)
2191{
2192 if (!ch)
2193 return NULL;
2194
2195 return container_of(ch, struct dma_pl330_chan, chan);
2196}
2197
2198static inline struct dma_pl330_desc *
2199to_desc(struct dma_async_tx_descriptor *tx)
2200{
2201 return container_of(tx, struct dma_pl330_desc, txd);
2202}
2203
2204static inline void fill_queue(struct dma_pl330_chan *pch)
2205{
2206 struct dma_pl330_desc *desc;
2207 int ret;
2208
2209 list_for_each_entry(desc, &pch->work_list, node) {
2210
2211 /* If already submitted */
2212 if (desc->status == BUSY)
2213 continue;
2214
2215 ret = pl330_submit_req(pch->pl330_chid,
2216 &desc->req);
2217 if (!ret) {
2218 desc->status = BUSY;
2219 } else if (ret == -EAGAIN) {
2220 /* QFull or DMAC Dying */
2221 break;
2222 } else {
2223 /* Unacceptable request */
2224 desc->status = DONE;
2225 dev_err(pch->dmac->pif.dev, "%s:%d Bad Desc(%d)\n",
2226 __func__, __LINE__, desc->txd.cookie);
2227 tasklet_schedule(&pch->task);
2228 }
2229 }
2230}
2231
2232static void pl330_tasklet(unsigned long data)
2233{
2234 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2235 struct dma_pl330_desc *desc, *_dt;
2236 unsigned long flags;
2237
2238 spin_lock_irqsave(&pch->lock, flags);
2239
2240 /* Pick up ripe tomatoes */
2241 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2242 if (desc->status == DONE) {
2243 if (!pch->cyclic)
2244 dma_cookie_complete(&desc->txd);
2245 list_move_tail(&desc->node, &pch->completed_list);
2246 }
2247
2248 /* Try to submit a req imm. next to the last completed cookie */
2249 fill_queue(pch);
2250
2251 /* Make sure the PL330 Channel thread is active */
2252 pl330_chan_ctrl(pch->pl330_chid, PL330_OP_START);
2253
2254 while (!list_empty(&pch->completed_list)) {
2255 dma_async_tx_callback callback;
2256 void *callback_param;
2257
2258 desc = list_first_entry(&pch->completed_list,
2259 struct dma_pl330_desc, node);
2260
2261 callback = desc->txd.callback;
2262 callback_param = desc->txd.callback_param;
2263
2264 if (pch->cyclic) {
2265 desc->status = PREP;
2266 list_move_tail(&desc->node, &pch->work_list);
2267 } else {
2268 desc->status = FREE;
2269 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2270 }
2271
2272 dma_descriptor_unmap(&desc->txd);
2273
2274 if (callback) {
2275 spin_unlock_irqrestore(&pch->lock, flags);
2276 callback(callback_param);
2277 spin_lock_irqsave(&pch->lock, flags);
2278 }
2279 }
2280 spin_unlock_irqrestore(&pch->lock, flags);
2281}
2282
2283static void dma_pl330_rqcb(void *token, enum pl330_op_err err)
2284{
2285 struct dma_pl330_desc *desc = token;
2286 struct dma_pl330_chan *pch = desc->pchan;
2287 unsigned long flags;
2288
2289 /* If desc aborted */
2290 if (!pch)
2291 return;
2292
2293 spin_lock_irqsave(&pch->lock, flags);
2294
2295 desc->status = DONE;
2296
2297 spin_unlock_irqrestore(&pch->lock, flags);
2298
2299 tasklet_schedule(&pch->task);
2300}
2301
2302bool pl330_filter(struct dma_chan *chan, void *param)
2303{
2304 u8 *peri_id;
2305
2306 if (chan->device->dev->driver != &pl330_driver.drv)
2307 return false;
2308
2309 peri_id = chan->private;
2310 return *peri_id == (unsigned long)param;
2311}
2312EXPORT_SYMBOL(pl330_filter);
2313
2314static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2315 struct of_dma *ofdma)
2316{
2317 int count = dma_spec->args_count;
2318 struct dma_pl330_dmac *pdmac = ofdma->of_dma_data;
2319 unsigned int chan_id;
2320
2321 if (count != 1)
2322 return NULL;
2323
2324 chan_id = dma_spec->args[0];
2325 if (chan_id >= pdmac->num_peripherals)
2326 return NULL;
2327
2328 return dma_get_slave_channel(&pdmac->peripherals[chan_id].chan);
2329}
2330
2331static int pl330_alloc_chan_resources(struct dma_chan *chan)
2332{
2333 struct dma_pl330_chan *pch = to_pchan(chan);
2334 struct dma_pl330_dmac *pdmac = pch->dmac;
2335 unsigned long flags;
2336
2337 spin_lock_irqsave(&pch->lock, flags);
2338
2339 dma_cookie_init(chan);
2340 pch->cyclic = false;
2341
2342 pch->pl330_chid = pl330_request_channel(&pdmac->pif);
2343 if (!pch->pl330_chid) {
2344 spin_unlock_irqrestore(&pch->lock, flags);
2345 return -ENOMEM;
2346 }
2347
2348 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2349
2350 spin_unlock_irqrestore(&pch->lock, flags);
2351
2352 return 1;
2353}
2354
2355static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg)
2356{
2357 struct dma_pl330_chan *pch = to_pchan(chan);
2358 struct dma_pl330_desc *desc;
2359 unsigned long flags;
2360 struct dma_pl330_dmac *pdmac = pch->dmac;
2361 struct dma_slave_config *slave_config;
2362 LIST_HEAD(list);
2363
2364 switch (cmd) {
2365 case DMA_TERMINATE_ALL:
2366 spin_lock_irqsave(&pch->lock, flags);
2367
2368 /* FLUSH the PL330 Channel thread */
2369 pl330_chan_ctrl(pch->pl330_chid, PL330_OP_FLUSH);
2370
2371 /* Mark all desc done */
2372 list_for_each_entry(desc, &pch->submitted_list, node) {
2373 desc->status = FREE;
2374 dma_cookie_complete(&desc->txd);
2375 }
2376
2377 list_for_each_entry(desc, &pch->work_list , node) {
2378 desc->status = FREE;
2379 dma_cookie_complete(&desc->txd);
2380 }
2381
2382 list_for_each_entry(desc, &pch->completed_list , node) {
2383 desc->status = FREE;
2384 dma_cookie_complete(&desc->txd);
2385 }
2386
2387 list_splice_tail_init(&pch->submitted_list, &pdmac->desc_pool);
2388 list_splice_tail_init(&pch->work_list, &pdmac->desc_pool);
2389 list_splice_tail_init(&pch->completed_list, &pdmac->desc_pool);
2390 spin_unlock_irqrestore(&pch->lock, flags);
2391 break;
2392 case DMA_SLAVE_CONFIG:
2393 slave_config = (struct dma_slave_config *)arg;
2394
2395 if (slave_config->direction == DMA_MEM_TO_DEV) {
2396 if (slave_config->dst_addr)
2397 pch->fifo_addr = slave_config->dst_addr;
2398 if (slave_config->dst_addr_width)
2399 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2400 if (slave_config->dst_maxburst)
2401 pch->burst_len = slave_config->dst_maxburst;
2402 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
2403 if (slave_config->src_addr)
2404 pch->fifo_addr = slave_config->src_addr;
2405 if (slave_config->src_addr_width)
2406 pch->burst_sz = __ffs(slave_config->src_addr_width);
2407 if (slave_config->src_maxburst)
2408 pch->burst_len = slave_config->src_maxburst;
2409 }
2410 break;
2411 default:
2412 dev_err(pch->dmac->pif.dev, "Not supported command.\n");
2413 return -ENXIO;
2414 }
2415
2416 return 0;
2417}
2418
2419static void pl330_free_chan_resources(struct dma_chan *chan)
2420{
2421 struct dma_pl330_chan *pch = to_pchan(chan);
2422 unsigned long flags;
2423
2424 tasklet_kill(&pch->task);
2425
2426 spin_lock_irqsave(&pch->lock, flags);
2427
2428 pl330_release_channel(pch->pl330_chid);
2429 pch->pl330_chid = NULL;
2430
2431 if (pch->cyclic)
2432 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2433
2434 spin_unlock_irqrestore(&pch->lock, flags);
2435}
2436
2437static enum dma_status
2438pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2439 struct dma_tx_state *txstate)
2440{
2441 return dma_cookie_status(chan, cookie, txstate);
2442}
2443
2444static void pl330_issue_pending(struct dma_chan *chan)
2445{
2446 struct dma_pl330_chan *pch = to_pchan(chan);
2447 unsigned long flags;
2448
2449 spin_lock_irqsave(&pch->lock, flags);
2450 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2451 spin_unlock_irqrestore(&pch->lock, flags);
2452
2453 pl330_tasklet((unsigned long)pch);
2454}
2455
2456/*
2457 * We returned the last one of the circular list of descriptor(s)
2458 * from prep_xxx, so the argument to submit corresponds to the last
2459 * descriptor of the list.
2460 */
2461static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2462{
2463 struct dma_pl330_desc *desc, *last = to_desc(tx);
2464 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2465 dma_cookie_t cookie;
2466 unsigned long flags;
2467
2468 spin_lock_irqsave(&pch->lock, flags);
2469
2470 /* Assign cookies to all nodes */
2471 while (!list_empty(&last->node)) {
2472 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2473 if (pch->cyclic) {
2474 desc->txd.callback = last->txd.callback;
2475 desc->txd.callback_param = last->txd.callback_param;
2476 }
2477
2478 dma_cookie_assign(&desc->txd);
2479
2480 list_move_tail(&desc->node, &pch->submitted_list);
2481 }
2482
2483 cookie = dma_cookie_assign(&last->txd);
2484 list_add_tail(&last->node, &pch->submitted_list);
2485 spin_unlock_irqrestore(&pch->lock, flags);
2486
2487 return cookie;
2488}
2489
2490static inline void _init_desc(struct dma_pl330_desc *desc)
2491{
2492 desc->req.x = &desc->px;
2493 desc->req.token = desc;
2494 desc->rqcfg.swap = SWAP_NO;
2495 desc->rqcfg.scctl = SCCTRL0;
2496 desc->rqcfg.dcctl = DCCTRL0;
2497 desc->req.cfg = &desc->rqcfg;
2498 desc->req.xfer_cb = dma_pl330_rqcb;
2499 desc->txd.tx_submit = pl330_tx_submit;
2500
2501 INIT_LIST_HEAD(&desc->node);
2502}
2503
2504/* Returns the number of descriptors added to the DMAC pool */
2505static int add_desc(struct dma_pl330_dmac *pdmac, gfp_t flg, int count)
2506{
2507 struct dma_pl330_desc *desc;
2508 unsigned long flags;
2509 int i;
2510
2511 if (!pdmac)
2512 return 0;
2513
2514 desc = kcalloc(count, sizeof(*desc), flg);
2515 if (!desc)
2516 return 0;
2517
2518 spin_lock_irqsave(&pdmac->pool_lock, flags);
2519
2520 for (i = 0; i < count; i++) {
2521 _init_desc(&desc[i]);
2522 list_add_tail(&desc[i].node, &pdmac->desc_pool);
2523 }
2524
2525 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2526
2527 return count;
2528}
2529
2530static struct dma_pl330_desc *
2531pluck_desc(struct dma_pl330_dmac *pdmac)
2532{
2533 struct dma_pl330_desc *desc = NULL;
2534 unsigned long flags;
2535
2536 if (!pdmac)
2537 return NULL;
2538
2539 spin_lock_irqsave(&pdmac->pool_lock, flags);
2540
2541 if (!list_empty(&pdmac->desc_pool)) {
2542 desc = list_entry(pdmac->desc_pool.next,
2543 struct dma_pl330_desc, node);
2544
2545 list_del_init(&desc->node);
2546
2547 desc->status = PREP;
2548 desc->txd.callback = NULL;
2549 }
2550
2551 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2552
2553 return desc;
2554}
2555
2556static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2557{
2558 struct dma_pl330_dmac *pdmac = pch->dmac;
2559 u8 *peri_id = pch->chan.private;
2560 struct dma_pl330_desc *desc;
2561
2562 /* Pluck one desc from the pool of DMAC */
2563 desc = pluck_desc(pdmac);
2564
2565 /* If the DMAC pool is empty, alloc new */
2566 if (!desc) {
2567 if (!add_desc(pdmac, GFP_ATOMIC, 1))
2568 return NULL;
2569
2570 /* Try again */
2571 desc = pluck_desc(pdmac);
2572 if (!desc) {
2573 dev_err(pch->dmac->pif.dev,
2574 "%s:%d ALERT!\n", __func__, __LINE__);
2575 return NULL;
2576 }
2577 }
2578
2579 /* Initialize the descriptor */
2580 desc->pchan = pch;
2581 desc->txd.cookie = 0;
2582 async_tx_ack(&desc->txd);
2583
2584 desc->req.peri = peri_id ? pch->chan.chan_id : 0;
2585 desc->rqcfg.pcfg = &pch->dmac->pif.pcfg;
2586
2587 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2588
2589 return desc;
2590}
2591
2592static inline void fill_px(struct pl330_xfer *px,
2593 dma_addr_t dst, dma_addr_t src, size_t len)
2594{
2595 px->next = NULL;
2596 px->bytes = len;
2597 px->dst_addr = dst;
2598 px->src_addr = src;
2599}
2600
2601static struct dma_pl330_desc *
2602__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2603 dma_addr_t src, size_t len)
2604{
2605 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2606
2607 if (!desc) {
2608 dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n",
2609 __func__, __LINE__);
2610 return NULL;
2611 }
2612
2613 /*
2614 * Ideally we should lookout for reqs bigger than
2615 * those that can be programmed with 256 bytes of
2616 * MC buffer, but considering a req size is seldom
2617 * going to be word-unaligned and more than 200MB,
2618 * we take it easy.
2619 * Also, should the limit is reached we'd rather
2620 * have the platform increase MC buffer size than
2621 * complicating this API driver.
2622 */
2623 fill_px(&desc->px, dst, src, len);
2624
2625 return desc;
2626}
2627
2628/* Call after fixing burst size */
2629static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2630{
2631 struct dma_pl330_chan *pch = desc->pchan;
2632 struct pl330_info *pi = &pch->dmac->pif;
2633 int burst_len;
2634
2635 burst_len = pi->pcfg.data_bus_width / 8;
2636 burst_len *= pi->pcfg.data_buf_dep;
2637 burst_len >>= desc->rqcfg.brst_size;
2638
2639 /* src/dst_burst_len can't be more than 16 */
2640 if (burst_len > 16)
2641 burst_len = 16;
2642
2643 while (burst_len > 1) {
2644 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2645 break;
2646 burst_len--;
2647 }
2648
2649 return burst_len;
2650}
2651
2652static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2653 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2654 size_t period_len, enum dma_transfer_direction direction,
2655 unsigned long flags, void *context)
2656{
2657 struct dma_pl330_desc *desc = NULL, *first = NULL;
2658 struct dma_pl330_chan *pch = to_pchan(chan);
2659 struct dma_pl330_dmac *pdmac = pch->dmac;
2660 unsigned int i;
2661 dma_addr_t dst;
2662 dma_addr_t src;
2663
2664 if (len % period_len != 0)
2665 return NULL;
2666
2667 if (!is_slave_direction(direction)) {
2668 dev_err(pch->dmac->pif.dev, "%s:%d Invalid dma direction\n",
2669 __func__, __LINE__);
2670 return NULL;
2671 }
2672
2673 for (i = 0; i < len / period_len; i++) {
2674 desc = pl330_get_desc(pch);
2675 if (!desc) {
2676 dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n",
2677 __func__, __LINE__);
2678
2679 if (!first)
2680 return NULL;
2681
2682 spin_lock_irqsave(&pdmac->pool_lock, flags);
2683
2684 while (!list_empty(&first->node)) {
2685 desc = list_entry(first->node.next,
2686 struct dma_pl330_desc, node);
2687 list_move_tail(&desc->node, &pdmac->desc_pool);
2688 }
2689
2690 list_move_tail(&first->node, &pdmac->desc_pool);
2691
2692 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2693
2694 return NULL;
2695 }
2696
2697 switch (direction) {
2698 case DMA_MEM_TO_DEV:
2699 desc->rqcfg.src_inc = 1;
2700 desc->rqcfg.dst_inc = 0;
2701 desc->req.rqtype = MEMTODEV;
2702 src = dma_addr;
2703 dst = pch->fifo_addr;
2704 break;
2705 case DMA_DEV_TO_MEM:
2706 desc->rqcfg.src_inc = 0;
2707 desc->rqcfg.dst_inc = 1;
2708 desc->req.rqtype = DEVTOMEM;
2709 src = pch->fifo_addr;
2710 dst = dma_addr;
2711 break;
2712 default:
2713 break;
2714 }
2715
2716 desc->rqcfg.brst_size = pch->burst_sz;
2717 desc->rqcfg.brst_len = 1;
2718 fill_px(&desc->px, dst, src, period_len);
2719
2720 if (!first)
2721 first = desc;
2722 else
2723 list_add_tail(&desc->node, &first->node);
2724
2725 dma_addr += period_len;
2726 }
2727
2728 if (!desc)
2729 return NULL;
2730
2731 pch->cyclic = true;
2732 desc->txd.flags = flags;
2733
2734 return &desc->txd;
2735}
2736
2737static struct dma_async_tx_descriptor *
2738pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2739 dma_addr_t src, size_t len, unsigned long flags)
2740{
2741 struct dma_pl330_desc *desc;
2742 struct dma_pl330_chan *pch = to_pchan(chan);
2743 struct pl330_info *pi;
2744 int burst;
2745
2746 if (unlikely(!pch || !len))
2747 return NULL;
2748
2749 pi = &pch->dmac->pif;
2750
2751 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2752 if (!desc)
2753 return NULL;
2754
2755 desc->rqcfg.src_inc = 1;
2756 desc->rqcfg.dst_inc = 1;
2757 desc->req.rqtype = MEMTOMEM;
2758
2759 /* Select max possible burst size */
2760 burst = pi->pcfg.data_bus_width / 8;
2761
2762 while (burst > 1) {
2763 if (!(len % burst))
2764 break;
2765 burst /= 2;
2766 }
2767
2768 desc->rqcfg.brst_size = 0;
2769 while (burst != (1 << desc->rqcfg.brst_size))
2770 desc->rqcfg.brst_size++;
2771
2772 desc->rqcfg.brst_len = get_burst_len(desc, len);
2773
2774 desc->txd.flags = flags;
2775
2776 return &desc->txd;
2777}
2778
2779static void __pl330_giveback_desc(struct dma_pl330_dmac *pdmac,
2780 struct dma_pl330_desc *first)
2781{
2782 unsigned long flags;
2783 struct dma_pl330_desc *desc;
2784
2785 if (!first)
2786 return;
2787
2788 spin_lock_irqsave(&pdmac->pool_lock, flags);
2789
2790 while (!list_empty(&first->node)) {
2791 desc = list_entry(first->node.next,
2792 struct dma_pl330_desc, node);
2793 list_move_tail(&desc->node, &pdmac->desc_pool);
2794 }
2795
2796 list_move_tail(&first->node, &pdmac->desc_pool);
2797
2798 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2799}
2800
2801static struct dma_async_tx_descriptor *
2802pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2803 unsigned int sg_len, enum dma_transfer_direction direction,
2804 unsigned long flg, void *context)
2805{
2806 struct dma_pl330_desc *first, *desc = NULL;
2807 struct dma_pl330_chan *pch = to_pchan(chan);
2808 struct scatterlist *sg;
2809 int i;
2810 dma_addr_t addr;
2811
2812 if (unlikely(!pch || !sgl || !sg_len))
2813 return NULL;
2814
2815 addr = pch->fifo_addr;
2816
2817 first = NULL;
2818
2819 for_each_sg(sgl, sg, sg_len, i) {
2820
2821 desc = pl330_get_desc(pch);
2822 if (!desc) {
2823 struct dma_pl330_dmac *pdmac = pch->dmac;
2824
2825 dev_err(pch->dmac->pif.dev,
2826 "%s:%d Unable to fetch desc\n",
2827 __func__, __LINE__);
2828 __pl330_giveback_desc(pdmac, first);
2829
2830 return NULL;
2831 }
2832
2833 if (!first)
2834 first = desc;
2835 else
2836 list_add_tail(&desc->node, &first->node);
2837
2838 if (direction == DMA_MEM_TO_DEV) {
2839 desc->rqcfg.src_inc = 1;
2840 desc->rqcfg.dst_inc = 0;
2841 desc->req.rqtype = MEMTODEV;
2842 fill_px(&desc->px,
2843 addr, sg_dma_address(sg), sg_dma_len(sg));
2844 } else {
2845 desc->rqcfg.src_inc = 0;
2846 desc->rqcfg.dst_inc = 1;
2847 desc->req.rqtype = DEVTOMEM;
2848 fill_px(&desc->px,
2849 sg_dma_address(sg), addr, sg_dma_len(sg));
2850 }
2851
2852 desc->rqcfg.brst_size = pch->burst_sz;
2853 desc->rqcfg.brst_len = 1;
2854 }
2855
2856 /* Return the last desc in the chain */
2857 desc->txd.flags = flg;
2858 return &desc->txd;
2859}
2860
2861static irqreturn_t pl330_irq_handler(int irq, void *data)
2862{
2863 if (pl330_update(data))
2864 return IRQ_HANDLED;
2865 else
2866 return IRQ_NONE;
2867}
2868
2869#define PL330_DMA_BUSWIDTHS \
2870 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2871 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2872 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2873 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2874 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2875
2876static int pl330_dma_device_slave_caps(struct dma_chan *dchan,
2877 struct dma_slave_caps *caps)
2878{
2879 caps->src_addr_widths = PL330_DMA_BUSWIDTHS;
2880 caps->dstn_addr_widths = PL330_DMA_BUSWIDTHS;
2881 caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2882 caps->cmd_pause = false;
2883 caps->cmd_terminate = true;
2884 caps->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
2885
2886 return 0;
2887}
2888
2889static int
2890pl330_probe(struct amba_device *adev, const struct amba_id *id)
2891{
2892 struct dma_pl330_platdata *pdat;
2893 struct dma_pl330_dmac *pdmac;
2894 struct dma_pl330_chan *pch, *_p;
2895 struct pl330_info *pi;
2896 struct dma_device *pd;
2897 struct resource *res;
2898 int i, ret, irq;
2899 int num_chan;
2900
2901 pdat = dev_get_platdata(&adev->dev);
2902
2903 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2904 if (ret)
2905 return ret;
2906
2907 /* Allocate a new DMAC and its Channels */
2908 pdmac = devm_kzalloc(&adev->dev, sizeof(*pdmac), GFP_KERNEL);
2909 if (!pdmac) {
2910 dev_err(&adev->dev, "unable to allocate mem\n");
2911 return -ENOMEM;
2912 }
2913
2914 pi = &pdmac->pif;
2915 pi->dev = &adev->dev;
2916 pi->pl330_data = NULL;
2917 pi->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
2918
2919 res = &adev->res;
2920 pi->base = devm_ioremap_resource(&adev->dev, res);
2921 if (IS_ERR(pi->base))
2922 return PTR_ERR(pi->base);
2923
2924 amba_set_drvdata(adev, pdmac);
2925
2926 for (i = 0; i < AMBA_NR_IRQS; i++) {
2927 irq = adev->irq[i];
2928 if (irq) {
2929 ret = devm_request_irq(&adev->dev, irq,
2930 pl330_irq_handler, 0,
2931 dev_name(&adev->dev), pi);
2932 if (ret)
2933 return ret;
2934 } else {
2935 break;
2936 }
2937 }
2938
2939 pi->pcfg.periph_id = adev->periphid;
2940 ret = pl330_add(pi);
2941 if (ret)
2942 return ret;
2943
2944 INIT_LIST_HEAD(&pdmac->desc_pool);
2945 spin_lock_init(&pdmac->pool_lock);
2946
2947 /* Create a descriptor pool of default size */
2948 if (!add_desc(pdmac, GFP_KERNEL, NR_DEFAULT_DESC))
2949 dev_warn(&adev->dev, "unable to allocate desc\n");
2950
2951 pd = &pdmac->ddma;
2952 INIT_LIST_HEAD(&pd->channels);
2953
2954 /* Initialize channel parameters */
2955 if (pdat)
2956 num_chan = max_t(int, pdat->nr_valid_peri, pi->pcfg.num_chan);
2957 else
2958 num_chan = max_t(int, pi->pcfg.num_peri, pi->pcfg.num_chan);
2959
2960 pdmac->num_peripherals = num_chan;
2961
2962 pdmac->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
2963 if (!pdmac->peripherals) {
2964 ret = -ENOMEM;
2965 dev_err(&adev->dev, "unable to allocate pdmac->peripherals\n");
2966 goto probe_err2;
2967 }
2968
2969 for (i = 0; i < num_chan; i++) {
2970 pch = &pdmac->peripherals[i];
2971 if (!adev->dev.of_node)
2972 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2973 else
2974 pch->chan.private = adev->dev.of_node;
2975
2976 INIT_LIST_HEAD(&pch->submitted_list);
2977 INIT_LIST_HEAD(&pch->work_list);
2978 INIT_LIST_HEAD(&pch->completed_list);
2979 spin_lock_init(&pch->lock);
2980 pch->pl330_chid = NULL;
2981 pch->chan.device = pd;
2982 pch->dmac = pdmac;
2983
2984 /* Add the channel to the DMAC list */
2985 list_add_tail(&pch->chan.device_node, &pd->channels);
2986 }
2987
2988 pd->dev = &adev->dev;
2989 if (pdat) {
2990 pd->cap_mask = pdat->cap_mask;
2991 } else {
2992 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
2993 if (pi->pcfg.num_peri) {
2994 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2995 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
2996 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
2997 }
2998 }
2999
3000 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
3001 pd->device_free_chan_resources = pl330_free_chan_resources;
3002 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
3003 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
3004 pd->device_tx_status = pl330_tx_status;
3005 pd->device_prep_slave_sg = pl330_prep_slave_sg;
3006 pd->device_control = pl330_control;
3007 pd->device_issue_pending = pl330_issue_pending;
3008 pd->device_slave_caps = pl330_dma_device_slave_caps;
3009
3010 ret = dma_async_device_register(pd);
3011 if (ret) {
3012 dev_err(&adev->dev, "unable to register DMAC\n");
3013 goto probe_err3;
3014 }
3015
3016 if (adev->dev.of_node) {
3017 ret = of_dma_controller_register(adev->dev.of_node,
3018 of_dma_pl330_xlate, pdmac);
3019 if (ret) {
3020 dev_err(&adev->dev,
3021 "unable to register DMA to the generic DT DMA helpers\n");
3022 }
3023 }
3024
3025 adev->dev.dma_parms = &pdmac->dma_parms;
3026
3027 /*
3028 * This is the limit for transfers with a buswidth of 1, larger
3029 * buswidths will have larger limits.
3030 */
3031 ret = dma_set_max_seg_size(&adev->dev, 1900800);
3032 if (ret)
3033 dev_err(&adev->dev, "unable to set the seg size\n");
3034
3035
3036 dev_info(&adev->dev,
3037 "Loaded driver for PL330 DMAC-%d\n", adev->periphid);
3038 dev_info(&adev->dev,
3039 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
3040 pi->pcfg.data_buf_dep,
3041 pi->pcfg.data_bus_width / 8, pi->pcfg.num_chan,
3042 pi->pcfg.num_peri, pi->pcfg.num_events);
3043
3044 return 0;
3045probe_err3:
3046 /* Idle the DMAC */
3047 list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels,
3048 chan.device_node) {
3049
3050 /* Remove the channel */
3051 list_del(&pch->chan.device_node);
3052
3053 /* Flush the channel */
3054 pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0);
3055 pl330_free_chan_resources(&pch->chan);
3056 }
3057probe_err2:
3058 pl330_del(pi);
3059
3060 return ret;
3061}
3062
3063static int pl330_remove(struct amba_device *adev)
3064{
3065 struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev);
3066 struct dma_pl330_chan *pch, *_p;
3067 struct pl330_info *pi;
3068
3069 if (!pdmac)
3070 return 0;
3071
3072 if (adev->dev.of_node)
3073 of_dma_controller_free(adev->dev.of_node);
3074
3075 dma_async_device_unregister(&pdmac->ddma);
3076
3077 /* Idle the DMAC */
3078 list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels,
3079 chan.device_node) {
3080
3081 /* Remove the channel */
3082 list_del(&pch->chan.device_node);
3083
3084 /* Flush the channel */
3085 pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0);
3086 pl330_free_chan_resources(&pch->chan);
3087 }
3088
3089 pi = &pdmac->pif;
3090
3091 pl330_del(pi);
3092
3093 return 0;
3094}
3095
3096static struct amba_id pl330_ids[] = {
3097 {
3098 .id = 0x00041330,
3099 .mask = 0x000fffff,
3100 },
3101 { 0, 0 },
3102};
3103
3104MODULE_DEVICE_TABLE(amba, pl330_ids);
3105
3106static struct amba_driver pl330_driver = {
3107 .drv = {
3108 .owner = THIS_MODULE,
3109 .name = "dma-pl330",
3110 },
3111 .id_table = pl330_ids,
3112 .probe = pl330_probe,
3113 .remove = pl330_remove,
3114};
3115
3116module_amba_driver(pl330_driver);
3117
3118MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
3119MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3120MODULE_LICENSE("GPL");
1/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <linux/init.h>
17#include <linux/slab.h>
18#include <linux/module.h>
19#include <linux/string.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmaengine.h>
24#include <linux/amba/bus.h>
25#include <linux/amba/pl330.h>
26#include <linux/scatterlist.h>
27#include <linux/of.h>
28#include <linux/of_dma.h>
29#include <linux/err.h>
30#include <linux/pm_runtime.h>
31
32#include "dmaengine.h"
33#define PL330_MAX_CHAN 8
34#define PL330_MAX_IRQS 32
35#define PL330_MAX_PERI 32
36#define PL330_MAX_BURST 16
37
38#define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
39
40enum pl330_cachectrl {
41 CCTRL0, /* Noncacheable and nonbufferable */
42 CCTRL1, /* Bufferable only */
43 CCTRL2, /* Cacheable, but do not allocate */
44 CCTRL3, /* Cacheable and bufferable, but do not allocate */
45 INVALID1, /* AWCACHE = 0x1000 */
46 INVALID2,
47 CCTRL6, /* Cacheable write-through, allocate on writes only */
48 CCTRL7, /* Cacheable write-back, allocate on writes only */
49};
50
51enum pl330_byteswap {
52 SWAP_NO,
53 SWAP_2,
54 SWAP_4,
55 SWAP_8,
56 SWAP_16,
57};
58
59/* Register and Bit field Definitions */
60#define DS 0x0
61#define DS_ST_STOP 0x0
62#define DS_ST_EXEC 0x1
63#define DS_ST_CMISS 0x2
64#define DS_ST_UPDTPC 0x3
65#define DS_ST_WFE 0x4
66#define DS_ST_ATBRR 0x5
67#define DS_ST_QBUSY 0x6
68#define DS_ST_WFP 0x7
69#define DS_ST_KILL 0x8
70#define DS_ST_CMPLT 0x9
71#define DS_ST_FLTCMP 0xe
72#define DS_ST_FAULT 0xf
73
74#define DPC 0x4
75#define INTEN 0x20
76#define ES 0x24
77#define INTSTATUS 0x28
78#define INTCLR 0x2c
79#define FSM 0x30
80#define FSC 0x34
81#define FTM 0x38
82
83#define _FTC 0x40
84#define FTC(n) (_FTC + (n)*0x4)
85
86#define _CS 0x100
87#define CS(n) (_CS + (n)*0x8)
88#define CS_CNS (1 << 21)
89
90#define _CPC 0x104
91#define CPC(n) (_CPC + (n)*0x8)
92
93#define _SA 0x400
94#define SA(n) (_SA + (n)*0x20)
95
96#define _DA 0x404
97#define DA(n) (_DA + (n)*0x20)
98
99#define _CC 0x408
100#define CC(n) (_CC + (n)*0x20)
101
102#define CC_SRCINC (1 << 0)
103#define CC_DSTINC (1 << 14)
104#define CC_SRCPRI (1 << 8)
105#define CC_DSTPRI (1 << 22)
106#define CC_SRCNS (1 << 9)
107#define CC_DSTNS (1 << 23)
108#define CC_SRCIA (1 << 10)
109#define CC_DSTIA (1 << 24)
110#define CC_SRCBRSTLEN_SHFT 4
111#define CC_DSTBRSTLEN_SHFT 18
112#define CC_SRCBRSTSIZE_SHFT 1
113#define CC_DSTBRSTSIZE_SHFT 15
114#define CC_SRCCCTRL_SHFT 11
115#define CC_SRCCCTRL_MASK 0x7
116#define CC_DSTCCTRL_SHFT 25
117#define CC_DRCCCTRL_MASK 0x7
118#define CC_SWAP_SHFT 28
119
120#define _LC0 0x40c
121#define LC0(n) (_LC0 + (n)*0x20)
122
123#define _LC1 0x410
124#define LC1(n) (_LC1 + (n)*0x20)
125
126#define DBGSTATUS 0xd00
127#define DBG_BUSY (1 << 0)
128
129#define DBGCMD 0xd04
130#define DBGINST0 0xd08
131#define DBGINST1 0xd0c
132
133#define CR0 0xe00
134#define CR1 0xe04
135#define CR2 0xe08
136#define CR3 0xe0c
137#define CR4 0xe10
138#define CRD 0xe14
139
140#define PERIPH_ID 0xfe0
141#define PERIPH_REV_SHIFT 20
142#define PERIPH_REV_MASK 0xf
143#define PERIPH_REV_R0P0 0
144#define PERIPH_REV_R1P0 1
145#define PERIPH_REV_R1P1 2
146
147#define CR0_PERIPH_REQ_SET (1 << 0)
148#define CR0_BOOT_EN_SET (1 << 1)
149#define CR0_BOOT_MAN_NS (1 << 2)
150#define CR0_NUM_CHANS_SHIFT 4
151#define CR0_NUM_CHANS_MASK 0x7
152#define CR0_NUM_PERIPH_SHIFT 12
153#define CR0_NUM_PERIPH_MASK 0x1f
154#define CR0_NUM_EVENTS_SHIFT 17
155#define CR0_NUM_EVENTS_MASK 0x1f
156
157#define CR1_ICACHE_LEN_SHIFT 0
158#define CR1_ICACHE_LEN_MASK 0x7
159#define CR1_NUM_ICACHELINES_SHIFT 4
160#define CR1_NUM_ICACHELINES_MASK 0xf
161
162#define CRD_DATA_WIDTH_SHIFT 0
163#define CRD_DATA_WIDTH_MASK 0x7
164#define CRD_WR_CAP_SHIFT 4
165#define CRD_WR_CAP_MASK 0x7
166#define CRD_WR_Q_DEP_SHIFT 8
167#define CRD_WR_Q_DEP_MASK 0xf
168#define CRD_RD_CAP_SHIFT 12
169#define CRD_RD_CAP_MASK 0x7
170#define CRD_RD_Q_DEP_SHIFT 16
171#define CRD_RD_Q_DEP_MASK 0xf
172#define CRD_DATA_BUFF_SHIFT 20
173#define CRD_DATA_BUFF_MASK 0x3ff
174
175#define PART 0x330
176#define DESIGNER 0x41
177#define REVISION 0x0
178#define INTEG_CFG 0x0
179#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
180
181#define PL330_STATE_STOPPED (1 << 0)
182#define PL330_STATE_EXECUTING (1 << 1)
183#define PL330_STATE_WFE (1 << 2)
184#define PL330_STATE_FAULTING (1 << 3)
185#define PL330_STATE_COMPLETING (1 << 4)
186#define PL330_STATE_WFP (1 << 5)
187#define PL330_STATE_KILLING (1 << 6)
188#define PL330_STATE_FAULT_COMPLETING (1 << 7)
189#define PL330_STATE_CACHEMISS (1 << 8)
190#define PL330_STATE_UPDTPC (1 << 9)
191#define PL330_STATE_ATBARRIER (1 << 10)
192#define PL330_STATE_QUEUEBUSY (1 << 11)
193#define PL330_STATE_INVALID (1 << 15)
194
195#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
196 | PL330_STATE_WFE | PL330_STATE_FAULTING)
197
198#define CMD_DMAADDH 0x54
199#define CMD_DMAEND 0x00
200#define CMD_DMAFLUSHP 0x35
201#define CMD_DMAGO 0xa0
202#define CMD_DMALD 0x04
203#define CMD_DMALDP 0x25
204#define CMD_DMALP 0x20
205#define CMD_DMALPEND 0x28
206#define CMD_DMAKILL 0x01
207#define CMD_DMAMOV 0xbc
208#define CMD_DMANOP 0x18
209#define CMD_DMARMB 0x12
210#define CMD_DMASEV 0x34
211#define CMD_DMAST 0x08
212#define CMD_DMASTP 0x29
213#define CMD_DMASTZ 0x0c
214#define CMD_DMAWFE 0x36
215#define CMD_DMAWFP 0x30
216#define CMD_DMAWMB 0x13
217
218#define SZ_DMAADDH 3
219#define SZ_DMAEND 1
220#define SZ_DMAFLUSHP 2
221#define SZ_DMALD 1
222#define SZ_DMALDP 2
223#define SZ_DMALP 2
224#define SZ_DMALPEND 2
225#define SZ_DMAKILL 1
226#define SZ_DMAMOV 6
227#define SZ_DMANOP 1
228#define SZ_DMARMB 1
229#define SZ_DMASEV 2
230#define SZ_DMAST 1
231#define SZ_DMASTP 2
232#define SZ_DMASTZ 1
233#define SZ_DMAWFE 2
234#define SZ_DMAWFP 2
235#define SZ_DMAWMB 1
236#define SZ_DMAGO 6
237
238#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
239#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
240
241#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
242#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
243
244/*
245 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
246 * at 1byte/burst for P<->M and M<->M respectively.
247 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
248 * should be enough for P<->M and M<->M respectively.
249 */
250#define MCODE_BUFF_PER_REQ 256
251
252/* Use this _only_ to wait on transient states */
253#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
254
255#ifdef PL330_DEBUG_MCGEN
256static unsigned cmd_line;
257#define PL330_DBGCMD_DUMP(off, x...) do { \
258 printk("%x:", cmd_line); \
259 printk(x); \
260 cmd_line += off; \
261 } while (0)
262#define PL330_DBGMC_START(addr) (cmd_line = addr)
263#else
264#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
265#define PL330_DBGMC_START(addr) do {} while (0)
266#endif
267
268/* The number of default descriptors */
269
270#define NR_DEFAULT_DESC 16
271
272/* Delay for runtime PM autosuspend, ms */
273#define PL330_AUTOSUSPEND_DELAY 20
274
275/* Populated by the PL330 core driver for DMA API driver's info */
276struct pl330_config {
277 u32 periph_id;
278#define DMAC_MODE_NS (1 << 0)
279 unsigned int mode;
280 unsigned int data_bus_width:10; /* In number of bits */
281 unsigned int data_buf_dep:11;
282 unsigned int num_chan:4;
283 unsigned int num_peri:6;
284 u32 peri_ns;
285 unsigned int num_events:6;
286 u32 irq_ns;
287};
288
289/**
290 * Request Configuration.
291 * The PL330 core does not modify this and uses the last
292 * working configuration if the request doesn't provide any.
293 *
294 * The Client may want to provide this info only for the
295 * first request and a request with new settings.
296 */
297struct pl330_reqcfg {
298 /* Address Incrementing */
299 unsigned dst_inc:1;
300 unsigned src_inc:1;
301
302 /*
303 * For now, the SRC & DST protection levels
304 * and burst size/length are assumed same.
305 */
306 bool nonsecure;
307 bool privileged;
308 bool insnaccess;
309 unsigned brst_len:5;
310 unsigned brst_size:3; /* in power of 2 */
311
312 enum pl330_cachectrl dcctl;
313 enum pl330_cachectrl scctl;
314 enum pl330_byteswap swap;
315 struct pl330_config *pcfg;
316};
317
318/*
319 * One cycle of DMAC operation.
320 * There may be more than one xfer in a request.
321 */
322struct pl330_xfer {
323 u32 src_addr;
324 u32 dst_addr;
325 /* Size to xfer */
326 u32 bytes;
327};
328
329/* The xfer callbacks are made with one of these arguments. */
330enum pl330_op_err {
331 /* The all xfers in the request were success. */
332 PL330_ERR_NONE,
333 /* If req aborted due to global error. */
334 PL330_ERR_ABORT,
335 /* If req failed due to problem with Channel. */
336 PL330_ERR_FAIL,
337};
338
339enum dmamov_dst {
340 SAR = 0,
341 CCR,
342 DAR,
343};
344
345enum pl330_dst {
346 SRC = 0,
347 DST,
348};
349
350enum pl330_cond {
351 SINGLE,
352 BURST,
353 ALWAYS,
354};
355
356struct dma_pl330_desc;
357
358struct _pl330_req {
359 u32 mc_bus;
360 void *mc_cpu;
361 struct dma_pl330_desc *desc;
362};
363
364/* ToBeDone for tasklet */
365struct _pl330_tbd {
366 bool reset_dmac;
367 bool reset_mngr;
368 u8 reset_chan;
369};
370
371/* A DMAC Thread */
372struct pl330_thread {
373 u8 id;
374 int ev;
375 /* If the channel is not yet acquired by any client */
376 bool free;
377 /* Parent DMAC */
378 struct pl330_dmac *dmac;
379 /* Only two at a time */
380 struct _pl330_req req[2];
381 /* Index of the last enqueued request */
382 unsigned lstenq;
383 /* Index of the last submitted request or -1 if the DMA is stopped */
384 int req_running;
385};
386
387enum pl330_dmac_state {
388 UNINIT,
389 INIT,
390 DYING,
391};
392
393enum desc_status {
394 /* In the DMAC pool */
395 FREE,
396 /*
397 * Allocated to some channel during prep_xxx
398 * Also may be sitting on the work_list.
399 */
400 PREP,
401 /*
402 * Sitting on the work_list and already submitted
403 * to the PL330 core. Not more than two descriptors
404 * of a channel can be BUSY at any time.
405 */
406 BUSY,
407 /*
408 * Sitting on the channel work_list but xfer done
409 * by PL330 core
410 */
411 DONE,
412};
413
414struct dma_pl330_chan {
415 /* Schedule desc completion */
416 struct tasklet_struct task;
417
418 /* DMA-Engine Channel */
419 struct dma_chan chan;
420
421 /* List of submitted descriptors */
422 struct list_head submitted_list;
423 /* List of issued descriptors */
424 struct list_head work_list;
425 /* List of completed descriptors */
426 struct list_head completed_list;
427
428 /* Pointer to the DMAC that manages this channel,
429 * NULL if the channel is available to be acquired.
430 * As the parent, this DMAC also provides descriptors
431 * to the channel.
432 */
433 struct pl330_dmac *dmac;
434
435 /* To protect channel manipulation */
436 spinlock_t lock;
437
438 /*
439 * Hardware channel thread of PL330 DMAC. NULL if the channel is
440 * available.
441 */
442 struct pl330_thread *thread;
443
444 /* For D-to-M and M-to-D channels */
445 int burst_sz; /* the peripheral fifo width */
446 int burst_len; /* the number of burst */
447 dma_addr_t fifo_addr;
448
449 /* for cyclic capability */
450 bool cyclic;
451};
452
453struct pl330_dmac {
454 /* DMA-Engine Device */
455 struct dma_device ddma;
456
457 /* Holds info about sg limitations */
458 struct device_dma_parameters dma_parms;
459
460 /* Pool of descriptors available for the DMAC's channels */
461 struct list_head desc_pool;
462 /* To protect desc_pool manipulation */
463 spinlock_t pool_lock;
464
465 /* Size of MicroCode buffers for each channel. */
466 unsigned mcbufsz;
467 /* ioremap'ed address of PL330 registers. */
468 void __iomem *base;
469 /* Populated by the PL330 core driver during pl330_add */
470 struct pl330_config pcfg;
471
472 spinlock_t lock;
473 /* Maximum possible events/irqs */
474 int events[32];
475 /* BUS address of MicroCode buffer */
476 dma_addr_t mcode_bus;
477 /* CPU address of MicroCode buffer */
478 void *mcode_cpu;
479 /* List of all Channel threads */
480 struct pl330_thread *channels;
481 /* Pointer to the MANAGER thread */
482 struct pl330_thread *manager;
483 /* To handle bad news in interrupt */
484 struct tasklet_struct tasks;
485 struct _pl330_tbd dmac_tbd;
486 /* State of DMAC operation */
487 enum pl330_dmac_state state;
488 /* Holds list of reqs with due callbacks */
489 struct list_head req_done;
490
491 /* Peripheral channels connected to this DMAC */
492 unsigned int num_peripherals;
493 struct dma_pl330_chan *peripherals; /* keep at end */
494 int quirks;
495};
496
497static struct pl330_of_quirks {
498 char *quirk;
499 int id;
500} of_quirks[] = {
501 {
502 .quirk = "arm,pl330-broken-no-flushp",
503 .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
504 }
505};
506
507struct dma_pl330_desc {
508 /* To attach to a queue as child */
509 struct list_head node;
510
511 /* Descriptor for the DMA Engine API */
512 struct dma_async_tx_descriptor txd;
513
514 /* Xfer for PL330 core */
515 struct pl330_xfer px;
516
517 struct pl330_reqcfg rqcfg;
518
519 enum desc_status status;
520
521 int bytes_requested;
522 bool last;
523
524 /* The channel which currently holds this desc */
525 struct dma_pl330_chan *pchan;
526
527 enum dma_transfer_direction rqtype;
528 /* Index of peripheral for the xfer. */
529 unsigned peri:5;
530 /* Hook to attach to DMAC's list of reqs with due callback */
531 struct list_head rqd;
532};
533
534struct _xfer_spec {
535 u32 ccr;
536 struct dma_pl330_desc *desc;
537};
538
539static inline bool _queue_empty(struct pl330_thread *thrd)
540{
541 return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL;
542}
543
544static inline bool _queue_full(struct pl330_thread *thrd)
545{
546 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
547}
548
549static inline bool is_manager(struct pl330_thread *thrd)
550{
551 return thrd->dmac->manager == thrd;
552}
553
554/* If manager of the thread is in Non-Secure mode */
555static inline bool _manager_ns(struct pl330_thread *thrd)
556{
557 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
558}
559
560static inline u32 get_revision(u32 periph_id)
561{
562 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
563}
564
565static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
566 enum pl330_dst da, u16 val)
567{
568 if (dry_run)
569 return SZ_DMAADDH;
570
571 buf[0] = CMD_DMAADDH;
572 buf[0] |= (da << 1);
573 *((__le16 *)&buf[1]) = cpu_to_le16(val);
574
575 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
576 da == 1 ? "DA" : "SA", val);
577
578 return SZ_DMAADDH;
579}
580
581static inline u32 _emit_END(unsigned dry_run, u8 buf[])
582{
583 if (dry_run)
584 return SZ_DMAEND;
585
586 buf[0] = CMD_DMAEND;
587
588 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
589
590 return SZ_DMAEND;
591}
592
593static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
594{
595 if (dry_run)
596 return SZ_DMAFLUSHP;
597
598 buf[0] = CMD_DMAFLUSHP;
599
600 peri &= 0x1f;
601 peri <<= 3;
602 buf[1] = peri;
603
604 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
605
606 return SZ_DMAFLUSHP;
607}
608
609static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
610{
611 if (dry_run)
612 return SZ_DMALD;
613
614 buf[0] = CMD_DMALD;
615
616 if (cond == SINGLE)
617 buf[0] |= (0 << 1) | (1 << 0);
618 else if (cond == BURST)
619 buf[0] |= (1 << 1) | (1 << 0);
620
621 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
622 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
623
624 return SZ_DMALD;
625}
626
627static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
628 enum pl330_cond cond, u8 peri)
629{
630 if (dry_run)
631 return SZ_DMALDP;
632
633 buf[0] = CMD_DMALDP;
634
635 if (cond == BURST)
636 buf[0] |= (1 << 1);
637
638 peri &= 0x1f;
639 peri <<= 3;
640 buf[1] = peri;
641
642 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
643 cond == SINGLE ? 'S' : 'B', peri >> 3);
644
645 return SZ_DMALDP;
646}
647
648static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
649 unsigned loop, u8 cnt)
650{
651 if (dry_run)
652 return SZ_DMALP;
653
654 buf[0] = CMD_DMALP;
655
656 if (loop)
657 buf[0] |= (1 << 1);
658
659 cnt--; /* DMAC increments by 1 internally */
660 buf[1] = cnt;
661
662 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
663
664 return SZ_DMALP;
665}
666
667struct _arg_LPEND {
668 enum pl330_cond cond;
669 bool forever;
670 unsigned loop;
671 u8 bjump;
672};
673
674static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
675 const struct _arg_LPEND *arg)
676{
677 enum pl330_cond cond = arg->cond;
678 bool forever = arg->forever;
679 unsigned loop = arg->loop;
680 u8 bjump = arg->bjump;
681
682 if (dry_run)
683 return SZ_DMALPEND;
684
685 buf[0] = CMD_DMALPEND;
686
687 if (loop)
688 buf[0] |= (1 << 2);
689
690 if (!forever)
691 buf[0] |= (1 << 4);
692
693 if (cond == SINGLE)
694 buf[0] |= (0 << 1) | (1 << 0);
695 else if (cond == BURST)
696 buf[0] |= (1 << 1) | (1 << 0);
697
698 buf[1] = bjump;
699
700 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
701 forever ? "FE" : "END",
702 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
703 loop ? '1' : '0',
704 bjump);
705
706 return SZ_DMALPEND;
707}
708
709static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
710{
711 if (dry_run)
712 return SZ_DMAKILL;
713
714 buf[0] = CMD_DMAKILL;
715
716 return SZ_DMAKILL;
717}
718
719static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
720 enum dmamov_dst dst, u32 val)
721{
722 if (dry_run)
723 return SZ_DMAMOV;
724
725 buf[0] = CMD_DMAMOV;
726 buf[1] = dst;
727 *((__le32 *)&buf[2]) = cpu_to_le32(val);
728
729 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
730 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
731
732 return SZ_DMAMOV;
733}
734
735static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
736{
737 if (dry_run)
738 return SZ_DMANOP;
739
740 buf[0] = CMD_DMANOP;
741
742 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
743
744 return SZ_DMANOP;
745}
746
747static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
748{
749 if (dry_run)
750 return SZ_DMARMB;
751
752 buf[0] = CMD_DMARMB;
753
754 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
755
756 return SZ_DMARMB;
757}
758
759static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
760{
761 if (dry_run)
762 return SZ_DMASEV;
763
764 buf[0] = CMD_DMASEV;
765
766 ev &= 0x1f;
767 ev <<= 3;
768 buf[1] = ev;
769
770 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
771
772 return SZ_DMASEV;
773}
774
775static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
776{
777 if (dry_run)
778 return SZ_DMAST;
779
780 buf[0] = CMD_DMAST;
781
782 if (cond == SINGLE)
783 buf[0] |= (0 << 1) | (1 << 0);
784 else if (cond == BURST)
785 buf[0] |= (1 << 1) | (1 << 0);
786
787 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
788 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
789
790 return SZ_DMAST;
791}
792
793static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
794 enum pl330_cond cond, u8 peri)
795{
796 if (dry_run)
797 return SZ_DMASTP;
798
799 buf[0] = CMD_DMASTP;
800
801 if (cond == BURST)
802 buf[0] |= (1 << 1);
803
804 peri &= 0x1f;
805 peri <<= 3;
806 buf[1] = peri;
807
808 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
809 cond == SINGLE ? 'S' : 'B', peri >> 3);
810
811 return SZ_DMASTP;
812}
813
814static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
815{
816 if (dry_run)
817 return SZ_DMASTZ;
818
819 buf[0] = CMD_DMASTZ;
820
821 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
822
823 return SZ_DMASTZ;
824}
825
826static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
827 unsigned invalidate)
828{
829 if (dry_run)
830 return SZ_DMAWFE;
831
832 buf[0] = CMD_DMAWFE;
833
834 ev &= 0x1f;
835 ev <<= 3;
836 buf[1] = ev;
837
838 if (invalidate)
839 buf[1] |= (1 << 1);
840
841 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
842 ev >> 3, invalidate ? ", I" : "");
843
844 return SZ_DMAWFE;
845}
846
847static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
848 enum pl330_cond cond, u8 peri)
849{
850 if (dry_run)
851 return SZ_DMAWFP;
852
853 buf[0] = CMD_DMAWFP;
854
855 if (cond == SINGLE)
856 buf[0] |= (0 << 1) | (0 << 0);
857 else if (cond == BURST)
858 buf[0] |= (1 << 1) | (0 << 0);
859 else
860 buf[0] |= (0 << 1) | (1 << 0);
861
862 peri &= 0x1f;
863 peri <<= 3;
864 buf[1] = peri;
865
866 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
867 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
868
869 return SZ_DMAWFP;
870}
871
872static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
873{
874 if (dry_run)
875 return SZ_DMAWMB;
876
877 buf[0] = CMD_DMAWMB;
878
879 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
880
881 return SZ_DMAWMB;
882}
883
884struct _arg_GO {
885 u8 chan;
886 u32 addr;
887 unsigned ns;
888};
889
890static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
891 const struct _arg_GO *arg)
892{
893 u8 chan = arg->chan;
894 u32 addr = arg->addr;
895 unsigned ns = arg->ns;
896
897 if (dry_run)
898 return SZ_DMAGO;
899
900 buf[0] = CMD_DMAGO;
901 buf[0] |= (ns << 1);
902
903 buf[1] = chan & 0x7;
904
905 *((__le32 *)&buf[2]) = cpu_to_le32(addr);
906
907 return SZ_DMAGO;
908}
909
910#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
911
912/* Returns Time-Out */
913static bool _until_dmac_idle(struct pl330_thread *thrd)
914{
915 void __iomem *regs = thrd->dmac->base;
916 unsigned long loops = msecs_to_loops(5);
917
918 do {
919 /* Until Manager is Idle */
920 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
921 break;
922
923 cpu_relax();
924 } while (--loops);
925
926 if (!loops)
927 return true;
928
929 return false;
930}
931
932static inline void _execute_DBGINSN(struct pl330_thread *thrd,
933 u8 insn[], bool as_manager)
934{
935 void __iomem *regs = thrd->dmac->base;
936 u32 val;
937
938 val = (insn[0] << 16) | (insn[1] << 24);
939 if (!as_manager) {
940 val |= (1 << 0);
941 val |= (thrd->id << 8); /* Channel Number */
942 }
943 writel(val, regs + DBGINST0);
944
945 val = le32_to_cpu(*((__le32 *)&insn[2]));
946 writel(val, regs + DBGINST1);
947
948 /* If timed out due to halted state-machine */
949 if (_until_dmac_idle(thrd)) {
950 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
951 return;
952 }
953
954 /* Get going */
955 writel(0, regs + DBGCMD);
956}
957
958static inline u32 _state(struct pl330_thread *thrd)
959{
960 void __iomem *regs = thrd->dmac->base;
961 u32 val;
962
963 if (is_manager(thrd))
964 val = readl(regs + DS) & 0xf;
965 else
966 val = readl(regs + CS(thrd->id)) & 0xf;
967
968 switch (val) {
969 case DS_ST_STOP:
970 return PL330_STATE_STOPPED;
971 case DS_ST_EXEC:
972 return PL330_STATE_EXECUTING;
973 case DS_ST_CMISS:
974 return PL330_STATE_CACHEMISS;
975 case DS_ST_UPDTPC:
976 return PL330_STATE_UPDTPC;
977 case DS_ST_WFE:
978 return PL330_STATE_WFE;
979 case DS_ST_FAULT:
980 return PL330_STATE_FAULTING;
981 case DS_ST_ATBRR:
982 if (is_manager(thrd))
983 return PL330_STATE_INVALID;
984 else
985 return PL330_STATE_ATBARRIER;
986 case DS_ST_QBUSY:
987 if (is_manager(thrd))
988 return PL330_STATE_INVALID;
989 else
990 return PL330_STATE_QUEUEBUSY;
991 case DS_ST_WFP:
992 if (is_manager(thrd))
993 return PL330_STATE_INVALID;
994 else
995 return PL330_STATE_WFP;
996 case DS_ST_KILL:
997 if (is_manager(thrd))
998 return PL330_STATE_INVALID;
999 else
1000 return PL330_STATE_KILLING;
1001 case DS_ST_CMPLT:
1002 if (is_manager(thrd))
1003 return PL330_STATE_INVALID;
1004 else
1005 return PL330_STATE_COMPLETING;
1006 case DS_ST_FLTCMP:
1007 if (is_manager(thrd))
1008 return PL330_STATE_INVALID;
1009 else
1010 return PL330_STATE_FAULT_COMPLETING;
1011 default:
1012 return PL330_STATE_INVALID;
1013 }
1014}
1015
1016static void _stop(struct pl330_thread *thrd)
1017{
1018 void __iomem *regs = thrd->dmac->base;
1019 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1020
1021 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1022 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1023
1024 /* Return if nothing needs to be done */
1025 if (_state(thrd) == PL330_STATE_COMPLETING
1026 || _state(thrd) == PL330_STATE_KILLING
1027 || _state(thrd) == PL330_STATE_STOPPED)
1028 return;
1029
1030 _emit_KILL(0, insn);
1031
1032 /* Stop generating interrupts for SEV */
1033 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1034
1035 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1036}
1037
1038/* Start doing req 'idx' of thread 'thrd' */
1039static bool _trigger(struct pl330_thread *thrd)
1040{
1041 void __iomem *regs = thrd->dmac->base;
1042 struct _pl330_req *req;
1043 struct dma_pl330_desc *desc;
1044 struct _arg_GO go;
1045 unsigned ns;
1046 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1047 int idx;
1048
1049 /* Return if already ACTIVE */
1050 if (_state(thrd) != PL330_STATE_STOPPED)
1051 return true;
1052
1053 idx = 1 - thrd->lstenq;
1054 if (thrd->req[idx].desc != NULL) {
1055 req = &thrd->req[idx];
1056 } else {
1057 idx = thrd->lstenq;
1058 if (thrd->req[idx].desc != NULL)
1059 req = &thrd->req[idx];
1060 else
1061 req = NULL;
1062 }
1063
1064 /* Return if no request */
1065 if (!req)
1066 return true;
1067
1068 /* Return if req is running */
1069 if (idx == thrd->req_running)
1070 return true;
1071
1072 desc = req->desc;
1073
1074 ns = desc->rqcfg.nonsecure ? 1 : 0;
1075
1076 /* See 'Abort Sources' point-4 at Page 2-25 */
1077 if (_manager_ns(thrd) && !ns)
1078 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1079 __func__, __LINE__);
1080
1081 go.chan = thrd->id;
1082 go.addr = req->mc_bus;
1083 go.ns = ns;
1084 _emit_GO(0, insn, &go);
1085
1086 /* Set to generate interrupts for SEV */
1087 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1088
1089 /* Only manager can execute GO */
1090 _execute_DBGINSN(thrd, insn, true);
1091
1092 thrd->req_running = idx;
1093
1094 return true;
1095}
1096
1097static bool _start(struct pl330_thread *thrd)
1098{
1099 switch (_state(thrd)) {
1100 case PL330_STATE_FAULT_COMPLETING:
1101 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1102
1103 if (_state(thrd) == PL330_STATE_KILLING)
1104 UNTIL(thrd, PL330_STATE_STOPPED)
1105
1106 case PL330_STATE_FAULTING:
1107 _stop(thrd);
1108
1109 case PL330_STATE_KILLING:
1110 case PL330_STATE_COMPLETING:
1111 UNTIL(thrd, PL330_STATE_STOPPED)
1112
1113 case PL330_STATE_STOPPED:
1114 return _trigger(thrd);
1115
1116 case PL330_STATE_WFP:
1117 case PL330_STATE_QUEUEBUSY:
1118 case PL330_STATE_ATBARRIER:
1119 case PL330_STATE_UPDTPC:
1120 case PL330_STATE_CACHEMISS:
1121 case PL330_STATE_EXECUTING:
1122 return true;
1123
1124 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1125 default:
1126 return false;
1127 }
1128}
1129
1130static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1131 const struct _xfer_spec *pxs, int cyc)
1132{
1133 int off = 0;
1134 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1135
1136 /* check lock-up free version */
1137 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1138 while (cyc--) {
1139 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1140 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1141 }
1142 } else {
1143 while (cyc--) {
1144 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1145 off += _emit_RMB(dry_run, &buf[off]);
1146 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1147 off += _emit_WMB(dry_run, &buf[off]);
1148 }
1149 }
1150
1151 return off;
1152}
1153
1154static inline int _ldst_devtomem(struct pl330_dmac *pl330, unsigned dry_run,
1155 u8 buf[], const struct _xfer_spec *pxs,
1156 int cyc)
1157{
1158 int off = 0;
1159 enum pl330_cond cond;
1160
1161 if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
1162 cond = BURST;
1163 else
1164 cond = SINGLE;
1165
1166 while (cyc--) {
1167 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1168 off += _emit_LDP(dry_run, &buf[off], cond, pxs->desc->peri);
1169 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1170
1171 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1172 off += _emit_FLUSHP(dry_run, &buf[off],
1173 pxs->desc->peri);
1174 }
1175
1176 return off;
1177}
1178
1179static inline int _ldst_memtodev(struct pl330_dmac *pl330,
1180 unsigned dry_run, u8 buf[],
1181 const struct _xfer_spec *pxs, int cyc)
1182{
1183 int off = 0;
1184 enum pl330_cond cond;
1185
1186 if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
1187 cond = BURST;
1188 else
1189 cond = SINGLE;
1190
1191 while (cyc--) {
1192 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1193 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1194 off += _emit_STP(dry_run, &buf[off], cond, pxs->desc->peri);
1195
1196 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1197 off += _emit_FLUSHP(dry_run, &buf[off],
1198 pxs->desc->peri);
1199 }
1200
1201 return off;
1202}
1203
1204static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1205 const struct _xfer_spec *pxs, int cyc)
1206{
1207 int off = 0;
1208
1209 switch (pxs->desc->rqtype) {
1210 case DMA_MEM_TO_DEV:
1211 off += _ldst_memtodev(pl330, dry_run, &buf[off], pxs, cyc);
1212 break;
1213 case DMA_DEV_TO_MEM:
1214 off += _ldst_devtomem(pl330, dry_run, &buf[off], pxs, cyc);
1215 break;
1216 case DMA_MEM_TO_MEM:
1217 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1218 break;
1219 default:
1220 off += 0x40000000; /* Scare off the Client */
1221 break;
1222 }
1223
1224 return off;
1225}
1226
1227/* Returns bytes consumed and updates bursts */
1228static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1229 unsigned long *bursts, const struct _xfer_spec *pxs)
1230{
1231 int cyc, cycmax, szlp, szlpend, szbrst, off;
1232 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1233 struct _arg_LPEND lpend;
1234
1235 if (*bursts == 1)
1236 return _bursts(pl330, dry_run, buf, pxs, 1);
1237
1238 /* Max iterations possible in DMALP is 256 */
1239 if (*bursts >= 256*256) {
1240 lcnt1 = 256;
1241 lcnt0 = 256;
1242 cyc = *bursts / lcnt1 / lcnt0;
1243 } else if (*bursts > 256) {
1244 lcnt1 = 256;
1245 lcnt0 = *bursts / lcnt1;
1246 cyc = 1;
1247 } else {
1248 lcnt1 = *bursts;
1249 lcnt0 = 0;
1250 cyc = 1;
1251 }
1252
1253 szlp = _emit_LP(1, buf, 0, 0);
1254 szbrst = _bursts(pl330, 1, buf, pxs, 1);
1255
1256 lpend.cond = ALWAYS;
1257 lpend.forever = false;
1258 lpend.loop = 0;
1259 lpend.bjump = 0;
1260 szlpend = _emit_LPEND(1, buf, &lpend);
1261
1262 if (lcnt0) {
1263 szlp *= 2;
1264 szlpend *= 2;
1265 }
1266
1267 /*
1268 * Max bursts that we can unroll due to limit on the
1269 * size of backward jump that can be encoded in DMALPEND
1270 * which is 8-bits and hence 255
1271 */
1272 cycmax = (255 - (szlp + szlpend)) / szbrst;
1273
1274 cyc = (cycmax < cyc) ? cycmax : cyc;
1275
1276 off = 0;
1277
1278 if (lcnt0) {
1279 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1280 ljmp0 = off;
1281 }
1282
1283 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1284 ljmp1 = off;
1285
1286 off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
1287
1288 lpend.cond = ALWAYS;
1289 lpend.forever = false;
1290 lpend.loop = 1;
1291 lpend.bjump = off - ljmp1;
1292 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1293
1294 if (lcnt0) {
1295 lpend.cond = ALWAYS;
1296 lpend.forever = false;
1297 lpend.loop = 0;
1298 lpend.bjump = off - ljmp0;
1299 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1300 }
1301
1302 *bursts = lcnt1 * cyc;
1303 if (lcnt0)
1304 *bursts *= lcnt0;
1305
1306 return off;
1307}
1308
1309static inline int _setup_loops(struct pl330_dmac *pl330,
1310 unsigned dry_run, u8 buf[],
1311 const struct _xfer_spec *pxs)
1312{
1313 struct pl330_xfer *x = &pxs->desc->px;
1314 u32 ccr = pxs->ccr;
1315 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1316 int off = 0;
1317
1318 while (bursts) {
1319 c = bursts;
1320 off += _loop(pl330, dry_run, &buf[off], &c, pxs);
1321 bursts -= c;
1322 }
1323
1324 return off;
1325}
1326
1327static inline int _setup_xfer(struct pl330_dmac *pl330,
1328 unsigned dry_run, u8 buf[],
1329 const struct _xfer_spec *pxs)
1330{
1331 struct pl330_xfer *x = &pxs->desc->px;
1332 int off = 0;
1333
1334 /* DMAMOV SAR, x->src_addr */
1335 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1336 /* DMAMOV DAR, x->dst_addr */
1337 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1338
1339 /* Setup Loop(s) */
1340 off += _setup_loops(pl330, dry_run, &buf[off], pxs);
1341
1342 return off;
1343}
1344
1345/*
1346 * A req is a sequence of one or more xfer units.
1347 * Returns the number of bytes taken to setup the MC for the req.
1348 */
1349static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
1350 struct pl330_thread *thrd, unsigned index,
1351 struct _xfer_spec *pxs)
1352{
1353 struct _pl330_req *req = &thrd->req[index];
1354 struct pl330_xfer *x;
1355 u8 *buf = req->mc_cpu;
1356 int off = 0;
1357
1358 PL330_DBGMC_START(req->mc_bus);
1359
1360 /* DMAMOV CCR, ccr */
1361 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1362
1363 x = &pxs->desc->px;
1364 /* Error if xfer length is not aligned at burst size */
1365 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1366 return -EINVAL;
1367
1368 off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
1369
1370 /* DMASEV peripheral/event */
1371 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1372 /* DMAEND */
1373 off += _emit_END(dry_run, &buf[off]);
1374
1375 return off;
1376}
1377
1378static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1379{
1380 u32 ccr = 0;
1381
1382 if (rqc->src_inc)
1383 ccr |= CC_SRCINC;
1384
1385 if (rqc->dst_inc)
1386 ccr |= CC_DSTINC;
1387
1388 /* We set same protection levels for Src and DST for now */
1389 if (rqc->privileged)
1390 ccr |= CC_SRCPRI | CC_DSTPRI;
1391 if (rqc->nonsecure)
1392 ccr |= CC_SRCNS | CC_DSTNS;
1393 if (rqc->insnaccess)
1394 ccr |= CC_SRCIA | CC_DSTIA;
1395
1396 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1397 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1398
1399 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1400 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1401
1402 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1403 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1404
1405 ccr |= (rqc->swap << CC_SWAP_SHFT);
1406
1407 return ccr;
1408}
1409
1410/*
1411 * Submit a list of xfers after which the client wants notification.
1412 * Client is not notified after each xfer unit, just once after all
1413 * xfer units are done or some error occurs.
1414 */
1415static int pl330_submit_req(struct pl330_thread *thrd,
1416 struct dma_pl330_desc *desc)
1417{
1418 struct pl330_dmac *pl330 = thrd->dmac;
1419 struct _xfer_spec xs;
1420 unsigned long flags;
1421 unsigned idx;
1422 u32 ccr;
1423 int ret = 0;
1424
1425 if (pl330->state == DYING
1426 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1427 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1428 __func__, __LINE__);
1429 return -EAGAIN;
1430 }
1431
1432 /* If request for non-existing peripheral */
1433 if (desc->rqtype != DMA_MEM_TO_MEM &&
1434 desc->peri >= pl330->pcfg.num_peri) {
1435 dev_info(thrd->dmac->ddma.dev,
1436 "%s:%d Invalid peripheral(%u)!\n",
1437 __func__, __LINE__, desc->peri);
1438 return -EINVAL;
1439 }
1440
1441 spin_lock_irqsave(&pl330->lock, flags);
1442
1443 if (_queue_full(thrd)) {
1444 ret = -EAGAIN;
1445 goto xfer_exit;
1446 }
1447
1448 /* Prefer Secure Channel */
1449 if (!_manager_ns(thrd))
1450 desc->rqcfg.nonsecure = 0;
1451 else
1452 desc->rqcfg.nonsecure = 1;
1453
1454 ccr = _prepare_ccr(&desc->rqcfg);
1455
1456 idx = thrd->req[0].desc == NULL ? 0 : 1;
1457
1458 xs.ccr = ccr;
1459 xs.desc = desc;
1460
1461 /* First dry run to check if req is acceptable */
1462 ret = _setup_req(pl330, 1, thrd, idx, &xs);
1463 if (ret < 0)
1464 goto xfer_exit;
1465
1466 if (ret > pl330->mcbufsz / 2) {
1467 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1468 __func__, __LINE__, ret, pl330->mcbufsz / 2);
1469 ret = -ENOMEM;
1470 goto xfer_exit;
1471 }
1472
1473 /* Hook the request */
1474 thrd->lstenq = idx;
1475 thrd->req[idx].desc = desc;
1476 _setup_req(pl330, 0, thrd, idx, &xs);
1477
1478 ret = 0;
1479
1480xfer_exit:
1481 spin_unlock_irqrestore(&pl330->lock, flags);
1482
1483 return ret;
1484}
1485
1486static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1487{
1488 struct dma_pl330_chan *pch;
1489 unsigned long flags;
1490
1491 if (!desc)
1492 return;
1493
1494 pch = desc->pchan;
1495
1496 /* If desc aborted */
1497 if (!pch)
1498 return;
1499
1500 spin_lock_irqsave(&pch->lock, flags);
1501
1502 desc->status = DONE;
1503
1504 spin_unlock_irqrestore(&pch->lock, flags);
1505
1506 tasklet_schedule(&pch->task);
1507}
1508
1509static void pl330_dotask(unsigned long data)
1510{
1511 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1512 unsigned long flags;
1513 int i;
1514
1515 spin_lock_irqsave(&pl330->lock, flags);
1516
1517 /* The DMAC itself gone nuts */
1518 if (pl330->dmac_tbd.reset_dmac) {
1519 pl330->state = DYING;
1520 /* Reset the manager too */
1521 pl330->dmac_tbd.reset_mngr = true;
1522 /* Clear the reset flag */
1523 pl330->dmac_tbd.reset_dmac = false;
1524 }
1525
1526 if (pl330->dmac_tbd.reset_mngr) {
1527 _stop(pl330->manager);
1528 /* Reset all channels */
1529 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1530 /* Clear the reset flag */
1531 pl330->dmac_tbd.reset_mngr = false;
1532 }
1533
1534 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1535
1536 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1537 struct pl330_thread *thrd = &pl330->channels[i];
1538 void __iomem *regs = pl330->base;
1539 enum pl330_op_err err;
1540
1541 _stop(thrd);
1542
1543 if (readl(regs + FSC) & (1 << thrd->id))
1544 err = PL330_ERR_FAIL;
1545 else
1546 err = PL330_ERR_ABORT;
1547
1548 spin_unlock_irqrestore(&pl330->lock, flags);
1549 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1550 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1551 spin_lock_irqsave(&pl330->lock, flags);
1552
1553 thrd->req[0].desc = NULL;
1554 thrd->req[1].desc = NULL;
1555 thrd->req_running = -1;
1556
1557 /* Clear the reset flag */
1558 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1559 }
1560 }
1561
1562 spin_unlock_irqrestore(&pl330->lock, flags);
1563
1564 return;
1565}
1566
1567/* Returns 1 if state was updated, 0 otherwise */
1568static int pl330_update(struct pl330_dmac *pl330)
1569{
1570 struct dma_pl330_desc *descdone, *tmp;
1571 unsigned long flags;
1572 void __iomem *regs;
1573 u32 val;
1574 int id, ev, ret = 0;
1575
1576 regs = pl330->base;
1577
1578 spin_lock_irqsave(&pl330->lock, flags);
1579
1580 val = readl(regs + FSM) & 0x1;
1581 if (val)
1582 pl330->dmac_tbd.reset_mngr = true;
1583 else
1584 pl330->dmac_tbd.reset_mngr = false;
1585
1586 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1587 pl330->dmac_tbd.reset_chan |= val;
1588 if (val) {
1589 int i = 0;
1590 while (i < pl330->pcfg.num_chan) {
1591 if (val & (1 << i)) {
1592 dev_info(pl330->ddma.dev,
1593 "Reset Channel-%d\t CS-%x FTC-%x\n",
1594 i, readl(regs + CS(i)),
1595 readl(regs + FTC(i)));
1596 _stop(&pl330->channels[i]);
1597 }
1598 i++;
1599 }
1600 }
1601
1602 /* Check which event happened i.e, thread notified */
1603 val = readl(regs + ES);
1604 if (pl330->pcfg.num_events < 32
1605 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1606 pl330->dmac_tbd.reset_dmac = true;
1607 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1608 __LINE__);
1609 ret = 1;
1610 goto updt_exit;
1611 }
1612
1613 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1614 if (val & (1 << ev)) { /* Event occurred */
1615 struct pl330_thread *thrd;
1616 u32 inten = readl(regs + INTEN);
1617 int active;
1618
1619 /* Clear the event */
1620 if (inten & (1 << ev))
1621 writel(1 << ev, regs + INTCLR);
1622
1623 ret = 1;
1624
1625 id = pl330->events[ev];
1626
1627 thrd = &pl330->channels[id];
1628
1629 active = thrd->req_running;
1630 if (active == -1) /* Aborted */
1631 continue;
1632
1633 /* Detach the req */
1634 descdone = thrd->req[active].desc;
1635 thrd->req[active].desc = NULL;
1636
1637 thrd->req_running = -1;
1638
1639 /* Get going again ASAP */
1640 _start(thrd);
1641
1642 /* For now, just make a list of callbacks to be done */
1643 list_add_tail(&descdone->rqd, &pl330->req_done);
1644 }
1645 }
1646
1647 /* Now that we are in no hurry, do the callbacks */
1648 list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) {
1649 list_del(&descdone->rqd);
1650 spin_unlock_irqrestore(&pl330->lock, flags);
1651 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1652 spin_lock_irqsave(&pl330->lock, flags);
1653 }
1654
1655updt_exit:
1656 spin_unlock_irqrestore(&pl330->lock, flags);
1657
1658 if (pl330->dmac_tbd.reset_dmac
1659 || pl330->dmac_tbd.reset_mngr
1660 || pl330->dmac_tbd.reset_chan) {
1661 ret = 1;
1662 tasklet_schedule(&pl330->tasks);
1663 }
1664
1665 return ret;
1666}
1667
1668/* Reserve an event */
1669static inline int _alloc_event(struct pl330_thread *thrd)
1670{
1671 struct pl330_dmac *pl330 = thrd->dmac;
1672 int ev;
1673
1674 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1675 if (pl330->events[ev] == -1) {
1676 pl330->events[ev] = thrd->id;
1677 return ev;
1678 }
1679
1680 return -1;
1681}
1682
1683static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1684{
1685 return pl330->pcfg.irq_ns & (1 << i);
1686}
1687
1688/* Upon success, returns IdentityToken for the
1689 * allocated channel, NULL otherwise.
1690 */
1691static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1692{
1693 struct pl330_thread *thrd = NULL;
1694 unsigned long flags;
1695 int chans, i;
1696
1697 if (pl330->state == DYING)
1698 return NULL;
1699
1700 chans = pl330->pcfg.num_chan;
1701
1702 spin_lock_irqsave(&pl330->lock, flags);
1703
1704 for (i = 0; i < chans; i++) {
1705 thrd = &pl330->channels[i];
1706 if ((thrd->free) && (!_manager_ns(thrd) ||
1707 _chan_ns(pl330, i))) {
1708 thrd->ev = _alloc_event(thrd);
1709 if (thrd->ev >= 0) {
1710 thrd->free = false;
1711 thrd->lstenq = 1;
1712 thrd->req[0].desc = NULL;
1713 thrd->req[1].desc = NULL;
1714 thrd->req_running = -1;
1715 break;
1716 }
1717 }
1718 thrd = NULL;
1719 }
1720
1721 spin_unlock_irqrestore(&pl330->lock, flags);
1722
1723 return thrd;
1724}
1725
1726/* Release an event */
1727static inline void _free_event(struct pl330_thread *thrd, int ev)
1728{
1729 struct pl330_dmac *pl330 = thrd->dmac;
1730
1731 /* If the event is valid and was held by the thread */
1732 if (ev >= 0 && ev < pl330->pcfg.num_events
1733 && pl330->events[ev] == thrd->id)
1734 pl330->events[ev] = -1;
1735}
1736
1737static void pl330_release_channel(struct pl330_thread *thrd)
1738{
1739 struct pl330_dmac *pl330;
1740 unsigned long flags;
1741
1742 if (!thrd || thrd->free)
1743 return;
1744
1745 _stop(thrd);
1746
1747 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1748 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1749
1750 pl330 = thrd->dmac;
1751
1752 spin_lock_irqsave(&pl330->lock, flags);
1753 _free_event(thrd, thrd->ev);
1754 thrd->free = true;
1755 spin_unlock_irqrestore(&pl330->lock, flags);
1756}
1757
1758/* Initialize the structure for PL330 configuration, that can be used
1759 * by the client driver the make best use of the DMAC
1760 */
1761static void read_dmac_config(struct pl330_dmac *pl330)
1762{
1763 void __iomem *regs = pl330->base;
1764 u32 val;
1765
1766 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1767 val &= CRD_DATA_WIDTH_MASK;
1768 pl330->pcfg.data_bus_width = 8 * (1 << val);
1769
1770 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1771 val &= CRD_DATA_BUFF_MASK;
1772 pl330->pcfg.data_buf_dep = val + 1;
1773
1774 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1775 val &= CR0_NUM_CHANS_MASK;
1776 val += 1;
1777 pl330->pcfg.num_chan = val;
1778
1779 val = readl(regs + CR0);
1780 if (val & CR0_PERIPH_REQ_SET) {
1781 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1782 val += 1;
1783 pl330->pcfg.num_peri = val;
1784 pl330->pcfg.peri_ns = readl(regs + CR4);
1785 } else {
1786 pl330->pcfg.num_peri = 0;
1787 }
1788
1789 val = readl(regs + CR0);
1790 if (val & CR0_BOOT_MAN_NS)
1791 pl330->pcfg.mode |= DMAC_MODE_NS;
1792 else
1793 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1794
1795 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1796 val &= CR0_NUM_EVENTS_MASK;
1797 val += 1;
1798 pl330->pcfg.num_events = val;
1799
1800 pl330->pcfg.irq_ns = readl(regs + CR3);
1801}
1802
1803static inline void _reset_thread(struct pl330_thread *thrd)
1804{
1805 struct pl330_dmac *pl330 = thrd->dmac;
1806
1807 thrd->req[0].mc_cpu = pl330->mcode_cpu
1808 + (thrd->id * pl330->mcbufsz);
1809 thrd->req[0].mc_bus = pl330->mcode_bus
1810 + (thrd->id * pl330->mcbufsz);
1811 thrd->req[0].desc = NULL;
1812
1813 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1814 + pl330->mcbufsz / 2;
1815 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1816 + pl330->mcbufsz / 2;
1817 thrd->req[1].desc = NULL;
1818
1819 thrd->req_running = -1;
1820}
1821
1822static int dmac_alloc_threads(struct pl330_dmac *pl330)
1823{
1824 int chans = pl330->pcfg.num_chan;
1825 struct pl330_thread *thrd;
1826 int i;
1827
1828 /* Allocate 1 Manager and 'chans' Channel threads */
1829 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
1830 GFP_KERNEL);
1831 if (!pl330->channels)
1832 return -ENOMEM;
1833
1834 /* Init Channel threads */
1835 for (i = 0; i < chans; i++) {
1836 thrd = &pl330->channels[i];
1837 thrd->id = i;
1838 thrd->dmac = pl330;
1839 _reset_thread(thrd);
1840 thrd->free = true;
1841 }
1842
1843 /* MANAGER is indexed at the end */
1844 thrd = &pl330->channels[chans];
1845 thrd->id = chans;
1846 thrd->dmac = pl330;
1847 thrd->free = false;
1848 pl330->manager = thrd;
1849
1850 return 0;
1851}
1852
1853static int dmac_alloc_resources(struct pl330_dmac *pl330)
1854{
1855 int chans = pl330->pcfg.num_chan;
1856 int ret;
1857
1858 /*
1859 * Alloc MicroCode buffer for 'chans' Channel threads.
1860 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1861 */
1862 pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev,
1863 chans * pl330->mcbufsz,
1864 &pl330->mcode_bus, GFP_KERNEL);
1865 if (!pl330->mcode_cpu) {
1866 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1867 __func__, __LINE__);
1868 return -ENOMEM;
1869 }
1870
1871 ret = dmac_alloc_threads(pl330);
1872 if (ret) {
1873 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1874 __func__, __LINE__);
1875 dma_free_coherent(pl330->ddma.dev,
1876 chans * pl330->mcbufsz,
1877 pl330->mcode_cpu, pl330->mcode_bus);
1878 return ret;
1879 }
1880
1881 return 0;
1882}
1883
1884static int pl330_add(struct pl330_dmac *pl330)
1885{
1886 void __iomem *regs;
1887 int i, ret;
1888
1889 regs = pl330->base;
1890
1891 /* Check if we can handle this DMAC */
1892 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1893 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1894 pl330->pcfg.periph_id);
1895 return -EINVAL;
1896 }
1897
1898 /* Read the configuration of the DMAC */
1899 read_dmac_config(pl330);
1900
1901 if (pl330->pcfg.num_events == 0) {
1902 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1903 __func__, __LINE__);
1904 return -EINVAL;
1905 }
1906
1907 spin_lock_init(&pl330->lock);
1908
1909 INIT_LIST_HEAD(&pl330->req_done);
1910
1911 /* Use default MC buffer size if not provided */
1912 if (!pl330->mcbufsz)
1913 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1914
1915 /* Mark all events as free */
1916 for (i = 0; i < pl330->pcfg.num_events; i++)
1917 pl330->events[i] = -1;
1918
1919 /* Allocate resources needed by the DMAC */
1920 ret = dmac_alloc_resources(pl330);
1921 if (ret) {
1922 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1923 return ret;
1924 }
1925
1926 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1927
1928 pl330->state = INIT;
1929
1930 return 0;
1931}
1932
1933static int dmac_free_threads(struct pl330_dmac *pl330)
1934{
1935 struct pl330_thread *thrd;
1936 int i;
1937
1938 /* Release Channel threads */
1939 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1940 thrd = &pl330->channels[i];
1941 pl330_release_channel(thrd);
1942 }
1943
1944 /* Free memory */
1945 kfree(pl330->channels);
1946
1947 return 0;
1948}
1949
1950static void pl330_del(struct pl330_dmac *pl330)
1951{
1952 pl330->state = UNINIT;
1953
1954 tasklet_kill(&pl330->tasks);
1955
1956 /* Free DMAC resources */
1957 dmac_free_threads(pl330);
1958
1959 dma_free_coherent(pl330->ddma.dev,
1960 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
1961 pl330->mcode_bus);
1962}
1963
1964/* forward declaration */
1965static struct amba_driver pl330_driver;
1966
1967static inline struct dma_pl330_chan *
1968to_pchan(struct dma_chan *ch)
1969{
1970 if (!ch)
1971 return NULL;
1972
1973 return container_of(ch, struct dma_pl330_chan, chan);
1974}
1975
1976static inline struct dma_pl330_desc *
1977to_desc(struct dma_async_tx_descriptor *tx)
1978{
1979 return container_of(tx, struct dma_pl330_desc, txd);
1980}
1981
1982static inline void fill_queue(struct dma_pl330_chan *pch)
1983{
1984 struct dma_pl330_desc *desc;
1985 int ret;
1986
1987 list_for_each_entry(desc, &pch->work_list, node) {
1988
1989 /* If already submitted */
1990 if (desc->status == BUSY)
1991 continue;
1992
1993 ret = pl330_submit_req(pch->thread, desc);
1994 if (!ret) {
1995 desc->status = BUSY;
1996 } else if (ret == -EAGAIN) {
1997 /* QFull or DMAC Dying */
1998 break;
1999 } else {
2000 /* Unacceptable request */
2001 desc->status = DONE;
2002 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
2003 __func__, __LINE__, desc->txd.cookie);
2004 tasklet_schedule(&pch->task);
2005 }
2006 }
2007}
2008
2009static void pl330_tasklet(unsigned long data)
2010{
2011 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2012 struct dma_pl330_desc *desc, *_dt;
2013 unsigned long flags;
2014 bool power_down = false;
2015
2016 spin_lock_irqsave(&pch->lock, flags);
2017
2018 /* Pick up ripe tomatoes */
2019 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2020 if (desc->status == DONE) {
2021 if (!pch->cyclic)
2022 dma_cookie_complete(&desc->txd);
2023 list_move_tail(&desc->node, &pch->completed_list);
2024 }
2025
2026 /* Try to submit a req imm. next to the last completed cookie */
2027 fill_queue(pch);
2028
2029 if (list_empty(&pch->work_list)) {
2030 spin_lock(&pch->thread->dmac->lock);
2031 _stop(pch->thread);
2032 spin_unlock(&pch->thread->dmac->lock);
2033 power_down = true;
2034 } else {
2035 /* Make sure the PL330 Channel thread is active */
2036 spin_lock(&pch->thread->dmac->lock);
2037 _start(pch->thread);
2038 spin_unlock(&pch->thread->dmac->lock);
2039 }
2040
2041 while (!list_empty(&pch->completed_list)) {
2042 dma_async_tx_callback callback;
2043 void *callback_param;
2044
2045 desc = list_first_entry(&pch->completed_list,
2046 struct dma_pl330_desc, node);
2047
2048 callback = desc->txd.callback;
2049 callback_param = desc->txd.callback_param;
2050
2051 if (pch->cyclic) {
2052 desc->status = PREP;
2053 list_move_tail(&desc->node, &pch->work_list);
2054 if (power_down) {
2055 spin_lock(&pch->thread->dmac->lock);
2056 _start(pch->thread);
2057 spin_unlock(&pch->thread->dmac->lock);
2058 power_down = false;
2059 }
2060 } else {
2061 desc->status = FREE;
2062 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2063 }
2064
2065 dma_descriptor_unmap(&desc->txd);
2066
2067 if (callback) {
2068 spin_unlock_irqrestore(&pch->lock, flags);
2069 callback(callback_param);
2070 spin_lock_irqsave(&pch->lock, flags);
2071 }
2072 }
2073 spin_unlock_irqrestore(&pch->lock, flags);
2074
2075 /* If work list empty, power down */
2076 if (power_down) {
2077 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2078 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2079 }
2080}
2081
2082bool pl330_filter(struct dma_chan *chan, void *param)
2083{
2084 u8 *peri_id;
2085
2086 if (chan->device->dev->driver != &pl330_driver.drv)
2087 return false;
2088
2089 peri_id = chan->private;
2090 return *peri_id == (unsigned long)param;
2091}
2092EXPORT_SYMBOL(pl330_filter);
2093
2094static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2095 struct of_dma *ofdma)
2096{
2097 int count = dma_spec->args_count;
2098 struct pl330_dmac *pl330 = ofdma->of_dma_data;
2099 unsigned int chan_id;
2100
2101 if (!pl330)
2102 return NULL;
2103
2104 if (count != 1)
2105 return NULL;
2106
2107 chan_id = dma_spec->args[0];
2108 if (chan_id >= pl330->num_peripherals)
2109 return NULL;
2110
2111 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2112}
2113
2114static int pl330_alloc_chan_resources(struct dma_chan *chan)
2115{
2116 struct dma_pl330_chan *pch = to_pchan(chan);
2117 struct pl330_dmac *pl330 = pch->dmac;
2118 unsigned long flags;
2119
2120 spin_lock_irqsave(&pch->lock, flags);
2121
2122 dma_cookie_init(chan);
2123 pch->cyclic = false;
2124
2125 pch->thread = pl330_request_channel(pl330);
2126 if (!pch->thread) {
2127 spin_unlock_irqrestore(&pch->lock, flags);
2128 return -ENOMEM;
2129 }
2130
2131 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2132
2133 spin_unlock_irqrestore(&pch->lock, flags);
2134
2135 return 1;
2136}
2137
2138static int pl330_config(struct dma_chan *chan,
2139 struct dma_slave_config *slave_config)
2140{
2141 struct dma_pl330_chan *pch = to_pchan(chan);
2142
2143 if (slave_config->direction == DMA_MEM_TO_DEV) {
2144 if (slave_config->dst_addr)
2145 pch->fifo_addr = slave_config->dst_addr;
2146 if (slave_config->dst_addr_width)
2147 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2148 if (slave_config->dst_maxburst)
2149 pch->burst_len = slave_config->dst_maxburst;
2150 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
2151 if (slave_config->src_addr)
2152 pch->fifo_addr = slave_config->src_addr;
2153 if (slave_config->src_addr_width)
2154 pch->burst_sz = __ffs(slave_config->src_addr_width);
2155 if (slave_config->src_maxburst)
2156 pch->burst_len = slave_config->src_maxburst;
2157 }
2158
2159 return 0;
2160}
2161
2162static int pl330_terminate_all(struct dma_chan *chan)
2163{
2164 struct dma_pl330_chan *pch = to_pchan(chan);
2165 struct dma_pl330_desc *desc;
2166 unsigned long flags;
2167 struct pl330_dmac *pl330 = pch->dmac;
2168 LIST_HEAD(list);
2169
2170 pm_runtime_get_sync(pl330->ddma.dev);
2171 spin_lock_irqsave(&pch->lock, flags);
2172 spin_lock(&pl330->lock);
2173 _stop(pch->thread);
2174 spin_unlock(&pl330->lock);
2175
2176 pch->thread->req[0].desc = NULL;
2177 pch->thread->req[1].desc = NULL;
2178 pch->thread->req_running = -1;
2179
2180 /* Mark all desc done */
2181 list_for_each_entry(desc, &pch->submitted_list, node) {
2182 desc->status = FREE;
2183 dma_cookie_complete(&desc->txd);
2184 }
2185
2186 list_for_each_entry(desc, &pch->work_list , node) {
2187 desc->status = FREE;
2188 dma_cookie_complete(&desc->txd);
2189 }
2190
2191 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2192 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2193 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2194 spin_unlock_irqrestore(&pch->lock, flags);
2195 pm_runtime_mark_last_busy(pl330->ddma.dev);
2196 pm_runtime_put_autosuspend(pl330->ddma.dev);
2197
2198 return 0;
2199}
2200
2201/*
2202 * We don't support DMA_RESUME command because of hardware
2203 * limitations, so after pausing the channel we cannot restore
2204 * it to active state. We have to terminate channel and setup
2205 * DMA transfer again. This pause feature was implemented to
2206 * allow safely read residue before channel termination.
2207 */
2208static int pl330_pause(struct dma_chan *chan)
2209{
2210 struct dma_pl330_chan *pch = to_pchan(chan);
2211 struct pl330_dmac *pl330 = pch->dmac;
2212 unsigned long flags;
2213
2214 pm_runtime_get_sync(pl330->ddma.dev);
2215 spin_lock_irqsave(&pch->lock, flags);
2216
2217 spin_lock(&pl330->lock);
2218 _stop(pch->thread);
2219 spin_unlock(&pl330->lock);
2220
2221 spin_unlock_irqrestore(&pch->lock, flags);
2222 pm_runtime_mark_last_busy(pl330->ddma.dev);
2223 pm_runtime_put_autosuspend(pl330->ddma.dev);
2224
2225 return 0;
2226}
2227
2228static void pl330_free_chan_resources(struct dma_chan *chan)
2229{
2230 struct dma_pl330_chan *pch = to_pchan(chan);
2231 unsigned long flags;
2232
2233 tasklet_kill(&pch->task);
2234
2235 pm_runtime_get_sync(pch->dmac->ddma.dev);
2236 spin_lock_irqsave(&pch->lock, flags);
2237
2238 pl330_release_channel(pch->thread);
2239 pch->thread = NULL;
2240
2241 if (pch->cyclic)
2242 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2243
2244 spin_unlock_irqrestore(&pch->lock, flags);
2245 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2246 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2247}
2248
2249static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2250 struct dma_pl330_desc *desc)
2251{
2252 struct pl330_thread *thrd = pch->thread;
2253 struct pl330_dmac *pl330 = pch->dmac;
2254 void __iomem *regs = thrd->dmac->base;
2255 u32 val, addr;
2256
2257 pm_runtime_get_sync(pl330->ddma.dev);
2258 val = addr = 0;
2259 if (desc->rqcfg.src_inc) {
2260 val = readl(regs + SA(thrd->id));
2261 addr = desc->px.src_addr;
2262 } else {
2263 val = readl(regs + DA(thrd->id));
2264 addr = desc->px.dst_addr;
2265 }
2266 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2267 pm_runtime_put_autosuspend(pl330->ddma.dev);
2268 return val - addr;
2269}
2270
2271static enum dma_status
2272pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2273 struct dma_tx_state *txstate)
2274{
2275 enum dma_status ret;
2276 unsigned long flags;
2277 struct dma_pl330_desc *desc, *running = NULL;
2278 struct dma_pl330_chan *pch = to_pchan(chan);
2279 unsigned int transferred, residual = 0;
2280
2281 ret = dma_cookie_status(chan, cookie, txstate);
2282
2283 if (!txstate)
2284 return ret;
2285
2286 if (ret == DMA_COMPLETE)
2287 goto out;
2288
2289 spin_lock_irqsave(&pch->lock, flags);
2290
2291 if (pch->thread->req_running != -1)
2292 running = pch->thread->req[pch->thread->req_running].desc;
2293
2294 /* Check in pending list */
2295 list_for_each_entry(desc, &pch->work_list, node) {
2296 if (desc->status == DONE)
2297 transferred = desc->bytes_requested;
2298 else if (running && desc == running)
2299 transferred =
2300 pl330_get_current_xferred_count(pch, desc);
2301 else
2302 transferred = 0;
2303 residual += desc->bytes_requested - transferred;
2304 if (desc->txd.cookie == cookie) {
2305 switch (desc->status) {
2306 case DONE:
2307 ret = DMA_COMPLETE;
2308 break;
2309 case PREP:
2310 case BUSY:
2311 ret = DMA_IN_PROGRESS;
2312 break;
2313 default:
2314 WARN_ON(1);
2315 }
2316 break;
2317 }
2318 if (desc->last)
2319 residual = 0;
2320 }
2321 spin_unlock_irqrestore(&pch->lock, flags);
2322
2323out:
2324 dma_set_residue(txstate, residual);
2325
2326 return ret;
2327}
2328
2329static void pl330_issue_pending(struct dma_chan *chan)
2330{
2331 struct dma_pl330_chan *pch = to_pchan(chan);
2332 unsigned long flags;
2333
2334 spin_lock_irqsave(&pch->lock, flags);
2335 if (list_empty(&pch->work_list)) {
2336 /*
2337 * Warn on nothing pending. Empty submitted_list may
2338 * break our pm_runtime usage counter as it is
2339 * updated on work_list emptiness status.
2340 */
2341 WARN_ON(list_empty(&pch->submitted_list));
2342 pm_runtime_get_sync(pch->dmac->ddma.dev);
2343 }
2344 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2345 spin_unlock_irqrestore(&pch->lock, flags);
2346
2347 pl330_tasklet((unsigned long)pch);
2348}
2349
2350/*
2351 * We returned the last one of the circular list of descriptor(s)
2352 * from prep_xxx, so the argument to submit corresponds to the last
2353 * descriptor of the list.
2354 */
2355static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2356{
2357 struct dma_pl330_desc *desc, *last = to_desc(tx);
2358 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2359 dma_cookie_t cookie;
2360 unsigned long flags;
2361
2362 spin_lock_irqsave(&pch->lock, flags);
2363
2364 /* Assign cookies to all nodes */
2365 while (!list_empty(&last->node)) {
2366 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2367 if (pch->cyclic) {
2368 desc->txd.callback = last->txd.callback;
2369 desc->txd.callback_param = last->txd.callback_param;
2370 }
2371 desc->last = false;
2372
2373 dma_cookie_assign(&desc->txd);
2374
2375 list_move_tail(&desc->node, &pch->submitted_list);
2376 }
2377
2378 last->last = true;
2379 cookie = dma_cookie_assign(&last->txd);
2380 list_add_tail(&last->node, &pch->submitted_list);
2381 spin_unlock_irqrestore(&pch->lock, flags);
2382
2383 return cookie;
2384}
2385
2386static inline void _init_desc(struct dma_pl330_desc *desc)
2387{
2388 desc->rqcfg.swap = SWAP_NO;
2389 desc->rqcfg.scctl = CCTRL0;
2390 desc->rqcfg.dcctl = CCTRL0;
2391 desc->txd.tx_submit = pl330_tx_submit;
2392
2393 INIT_LIST_HEAD(&desc->node);
2394}
2395
2396/* Returns the number of descriptors added to the DMAC pool */
2397static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count)
2398{
2399 struct dma_pl330_desc *desc;
2400 unsigned long flags;
2401 int i;
2402
2403 desc = kcalloc(count, sizeof(*desc), flg);
2404 if (!desc)
2405 return 0;
2406
2407 spin_lock_irqsave(&pl330->pool_lock, flags);
2408
2409 for (i = 0; i < count; i++) {
2410 _init_desc(&desc[i]);
2411 list_add_tail(&desc[i].node, &pl330->desc_pool);
2412 }
2413
2414 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2415
2416 return count;
2417}
2418
2419static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330)
2420{
2421 struct dma_pl330_desc *desc = NULL;
2422 unsigned long flags;
2423
2424 spin_lock_irqsave(&pl330->pool_lock, flags);
2425
2426 if (!list_empty(&pl330->desc_pool)) {
2427 desc = list_entry(pl330->desc_pool.next,
2428 struct dma_pl330_desc, node);
2429
2430 list_del_init(&desc->node);
2431
2432 desc->status = PREP;
2433 desc->txd.callback = NULL;
2434 }
2435
2436 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2437
2438 return desc;
2439}
2440
2441static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2442{
2443 struct pl330_dmac *pl330 = pch->dmac;
2444 u8 *peri_id = pch->chan.private;
2445 struct dma_pl330_desc *desc;
2446
2447 /* Pluck one desc from the pool of DMAC */
2448 desc = pluck_desc(pl330);
2449
2450 /* If the DMAC pool is empty, alloc new */
2451 if (!desc) {
2452 if (!add_desc(pl330, GFP_ATOMIC, 1))
2453 return NULL;
2454
2455 /* Try again */
2456 desc = pluck_desc(pl330);
2457 if (!desc) {
2458 dev_err(pch->dmac->ddma.dev,
2459 "%s:%d ALERT!\n", __func__, __LINE__);
2460 return NULL;
2461 }
2462 }
2463
2464 /* Initialize the descriptor */
2465 desc->pchan = pch;
2466 desc->txd.cookie = 0;
2467 async_tx_ack(&desc->txd);
2468
2469 desc->peri = peri_id ? pch->chan.chan_id : 0;
2470 desc->rqcfg.pcfg = &pch->dmac->pcfg;
2471
2472 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2473
2474 return desc;
2475}
2476
2477static inline void fill_px(struct pl330_xfer *px,
2478 dma_addr_t dst, dma_addr_t src, size_t len)
2479{
2480 px->bytes = len;
2481 px->dst_addr = dst;
2482 px->src_addr = src;
2483}
2484
2485static struct dma_pl330_desc *
2486__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2487 dma_addr_t src, size_t len)
2488{
2489 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2490
2491 if (!desc) {
2492 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2493 __func__, __LINE__);
2494 return NULL;
2495 }
2496
2497 /*
2498 * Ideally we should lookout for reqs bigger than
2499 * those that can be programmed with 256 bytes of
2500 * MC buffer, but considering a req size is seldom
2501 * going to be word-unaligned and more than 200MB,
2502 * we take it easy.
2503 * Also, should the limit is reached we'd rather
2504 * have the platform increase MC buffer size than
2505 * complicating this API driver.
2506 */
2507 fill_px(&desc->px, dst, src, len);
2508
2509 return desc;
2510}
2511
2512/* Call after fixing burst size */
2513static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2514{
2515 struct dma_pl330_chan *pch = desc->pchan;
2516 struct pl330_dmac *pl330 = pch->dmac;
2517 int burst_len;
2518
2519 burst_len = pl330->pcfg.data_bus_width / 8;
2520 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2521 burst_len >>= desc->rqcfg.brst_size;
2522
2523 /* src/dst_burst_len can't be more than 16 */
2524 if (burst_len > 16)
2525 burst_len = 16;
2526
2527 while (burst_len > 1) {
2528 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2529 break;
2530 burst_len--;
2531 }
2532
2533 return burst_len;
2534}
2535
2536static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2537 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2538 size_t period_len, enum dma_transfer_direction direction,
2539 unsigned long flags)
2540{
2541 struct dma_pl330_desc *desc = NULL, *first = NULL;
2542 struct dma_pl330_chan *pch = to_pchan(chan);
2543 struct pl330_dmac *pl330 = pch->dmac;
2544 unsigned int i;
2545 dma_addr_t dst;
2546 dma_addr_t src;
2547
2548 if (len % period_len != 0)
2549 return NULL;
2550
2551 if (!is_slave_direction(direction)) {
2552 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2553 __func__, __LINE__);
2554 return NULL;
2555 }
2556
2557 for (i = 0; i < len / period_len; i++) {
2558 desc = pl330_get_desc(pch);
2559 if (!desc) {
2560 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2561 __func__, __LINE__);
2562
2563 if (!first)
2564 return NULL;
2565
2566 spin_lock_irqsave(&pl330->pool_lock, flags);
2567
2568 while (!list_empty(&first->node)) {
2569 desc = list_entry(first->node.next,
2570 struct dma_pl330_desc, node);
2571 list_move_tail(&desc->node, &pl330->desc_pool);
2572 }
2573
2574 list_move_tail(&first->node, &pl330->desc_pool);
2575
2576 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2577
2578 return NULL;
2579 }
2580
2581 switch (direction) {
2582 case DMA_MEM_TO_DEV:
2583 desc->rqcfg.src_inc = 1;
2584 desc->rqcfg.dst_inc = 0;
2585 src = dma_addr;
2586 dst = pch->fifo_addr;
2587 break;
2588 case DMA_DEV_TO_MEM:
2589 desc->rqcfg.src_inc = 0;
2590 desc->rqcfg.dst_inc = 1;
2591 src = pch->fifo_addr;
2592 dst = dma_addr;
2593 break;
2594 default:
2595 break;
2596 }
2597
2598 desc->rqtype = direction;
2599 desc->rqcfg.brst_size = pch->burst_sz;
2600 desc->rqcfg.brst_len = 1;
2601 desc->bytes_requested = period_len;
2602 fill_px(&desc->px, dst, src, period_len);
2603
2604 if (!first)
2605 first = desc;
2606 else
2607 list_add_tail(&desc->node, &first->node);
2608
2609 dma_addr += period_len;
2610 }
2611
2612 if (!desc)
2613 return NULL;
2614
2615 pch->cyclic = true;
2616 desc->txd.flags = flags;
2617
2618 return &desc->txd;
2619}
2620
2621static struct dma_async_tx_descriptor *
2622pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2623 dma_addr_t src, size_t len, unsigned long flags)
2624{
2625 struct dma_pl330_desc *desc;
2626 struct dma_pl330_chan *pch = to_pchan(chan);
2627 struct pl330_dmac *pl330;
2628 int burst;
2629
2630 if (unlikely(!pch || !len))
2631 return NULL;
2632
2633 pl330 = pch->dmac;
2634
2635 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2636 if (!desc)
2637 return NULL;
2638
2639 desc->rqcfg.src_inc = 1;
2640 desc->rqcfg.dst_inc = 1;
2641 desc->rqtype = DMA_MEM_TO_MEM;
2642
2643 /* Select max possible burst size */
2644 burst = pl330->pcfg.data_bus_width / 8;
2645
2646 /*
2647 * Make sure we use a burst size that aligns with all the memcpy
2648 * parameters because our DMA programming algorithm doesn't cope with
2649 * transfers which straddle an entry in the DMA device's MFIFO.
2650 */
2651 while ((src | dst | len) & (burst - 1))
2652 burst /= 2;
2653
2654 desc->rqcfg.brst_size = 0;
2655 while (burst != (1 << desc->rqcfg.brst_size))
2656 desc->rqcfg.brst_size++;
2657
2658 /*
2659 * If burst size is smaller than bus width then make sure we only
2660 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2661 */
2662 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2663 desc->rqcfg.brst_len = 1;
2664
2665 desc->rqcfg.brst_len = get_burst_len(desc, len);
2666 desc->bytes_requested = len;
2667
2668 desc->txd.flags = flags;
2669
2670 return &desc->txd;
2671}
2672
2673static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2674 struct dma_pl330_desc *first)
2675{
2676 unsigned long flags;
2677 struct dma_pl330_desc *desc;
2678
2679 if (!first)
2680 return;
2681
2682 spin_lock_irqsave(&pl330->pool_lock, flags);
2683
2684 while (!list_empty(&first->node)) {
2685 desc = list_entry(first->node.next,
2686 struct dma_pl330_desc, node);
2687 list_move_tail(&desc->node, &pl330->desc_pool);
2688 }
2689
2690 list_move_tail(&first->node, &pl330->desc_pool);
2691
2692 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2693}
2694
2695static struct dma_async_tx_descriptor *
2696pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2697 unsigned int sg_len, enum dma_transfer_direction direction,
2698 unsigned long flg, void *context)
2699{
2700 struct dma_pl330_desc *first, *desc = NULL;
2701 struct dma_pl330_chan *pch = to_pchan(chan);
2702 struct scatterlist *sg;
2703 int i;
2704 dma_addr_t addr;
2705
2706 if (unlikely(!pch || !sgl || !sg_len))
2707 return NULL;
2708
2709 addr = pch->fifo_addr;
2710
2711 first = NULL;
2712
2713 for_each_sg(sgl, sg, sg_len, i) {
2714
2715 desc = pl330_get_desc(pch);
2716 if (!desc) {
2717 struct pl330_dmac *pl330 = pch->dmac;
2718
2719 dev_err(pch->dmac->ddma.dev,
2720 "%s:%d Unable to fetch desc\n",
2721 __func__, __LINE__);
2722 __pl330_giveback_desc(pl330, first);
2723
2724 return NULL;
2725 }
2726
2727 if (!first)
2728 first = desc;
2729 else
2730 list_add_tail(&desc->node, &first->node);
2731
2732 if (direction == DMA_MEM_TO_DEV) {
2733 desc->rqcfg.src_inc = 1;
2734 desc->rqcfg.dst_inc = 0;
2735 fill_px(&desc->px,
2736 addr, sg_dma_address(sg), sg_dma_len(sg));
2737 } else {
2738 desc->rqcfg.src_inc = 0;
2739 desc->rqcfg.dst_inc = 1;
2740 fill_px(&desc->px,
2741 sg_dma_address(sg), addr, sg_dma_len(sg));
2742 }
2743
2744 desc->rqcfg.brst_size = pch->burst_sz;
2745 desc->rqcfg.brst_len = 1;
2746 desc->rqtype = direction;
2747 desc->bytes_requested = sg_dma_len(sg);
2748 }
2749
2750 /* Return the last desc in the chain */
2751 desc->txd.flags = flg;
2752 return &desc->txd;
2753}
2754
2755static irqreturn_t pl330_irq_handler(int irq, void *data)
2756{
2757 if (pl330_update(data))
2758 return IRQ_HANDLED;
2759 else
2760 return IRQ_NONE;
2761}
2762
2763#define PL330_DMA_BUSWIDTHS \
2764 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2765 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2766 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2767 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2768 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2769
2770/*
2771 * Runtime PM callbacks are provided by amba/bus.c driver.
2772 *
2773 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2774 * bus driver will only disable/enable the clock in runtime PM callbacks.
2775 */
2776static int __maybe_unused pl330_suspend(struct device *dev)
2777{
2778 struct amba_device *pcdev = to_amba_device(dev);
2779
2780 pm_runtime_disable(dev);
2781
2782 if (!pm_runtime_status_suspended(dev)) {
2783 /* amba did not disable the clock */
2784 amba_pclk_disable(pcdev);
2785 }
2786 amba_pclk_unprepare(pcdev);
2787
2788 return 0;
2789}
2790
2791static int __maybe_unused pl330_resume(struct device *dev)
2792{
2793 struct amba_device *pcdev = to_amba_device(dev);
2794 int ret;
2795
2796 ret = amba_pclk_prepare(pcdev);
2797 if (ret)
2798 return ret;
2799
2800 if (!pm_runtime_status_suspended(dev))
2801 ret = amba_pclk_enable(pcdev);
2802
2803 pm_runtime_enable(dev);
2804
2805 return ret;
2806}
2807
2808static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume);
2809
2810static int
2811pl330_probe(struct amba_device *adev, const struct amba_id *id)
2812{
2813 struct dma_pl330_platdata *pdat;
2814 struct pl330_config *pcfg;
2815 struct pl330_dmac *pl330;
2816 struct dma_pl330_chan *pch, *_p;
2817 struct dma_device *pd;
2818 struct resource *res;
2819 int i, ret, irq;
2820 int num_chan;
2821 struct device_node *np = adev->dev.of_node;
2822
2823 pdat = dev_get_platdata(&adev->dev);
2824
2825 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2826 if (ret)
2827 return ret;
2828
2829 /* Allocate a new DMAC and its Channels */
2830 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
2831 if (!pl330) {
2832 dev_err(&adev->dev, "unable to allocate mem\n");
2833 return -ENOMEM;
2834 }
2835
2836 pd = &pl330->ddma;
2837 pd->dev = &adev->dev;
2838
2839 pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
2840
2841 /* get quirk */
2842 for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
2843 if (of_property_read_bool(np, of_quirks[i].quirk))
2844 pl330->quirks |= of_quirks[i].id;
2845
2846 res = &adev->res;
2847 pl330->base = devm_ioremap_resource(&adev->dev, res);
2848 if (IS_ERR(pl330->base))
2849 return PTR_ERR(pl330->base);
2850
2851 amba_set_drvdata(adev, pl330);
2852
2853 for (i = 0; i < AMBA_NR_IRQS; i++) {
2854 irq = adev->irq[i];
2855 if (irq) {
2856 ret = devm_request_irq(&adev->dev, irq,
2857 pl330_irq_handler, 0,
2858 dev_name(&adev->dev), pl330);
2859 if (ret)
2860 return ret;
2861 } else {
2862 break;
2863 }
2864 }
2865
2866 pcfg = &pl330->pcfg;
2867
2868 pcfg->periph_id = adev->periphid;
2869 ret = pl330_add(pl330);
2870 if (ret)
2871 return ret;
2872
2873 INIT_LIST_HEAD(&pl330->desc_pool);
2874 spin_lock_init(&pl330->pool_lock);
2875
2876 /* Create a descriptor pool of default size */
2877 if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC))
2878 dev_warn(&adev->dev, "unable to allocate desc\n");
2879
2880 INIT_LIST_HEAD(&pd->channels);
2881
2882 /* Initialize channel parameters */
2883 if (pdat)
2884 num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan);
2885 else
2886 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
2887
2888 pl330->num_peripherals = num_chan;
2889
2890 pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
2891 if (!pl330->peripherals) {
2892 ret = -ENOMEM;
2893 dev_err(&adev->dev, "unable to allocate pl330->peripherals\n");
2894 goto probe_err2;
2895 }
2896
2897 for (i = 0; i < num_chan; i++) {
2898 pch = &pl330->peripherals[i];
2899 if (!adev->dev.of_node)
2900 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2901 else
2902 pch->chan.private = adev->dev.of_node;
2903
2904 INIT_LIST_HEAD(&pch->submitted_list);
2905 INIT_LIST_HEAD(&pch->work_list);
2906 INIT_LIST_HEAD(&pch->completed_list);
2907 spin_lock_init(&pch->lock);
2908 pch->thread = NULL;
2909 pch->chan.device = pd;
2910 pch->dmac = pl330;
2911
2912 /* Add the channel to the DMAC list */
2913 list_add_tail(&pch->chan.device_node, &pd->channels);
2914 }
2915
2916 if (pdat) {
2917 pd->cap_mask = pdat->cap_mask;
2918 } else {
2919 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
2920 if (pcfg->num_peri) {
2921 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2922 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
2923 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
2924 }
2925 }
2926
2927 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2928 pd->device_free_chan_resources = pl330_free_chan_resources;
2929 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
2930 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
2931 pd->device_tx_status = pl330_tx_status;
2932 pd->device_prep_slave_sg = pl330_prep_slave_sg;
2933 pd->device_config = pl330_config;
2934 pd->device_pause = pl330_pause;
2935 pd->device_terminate_all = pl330_terminate_all;
2936 pd->device_issue_pending = pl330_issue_pending;
2937 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
2938 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
2939 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2940 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2941 pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ?
2942 1 : PL330_MAX_BURST);
2943
2944 ret = dma_async_device_register(pd);
2945 if (ret) {
2946 dev_err(&adev->dev, "unable to register DMAC\n");
2947 goto probe_err3;
2948 }
2949
2950 if (adev->dev.of_node) {
2951 ret = of_dma_controller_register(adev->dev.of_node,
2952 of_dma_pl330_xlate, pl330);
2953 if (ret) {
2954 dev_err(&adev->dev,
2955 "unable to register DMA to the generic DT DMA helpers\n");
2956 }
2957 }
2958
2959 adev->dev.dma_parms = &pl330->dma_parms;
2960
2961 /*
2962 * This is the limit for transfers with a buswidth of 1, larger
2963 * buswidths will have larger limits.
2964 */
2965 ret = dma_set_max_seg_size(&adev->dev, 1900800);
2966 if (ret)
2967 dev_err(&adev->dev, "unable to set the seg size\n");
2968
2969
2970 dev_info(&adev->dev,
2971 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
2972 dev_info(&adev->dev,
2973 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2974 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
2975 pcfg->num_peri, pcfg->num_events);
2976
2977 pm_runtime_irq_safe(&adev->dev);
2978 pm_runtime_use_autosuspend(&adev->dev);
2979 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
2980 pm_runtime_mark_last_busy(&adev->dev);
2981 pm_runtime_put_autosuspend(&adev->dev);
2982
2983 return 0;
2984probe_err3:
2985 /* Idle the DMAC */
2986 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
2987 chan.device_node) {
2988
2989 /* Remove the channel */
2990 list_del(&pch->chan.device_node);
2991
2992 /* Flush the channel */
2993 if (pch->thread) {
2994 pl330_terminate_all(&pch->chan);
2995 pl330_free_chan_resources(&pch->chan);
2996 }
2997 }
2998probe_err2:
2999 pl330_del(pl330);
3000
3001 return ret;
3002}
3003
3004static int pl330_remove(struct amba_device *adev)
3005{
3006 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
3007 struct dma_pl330_chan *pch, *_p;
3008
3009 pm_runtime_get_noresume(pl330->ddma.dev);
3010
3011 if (adev->dev.of_node)
3012 of_dma_controller_free(adev->dev.of_node);
3013
3014 dma_async_device_unregister(&pl330->ddma);
3015
3016 /* Idle the DMAC */
3017 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3018 chan.device_node) {
3019
3020 /* Remove the channel */
3021 list_del(&pch->chan.device_node);
3022
3023 /* Flush the channel */
3024 if (pch->thread) {
3025 pl330_terminate_all(&pch->chan);
3026 pl330_free_chan_resources(&pch->chan);
3027 }
3028 }
3029
3030 pl330_del(pl330);
3031
3032 return 0;
3033}
3034
3035static struct amba_id pl330_ids[] = {
3036 {
3037 .id = 0x00041330,
3038 .mask = 0x000fffff,
3039 },
3040 { 0, 0 },
3041};
3042
3043MODULE_DEVICE_TABLE(amba, pl330_ids);
3044
3045static struct amba_driver pl330_driver = {
3046 .drv = {
3047 .owner = THIS_MODULE,
3048 .name = "dma-pl330",
3049 .pm = &pl330_pm,
3050 },
3051 .id_table = pl330_ids,
3052 .probe = pl330_probe,
3053 .remove = pl330_remove,
3054};
3055
3056module_amba_driver(pl330_driver);
3057
3058MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3059MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3060MODULE_LICENSE("GPL");