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1/*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
22#include <linux/power/smartreflex.h>
23#include <linux/i2c-omap.h>
24
25#include <linux/omap-dma.h>
26#include <linux/platform_data/spi-omap2-mcspi.h>
27#include <linux/platform_data/asoc-ti-mcbsp.h>
28#include <plat/dmtimer.h>
29
30#include "omap_hwmod.h"
31#include "omap_hwmod_common_data.h"
32#include "cm1_7xx.h"
33#include "cm2_7xx.h"
34#include "prm7xx.h"
35#include "i2c.h"
36#include "mmc.h"
37#include "wd_timer.h"
38
39/* Base offset for all DRA7XX interrupts external to MPUSS */
40#define DRA7XX_IRQ_GIC_START 32
41
42/* Base offset for all DRA7XX dma requests */
43#define DRA7XX_DMA_REQ_START 1
44
45
46/*
47 * IP blocks
48 */
49
50/*
51 * 'l3' class
52 * instance(s): l3_instr, l3_main_1, l3_main_2
53 */
54static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
55 .name = "l3",
56};
57
58/* l3_instr */
59static struct omap_hwmod dra7xx_l3_instr_hwmod = {
60 .name = "l3_instr",
61 .class = &dra7xx_l3_hwmod_class,
62 .clkdm_name = "l3instr_clkdm",
63 .prcm = {
64 .omap4 = {
65 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
66 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
67 .modulemode = MODULEMODE_HWCTRL,
68 },
69 },
70};
71
72/* l3_main_1 */
73static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
74 .name = "l3_main_1",
75 .class = &dra7xx_l3_hwmod_class,
76 .clkdm_name = "l3main1_clkdm",
77 .prcm = {
78 .omap4 = {
79 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
80 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
81 },
82 },
83};
84
85/* l3_main_2 */
86static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
87 .name = "l3_main_2",
88 .class = &dra7xx_l3_hwmod_class,
89 .clkdm_name = "l3instr_clkdm",
90 .prcm = {
91 .omap4 = {
92 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
93 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
94 .modulemode = MODULEMODE_HWCTRL,
95 },
96 },
97};
98
99/*
100 * 'l4' class
101 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
102 */
103static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
104 .name = "l4",
105};
106
107/* l4_cfg */
108static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
109 .name = "l4_cfg",
110 .class = &dra7xx_l4_hwmod_class,
111 .clkdm_name = "l4cfg_clkdm",
112 .prcm = {
113 .omap4 = {
114 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
116 },
117 },
118};
119
120/* l4_per1 */
121static struct omap_hwmod dra7xx_l4_per1_hwmod = {
122 .name = "l4_per1",
123 .class = &dra7xx_l4_hwmod_class,
124 .clkdm_name = "l4per_clkdm",
125 .prcm = {
126 .omap4 = {
127 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
128 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
129 },
130 },
131};
132
133/* l4_per2 */
134static struct omap_hwmod dra7xx_l4_per2_hwmod = {
135 .name = "l4_per2",
136 .class = &dra7xx_l4_hwmod_class,
137 .clkdm_name = "l4per2_clkdm",
138 .prcm = {
139 .omap4 = {
140 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
141 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
142 },
143 },
144};
145
146/* l4_per3 */
147static struct omap_hwmod dra7xx_l4_per3_hwmod = {
148 .name = "l4_per3",
149 .class = &dra7xx_l4_hwmod_class,
150 .clkdm_name = "l4per3_clkdm",
151 .prcm = {
152 .omap4 = {
153 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
154 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
155 },
156 },
157};
158
159/* l4_wkup */
160static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
161 .name = "l4_wkup",
162 .class = &dra7xx_l4_hwmod_class,
163 .clkdm_name = "wkupaon_clkdm",
164 .prcm = {
165 .omap4 = {
166 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
167 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
168 },
169 },
170};
171
172/*
173 * 'atl' class
174 *
175 */
176
177static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
178 .name = "atl",
179};
180
181/* atl */
182static struct omap_hwmod dra7xx_atl_hwmod = {
183 .name = "atl",
184 .class = &dra7xx_atl_hwmod_class,
185 .clkdm_name = "atl_clkdm",
186 .main_clk = "atl_gfclk_mux",
187 .prcm = {
188 .omap4 = {
189 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
190 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
191 .modulemode = MODULEMODE_SWCTRL,
192 },
193 },
194};
195
196/*
197 * 'bb2d' class
198 *
199 */
200
201static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
202 .name = "bb2d",
203};
204
205/* bb2d */
206static struct omap_hwmod dra7xx_bb2d_hwmod = {
207 .name = "bb2d",
208 .class = &dra7xx_bb2d_hwmod_class,
209 .clkdm_name = "dss_clkdm",
210 .main_clk = "dpll_core_h24x2_ck",
211 .prcm = {
212 .omap4 = {
213 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
214 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
215 .modulemode = MODULEMODE_SWCTRL,
216 },
217 },
218};
219
220/*
221 * 'counter' class
222 *
223 */
224
225static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
226 .rev_offs = 0x0000,
227 .sysc_offs = 0x0010,
228 .sysc_flags = SYSC_HAS_SIDLEMODE,
229 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
230 SIDLE_SMART_WKUP),
231 .sysc_fields = &omap_hwmod_sysc_type1,
232};
233
234static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
235 .name = "counter",
236 .sysc = &dra7xx_counter_sysc,
237};
238
239/* counter_32k */
240static struct omap_hwmod dra7xx_counter_32k_hwmod = {
241 .name = "counter_32k",
242 .class = &dra7xx_counter_hwmod_class,
243 .clkdm_name = "wkupaon_clkdm",
244 .flags = HWMOD_SWSUP_SIDLE,
245 .main_clk = "wkupaon_iclk_mux",
246 .prcm = {
247 .omap4 = {
248 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
249 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
250 },
251 },
252};
253
254/*
255 * 'ctrl_module' class
256 *
257 */
258
259static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
260 .name = "ctrl_module",
261};
262
263/* ctrl_module_wkup */
264static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
265 .name = "ctrl_module_wkup",
266 .class = &dra7xx_ctrl_module_hwmod_class,
267 .clkdm_name = "wkupaon_clkdm",
268 .prcm = {
269 .omap4 = {
270 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
271 },
272 },
273};
274
275/*
276 * 'dcan' class
277 *
278 */
279
280static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
281 .name = "dcan",
282};
283
284/* dcan1 */
285static struct omap_hwmod dra7xx_dcan1_hwmod = {
286 .name = "dcan1",
287 .class = &dra7xx_dcan_hwmod_class,
288 .clkdm_name = "wkupaon_clkdm",
289 .main_clk = "dcan1_sys_clk_mux",
290 .prcm = {
291 .omap4 = {
292 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
293 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
294 .modulemode = MODULEMODE_SWCTRL,
295 },
296 },
297};
298
299/* dcan2 */
300static struct omap_hwmod dra7xx_dcan2_hwmod = {
301 .name = "dcan2",
302 .class = &dra7xx_dcan_hwmod_class,
303 .clkdm_name = "l4per2_clkdm",
304 .main_clk = "sys_clkin1",
305 .prcm = {
306 .omap4 = {
307 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
308 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
309 .modulemode = MODULEMODE_SWCTRL,
310 },
311 },
312};
313
314/*
315 * 'dma' class
316 *
317 */
318
319static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
320 .rev_offs = 0x0000,
321 .sysc_offs = 0x002c,
322 .syss_offs = 0x0028,
323 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
324 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
325 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
326 SYSS_HAS_RESET_STATUS),
327 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
328 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
329 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
330 .sysc_fields = &omap_hwmod_sysc_type1,
331};
332
333static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
334 .name = "dma",
335 .sysc = &dra7xx_dma_sysc,
336};
337
338/* dma dev_attr */
339static struct omap_dma_dev_attr dma_dev_attr = {
340 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
341 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
342 .lch_count = 32,
343};
344
345/* dma_system */
346static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
347 { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
348 { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
349 { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
350 { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
351 { .irq = -1 }
352};
353
354static struct omap_hwmod dra7xx_dma_system_hwmod = {
355 .name = "dma_system",
356 .class = &dra7xx_dma_hwmod_class,
357 .clkdm_name = "dma_clkdm",
358 .mpu_irqs = dra7xx_dma_system_irqs,
359 .main_clk = "l3_iclk_div",
360 .prcm = {
361 .omap4 = {
362 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
363 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
364 },
365 },
366 .dev_attr = &dma_dev_attr,
367};
368
369/*
370 * 'dss' class
371 *
372 */
373
374static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
375 .rev_offs = 0x0000,
376 .syss_offs = 0x0014,
377 .sysc_flags = SYSS_HAS_RESET_STATUS,
378};
379
380static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
381 .name = "dss",
382 .sysc = &dra7xx_dss_sysc,
383 .reset = omap_dss_reset,
384};
385
386/* dss */
387static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
388 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
389 { .dma_req = -1 }
390};
391
392static struct omap_hwmod_opt_clk dss_opt_clks[] = {
393 { .role = "dss_clk", .clk = "dss_dss_clk" },
394 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
395 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
396 { .role = "video2_clk", .clk = "dss_video2_clk" },
397 { .role = "video1_clk", .clk = "dss_video1_clk" },
398 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
399};
400
401static struct omap_hwmod dra7xx_dss_hwmod = {
402 .name = "dss_core",
403 .class = &dra7xx_dss_hwmod_class,
404 .clkdm_name = "dss_clkdm",
405 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
406 .sdma_reqs = dra7xx_dss_sdma_reqs,
407 .main_clk = "dss_dss_clk",
408 .prcm = {
409 .omap4 = {
410 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
411 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
412 .modulemode = MODULEMODE_SWCTRL,
413 },
414 },
415 .opt_clks = dss_opt_clks,
416 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
417};
418
419/*
420 * 'dispc' class
421 * display controller
422 */
423
424static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
425 .rev_offs = 0x0000,
426 .sysc_offs = 0x0010,
427 .syss_offs = 0x0014,
428 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
429 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
430 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
431 SYSS_HAS_RESET_STATUS),
432 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
433 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
434 .sysc_fields = &omap_hwmod_sysc_type1,
435};
436
437static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
438 .name = "dispc",
439 .sysc = &dra7xx_dispc_sysc,
440};
441
442/* dss_dispc */
443/* dss_dispc dev_attr */
444static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
445 .has_framedonetv_irq = 1,
446 .manager_count = 4,
447};
448
449static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
450 .name = "dss_dispc",
451 .class = &dra7xx_dispc_hwmod_class,
452 .clkdm_name = "dss_clkdm",
453 .main_clk = "dss_dss_clk",
454 .prcm = {
455 .omap4 = {
456 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
457 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
458 },
459 },
460 .dev_attr = &dss_dispc_dev_attr,
461};
462
463/*
464 * 'hdmi' class
465 * hdmi controller
466 */
467
468static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
469 .rev_offs = 0x0000,
470 .sysc_offs = 0x0010,
471 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
472 SYSC_HAS_SOFTRESET),
473 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
474 SIDLE_SMART_WKUP),
475 .sysc_fields = &omap_hwmod_sysc_type2,
476};
477
478static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
479 .name = "hdmi",
480 .sysc = &dra7xx_hdmi_sysc,
481};
482
483/* dss_hdmi */
484
485static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
486 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
487};
488
489static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
490 .name = "dss_hdmi",
491 .class = &dra7xx_hdmi_hwmod_class,
492 .clkdm_name = "dss_clkdm",
493 .main_clk = "dss_48mhz_clk",
494 .prcm = {
495 .omap4 = {
496 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
497 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
498 },
499 },
500 .opt_clks = dss_hdmi_opt_clks,
501 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
502};
503
504/*
505 * 'elm' class
506 *
507 */
508
509static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
510 .rev_offs = 0x0000,
511 .sysc_offs = 0x0010,
512 .syss_offs = 0x0014,
513 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
514 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
515 SYSS_HAS_RESET_STATUS),
516 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
517 SIDLE_SMART_WKUP),
518 .sysc_fields = &omap_hwmod_sysc_type1,
519};
520
521static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
522 .name = "elm",
523 .sysc = &dra7xx_elm_sysc,
524};
525
526/* elm */
527
528static struct omap_hwmod dra7xx_elm_hwmod = {
529 .name = "elm",
530 .class = &dra7xx_elm_hwmod_class,
531 .clkdm_name = "l4per_clkdm",
532 .main_clk = "l3_iclk_div",
533 .prcm = {
534 .omap4 = {
535 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
536 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
537 },
538 },
539};
540
541/*
542 * 'gpio' class
543 *
544 */
545
546static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
547 .rev_offs = 0x0000,
548 .sysc_offs = 0x0010,
549 .syss_offs = 0x0114,
550 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
551 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
552 SYSS_HAS_RESET_STATUS),
553 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
554 SIDLE_SMART_WKUP),
555 .sysc_fields = &omap_hwmod_sysc_type1,
556};
557
558static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
559 .name = "gpio",
560 .sysc = &dra7xx_gpio_sysc,
561 .rev = 2,
562};
563
564/* gpio dev_attr */
565static struct omap_gpio_dev_attr gpio_dev_attr = {
566 .bank_width = 32,
567 .dbck_flag = true,
568};
569
570/* gpio1 */
571static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
572 { .role = "dbclk", .clk = "gpio1_dbclk" },
573};
574
575static struct omap_hwmod dra7xx_gpio1_hwmod = {
576 .name = "gpio1",
577 .class = &dra7xx_gpio_hwmod_class,
578 .clkdm_name = "wkupaon_clkdm",
579 .main_clk = "wkupaon_iclk_mux",
580 .prcm = {
581 .omap4 = {
582 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
583 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
584 .modulemode = MODULEMODE_HWCTRL,
585 },
586 },
587 .opt_clks = gpio1_opt_clks,
588 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
589 .dev_attr = &gpio_dev_attr,
590};
591
592/* gpio2 */
593static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
594 { .role = "dbclk", .clk = "gpio2_dbclk" },
595};
596
597static struct omap_hwmod dra7xx_gpio2_hwmod = {
598 .name = "gpio2",
599 .class = &dra7xx_gpio_hwmod_class,
600 .clkdm_name = "l4per_clkdm",
601 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
602 .main_clk = "l3_iclk_div",
603 .prcm = {
604 .omap4 = {
605 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
606 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
607 .modulemode = MODULEMODE_HWCTRL,
608 },
609 },
610 .opt_clks = gpio2_opt_clks,
611 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
612 .dev_attr = &gpio_dev_attr,
613};
614
615/* gpio3 */
616static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
617 { .role = "dbclk", .clk = "gpio3_dbclk" },
618};
619
620static struct omap_hwmod dra7xx_gpio3_hwmod = {
621 .name = "gpio3",
622 .class = &dra7xx_gpio_hwmod_class,
623 .clkdm_name = "l4per_clkdm",
624 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
625 .main_clk = "l3_iclk_div",
626 .prcm = {
627 .omap4 = {
628 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
629 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
630 .modulemode = MODULEMODE_HWCTRL,
631 },
632 },
633 .opt_clks = gpio3_opt_clks,
634 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
635 .dev_attr = &gpio_dev_attr,
636};
637
638/* gpio4 */
639static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
640 { .role = "dbclk", .clk = "gpio4_dbclk" },
641};
642
643static struct omap_hwmod dra7xx_gpio4_hwmod = {
644 .name = "gpio4",
645 .class = &dra7xx_gpio_hwmod_class,
646 .clkdm_name = "l4per_clkdm",
647 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
648 .main_clk = "l3_iclk_div",
649 .prcm = {
650 .omap4 = {
651 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
652 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
653 .modulemode = MODULEMODE_HWCTRL,
654 },
655 },
656 .opt_clks = gpio4_opt_clks,
657 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
658 .dev_attr = &gpio_dev_attr,
659};
660
661/* gpio5 */
662static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
663 { .role = "dbclk", .clk = "gpio5_dbclk" },
664};
665
666static struct omap_hwmod dra7xx_gpio5_hwmod = {
667 .name = "gpio5",
668 .class = &dra7xx_gpio_hwmod_class,
669 .clkdm_name = "l4per_clkdm",
670 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
671 .main_clk = "l3_iclk_div",
672 .prcm = {
673 .omap4 = {
674 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
675 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
676 .modulemode = MODULEMODE_HWCTRL,
677 },
678 },
679 .opt_clks = gpio5_opt_clks,
680 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
681 .dev_attr = &gpio_dev_attr,
682};
683
684/* gpio6 */
685static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
686 { .role = "dbclk", .clk = "gpio6_dbclk" },
687};
688
689static struct omap_hwmod dra7xx_gpio6_hwmod = {
690 .name = "gpio6",
691 .class = &dra7xx_gpio_hwmod_class,
692 .clkdm_name = "l4per_clkdm",
693 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
694 .main_clk = "l3_iclk_div",
695 .prcm = {
696 .omap4 = {
697 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
698 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
699 .modulemode = MODULEMODE_HWCTRL,
700 },
701 },
702 .opt_clks = gpio6_opt_clks,
703 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
704 .dev_attr = &gpio_dev_attr,
705};
706
707/* gpio7 */
708static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
709 { .role = "dbclk", .clk = "gpio7_dbclk" },
710};
711
712static struct omap_hwmod dra7xx_gpio7_hwmod = {
713 .name = "gpio7",
714 .class = &dra7xx_gpio_hwmod_class,
715 .clkdm_name = "l4per_clkdm",
716 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
717 .main_clk = "l3_iclk_div",
718 .prcm = {
719 .omap4 = {
720 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
721 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
722 .modulemode = MODULEMODE_HWCTRL,
723 },
724 },
725 .opt_clks = gpio7_opt_clks,
726 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
727 .dev_attr = &gpio_dev_attr,
728};
729
730/* gpio8 */
731static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
732 { .role = "dbclk", .clk = "gpio8_dbclk" },
733};
734
735static struct omap_hwmod dra7xx_gpio8_hwmod = {
736 .name = "gpio8",
737 .class = &dra7xx_gpio_hwmod_class,
738 .clkdm_name = "l4per_clkdm",
739 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
740 .main_clk = "l3_iclk_div",
741 .prcm = {
742 .omap4 = {
743 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
744 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
745 .modulemode = MODULEMODE_HWCTRL,
746 },
747 },
748 .opt_clks = gpio8_opt_clks,
749 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
750 .dev_attr = &gpio_dev_attr,
751};
752
753/*
754 * 'gpmc' class
755 *
756 */
757
758static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
759 .rev_offs = 0x0000,
760 .sysc_offs = 0x0010,
761 .syss_offs = 0x0014,
762 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
763 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
764 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
765 SIDLE_SMART_WKUP),
766 .sysc_fields = &omap_hwmod_sysc_type1,
767};
768
769static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
770 .name = "gpmc",
771 .sysc = &dra7xx_gpmc_sysc,
772};
773
774/* gpmc */
775
776static struct omap_hwmod dra7xx_gpmc_hwmod = {
777 .name = "gpmc",
778 .class = &dra7xx_gpmc_hwmod_class,
779 .clkdm_name = "l3main1_clkdm",
780 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
781 .main_clk = "l3_iclk_div",
782 .prcm = {
783 .omap4 = {
784 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
785 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
786 .modulemode = MODULEMODE_HWCTRL,
787 },
788 },
789};
790
791/*
792 * 'hdq1w' class
793 *
794 */
795
796static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
797 .rev_offs = 0x0000,
798 .sysc_offs = 0x0014,
799 .syss_offs = 0x0018,
800 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
801 SYSS_HAS_RESET_STATUS),
802 .sysc_fields = &omap_hwmod_sysc_type1,
803};
804
805static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
806 .name = "hdq1w",
807 .sysc = &dra7xx_hdq1w_sysc,
808};
809
810/* hdq1w */
811
812static struct omap_hwmod dra7xx_hdq1w_hwmod = {
813 .name = "hdq1w",
814 .class = &dra7xx_hdq1w_hwmod_class,
815 .clkdm_name = "l4per_clkdm",
816 .flags = HWMOD_INIT_NO_RESET,
817 .main_clk = "func_12m_fclk",
818 .prcm = {
819 .omap4 = {
820 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
821 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
822 .modulemode = MODULEMODE_SWCTRL,
823 },
824 },
825};
826
827/*
828 * 'i2c' class
829 *
830 */
831
832static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
833 .sysc_offs = 0x0010,
834 .syss_offs = 0x0090,
835 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
836 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
837 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
838 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
839 SIDLE_SMART_WKUP),
840 .clockact = CLOCKACT_TEST_ICLK,
841 .sysc_fields = &omap_hwmod_sysc_type1,
842};
843
844static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
845 .name = "i2c",
846 .sysc = &dra7xx_i2c_sysc,
847 .reset = &omap_i2c_reset,
848 .rev = OMAP_I2C_IP_VERSION_2,
849};
850
851/* i2c dev_attr */
852static struct omap_i2c_dev_attr i2c_dev_attr = {
853 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
854};
855
856/* i2c1 */
857static struct omap_hwmod dra7xx_i2c1_hwmod = {
858 .name = "i2c1",
859 .class = &dra7xx_i2c_hwmod_class,
860 .clkdm_name = "l4per_clkdm",
861 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
862 .main_clk = "func_96m_fclk",
863 .prcm = {
864 .omap4 = {
865 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
866 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
867 .modulemode = MODULEMODE_SWCTRL,
868 },
869 },
870 .dev_attr = &i2c_dev_attr,
871};
872
873/* i2c2 */
874static struct omap_hwmod dra7xx_i2c2_hwmod = {
875 .name = "i2c2",
876 .class = &dra7xx_i2c_hwmod_class,
877 .clkdm_name = "l4per_clkdm",
878 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
879 .main_clk = "func_96m_fclk",
880 .prcm = {
881 .omap4 = {
882 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
883 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
884 .modulemode = MODULEMODE_SWCTRL,
885 },
886 },
887 .dev_attr = &i2c_dev_attr,
888};
889
890/* i2c3 */
891static struct omap_hwmod dra7xx_i2c3_hwmod = {
892 .name = "i2c3",
893 .class = &dra7xx_i2c_hwmod_class,
894 .clkdm_name = "l4per_clkdm",
895 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
896 .main_clk = "func_96m_fclk",
897 .prcm = {
898 .omap4 = {
899 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
900 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
901 .modulemode = MODULEMODE_SWCTRL,
902 },
903 },
904 .dev_attr = &i2c_dev_attr,
905};
906
907/* i2c4 */
908static struct omap_hwmod dra7xx_i2c4_hwmod = {
909 .name = "i2c4",
910 .class = &dra7xx_i2c_hwmod_class,
911 .clkdm_name = "l4per_clkdm",
912 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
913 .main_clk = "func_96m_fclk",
914 .prcm = {
915 .omap4 = {
916 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
917 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
918 .modulemode = MODULEMODE_SWCTRL,
919 },
920 },
921 .dev_attr = &i2c_dev_attr,
922};
923
924/* i2c5 */
925static struct omap_hwmod dra7xx_i2c5_hwmod = {
926 .name = "i2c5",
927 .class = &dra7xx_i2c_hwmod_class,
928 .clkdm_name = "ipu_clkdm",
929 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
930 .main_clk = "func_96m_fclk",
931 .prcm = {
932 .omap4 = {
933 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
934 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
935 .modulemode = MODULEMODE_SWCTRL,
936 },
937 },
938 .dev_attr = &i2c_dev_attr,
939};
940
941/*
942 * 'mcspi' class
943 *
944 */
945
946static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
947 .rev_offs = 0x0000,
948 .sysc_offs = 0x0010,
949 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
950 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
951 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
952 SIDLE_SMART_WKUP),
953 .sysc_fields = &omap_hwmod_sysc_type2,
954};
955
956static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
957 .name = "mcspi",
958 .sysc = &dra7xx_mcspi_sysc,
959 .rev = OMAP4_MCSPI_REV,
960};
961
962/* mcspi1 */
963/* mcspi1 dev_attr */
964static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
965 .num_chipselect = 4,
966};
967
968static struct omap_hwmod dra7xx_mcspi1_hwmod = {
969 .name = "mcspi1",
970 .class = &dra7xx_mcspi_hwmod_class,
971 .clkdm_name = "l4per_clkdm",
972 .main_clk = "func_48m_fclk",
973 .prcm = {
974 .omap4 = {
975 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
976 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
977 .modulemode = MODULEMODE_SWCTRL,
978 },
979 },
980 .dev_attr = &mcspi1_dev_attr,
981};
982
983/* mcspi2 */
984/* mcspi2 dev_attr */
985static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
986 .num_chipselect = 2,
987};
988
989static struct omap_hwmod dra7xx_mcspi2_hwmod = {
990 .name = "mcspi2",
991 .class = &dra7xx_mcspi_hwmod_class,
992 .clkdm_name = "l4per_clkdm",
993 .main_clk = "func_48m_fclk",
994 .prcm = {
995 .omap4 = {
996 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
997 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
998 .modulemode = MODULEMODE_SWCTRL,
999 },
1000 },
1001 .dev_attr = &mcspi2_dev_attr,
1002};
1003
1004/* mcspi3 */
1005/* mcspi3 dev_attr */
1006static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1007 .num_chipselect = 2,
1008};
1009
1010static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1011 .name = "mcspi3",
1012 .class = &dra7xx_mcspi_hwmod_class,
1013 .clkdm_name = "l4per_clkdm",
1014 .main_clk = "func_48m_fclk",
1015 .prcm = {
1016 .omap4 = {
1017 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1018 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1019 .modulemode = MODULEMODE_SWCTRL,
1020 },
1021 },
1022 .dev_attr = &mcspi3_dev_attr,
1023};
1024
1025/* mcspi4 */
1026/* mcspi4 dev_attr */
1027static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1028 .num_chipselect = 1,
1029};
1030
1031static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1032 .name = "mcspi4",
1033 .class = &dra7xx_mcspi_hwmod_class,
1034 .clkdm_name = "l4per_clkdm",
1035 .main_clk = "func_48m_fclk",
1036 .prcm = {
1037 .omap4 = {
1038 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1039 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1040 .modulemode = MODULEMODE_SWCTRL,
1041 },
1042 },
1043 .dev_attr = &mcspi4_dev_attr,
1044};
1045
1046/*
1047 * 'mmc' class
1048 *
1049 */
1050
1051static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1052 .rev_offs = 0x0000,
1053 .sysc_offs = 0x0010,
1054 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1055 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1056 SYSC_HAS_SOFTRESET),
1057 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1058 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1059 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1060 .sysc_fields = &omap_hwmod_sysc_type2,
1061};
1062
1063static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1064 .name = "mmc",
1065 .sysc = &dra7xx_mmc_sysc,
1066};
1067
1068/* mmc1 */
1069static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1070 { .role = "clk32k", .clk = "mmc1_clk32k" },
1071};
1072
1073/* mmc1 dev_attr */
1074static struct omap_mmc_dev_attr mmc1_dev_attr = {
1075 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1076};
1077
1078static struct omap_hwmod dra7xx_mmc1_hwmod = {
1079 .name = "mmc1",
1080 .class = &dra7xx_mmc_hwmod_class,
1081 .clkdm_name = "l3init_clkdm",
1082 .main_clk = "mmc1_fclk_div",
1083 .prcm = {
1084 .omap4 = {
1085 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1086 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1087 .modulemode = MODULEMODE_SWCTRL,
1088 },
1089 },
1090 .opt_clks = mmc1_opt_clks,
1091 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1092 .dev_attr = &mmc1_dev_attr,
1093};
1094
1095/* mmc2 */
1096static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1097 { .role = "clk32k", .clk = "mmc2_clk32k" },
1098};
1099
1100static struct omap_hwmod dra7xx_mmc2_hwmod = {
1101 .name = "mmc2",
1102 .class = &dra7xx_mmc_hwmod_class,
1103 .clkdm_name = "l3init_clkdm",
1104 .main_clk = "mmc2_fclk_div",
1105 .prcm = {
1106 .omap4 = {
1107 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1108 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1109 .modulemode = MODULEMODE_SWCTRL,
1110 },
1111 },
1112 .opt_clks = mmc2_opt_clks,
1113 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1114};
1115
1116/* mmc3 */
1117static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1118 { .role = "clk32k", .clk = "mmc3_clk32k" },
1119};
1120
1121static struct omap_hwmod dra7xx_mmc3_hwmod = {
1122 .name = "mmc3",
1123 .class = &dra7xx_mmc_hwmod_class,
1124 .clkdm_name = "l4per_clkdm",
1125 .main_clk = "mmc3_gfclk_div",
1126 .prcm = {
1127 .omap4 = {
1128 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1129 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1130 .modulemode = MODULEMODE_SWCTRL,
1131 },
1132 },
1133 .opt_clks = mmc3_opt_clks,
1134 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1135};
1136
1137/* mmc4 */
1138static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1139 { .role = "clk32k", .clk = "mmc4_clk32k" },
1140};
1141
1142static struct omap_hwmod dra7xx_mmc4_hwmod = {
1143 .name = "mmc4",
1144 .class = &dra7xx_mmc_hwmod_class,
1145 .clkdm_name = "l4per_clkdm",
1146 .main_clk = "mmc4_gfclk_div",
1147 .prcm = {
1148 .omap4 = {
1149 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1150 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1151 .modulemode = MODULEMODE_SWCTRL,
1152 },
1153 },
1154 .opt_clks = mmc4_opt_clks,
1155 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1156};
1157
1158/*
1159 * 'mpu' class
1160 *
1161 */
1162
1163static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1164 .name = "mpu",
1165};
1166
1167/* mpu */
1168static struct omap_hwmod dra7xx_mpu_hwmod = {
1169 .name = "mpu",
1170 .class = &dra7xx_mpu_hwmod_class,
1171 .clkdm_name = "mpu_clkdm",
1172 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1173 .main_clk = "dpll_mpu_m2_ck",
1174 .prcm = {
1175 .omap4 = {
1176 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1177 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1178 },
1179 },
1180};
1181
1182/*
1183 * 'ocp2scp' class
1184 *
1185 */
1186
1187static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1188 .rev_offs = 0x0000,
1189 .sysc_offs = 0x0010,
1190 .syss_offs = 0x0014,
1191 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1192 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1193 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1194 SIDLE_SMART_WKUP),
1195 .sysc_fields = &omap_hwmod_sysc_type1,
1196};
1197
1198static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1199 .name = "ocp2scp",
1200 .sysc = &dra7xx_ocp2scp_sysc,
1201};
1202
1203/* ocp2scp1 */
1204static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1205 .name = "ocp2scp1",
1206 .class = &dra7xx_ocp2scp_hwmod_class,
1207 .clkdm_name = "l3init_clkdm",
1208 .main_clk = "l4_root_clk_div",
1209 .prcm = {
1210 .omap4 = {
1211 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1212 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1213 .modulemode = MODULEMODE_HWCTRL,
1214 },
1215 },
1216};
1217
1218/*
1219 * 'qspi' class
1220 *
1221 */
1222
1223static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1224 .sysc_offs = 0x0010,
1225 .sysc_flags = SYSC_HAS_SIDLEMODE,
1226 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1227 SIDLE_SMART_WKUP),
1228 .sysc_fields = &omap_hwmod_sysc_type2,
1229};
1230
1231static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1232 .name = "qspi",
1233 .sysc = &dra7xx_qspi_sysc,
1234};
1235
1236/* qspi */
1237static struct omap_hwmod dra7xx_qspi_hwmod = {
1238 .name = "qspi",
1239 .class = &dra7xx_qspi_hwmod_class,
1240 .clkdm_name = "l4per2_clkdm",
1241 .main_clk = "qspi_gfclk_div",
1242 .prcm = {
1243 .omap4 = {
1244 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1245 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1246 .modulemode = MODULEMODE_SWCTRL,
1247 },
1248 },
1249};
1250
1251/*
1252 * 'sata' class
1253 *
1254 */
1255
1256static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1257 .sysc_offs = 0x0000,
1258 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1259 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1260 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1261 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1262 .sysc_fields = &omap_hwmod_sysc_type2,
1263};
1264
1265static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1266 .name = "sata",
1267 .sysc = &dra7xx_sata_sysc,
1268};
1269
1270/* sata */
1271static struct omap_hwmod_opt_clk sata_opt_clks[] = {
1272 { .role = "ref_clk", .clk = "sata_ref_clk" },
1273};
1274
1275static struct omap_hwmod dra7xx_sata_hwmod = {
1276 .name = "sata",
1277 .class = &dra7xx_sata_hwmod_class,
1278 .clkdm_name = "l3init_clkdm",
1279 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1280 .main_clk = "func_48m_fclk",
1281 .prcm = {
1282 .omap4 = {
1283 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1284 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1285 .modulemode = MODULEMODE_SWCTRL,
1286 },
1287 },
1288 .opt_clks = sata_opt_clks,
1289 .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
1290};
1291
1292/*
1293 * 'smartreflex' class
1294 *
1295 */
1296
1297/* The IP is not compliant to type1 / type2 scheme */
1298static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1299 .sidle_shift = 24,
1300 .enwkup_shift = 26,
1301};
1302
1303static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1304 .sysc_offs = 0x0038,
1305 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1306 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1307 SIDLE_SMART_WKUP),
1308 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1309};
1310
1311static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1312 .name = "smartreflex",
1313 .sysc = &dra7xx_smartreflex_sysc,
1314 .rev = 2,
1315};
1316
1317/* smartreflex_core */
1318/* smartreflex_core dev_attr */
1319static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1320 .sensor_voltdm_name = "core",
1321};
1322
1323static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1324 .name = "smartreflex_core",
1325 .class = &dra7xx_smartreflex_hwmod_class,
1326 .clkdm_name = "coreaon_clkdm",
1327 .main_clk = "wkupaon_iclk_mux",
1328 .prcm = {
1329 .omap4 = {
1330 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1331 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1332 .modulemode = MODULEMODE_SWCTRL,
1333 },
1334 },
1335 .dev_attr = &smartreflex_core_dev_attr,
1336};
1337
1338/* smartreflex_mpu */
1339/* smartreflex_mpu dev_attr */
1340static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1341 .sensor_voltdm_name = "mpu",
1342};
1343
1344static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1345 .name = "smartreflex_mpu",
1346 .class = &dra7xx_smartreflex_hwmod_class,
1347 .clkdm_name = "coreaon_clkdm",
1348 .main_clk = "wkupaon_iclk_mux",
1349 .prcm = {
1350 .omap4 = {
1351 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1352 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1353 .modulemode = MODULEMODE_SWCTRL,
1354 },
1355 },
1356 .dev_attr = &smartreflex_mpu_dev_attr,
1357};
1358
1359/*
1360 * 'spinlock' class
1361 *
1362 */
1363
1364static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1365 .rev_offs = 0x0000,
1366 .sysc_offs = 0x0010,
1367 .syss_offs = 0x0014,
1368 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1369 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1370 SYSS_HAS_RESET_STATUS),
1371 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1372 .sysc_fields = &omap_hwmod_sysc_type1,
1373};
1374
1375static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1376 .name = "spinlock",
1377 .sysc = &dra7xx_spinlock_sysc,
1378};
1379
1380/* spinlock */
1381static struct omap_hwmod dra7xx_spinlock_hwmod = {
1382 .name = "spinlock",
1383 .class = &dra7xx_spinlock_hwmod_class,
1384 .clkdm_name = "l4cfg_clkdm",
1385 .main_clk = "l3_iclk_div",
1386 .prcm = {
1387 .omap4 = {
1388 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1389 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1390 },
1391 },
1392};
1393
1394/*
1395 * 'timer' class
1396 *
1397 * This class contains several variants: ['timer_1ms', 'timer_secure',
1398 * 'timer']
1399 */
1400
1401static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1402 .rev_offs = 0x0000,
1403 .sysc_offs = 0x0010,
1404 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1405 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1406 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1407 SIDLE_SMART_WKUP),
1408 .sysc_fields = &omap_hwmod_sysc_type2,
1409};
1410
1411static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1412 .name = "timer",
1413 .sysc = &dra7xx_timer_1ms_sysc,
1414};
1415
1416static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
1417 .rev_offs = 0x0000,
1418 .sysc_offs = 0x0010,
1419 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1420 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1421 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1422 SIDLE_SMART_WKUP),
1423 .sysc_fields = &omap_hwmod_sysc_type2,
1424};
1425
1426static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
1427 .name = "timer",
1428 .sysc = &dra7xx_timer_secure_sysc,
1429};
1430
1431static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1432 .rev_offs = 0x0000,
1433 .sysc_offs = 0x0010,
1434 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1435 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1436 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1437 SIDLE_SMART_WKUP),
1438 .sysc_fields = &omap_hwmod_sysc_type2,
1439};
1440
1441static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1442 .name = "timer",
1443 .sysc = &dra7xx_timer_sysc,
1444};
1445
1446/* timer1 */
1447static struct omap_hwmod dra7xx_timer1_hwmod = {
1448 .name = "timer1",
1449 .class = &dra7xx_timer_1ms_hwmod_class,
1450 .clkdm_name = "wkupaon_clkdm",
1451 .main_clk = "timer1_gfclk_mux",
1452 .prcm = {
1453 .omap4 = {
1454 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1455 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1456 .modulemode = MODULEMODE_SWCTRL,
1457 },
1458 },
1459};
1460
1461/* timer2 */
1462static struct omap_hwmod dra7xx_timer2_hwmod = {
1463 .name = "timer2",
1464 .class = &dra7xx_timer_1ms_hwmod_class,
1465 .clkdm_name = "l4per_clkdm",
1466 .main_clk = "timer2_gfclk_mux",
1467 .prcm = {
1468 .omap4 = {
1469 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1470 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1471 .modulemode = MODULEMODE_SWCTRL,
1472 },
1473 },
1474};
1475
1476/* timer3 */
1477static struct omap_hwmod dra7xx_timer3_hwmod = {
1478 .name = "timer3",
1479 .class = &dra7xx_timer_hwmod_class,
1480 .clkdm_name = "l4per_clkdm",
1481 .main_clk = "timer3_gfclk_mux",
1482 .prcm = {
1483 .omap4 = {
1484 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1485 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1486 .modulemode = MODULEMODE_SWCTRL,
1487 },
1488 },
1489};
1490
1491/* timer4 */
1492static struct omap_hwmod dra7xx_timer4_hwmod = {
1493 .name = "timer4",
1494 .class = &dra7xx_timer_secure_hwmod_class,
1495 .clkdm_name = "l4per_clkdm",
1496 .main_clk = "timer4_gfclk_mux",
1497 .prcm = {
1498 .omap4 = {
1499 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1500 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1501 .modulemode = MODULEMODE_SWCTRL,
1502 },
1503 },
1504};
1505
1506/* timer5 */
1507static struct omap_hwmod dra7xx_timer5_hwmod = {
1508 .name = "timer5",
1509 .class = &dra7xx_timer_hwmod_class,
1510 .clkdm_name = "ipu_clkdm",
1511 .main_clk = "timer5_gfclk_mux",
1512 .prcm = {
1513 .omap4 = {
1514 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1515 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1516 .modulemode = MODULEMODE_SWCTRL,
1517 },
1518 },
1519};
1520
1521/* timer6 */
1522static struct omap_hwmod dra7xx_timer6_hwmod = {
1523 .name = "timer6",
1524 .class = &dra7xx_timer_hwmod_class,
1525 .clkdm_name = "ipu_clkdm",
1526 .main_clk = "timer6_gfclk_mux",
1527 .prcm = {
1528 .omap4 = {
1529 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1530 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1531 .modulemode = MODULEMODE_SWCTRL,
1532 },
1533 },
1534};
1535
1536/* timer7 */
1537static struct omap_hwmod dra7xx_timer7_hwmod = {
1538 .name = "timer7",
1539 .class = &dra7xx_timer_hwmod_class,
1540 .clkdm_name = "ipu_clkdm",
1541 .main_clk = "timer7_gfclk_mux",
1542 .prcm = {
1543 .omap4 = {
1544 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1545 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1546 .modulemode = MODULEMODE_SWCTRL,
1547 },
1548 },
1549};
1550
1551/* timer8 */
1552static struct omap_hwmod dra7xx_timer8_hwmod = {
1553 .name = "timer8",
1554 .class = &dra7xx_timer_hwmod_class,
1555 .clkdm_name = "ipu_clkdm",
1556 .main_clk = "timer8_gfclk_mux",
1557 .prcm = {
1558 .omap4 = {
1559 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1560 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1561 .modulemode = MODULEMODE_SWCTRL,
1562 },
1563 },
1564};
1565
1566/* timer9 */
1567static struct omap_hwmod dra7xx_timer9_hwmod = {
1568 .name = "timer9",
1569 .class = &dra7xx_timer_hwmod_class,
1570 .clkdm_name = "l4per_clkdm",
1571 .main_clk = "timer9_gfclk_mux",
1572 .prcm = {
1573 .omap4 = {
1574 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1575 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1576 .modulemode = MODULEMODE_SWCTRL,
1577 },
1578 },
1579};
1580
1581/* timer10 */
1582static struct omap_hwmod dra7xx_timer10_hwmod = {
1583 .name = "timer10",
1584 .class = &dra7xx_timer_1ms_hwmod_class,
1585 .clkdm_name = "l4per_clkdm",
1586 .main_clk = "timer10_gfclk_mux",
1587 .prcm = {
1588 .omap4 = {
1589 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1590 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1591 .modulemode = MODULEMODE_SWCTRL,
1592 },
1593 },
1594};
1595
1596/* timer11 */
1597static struct omap_hwmod dra7xx_timer11_hwmod = {
1598 .name = "timer11",
1599 .class = &dra7xx_timer_hwmod_class,
1600 .clkdm_name = "l4per_clkdm",
1601 .main_clk = "timer11_gfclk_mux",
1602 .prcm = {
1603 .omap4 = {
1604 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1605 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1606 .modulemode = MODULEMODE_SWCTRL,
1607 },
1608 },
1609};
1610
1611/*
1612 * 'uart' class
1613 *
1614 */
1615
1616static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1617 .rev_offs = 0x0050,
1618 .sysc_offs = 0x0054,
1619 .syss_offs = 0x0058,
1620 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1621 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1622 SYSS_HAS_RESET_STATUS),
1623 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1624 SIDLE_SMART_WKUP),
1625 .sysc_fields = &omap_hwmod_sysc_type1,
1626};
1627
1628static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
1629 .name = "uart",
1630 .sysc = &dra7xx_uart_sysc,
1631};
1632
1633/* uart1 */
1634static struct omap_hwmod dra7xx_uart1_hwmod = {
1635 .name = "uart1",
1636 .class = &dra7xx_uart_hwmod_class,
1637 .clkdm_name = "l4per_clkdm",
1638 .main_clk = "uart1_gfclk_mux",
1639 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
1640 .prcm = {
1641 .omap4 = {
1642 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1643 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1644 .modulemode = MODULEMODE_SWCTRL,
1645 },
1646 },
1647};
1648
1649/* uart2 */
1650static struct omap_hwmod dra7xx_uart2_hwmod = {
1651 .name = "uart2",
1652 .class = &dra7xx_uart_hwmod_class,
1653 .clkdm_name = "l4per_clkdm",
1654 .main_clk = "uart2_gfclk_mux",
1655 .flags = HWMOD_SWSUP_SIDLE_ACT,
1656 .prcm = {
1657 .omap4 = {
1658 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1659 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1660 .modulemode = MODULEMODE_SWCTRL,
1661 },
1662 },
1663};
1664
1665/* uart3 */
1666static struct omap_hwmod dra7xx_uart3_hwmod = {
1667 .name = "uart3",
1668 .class = &dra7xx_uart_hwmod_class,
1669 .clkdm_name = "l4per_clkdm",
1670 .main_clk = "uart3_gfclk_mux",
1671 .flags = HWMOD_SWSUP_SIDLE_ACT,
1672 .prcm = {
1673 .omap4 = {
1674 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1675 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1676 .modulemode = MODULEMODE_SWCTRL,
1677 },
1678 },
1679};
1680
1681/* uart4 */
1682static struct omap_hwmod dra7xx_uart4_hwmod = {
1683 .name = "uart4",
1684 .class = &dra7xx_uart_hwmod_class,
1685 .clkdm_name = "l4per_clkdm",
1686 .main_clk = "uart4_gfclk_mux",
1687 .flags = HWMOD_SWSUP_SIDLE_ACT,
1688 .prcm = {
1689 .omap4 = {
1690 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1691 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1692 .modulemode = MODULEMODE_SWCTRL,
1693 },
1694 },
1695};
1696
1697/* uart5 */
1698static struct omap_hwmod dra7xx_uart5_hwmod = {
1699 .name = "uart5",
1700 .class = &dra7xx_uart_hwmod_class,
1701 .clkdm_name = "l4per_clkdm",
1702 .main_clk = "uart5_gfclk_mux",
1703 .flags = HWMOD_SWSUP_SIDLE_ACT,
1704 .prcm = {
1705 .omap4 = {
1706 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1707 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1708 .modulemode = MODULEMODE_SWCTRL,
1709 },
1710 },
1711};
1712
1713/* uart6 */
1714static struct omap_hwmod dra7xx_uart6_hwmod = {
1715 .name = "uart6",
1716 .class = &dra7xx_uart_hwmod_class,
1717 .clkdm_name = "ipu_clkdm",
1718 .main_clk = "uart6_gfclk_mux",
1719 .flags = HWMOD_SWSUP_SIDLE_ACT,
1720 .prcm = {
1721 .omap4 = {
1722 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
1723 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
1724 .modulemode = MODULEMODE_SWCTRL,
1725 },
1726 },
1727};
1728
1729/*
1730 * 'usb_otg_ss' class
1731 *
1732 */
1733
1734static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
1735 .name = "usb_otg_ss",
1736};
1737
1738/* usb_otg_ss1 */
1739static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
1740 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
1741};
1742
1743static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
1744 .name = "usb_otg_ss1",
1745 .class = &dra7xx_usb_otg_ss_hwmod_class,
1746 .clkdm_name = "l3init_clkdm",
1747 .main_clk = "dpll_core_h13x2_ck",
1748 .prcm = {
1749 .omap4 = {
1750 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
1751 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
1752 .modulemode = MODULEMODE_HWCTRL,
1753 },
1754 },
1755 .opt_clks = usb_otg_ss1_opt_clks,
1756 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
1757};
1758
1759/* usb_otg_ss2 */
1760static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
1761 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
1762};
1763
1764static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
1765 .name = "usb_otg_ss2",
1766 .class = &dra7xx_usb_otg_ss_hwmod_class,
1767 .clkdm_name = "l3init_clkdm",
1768 .main_clk = "dpll_core_h13x2_ck",
1769 .prcm = {
1770 .omap4 = {
1771 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
1772 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
1773 .modulemode = MODULEMODE_HWCTRL,
1774 },
1775 },
1776 .opt_clks = usb_otg_ss2_opt_clks,
1777 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
1778};
1779
1780/* usb_otg_ss3 */
1781static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
1782 .name = "usb_otg_ss3",
1783 .class = &dra7xx_usb_otg_ss_hwmod_class,
1784 .clkdm_name = "l3init_clkdm",
1785 .main_clk = "dpll_core_h13x2_ck",
1786 .prcm = {
1787 .omap4 = {
1788 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
1789 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
1790 .modulemode = MODULEMODE_HWCTRL,
1791 },
1792 },
1793};
1794
1795/* usb_otg_ss4 */
1796static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
1797 .name = "usb_otg_ss4",
1798 .class = &dra7xx_usb_otg_ss_hwmod_class,
1799 .clkdm_name = "l3init_clkdm",
1800 .main_clk = "dpll_core_h13x2_ck",
1801 .prcm = {
1802 .omap4 = {
1803 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
1804 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
1805 .modulemode = MODULEMODE_HWCTRL,
1806 },
1807 },
1808};
1809
1810/*
1811 * 'vcp' class
1812 *
1813 */
1814
1815static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
1816 .name = "vcp",
1817};
1818
1819/* vcp1 */
1820static struct omap_hwmod dra7xx_vcp1_hwmod = {
1821 .name = "vcp1",
1822 .class = &dra7xx_vcp_hwmod_class,
1823 .clkdm_name = "l3main1_clkdm",
1824 .main_clk = "l3_iclk_div",
1825 .prcm = {
1826 .omap4 = {
1827 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
1828 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
1829 },
1830 },
1831};
1832
1833/* vcp2 */
1834static struct omap_hwmod dra7xx_vcp2_hwmod = {
1835 .name = "vcp2",
1836 .class = &dra7xx_vcp_hwmod_class,
1837 .clkdm_name = "l3main1_clkdm",
1838 .main_clk = "l3_iclk_div",
1839 .prcm = {
1840 .omap4 = {
1841 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
1842 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
1843 },
1844 },
1845};
1846
1847/*
1848 * 'wd_timer' class
1849 *
1850 */
1851
1852static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
1853 .rev_offs = 0x0000,
1854 .sysc_offs = 0x0010,
1855 .syss_offs = 0x0014,
1856 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1857 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1858 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1859 SIDLE_SMART_WKUP),
1860 .sysc_fields = &omap_hwmod_sysc_type1,
1861};
1862
1863static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
1864 .name = "wd_timer",
1865 .sysc = &dra7xx_wd_timer_sysc,
1866 .pre_shutdown = &omap2_wd_timer_disable,
1867 .reset = &omap2_wd_timer_reset,
1868};
1869
1870/* wd_timer2 */
1871static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
1872 .name = "wd_timer2",
1873 .class = &dra7xx_wd_timer_hwmod_class,
1874 .clkdm_name = "wkupaon_clkdm",
1875 .main_clk = "sys_32k_ck",
1876 .prcm = {
1877 .omap4 = {
1878 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1879 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1880 .modulemode = MODULEMODE_SWCTRL,
1881 },
1882 },
1883};
1884
1885
1886/*
1887 * Interfaces
1888 */
1889
1890/* l3_main_2 -> l3_instr */
1891static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
1892 .master = &dra7xx_l3_main_2_hwmod,
1893 .slave = &dra7xx_l3_instr_hwmod,
1894 .clk = "l3_iclk_div",
1895 .user = OCP_USER_MPU | OCP_USER_SDMA,
1896};
1897
1898/* l4_cfg -> l3_main_1 */
1899static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
1900 .master = &dra7xx_l4_cfg_hwmod,
1901 .slave = &dra7xx_l3_main_1_hwmod,
1902 .clk = "l3_iclk_div",
1903 .user = OCP_USER_MPU | OCP_USER_SDMA,
1904};
1905
1906/* mpu -> l3_main_1 */
1907static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
1908 .master = &dra7xx_mpu_hwmod,
1909 .slave = &dra7xx_l3_main_1_hwmod,
1910 .clk = "l3_iclk_div",
1911 .user = OCP_USER_MPU,
1912};
1913
1914/* l3_main_1 -> l3_main_2 */
1915static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
1916 .master = &dra7xx_l3_main_1_hwmod,
1917 .slave = &dra7xx_l3_main_2_hwmod,
1918 .clk = "l3_iclk_div",
1919 .user = OCP_USER_MPU,
1920};
1921
1922/* l4_cfg -> l3_main_2 */
1923static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
1924 .master = &dra7xx_l4_cfg_hwmod,
1925 .slave = &dra7xx_l3_main_2_hwmod,
1926 .clk = "l3_iclk_div",
1927 .user = OCP_USER_MPU | OCP_USER_SDMA,
1928};
1929
1930/* l3_main_1 -> l4_cfg */
1931static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
1932 .master = &dra7xx_l3_main_1_hwmod,
1933 .slave = &dra7xx_l4_cfg_hwmod,
1934 .clk = "l3_iclk_div",
1935 .user = OCP_USER_MPU | OCP_USER_SDMA,
1936};
1937
1938/* l3_main_1 -> l4_per1 */
1939static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
1940 .master = &dra7xx_l3_main_1_hwmod,
1941 .slave = &dra7xx_l4_per1_hwmod,
1942 .clk = "l3_iclk_div",
1943 .user = OCP_USER_MPU | OCP_USER_SDMA,
1944};
1945
1946/* l3_main_1 -> l4_per2 */
1947static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
1948 .master = &dra7xx_l3_main_1_hwmod,
1949 .slave = &dra7xx_l4_per2_hwmod,
1950 .clk = "l3_iclk_div",
1951 .user = OCP_USER_MPU | OCP_USER_SDMA,
1952};
1953
1954/* l3_main_1 -> l4_per3 */
1955static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
1956 .master = &dra7xx_l3_main_1_hwmod,
1957 .slave = &dra7xx_l4_per3_hwmod,
1958 .clk = "l3_iclk_div",
1959 .user = OCP_USER_MPU | OCP_USER_SDMA,
1960};
1961
1962/* l3_main_1 -> l4_wkup */
1963static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
1964 .master = &dra7xx_l3_main_1_hwmod,
1965 .slave = &dra7xx_l4_wkup_hwmod,
1966 .clk = "wkupaon_iclk_mux",
1967 .user = OCP_USER_MPU | OCP_USER_SDMA,
1968};
1969
1970/* l4_per2 -> atl */
1971static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
1972 .master = &dra7xx_l4_per2_hwmod,
1973 .slave = &dra7xx_atl_hwmod,
1974 .clk = "l3_iclk_div",
1975 .user = OCP_USER_MPU | OCP_USER_SDMA,
1976};
1977
1978/* l3_main_1 -> bb2d */
1979static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
1980 .master = &dra7xx_l3_main_1_hwmod,
1981 .slave = &dra7xx_bb2d_hwmod,
1982 .clk = "l3_iclk_div",
1983 .user = OCP_USER_MPU | OCP_USER_SDMA,
1984};
1985
1986/* l4_wkup -> counter_32k */
1987static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
1988 .master = &dra7xx_l4_wkup_hwmod,
1989 .slave = &dra7xx_counter_32k_hwmod,
1990 .clk = "wkupaon_iclk_mux",
1991 .user = OCP_USER_MPU | OCP_USER_SDMA,
1992};
1993
1994/* l4_wkup -> ctrl_module_wkup */
1995static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
1996 .master = &dra7xx_l4_wkup_hwmod,
1997 .slave = &dra7xx_ctrl_module_wkup_hwmod,
1998 .clk = "wkupaon_iclk_mux",
1999 .user = OCP_USER_MPU | OCP_USER_SDMA,
2000};
2001
2002/* l4_wkup -> dcan1 */
2003static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2004 .master = &dra7xx_l4_wkup_hwmod,
2005 .slave = &dra7xx_dcan1_hwmod,
2006 .clk = "wkupaon_iclk_mux",
2007 .user = OCP_USER_MPU | OCP_USER_SDMA,
2008};
2009
2010/* l4_per2 -> dcan2 */
2011static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2012 .master = &dra7xx_l4_per2_hwmod,
2013 .slave = &dra7xx_dcan2_hwmod,
2014 .clk = "l3_iclk_div",
2015 .user = OCP_USER_MPU | OCP_USER_SDMA,
2016};
2017
2018static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2019 {
2020 .pa_start = 0x4a056000,
2021 .pa_end = 0x4a056fff,
2022 .flags = ADDR_TYPE_RT
2023 },
2024 { }
2025};
2026
2027/* l4_cfg -> dma_system */
2028static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2029 .master = &dra7xx_l4_cfg_hwmod,
2030 .slave = &dra7xx_dma_system_hwmod,
2031 .clk = "l3_iclk_div",
2032 .addr = dra7xx_dma_system_addrs,
2033 .user = OCP_USER_MPU | OCP_USER_SDMA,
2034};
2035
2036static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2037 {
2038 .name = "family",
2039 .pa_start = 0x58000000,
2040 .pa_end = 0x5800007f,
2041 .flags = ADDR_TYPE_RT
2042 },
2043};
2044
2045/* l3_main_1 -> dss */
2046static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2047 .master = &dra7xx_l3_main_1_hwmod,
2048 .slave = &dra7xx_dss_hwmod,
2049 .clk = "l3_iclk_div",
2050 .addr = dra7xx_dss_addrs,
2051 .user = OCP_USER_MPU | OCP_USER_SDMA,
2052};
2053
2054static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2055 {
2056 .name = "dispc",
2057 .pa_start = 0x58001000,
2058 .pa_end = 0x58001fff,
2059 .flags = ADDR_TYPE_RT
2060 },
2061};
2062
2063/* l3_main_1 -> dispc */
2064static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2065 .master = &dra7xx_l3_main_1_hwmod,
2066 .slave = &dra7xx_dss_dispc_hwmod,
2067 .clk = "l3_iclk_div",
2068 .addr = dra7xx_dss_dispc_addrs,
2069 .user = OCP_USER_MPU | OCP_USER_SDMA,
2070};
2071
2072static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2073 {
2074 .name = "hdmi_wp",
2075 .pa_start = 0x58040000,
2076 .pa_end = 0x580400ff,
2077 .flags = ADDR_TYPE_RT
2078 },
2079 { }
2080};
2081
2082/* l3_main_1 -> dispc */
2083static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2084 .master = &dra7xx_l3_main_1_hwmod,
2085 .slave = &dra7xx_dss_hdmi_hwmod,
2086 .clk = "l3_iclk_div",
2087 .addr = dra7xx_dss_hdmi_addrs,
2088 .user = OCP_USER_MPU | OCP_USER_SDMA,
2089};
2090
2091static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2092 {
2093 .pa_start = 0x48078000,
2094 .pa_end = 0x48078fff,
2095 .flags = ADDR_TYPE_RT
2096 },
2097 { }
2098};
2099
2100/* l4_per1 -> elm */
2101static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2102 .master = &dra7xx_l4_per1_hwmod,
2103 .slave = &dra7xx_elm_hwmod,
2104 .clk = "l3_iclk_div",
2105 .addr = dra7xx_elm_addrs,
2106 .user = OCP_USER_MPU | OCP_USER_SDMA,
2107};
2108
2109/* l4_wkup -> gpio1 */
2110static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2111 .master = &dra7xx_l4_wkup_hwmod,
2112 .slave = &dra7xx_gpio1_hwmod,
2113 .clk = "wkupaon_iclk_mux",
2114 .user = OCP_USER_MPU | OCP_USER_SDMA,
2115};
2116
2117/* l4_per1 -> gpio2 */
2118static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2119 .master = &dra7xx_l4_per1_hwmod,
2120 .slave = &dra7xx_gpio2_hwmod,
2121 .clk = "l3_iclk_div",
2122 .user = OCP_USER_MPU | OCP_USER_SDMA,
2123};
2124
2125/* l4_per1 -> gpio3 */
2126static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2127 .master = &dra7xx_l4_per1_hwmod,
2128 .slave = &dra7xx_gpio3_hwmod,
2129 .clk = "l3_iclk_div",
2130 .user = OCP_USER_MPU | OCP_USER_SDMA,
2131};
2132
2133/* l4_per1 -> gpio4 */
2134static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2135 .master = &dra7xx_l4_per1_hwmod,
2136 .slave = &dra7xx_gpio4_hwmod,
2137 .clk = "l3_iclk_div",
2138 .user = OCP_USER_MPU | OCP_USER_SDMA,
2139};
2140
2141/* l4_per1 -> gpio5 */
2142static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2143 .master = &dra7xx_l4_per1_hwmod,
2144 .slave = &dra7xx_gpio5_hwmod,
2145 .clk = "l3_iclk_div",
2146 .user = OCP_USER_MPU | OCP_USER_SDMA,
2147};
2148
2149/* l4_per1 -> gpio6 */
2150static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2151 .master = &dra7xx_l4_per1_hwmod,
2152 .slave = &dra7xx_gpio6_hwmod,
2153 .clk = "l3_iclk_div",
2154 .user = OCP_USER_MPU | OCP_USER_SDMA,
2155};
2156
2157/* l4_per1 -> gpio7 */
2158static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2159 .master = &dra7xx_l4_per1_hwmod,
2160 .slave = &dra7xx_gpio7_hwmod,
2161 .clk = "l3_iclk_div",
2162 .user = OCP_USER_MPU | OCP_USER_SDMA,
2163};
2164
2165/* l4_per1 -> gpio8 */
2166static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2167 .master = &dra7xx_l4_per1_hwmod,
2168 .slave = &dra7xx_gpio8_hwmod,
2169 .clk = "l3_iclk_div",
2170 .user = OCP_USER_MPU | OCP_USER_SDMA,
2171};
2172
2173static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2174 {
2175 .pa_start = 0x50000000,
2176 .pa_end = 0x500003ff,
2177 .flags = ADDR_TYPE_RT
2178 },
2179 { }
2180};
2181
2182/* l3_main_1 -> gpmc */
2183static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2184 .master = &dra7xx_l3_main_1_hwmod,
2185 .slave = &dra7xx_gpmc_hwmod,
2186 .clk = "l3_iclk_div",
2187 .addr = dra7xx_gpmc_addrs,
2188 .user = OCP_USER_MPU | OCP_USER_SDMA,
2189};
2190
2191static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2192 {
2193 .pa_start = 0x480b2000,
2194 .pa_end = 0x480b201f,
2195 .flags = ADDR_TYPE_RT
2196 },
2197 { }
2198};
2199
2200/* l4_per1 -> hdq1w */
2201static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2202 .master = &dra7xx_l4_per1_hwmod,
2203 .slave = &dra7xx_hdq1w_hwmod,
2204 .clk = "l3_iclk_div",
2205 .addr = dra7xx_hdq1w_addrs,
2206 .user = OCP_USER_MPU | OCP_USER_SDMA,
2207};
2208
2209/* l4_per1 -> i2c1 */
2210static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2211 .master = &dra7xx_l4_per1_hwmod,
2212 .slave = &dra7xx_i2c1_hwmod,
2213 .clk = "l3_iclk_div",
2214 .user = OCP_USER_MPU | OCP_USER_SDMA,
2215};
2216
2217/* l4_per1 -> i2c2 */
2218static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2219 .master = &dra7xx_l4_per1_hwmod,
2220 .slave = &dra7xx_i2c2_hwmod,
2221 .clk = "l3_iclk_div",
2222 .user = OCP_USER_MPU | OCP_USER_SDMA,
2223};
2224
2225/* l4_per1 -> i2c3 */
2226static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2227 .master = &dra7xx_l4_per1_hwmod,
2228 .slave = &dra7xx_i2c3_hwmod,
2229 .clk = "l3_iclk_div",
2230 .user = OCP_USER_MPU | OCP_USER_SDMA,
2231};
2232
2233/* l4_per1 -> i2c4 */
2234static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2235 .master = &dra7xx_l4_per1_hwmod,
2236 .slave = &dra7xx_i2c4_hwmod,
2237 .clk = "l3_iclk_div",
2238 .user = OCP_USER_MPU | OCP_USER_SDMA,
2239};
2240
2241/* l4_per1 -> i2c5 */
2242static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2243 .master = &dra7xx_l4_per1_hwmod,
2244 .slave = &dra7xx_i2c5_hwmod,
2245 .clk = "l3_iclk_div",
2246 .user = OCP_USER_MPU | OCP_USER_SDMA,
2247};
2248
2249/* l4_per1 -> mcspi1 */
2250static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2251 .master = &dra7xx_l4_per1_hwmod,
2252 .slave = &dra7xx_mcspi1_hwmod,
2253 .clk = "l3_iclk_div",
2254 .user = OCP_USER_MPU | OCP_USER_SDMA,
2255};
2256
2257/* l4_per1 -> mcspi2 */
2258static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2259 .master = &dra7xx_l4_per1_hwmod,
2260 .slave = &dra7xx_mcspi2_hwmod,
2261 .clk = "l3_iclk_div",
2262 .user = OCP_USER_MPU | OCP_USER_SDMA,
2263};
2264
2265/* l4_per1 -> mcspi3 */
2266static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2267 .master = &dra7xx_l4_per1_hwmod,
2268 .slave = &dra7xx_mcspi3_hwmod,
2269 .clk = "l3_iclk_div",
2270 .user = OCP_USER_MPU | OCP_USER_SDMA,
2271};
2272
2273/* l4_per1 -> mcspi4 */
2274static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2275 .master = &dra7xx_l4_per1_hwmod,
2276 .slave = &dra7xx_mcspi4_hwmod,
2277 .clk = "l3_iclk_div",
2278 .user = OCP_USER_MPU | OCP_USER_SDMA,
2279};
2280
2281/* l4_per1 -> mmc1 */
2282static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2283 .master = &dra7xx_l4_per1_hwmod,
2284 .slave = &dra7xx_mmc1_hwmod,
2285 .clk = "l3_iclk_div",
2286 .user = OCP_USER_MPU | OCP_USER_SDMA,
2287};
2288
2289/* l4_per1 -> mmc2 */
2290static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2291 .master = &dra7xx_l4_per1_hwmod,
2292 .slave = &dra7xx_mmc2_hwmod,
2293 .clk = "l3_iclk_div",
2294 .user = OCP_USER_MPU | OCP_USER_SDMA,
2295};
2296
2297/* l4_per1 -> mmc3 */
2298static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2299 .master = &dra7xx_l4_per1_hwmod,
2300 .slave = &dra7xx_mmc3_hwmod,
2301 .clk = "l3_iclk_div",
2302 .user = OCP_USER_MPU | OCP_USER_SDMA,
2303};
2304
2305/* l4_per1 -> mmc4 */
2306static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2307 .master = &dra7xx_l4_per1_hwmod,
2308 .slave = &dra7xx_mmc4_hwmod,
2309 .clk = "l3_iclk_div",
2310 .user = OCP_USER_MPU | OCP_USER_SDMA,
2311};
2312
2313/* l4_cfg -> mpu */
2314static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2315 .master = &dra7xx_l4_cfg_hwmod,
2316 .slave = &dra7xx_mpu_hwmod,
2317 .clk = "l3_iclk_div",
2318 .user = OCP_USER_MPU | OCP_USER_SDMA,
2319};
2320
2321static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
2322 {
2323 .pa_start = 0x4a080000,
2324 .pa_end = 0x4a08001f,
2325 .flags = ADDR_TYPE_RT
2326 },
2327 { }
2328};
2329
2330/* l4_cfg -> ocp2scp1 */
2331static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2332 .master = &dra7xx_l4_cfg_hwmod,
2333 .slave = &dra7xx_ocp2scp1_hwmod,
2334 .clk = "l4_root_clk_div",
2335 .addr = dra7xx_ocp2scp1_addrs,
2336 .user = OCP_USER_MPU | OCP_USER_SDMA,
2337};
2338
2339static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2340 {
2341 .pa_start = 0x4b300000,
2342 .pa_end = 0x4b30007f,
2343 .flags = ADDR_TYPE_RT
2344 },
2345 { }
2346};
2347
2348/* l3_main_1 -> qspi */
2349static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2350 .master = &dra7xx_l3_main_1_hwmod,
2351 .slave = &dra7xx_qspi_hwmod,
2352 .clk = "l3_iclk_div",
2353 .addr = dra7xx_qspi_addrs,
2354 .user = OCP_USER_MPU | OCP_USER_SDMA,
2355};
2356
2357static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2358 {
2359 .name = "sysc",
2360 .pa_start = 0x4a141100,
2361 .pa_end = 0x4a141107,
2362 .flags = ADDR_TYPE_RT
2363 },
2364 { }
2365};
2366
2367/* l4_cfg -> sata */
2368static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2369 .master = &dra7xx_l4_cfg_hwmod,
2370 .slave = &dra7xx_sata_hwmod,
2371 .clk = "l3_iclk_div",
2372 .addr = dra7xx_sata_addrs,
2373 .user = OCP_USER_MPU | OCP_USER_SDMA,
2374};
2375
2376static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2377 {
2378 .pa_start = 0x4a0dd000,
2379 .pa_end = 0x4a0dd07f,
2380 .flags = ADDR_TYPE_RT
2381 },
2382 { }
2383};
2384
2385/* l4_cfg -> smartreflex_core */
2386static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2387 .master = &dra7xx_l4_cfg_hwmod,
2388 .slave = &dra7xx_smartreflex_core_hwmod,
2389 .clk = "l4_root_clk_div",
2390 .addr = dra7xx_smartreflex_core_addrs,
2391 .user = OCP_USER_MPU | OCP_USER_SDMA,
2392};
2393
2394static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
2395 {
2396 .pa_start = 0x4a0d9000,
2397 .pa_end = 0x4a0d907f,
2398 .flags = ADDR_TYPE_RT
2399 },
2400 { }
2401};
2402
2403/* l4_cfg -> smartreflex_mpu */
2404static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
2405 .master = &dra7xx_l4_cfg_hwmod,
2406 .slave = &dra7xx_smartreflex_mpu_hwmod,
2407 .clk = "l4_root_clk_div",
2408 .addr = dra7xx_smartreflex_mpu_addrs,
2409 .user = OCP_USER_MPU | OCP_USER_SDMA,
2410};
2411
2412static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
2413 {
2414 .pa_start = 0x4a0f6000,
2415 .pa_end = 0x4a0f6fff,
2416 .flags = ADDR_TYPE_RT
2417 },
2418 { }
2419};
2420
2421/* l4_cfg -> spinlock */
2422static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
2423 .master = &dra7xx_l4_cfg_hwmod,
2424 .slave = &dra7xx_spinlock_hwmod,
2425 .clk = "l3_iclk_div",
2426 .addr = dra7xx_spinlock_addrs,
2427 .user = OCP_USER_MPU | OCP_USER_SDMA,
2428};
2429
2430/* l4_wkup -> timer1 */
2431static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
2432 .master = &dra7xx_l4_wkup_hwmod,
2433 .slave = &dra7xx_timer1_hwmod,
2434 .clk = "wkupaon_iclk_mux",
2435 .user = OCP_USER_MPU | OCP_USER_SDMA,
2436};
2437
2438/* l4_per1 -> timer2 */
2439static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
2440 .master = &dra7xx_l4_per1_hwmod,
2441 .slave = &dra7xx_timer2_hwmod,
2442 .clk = "l3_iclk_div",
2443 .user = OCP_USER_MPU | OCP_USER_SDMA,
2444};
2445
2446/* l4_per1 -> timer3 */
2447static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
2448 .master = &dra7xx_l4_per1_hwmod,
2449 .slave = &dra7xx_timer3_hwmod,
2450 .clk = "l3_iclk_div",
2451 .user = OCP_USER_MPU | OCP_USER_SDMA,
2452};
2453
2454/* l4_per1 -> timer4 */
2455static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
2456 .master = &dra7xx_l4_per1_hwmod,
2457 .slave = &dra7xx_timer4_hwmod,
2458 .clk = "l3_iclk_div",
2459 .user = OCP_USER_MPU | OCP_USER_SDMA,
2460};
2461
2462/* l4_per3 -> timer5 */
2463static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
2464 .master = &dra7xx_l4_per3_hwmod,
2465 .slave = &dra7xx_timer5_hwmod,
2466 .clk = "l3_iclk_div",
2467 .user = OCP_USER_MPU | OCP_USER_SDMA,
2468};
2469
2470/* l4_per3 -> timer6 */
2471static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
2472 .master = &dra7xx_l4_per3_hwmod,
2473 .slave = &dra7xx_timer6_hwmod,
2474 .clk = "l3_iclk_div",
2475 .user = OCP_USER_MPU | OCP_USER_SDMA,
2476};
2477
2478/* l4_per3 -> timer7 */
2479static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
2480 .master = &dra7xx_l4_per3_hwmod,
2481 .slave = &dra7xx_timer7_hwmod,
2482 .clk = "l3_iclk_div",
2483 .user = OCP_USER_MPU | OCP_USER_SDMA,
2484};
2485
2486/* l4_per3 -> timer8 */
2487static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
2488 .master = &dra7xx_l4_per3_hwmod,
2489 .slave = &dra7xx_timer8_hwmod,
2490 .clk = "l3_iclk_div",
2491 .user = OCP_USER_MPU | OCP_USER_SDMA,
2492};
2493
2494/* l4_per1 -> timer9 */
2495static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
2496 .master = &dra7xx_l4_per1_hwmod,
2497 .slave = &dra7xx_timer9_hwmod,
2498 .clk = "l3_iclk_div",
2499 .user = OCP_USER_MPU | OCP_USER_SDMA,
2500};
2501
2502/* l4_per1 -> timer10 */
2503static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
2504 .master = &dra7xx_l4_per1_hwmod,
2505 .slave = &dra7xx_timer10_hwmod,
2506 .clk = "l3_iclk_div",
2507 .user = OCP_USER_MPU | OCP_USER_SDMA,
2508};
2509
2510/* l4_per1 -> timer11 */
2511static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
2512 .master = &dra7xx_l4_per1_hwmod,
2513 .slave = &dra7xx_timer11_hwmod,
2514 .clk = "l3_iclk_div",
2515 .user = OCP_USER_MPU | OCP_USER_SDMA,
2516};
2517
2518/* l4_per1 -> uart1 */
2519static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
2520 .master = &dra7xx_l4_per1_hwmod,
2521 .slave = &dra7xx_uart1_hwmod,
2522 .clk = "l3_iclk_div",
2523 .user = OCP_USER_MPU | OCP_USER_SDMA,
2524};
2525
2526/* l4_per1 -> uart2 */
2527static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
2528 .master = &dra7xx_l4_per1_hwmod,
2529 .slave = &dra7xx_uart2_hwmod,
2530 .clk = "l3_iclk_div",
2531 .user = OCP_USER_MPU | OCP_USER_SDMA,
2532};
2533
2534/* l4_per1 -> uart3 */
2535static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
2536 .master = &dra7xx_l4_per1_hwmod,
2537 .slave = &dra7xx_uart3_hwmod,
2538 .clk = "l3_iclk_div",
2539 .user = OCP_USER_MPU | OCP_USER_SDMA,
2540};
2541
2542/* l4_per1 -> uart4 */
2543static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
2544 .master = &dra7xx_l4_per1_hwmod,
2545 .slave = &dra7xx_uart4_hwmod,
2546 .clk = "l3_iclk_div",
2547 .user = OCP_USER_MPU | OCP_USER_SDMA,
2548};
2549
2550/* l4_per1 -> uart5 */
2551static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
2552 .master = &dra7xx_l4_per1_hwmod,
2553 .slave = &dra7xx_uart5_hwmod,
2554 .clk = "l3_iclk_div",
2555 .user = OCP_USER_MPU | OCP_USER_SDMA,
2556};
2557
2558/* l4_per1 -> uart6 */
2559static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
2560 .master = &dra7xx_l4_per1_hwmod,
2561 .slave = &dra7xx_uart6_hwmod,
2562 .clk = "l3_iclk_div",
2563 .user = OCP_USER_MPU | OCP_USER_SDMA,
2564};
2565
2566/* l4_per3 -> usb_otg_ss1 */
2567static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
2568 .master = &dra7xx_l4_per3_hwmod,
2569 .slave = &dra7xx_usb_otg_ss1_hwmod,
2570 .clk = "dpll_core_h13x2_ck",
2571 .user = OCP_USER_MPU | OCP_USER_SDMA,
2572};
2573
2574/* l4_per3 -> usb_otg_ss2 */
2575static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
2576 .master = &dra7xx_l4_per3_hwmod,
2577 .slave = &dra7xx_usb_otg_ss2_hwmod,
2578 .clk = "dpll_core_h13x2_ck",
2579 .user = OCP_USER_MPU | OCP_USER_SDMA,
2580};
2581
2582/* l4_per3 -> usb_otg_ss3 */
2583static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
2584 .master = &dra7xx_l4_per3_hwmod,
2585 .slave = &dra7xx_usb_otg_ss3_hwmod,
2586 .clk = "dpll_core_h13x2_ck",
2587 .user = OCP_USER_MPU | OCP_USER_SDMA,
2588};
2589
2590/* l4_per3 -> usb_otg_ss4 */
2591static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
2592 .master = &dra7xx_l4_per3_hwmod,
2593 .slave = &dra7xx_usb_otg_ss4_hwmod,
2594 .clk = "dpll_core_h13x2_ck",
2595 .user = OCP_USER_MPU | OCP_USER_SDMA,
2596};
2597
2598/* l3_main_1 -> vcp1 */
2599static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
2600 .master = &dra7xx_l3_main_1_hwmod,
2601 .slave = &dra7xx_vcp1_hwmod,
2602 .clk = "l3_iclk_div",
2603 .user = OCP_USER_MPU | OCP_USER_SDMA,
2604};
2605
2606/* l4_per2 -> vcp1 */
2607static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
2608 .master = &dra7xx_l4_per2_hwmod,
2609 .slave = &dra7xx_vcp1_hwmod,
2610 .clk = "l3_iclk_div",
2611 .user = OCP_USER_MPU | OCP_USER_SDMA,
2612};
2613
2614/* l3_main_1 -> vcp2 */
2615static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
2616 .master = &dra7xx_l3_main_1_hwmod,
2617 .slave = &dra7xx_vcp2_hwmod,
2618 .clk = "l3_iclk_div",
2619 .user = OCP_USER_MPU | OCP_USER_SDMA,
2620};
2621
2622/* l4_per2 -> vcp2 */
2623static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
2624 .master = &dra7xx_l4_per2_hwmod,
2625 .slave = &dra7xx_vcp2_hwmod,
2626 .clk = "l3_iclk_div",
2627 .user = OCP_USER_MPU | OCP_USER_SDMA,
2628};
2629
2630/* l4_wkup -> wd_timer2 */
2631static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
2632 .master = &dra7xx_l4_wkup_hwmod,
2633 .slave = &dra7xx_wd_timer2_hwmod,
2634 .clk = "wkupaon_iclk_mux",
2635 .user = OCP_USER_MPU | OCP_USER_SDMA,
2636};
2637
2638static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
2639 &dra7xx_l3_main_2__l3_instr,
2640 &dra7xx_l4_cfg__l3_main_1,
2641 &dra7xx_mpu__l3_main_1,
2642 &dra7xx_l3_main_1__l3_main_2,
2643 &dra7xx_l4_cfg__l3_main_2,
2644 &dra7xx_l3_main_1__l4_cfg,
2645 &dra7xx_l3_main_1__l4_per1,
2646 &dra7xx_l3_main_1__l4_per2,
2647 &dra7xx_l3_main_1__l4_per3,
2648 &dra7xx_l3_main_1__l4_wkup,
2649 &dra7xx_l4_per2__atl,
2650 &dra7xx_l3_main_1__bb2d,
2651 &dra7xx_l4_wkup__counter_32k,
2652 &dra7xx_l4_wkup__ctrl_module_wkup,
2653 &dra7xx_l4_wkup__dcan1,
2654 &dra7xx_l4_per2__dcan2,
2655 &dra7xx_l4_cfg__dma_system,
2656 &dra7xx_l3_main_1__dss,
2657 &dra7xx_l3_main_1__dispc,
2658 &dra7xx_l3_main_1__hdmi,
2659 &dra7xx_l4_per1__elm,
2660 &dra7xx_l4_wkup__gpio1,
2661 &dra7xx_l4_per1__gpio2,
2662 &dra7xx_l4_per1__gpio3,
2663 &dra7xx_l4_per1__gpio4,
2664 &dra7xx_l4_per1__gpio5,
2665 &dra7xx_l4_per1__gpio6,
2666 &dra7xx_l4_per1__gpio7,
2667 &dra7xx_l4_per1__gpio8,
2668 &dra7xx_l3_main_1__gpmc,
2669 &dra7xx_l4_per1__hdq1w,
2670 &dra7xx_l4_per1__i2c1,
2671 &dra7xx_l4_per1__i2c2,
2672 &dra7xx_l4_per1__i2c3,
2673 &dra7xx_l4_per1__i2c4,
2674 &dra7xx_l4_per1__i2c5,
2675 &dra7xx_l4_per1__mcspi1,
2676 &dra7xx_l4_per1__mcspi2,
2677 &dra7xx_l4_per1__mcspi3,
2678 &dra7xx_l4_per1__mcspi4,
2679 &dra7xx_l4_per1__mmc1,
2680 &dra7xx_l4_per1__mmc2,
2681 &dra7xx_l4_per1__mmc3,
2682 &dra7xx_l4_per1__mmc4,
2683 &dra7xx_l4_cfg__mpu,
2684 &dra7xx_l4_cfg__ocp2scp1,
2685 &dra7xx_l3_main_1__qspi,
2686 &dra7xx_l4_cfg__sata,
2687 &dra7xx_l4_cfg__smartreflex_core,
2688 &dra7xx_l4_cfg__smartreflex_mpu,
2689 &dra7xx_l4_cfg__spinlock,
2690 &dra7xx_l4_wkup__timer1,
2691 &dra7xx_l4_per1__timer2,
2692 &dra7xx_l4_per1__timer3,
2693 &dra7xx_l4_per1__timer4,
2694 &dra7xx_l4_per3__timer5,
2695 &dra7xx_l4_per3__timer6,
2696 &dra7xx_l4_per3__timer7,
2697 &dra7xx_l4_per3__timer8,
2698 &dra7xx_l4_per1__timer9,
2699 &dra7xx_l4_per1__timer10,
2700 &dra7xx_l4_per1__timer11,
2701 &dra7xx_l4_per1__uart1,
2702 &dra7xx_l4_per1__uart2,
2703 &dra7xx_l4_per1__uart3,
2704 &dra7xx_l4_per1__uart4,
2705 &dra7xx_l4_per1__uart5,
2706 &dra7xx_l4_per1__uart6,
2707 &dra7xx_l4_per3__usb_otg_ss1,
2708 &dra7xx_l4_per3__usb_otg_ss2,
2709 &dra7xx_l4_per3__usb_otg_ss3,
2710 &dra7xx_l4_per3__usb_otg_ss4,
2711 &dra7xx_l3_main_1__vcp1,
2712 &dra7xx_l4_per2__vcp1,
2713 &dra7xx_l3_main_1__vcp2,
2714 &dra7xx_l4_per2__vcp2,
2715 &dra7xx_l4_wkup__wd_timer2,
2716 NULL,
2717};
2718
2719int __init dra7xx_hwmod_init(void)
2720{
2721 omap_hwmod_init();
2722 return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
2723}
1/*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
22#include <linux/platform_data/hsmmc-omap.h>
23#include <linux/power/smartreflex.h>
24#include <linux/i2c-omap.h>
25
26#include <linux/omap-dma.h>
27#include <linux/platform_data/spi-omap2-mcspi.h>
28#include <linux/platform_data/asoc-ti-mcbsp.h>
29#include <plat/dmtimer.h>
30
31#include "omap_hwmod.h"
32#include "omap_hwmod_common_data.h"
33#include "cm1_7xx.h"
34#include "cm2_7xx.h"
35#include "prm7xx.h"
36#include "i2c.h"
37#include "wd_timer.h"
38#include "soc.h"
39
40/* Base offset for all DRA7XX interrupts external to MPUSS */
41#define DRA7XX_IRQ_GIC_START 32
42
43/* Base offset for all DRA7XX dma requests */
44#define DRA7XX_DMA_REQ_START 1
45
46
47/*
48 * IP blocks
49 */
50
51/*
52 * 'dmm' class
53 * instance(s): dmm
54 */
55static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
56 .name = "dmm",
57};
58
59/* dmm */
60static struct omap_hwmod dra7xx_dmm_hwmod = {
61 .name = "dmm",
62 .class = &dra7xx_dmm_hwmod_class,
63 .clkdm_name = "emif_clkdm",
64 .prcm = {
65 .omap4 = {
66 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
67 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
68 },
69 },
70};
71
72/*
73 * 'l3' class
74 * instance(s): l3_instr, l3_main_1, l3_main_2
75 */
76static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
77 .name = "l3",
78};
79
80/* l3_instr */
81static struct omap_hwmod dra7xx_l3_instr_hwmod = {
82 .name = "l3_instr",
83 .class = &dra7xx_l3_hwmod_class,
84 .clkdm_name = "l3instr_clkdm",
85 .prcm = {
86 .omap4 = {
87 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
88 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
89 .modulemode = MODULEMODE_HWCTRL,
90 },
91 },
92};
93
94/* l3_main_1 */
95static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
96 .name = "l3_main_1",
97 .class = &dra7xx_l3_hwmod_class,
98 .clkdm_name = "l3main1_clkdm",
99 .prcm = {
100 .omap4 = {
101 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
102 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
103 },
104 },
105};
106
107/* l3_main_2 */
108static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
109 .name = "l3_main_2",
110 .class = &dra7xx_l3_hwmod_class,
111 .clkdm_name = "l3instr_clkdm",
112 .prcm = {
113 .omap4 = {
114 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
116 .modulemode = MODULEMODE_HWCTRL,
117 },
118 },
119};
120
121/*
122 * 'l4' class
123 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
124 */
125static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
126 .name = "l4",
127};
128
129/* l4_cfg */
130static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
131 .name = "l4_cfg",
132 .class = &dra7xx_l4_hwmod_class,
133 .clkdm_name = "l4cfg_clkdm",
134 .prcm = {
135 .omap4 = {
136 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
137 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
138 },
139 },
140};
141
142/* l4_per1 */
143static struct omap_hwmod dra7xx_l4_per1_hwmod = {
144 .name = "l4_per1",
145 .class = &dra7xx_l4_hwmod_class,
146 .clkdm_name = "l4per_clkdm",
147 .prcm = {
148 .omap4 = {
149 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
150 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
151 },
152 },
153};
154
155/* l4_per2 */
156static struct omap_hwmod dra7xx_l4_per2_hwmod = {
157 .name = "l4_per2",
158 .class = &dra7xx_l4_hwmod_class,
159 .clkdm_name = "l4per2_clkdm",
160 .prcm = {
161 .omap4 = {
162 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
163 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
164 },
165 },
166};
167
168/* l4_per3 */
169static struct omap_hwmod dra7xx_l4_per3_hwmod = {
170 .name = "l4_per3",
171 .class = &dra7xx_l4_hwmod_class,
172 .clkdm_name = "l4per3_clkdm",
173 .prcm = {
174 .omap4 = {
175 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
176 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
177 },
178 },
179};
180
181/* l4_wkup */
182static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
183 .name = "l4_wkup",
184 .class = &dra7xx_l4_hwmod_class,
185 .clkdm_name = "wkupaon_clkdm",
186 .prcm = {
187 .omap4 = {
188 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
189 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
190 },
191 },
192};
193
194/*
195 * 'atl' class
196 *
197 */
198
199static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
200 .name = "atl",
201};
202
203/* atl */
204static struct omap_hwmod dra7xx_atl_hwmod = {
205 .name = "atl",
206 .class = &dra7xx_atl_hwmod_class,
207 .clkdm_name = "atl_clkdm",
208 .main_clk = "atl_gfclk_mux",
209 .prcm = {
210 .omap4 = {
211 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
212 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
213 .modulemode = MODULEMODE_SWCTRL,
214 },
215 },
216};
217
218/*
219 * 'bb2d' class
220 *
221 */
222
223static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
224 .name = "bb2d",
225};
226
227/* bb2d */
228static struct omap_hwmod dra7xx_bb2d_hwmod = {
229 .name = "bb2d",
230 .class = &dra7xx_bb2d_hwmod_class,
231 .clkdm_name = "dss_clkdm",
232 .main_clk = "dpll_core_h24x2_ck",
233 .prcm = {
234 .omap4 = {
235 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
236 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_SWCTRL,
238 },
239 },
240};
241
242/*
243 * 'counter' class
244 *
245 */
246
247static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
248 .rev_offs = 0x0000,
249 .sysc_offs = 0x0010,
250 .sysc_flags = SYSC_HAS_SIDLEMODE,
251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
252 SIDLE_SMART_WKUP),
253 .sysc_fields = &omap_hwmod_sysc_type1,
254};
255
256static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
257 .name = "counter",
258 .sysc = &dra7xx_counter_sysc,
259};
260
261/* counter_32k */
262static struct omap_hwmod dra7xx_counter_32k_hwmod = {
263 .name = "counter_32k",
264 .class = &dra7xx_counter_hwmod_class,
265 .clkdm_name = "wkupaon_clkdm",
266 .flags = HWMOD_SWSUP_SIDLE,
267 .main_clk = "wkupaon_iclk_mux",
268 .prcm = {
269 .omap4 = {
270 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
271 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
272 },
273 },
274};
275
276/*
277 * 'ctrl_module' class
278 *
279 */
280
281static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
282 .name = "ctrl_module",
283};
284
285/* ctrl_module_wkup */
286static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
287 .name = "ctrl_module_wkup",
288 .class = &dra7xx_ctrl_module_hwmod_class,
289 .clkdm_name = "wkupaon_clkdm",
290 .prcm = {
291 .omap4 = {
292 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
293 },
294 },
295};
296
297/*
298 * 'gmac' class
299 * cpsw/gmac sub system
300 */
301static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
302 .rev_offs = 0x0,
303 .sysc_offs = 0x8,
304 .syss_offs = 0x4,
305 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
306 SYSS_HAS_RESET_STATUS),
307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
308 MSTANDBY_NO),
309 .sysc_fields = &omap_hwmod_sysc_type3,
310};
311
312static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
313 .name = "gmac",
314 .sysc = &dra7xx_gmac_sysc,
315};
316
317static struct omap_hwmod dra7xx_gmac_hwmod = {
318 .name = "gmac",
319 .class = &dra7xx_gmac_hwmod_class,
320 .clkdm_name = "gmac_clkdm",
321 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
322 .main_clk = "dpll_gmac_ck",
323 .mpu_rt_idx = 1,
324 .prcm = {
325 .omap4 = {
326 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
327 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
328 .modulemode = MODULEMODE_SWCTRL,
329 },
330 },
331};
332
333/*
334 * 'mdio' class
335 */
336static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
337 .name = "davinci_mdio",
338};
339
340static struct omap_hwmod dra7xx_mdio_hwmod = {
341 .name = "davinci_mdio",
342 .class = &dra7xx_mdio_hwmod_class,
343 .clkdm_name = "gmac_clkdm",
344 .main_clk = "dpll_gmac_ck",
345};
346
347/*
348 * 'dcan' class
349 *
350 */
351
352static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
353 .name = "dcan",
354};
355
356/* dcan1 */
357static struct omap_hwmod dra7xx_dcan1_hwmod = {
358 .name = "dcan1",
359 .class = &dra7xx_dcan_hwmod_class,
360 .clkdm_name = "wkupaon_clkdm",
361 .main_clk = "dcan1_sys_clk_mux",
362 .prcm = {
363 .omap4 = {
364 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
365 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
366 .modulemode = MODULEMODE_SWCTRL,
367 },
368 },
369};
370
371/* dcan2 */
372static struct omap_hwmod dra7xx_dcan2_hwmod = {
373 .name = "dcan2",
374 .class = &dra7xx_dcan_hwmod_class,
375 .clkdm_name = "l4per2_clkdm",
376 .main_clk = "sys_clkin1",
377 .prcm = {
378 .omap4 = {
379 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
380 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
381 .modulemode = MODULEMODE_SWCTRL,
382 },
383 },
384};
385
386/*
387 * 'dma' class
388 *
389 */
390
391static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
392 .rev_offs = 0x0000,
393 .sysc_offs = 0x002c,
394 .syss_offs = 0x0028,
395 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
396 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
397 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
398 SYSS_HAS_RESET_STATUS),
399 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
400 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
401 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
402 .sysc_fields = &omap_hwmod_sysc_type1,
403};
404
405static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
406 .name = "dma",
407 .sysc = &dra7xx_dma_sysc,
408};
409
410/* dma dev_attr */
411static struct omap_dma_dev_attr dma_dev_attr = {
412 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
413 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
414 .lch_count = 32,
415};
416
417/* dma_system */
418static struct omap_hwmod dra7xx_dma_system_hwmod = {
419 .name = "dma_system",
420 .class = &dra7xx_dma_hwmod_class,
421 .clkdm_name = "dma_clkdm",
422 .main_clk = "l3_iclk_div",
423 .prcm = {
424 .omap4 = {
425 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
426 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
427 },
428 },
429 .dev_attr = &dma_dev_attr,
430};
431
432/*
433 * 'tpcc' class
434 *
435 */
436static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
437 .name = "tpcc",
438};
439
440static struct omap_hwmod dra7xx_tpcc_hwmod = {
441 .name = "tpcc",
442 .class = &dra7xx_tpcc_hwmod_class,
443 .clkdm_name = "l3main1_clkdm",
444 .main_clk = "l3_iclk_div",
445 .prcm = {
446 .omap4 = {
447 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
448 .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
449 },
450 },
451};
452
453/*
454 * 'tptc' class
455 *
456 */
457static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
458 .name = "tptc",
459};
460
461/* tptc0 */
462static struct omap_hwmod dra7xx_tptc0_hwmod = {
463 .name = "tptc0",
464 .class = &dra7xx_tptc_hwmod_class,
465 .clkdm_name = "l3main1_clkdm",
466 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
467 .main_clk = "l3_iclk_div",
468 .prcm = {
469 .omap4 = {
470 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
471 .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
472 .modulemode = MODULEMODE_HWCTRL,
473 },
474 },
475};
476
477/* tptc1 */
478static struct omap_hwmod dra7xx_tptc1_hwmod = {
479 .name = "tptc1",
480 .class = &dra7xx_tptc_hwmod_class,
481 .clkdm_name = "l3main1_clkdm",
482 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
483 .main_clk = "l3_iclk_div",
484 .prcm = {
485 .omap4 = {
486 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
487 .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
488 .modulemode = MODULEMODE_HWCTRL,
489 },
490 },
491};
492
493/*
494 * 'dss' class
495 *
496 */
497
498static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
499 .rev_offs = 0x0000,
500 .syss_offs = 0x0014,
501 .sysc_flags = SYSS_HAS_RESET_STATUS,
502};
503
504static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
505 .name = "dss",
506 .sysc = &dra7xx_dss_sysc,
507 .reset = omap_dss_reset,
508};
509
510/* dss */
511static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
512 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
513 { .dma_req = -1 }
514};
515
516static struct omap_hwmod_opt_clk dss_opt_clks[] = {
517 { .role = "dss_clk", .clk = "dss_dss_clk" },
518 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
519 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
520 { .role = "video2_clk", .clk = "dss_video2_clk" },
521 { .role = "video1_clk", .clk = "dss_video1_clk" },
522 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
523 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
524};
525
526static struct omap_hwmod dra7xx_dss_hwmod = {
527 .name = "dss_core",
528 .class = &dra7xx_dss_hwmod_class,
529 .clkdm_name = "dss_clkdm",
530 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
531 .sdma_reqs = dra7xx_dss_sdma_reqs,
532 .main_clk = "dss_dss_clk",
533 .prcm = {
534 .omap4 = {
535 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
536 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
537 .modulemode = MODULEMODE_SWCTRL,
538 },
539 },
540 .opt_clks = dss_opt_clks,
541 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
542};
543
544/*
545 * 'dispc' class
546 * display controller
547 */
548
549static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
550 .rev_offs = 0x0000,
551 .sysc_offs = 0x0010,
552 .syss_offs = 0x0014,
553 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
554 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
555 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
556 SYSS_HAS_RESET_STATUS),
557 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
558 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
559 .sysc_fields = &omap_hwmod_sysc_type1,
560};
561
562static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
563 .name = "dispc",
564 .sysc = &dra7xx_dispc_sysc,
565};
566
567/* dss_dispc */
568/* dss_dispc dev_attr */
569static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
570 .has_framedonetv_irq = 1,
571 .manager_count = 4,
572};
573
574static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
575 .name = "dss_dispc",
576 .class = &dra7xx_dispc_hwmod_class,
577 .clkdm_name = "dss_clkdm",
578 .main_clk = "dss_dss_clk",
579 .prcm = {
580 .omap4 = {
581 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
582 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
583 },
584 },
585 .dev_attr = &dss_dispc_dev_attr,
586 .parent_hwmod = &dra7xx_dss_hwmod,
587};
588
589/*
590 * 'hdmi' class
591 * hdmi controller
592 */
593
594static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
595 .rev_offs = 0x0000,
596 .sysc_offs = 0x0010,
597 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
598 SYSC_HAS_SOFTRESET),
599 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
600 SIDLE_SMART_WKUP),
601 .sysc_fields = &omap_hwmod_sysc_type2,
602};
603
604static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
605 .name = "hdmi",
606 .sysc = &dra7xx_hdmi_sysc,
607};
608
609/* dss_hdmi */
610
611static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
612 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
613};
614
615static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
616 .name = "dss_hdmi",
617 .class = &dra7xx_hdmi_hwmod_class,
618 .clkdm_name = "dss_clkdm",
619 .main_clk = "dss_48mhz_clk",
620 .prcm = {
621 .omap4 = {
622 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
623 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
624 },
625 },
626 .opt_clks = dss_hdmi_opt_clks,
627 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
628 .parent_hwmod = &dra7xx_dss_hwmod,
629};
630
631/*
632 * 'elm' class
633 *
634 */
635
636static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
637 .rev_offs = 0x0000,
638 .sysc_offs = 0x0010,
639 .syss_offs = 0x0014,
640 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
641 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
642 SYSS_HAS_RESET_STATUS),
643 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
644 SIDLE_SMART_WKUP),
645 .sysc_fields = &omap_hwmod_sysc_type1,
646};
647
648static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
649 .name = "elm",
650 .sysc = &dra7xx_elm_sysc,
651};
652
653/* elm */
654
655static struct omap_hwmod dra7xx_elm_hwmod = {
656 .name = "elm",
657 .class = &dra7xx_elm_hwmod_class,
658 .clkdm_name = "l4per_clkdm",
659 .main_clk = "l3_iclk_div",
660 .prcm = {
661 .omap4 = {
662 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
663 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
664 },
665 },
666};
667
668/*
669 * 'gpio' class
670 *
671 */
672
673static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
674 .rev_offs = 0x0000,
675 .sysc_offs = 0x0010,
676 .syss_offs = 0x0114,
677 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
678 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
679 SYSS_HAS_RESET_STATUS),
680 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
681 SIDLE_SMART_WKUP),
682 .sysc_fields = &omap_hwmod_sysc_type1,
683};
684
685static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
686 .name = "gpio",
687 .sysc = &dra7xx_gpio_sysc,
688 .rev = 2,
689};
690
691/* gpio dev_attr */
692static struct omap_gpio_dev_attr gpio_dev_attr = {
693 .bank_width = 32,
694 .dbck_flag = true,
695};
696
697/* gpio1 */
698static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
699 { .role = "dbclk", .clk = "gpio1_dbclk" },
700};
701
702static struct omap_hwmod dra7xx_gpio1_hwmod = {
703 .name = "gpio1",
704 .class = &dra7xx_gpio_hwmod_class,
705 .clkdm_name = "wkupaon_clkdm",
706 .main_clk = "wkupaon_iclk_mux",
707 .prcm = {
708 .omap4 = {
709 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
710 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
711 .modulemode = MODULEMODE_HWCTRL,
712 },
713 },
714 .opt_clks = gpio1_opt_clks,
715 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
716 .dev_attr = &gpio_dev_attr,
717};
718
719/* gpio2 */
720static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
721 { .role = "dbclk", .clk = "gpio2_dbclk" },
722};
723
724static struct omap_hwmod dra7xx_gpio2_hwmod = {
725 .name = "gpio2",
726 .class = &dra7xx_gpio_hwmod_class,
727 .clkdm_name = "l4per_clkdm",
728 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
729 .main_clk = "l3_iclk_div",
730 .prcm = {
731 .omap4 = {
732 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
733 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
734 .modulemode = MODULEMODE_HWCTRL,
735 },
736 },
737 .opt_clks = gpio2_opt_clks,
738 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
739 .dev_attr = &gpio_dev_attr,
740};
741
742/* gpio3 */
743static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
744 { .role = "dbclk", .clk = "gpio3_dbclk" },
745};
746
747static struct omap_hwmod dra7xx_gpio3_hwmod = {
748 .name = "gpio3",
749 .class = &dra7xx_gpio_hwmod_class,
750 .clkdm_name = "l4per_clkdm",
751 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
752 .main_clk = "l3_iclk_div",
753 .prcm = {
754 .omap4 = {
755 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
756 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
757 .modulemode = MODULEMODE_HWCTRL,
758 },
759 },
760 .opt_clks = gpio3_opt_clks,
761 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
762 .dev_attr = &gpio_dev_attr,
763};
764
765/* gpio4 */
766static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
767 { .role = "dbclk", .clk = "gpio4_dbclk" },
768};
769
770static struct omap_hwmod dra7xx_gpio4_hwmod = {
771 .name = "gpio4",
772 .class = &dra7xx_gpio_hwmod_class,
773 .clkdm_name = "l4per_clkdm",
774 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
775 .main_clk = "l3_iclk_div",
776 .prcm = {
777 .omap4 = {
778 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
779 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
780 .modulemode = MODULEMODE_HWCTRL,
781 },
782 },
783 .opt_clks = gpio4_opt_clks,
784 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
785 .dev_attr = &gpio_dev_attr,
786};
787
788/* gpio5 */
789static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
790 { .role = "dbclk", .clk = "gpio5_dbclk" },
791};
792
793static struct omap_hwmod dra7xx_gpio5_hwmod = {
794 .name = "gpio5",
795 .class = &dra7xx_gpio_hwmod_class,
796 .clkdm_name = "l4per_clkdm",
797 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
798 .main_clk = "l3_iclk_div",
799 .prcm = {
800 .omap4 = {
801 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
802 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
803 .modulemode = MODULEMODE_HWCTRL,
804 },
805 },
806 .opt_clks = gpio5_opt_clks,
807 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
808 .dev_attr = &gpio_dev_attr,
809};
810
811/* gpio6 */
812static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
813 { .role = "dbclk", .clk = "gpio6_dbclk" },
814};
815
816static struct omap_hwmod dra7xx_gpio6_hwmod = {
817 .name = "gpio6",
818 .class = &dra7xx_gpio_hwmod_class,
819 .clkdm_name = "l4per_clkdm",
820 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
821 .main_clk = "l3_iclk_div",
822 .prcm = {
823 .omap4 = {
824 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
825 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
826 .modulemode = MODULEMODE_HWCTRL,
827 },
828 },
829 .opt_clks = gpio6_opt_clks,
830 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
831 .dev_attr = &gpio_dev_attr,
832};
833
834/* gpio7 */
835static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
836 { .role = "dbclk", .clk = "gpio7_dbclk" },
837};
838
839static struct omap_hwmod dra7xx_gpio7_hwmod = {
840 .name = "gpio7",
841 .class = &dra7xx_gpio_hwmod_class,
842 .clkdm_name = "l4per_clkdm",
843 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
844 .main_clk = "l3_iclk_div",
845 .prcm = {
846 .omap4 = {
847 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
848 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
849 .modulemode = MODULEMODE_HWCTRL,
850 },
851 },
852 .opt_clks = gpio7_opt_clks,
853 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
854 .dev_attr = &gpio_dev_attr,
855};
856
857/* gpio8 */
858static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
859 { .role = "dbclk", .clk = "gpio8_dbclk" },
860};
861
862static struct omap_hwmod dra7xx_gpio8_hwmod = {
863 .name = "gpio8",
864 .class = &dra7xx_gpio_hwmod_class,
865 .clkdm_name = "l4per_clkdm",
866 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
867 .main_clk = "l3_iclk_div",
868 .prcm = {
869 .omap4 = {
870 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
871 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
872 .modulemode = MODULEMODE_HWCTRL,
873 },
874 },
875 .opt_clks = gpio8_opt_clks,
876 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
877 .dev_attr = &gpio_dev_attr,
878};
879
880/*
881 * 'gpmc' class
882 *
883 */
884
885static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
886 .rev_offs = 0x0000,
887 .sysc_offs = 0x0010,
888 .syss_offs = 0x0014,
889 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
890 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
891 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
892 .sysc_fields = &omap_hwmod_sysc_type1,
893};
894
895static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
896 .name = "gpmc",
897 .sysc = &dra7xx_gpmc_sysc,
898};
899
900/* gpmc */
901
902static struct omap_hwmod dra7xx_gpmc_hwmod = {
903 .name = "gpmc",
904 .class = &dra7xx_gpmc_hwmod_class,
905 .clkdm_name = "l3main1_clkdm",
906 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
907 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
908 .main_clk = "l3_iclk_div",
909 .prcm = {
910 .omap4 = {
911 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
912 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
913 .modulemode = MODULEMODE_HWCTRL,
914 },
915 },
916};
917
918/*
919 * 'hdq1w' class
920 *
921 */
922
923static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
924 .rev_offs = 0x0000,
925 .sysc_offs = 0x0014,
926 .syss_offs = 0x0018,
927 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
928 SYSS_HAS_RESET_STATUS),
929 .sysc_fields = &omap_hwmod_sysc_type1,
930};
931
932static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
933 .name = "hdq1w",
934 .sysc = &dra7xx_hdq1w_sysc,
935};
936
937/* hdq1w */
938
939static struct omap_hwmod dra7xx_hdq1w_hwmod = {
940 .name = "hdq1w",
941 .class = &dra7xx_hdq1w_hwmod_class,
942 .clkdm_name = "l4per_clkdm",
943 .flags = HWMOD_INIT_NO_RESET,
944 .main_clk = "func_12m_fclk",
945 .prcm = {
946 .omap4 = {
947 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
948 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
949 .modulemode = MODULEMODE_SWCTRL,
950 },
951 },
952};
953
954/*
955 * 'i2c' class
956 *
957 */
958
959static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
960 .sysc_offs = 0x0010,
961 .syss_offs = 0x0090,
962 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
963 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
964 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
965 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
966 SIDLE_SMART_WKUP),
967 .clockact = CLOCKACT_TEST_ICLK,
968 .sysc_fields = &omap_hwmod_sysc_type1,
969};
970
971static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
972 .name = "i2c",
973 .sysc = &dra7xx_i2c_sysc,
974 .reset = &omap_i2c_reset,
975 .rev = OMAP_I2C_IP_VERSION_2,
976};
977
978/* i2c dev_attr */
979static struct omap_i2c_dev_attr i2c_dev_attr = {
980 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
981};
982
983/* i2c1 */
984static struct omap_hwmod dra7xx_i2c1_hwmod = {
985 .name = "i2c1",
986 .class = &dra7xx_i2c_hwmod_class,
987 .clkdm_name = "l4per_clkdm",
988 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
989 .main_clk = "func_96m_fclk",
990 .prcm = {
991 .omap4 = {
992 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
993 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
994 .modulemode = MODULEMODE_SWCTRL,
995 },
996 },
997 .dev_attr = &i2c_dev_attr,
998};
999
1000/* i2c2 */
1001static struct omap_hwmod dra7xx_i2c2_hwmod = {
1002 .name = "i2c2",
1003 .class = &dra7xx_i2c_hwmod_class,
1004 .clkdm_name = "l4per_clkdm",
1005 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1006 .main_clk = "func_96m_fclk",
1007 .prcm = {
1008 .omap4 = {
1009 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1010 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1011 .modulemode = MODULEMODE_SWCTRL,
1012 },
1013 },
1014 .dev_attr = &i2c_dev_attr,
1015};
1016
1017/* i2c3 */
1018static struct omap_hwmod dra7xx_i2c3_hwmod = {
1019 .name = "i2c3",
1020 .class = &dra7xx_i2c_hwmod_class,
1021 .clkdm_name = "l4per_clkdm",
1022 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1023 .main_clk = "func_96m_fclk",
1024 .prcm = {
1025 .omap4 = {
1026 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1027 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1028 .modulemode = MODULEMODE_SWCTRL,
1029 },
1030 },
1031 .dev_attr = &i2c_dev_attr,
1032};
1033
1034/* i2c4 */
1035static struct omap_hwmod dra7xx_i2c4_hwmod = {
1036 .name = "i2c4",
1037 .class = &dra7xx_i2c_hwmod_class,
1038 .clkdm_name = "l4per_clkdm",
1039 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1040 .main_clk = "func_96m_fclk",
1041 .prcm = {
1042 .omap4 = {
1043 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1044 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1045 .modulemode = MODULEMODE_SWCTRL,
1046 },
1047 },
1048 .dev_attr = &i2c_dev_attr,
1049};
1050
1051/* i2c5 */
1052static struct omap_hwmod dra7xx_i2c5_hwmod = {
1053 .name = "i2c5",
1054 .class = &dra7xx_i2c_hwmod_class,
1055 .clkdm_name = "ipu_clkdm",
1056 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1057 .main_clk = "func_96m_fclk",
1058 .prcm = {
1059 .omap4 = {
1060 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1061 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1062 .modulemode = MODULEMODE_SWCTRL,
1063 },
1064 },
1065 .dev_attr = &i2c_dev_attr,
1066};
1067
1068/*
1069 * 'mailbox' class
1070 *
1071 */
1072
1073static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1074 .rev_offs = 0x0000,
1075 .sysc_offs = 0x0010,
1076 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1077 SYSC_HAS_SOFTRESET),
1078 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1079 .sysc_fields = &omap_hwmod_sysc_type2,
1080};
1081
1082static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1083 .name = "mailbox",
1084 .sysc = &dra7xx_mailbox_sysc,
1085};
1086
1087/* mailbox1 */
1088static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1089 .name = "mailbox1",
1090 .class = &dra7xx_mailbox_hwmod_class,
1091 .clkdm_name = "l4cfg_clkdm",
1092 .prcm = {
1093 .omap4 = {
1094 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1095 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1096 },
1097 },
1098};
1099
1100/* mailbox2 */
1101static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1102 .name = "mailbox2",
1103 .class = &dra7xx_mailbox_hwmod_class,
1104 .clkdm_name = "l4cfg_clkdm",
1105 .prcm = {
1106 .omap4 = {
1107 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1108 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1109 },
1110 },
1111};
1112
1113/* mailbox3 */
1114static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1115 .name = "mailbox3",
1116 .class = &dra7xx_mailbox_hwmod_class,
1117 .clkdm_name = "l4cfg_clkdm",
1118 .prcm = {
1119 .omap4 = {
1120 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1121 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1122 },
1123 },
1124};
1125
1126/* mailbox4 */
1127static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1128 .name = "mailbox4",
1129 .class = &dra7xx_mailbox_hwmod_class,
1130 .clkdm_name = "l4cfg_clkdm",
1131 .prcm = {
1132 .omap4 = {
1133 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1134 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1135 },
1136 },
1137};
1138
1139/* mailbox5 */
1140static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1141 .name = "mailbox5",
1142 .class = &dra7xx_mailbox_hwmod_class,
1143 .clkdm_name = "l4cfg_clkdm",
1144 .prcm = {
1145 .omap4 = {
1146 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1147 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1148 },
1149 },
1150};
1151
1152/* mailbox6 */
1153static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1154 .name = "mailbox6",
1155 .class = &dra7xx_mailbox_hwmod_class,
1156 .clkdm_name = "l4cfg_clkdm",
1157 .prcm = {
1158 .omap4 = {
1159 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1160 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1161 },
1162 },
1163};
1164
1165/* mailbox7 */
1166static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1167 .name = "mailbox7",
1168 .class = &dra7xx_mailbox_hwmod_class,
1169 .clkdm_name = "l4cfg_clkdm",
1170 .prcm = {
1171 .omap4 = {
1172 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1173 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1174 },
1175 },
1176};
1177
1178/* mailbox8 */
1179static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1180 .name = "mailbox8",
1181 .class = &dra7xx_mailbox_hwmod_class,
1182 .clkdm_name = "l4cfg_clkdm",
1183 .prcm = {
1184 .omap4 = {
1185 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1186 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1187 },
1188 },
1189};
1190
1191/* mailbox9 */
1192static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1193 .name = "mailbox9",
1194 .class = &dra7xx_mailbox_hwmod_class,
1195 .clkdm_name = "l4cfg_clkdm",
1196 .prcm = {
1197 .omap4 = {
1198 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1199 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1200 },
1201 },
1202};
1203
1204/* mailbox10 */
1205static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1206 .name = "mailbox10",
1207 .class = &dra7xx_mailbox_hwmod_class,
1208 .clkdm_name = "l4cfg_clkdm",
1209 .prcm = {
1210 .omap4 = {
1211 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1212 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1213 },
1214 },
1215};
1216
1217/* mailbox11 */
1218static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1219 .name = "mailbox11",
1220 .class = &dra7xx_mailbox_hwmod_class,
1221 .clkdm_name = "l4cfg_clkdm",
1222 .prcm = {
1223 .omap4 = {
1224 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1225 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1226 },
1227 },
1228};
1229
1230/* mailbox12 */
1231static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1232 .name = "mailbox12",
1233 .class = &dra7xx_mailbox_hwmod_class,
1234 .clkdm_name = "l4cfg_clkdm",
1235 .prcm = {
1236 .omap4 = {
1237 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1238 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1239 },
1240 },
1241};
1242
1243/* mailbox13 */
1244static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1245 .name = "mailbox13",
1246 .class = &dra7xx_mailbox_hwmod_class,
1247 .clkdm_name = "l4cfg_clkdm",
1248 .prcm = {
1249 .omap4 = {
1250 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1251 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1252 },
1253 },
1254};
1255
1256/*
1257 * 'mcspi' class
1258 *
1259 */
1260
1261static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1262 .rev_offs = 0x0000,
1263 .sysc_offs = 0x0010,
1264 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1265 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1266 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1267 SIDLE_SMART_WKUP),
1268 .sysc_fields = &omap_hwmod_sysc_type2,
1269};
1270
1271static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1272 .name = "mcspi",
1273 .sysc = &dra7xx_mcspi_sysc,
1274 .rev = OMAP4_MCSPI_REV,
1275};
1276
1277/* mcspi1 */
1278/* mcspi1 dev_attr */
1279static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1280 .num_chipselect = 4,
1281};
1282
1283static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1284 .name = "mcspi1",
1285 .class = &dra7xx_mcspi_hwmod_class,
1286 .clkdm_name = "l4per_clkdm",
1287 .main_clk = "func_48m_fclk",
1288 .prcm = {
1289 .omap4 = {
1290 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1291 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1292 .modulemode = MODULEMODE_SWCTRL,
1293 },
1294 },
1295 .dev_attr = &mcspi1_dev_attr,
1296};
1297
1298/* mcspi2 */
1299/* mcspi2 dev_attr */
1300static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1301 .num_chipselect = 2,
1302};
1303
1304static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1305 .name = "mcspi2",
1306 .class = &dra7xx_mcspi_hwmod_class,
1307 .clkdm_name = "l4per_clkdm",
1308 .main_clk = "func_48m_fclk",
1309 .prcm = {
1310 .omap4 = {
1311 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1312 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1313 .modulemode = MODULEMODE_SWCTRL,
1314 },
1315 },
1316 .dev_attr = &mcspi2_dev_attr,
1317};
1318
1319/* mcspi3 */
1320/* mcspi3 dev_attr */
1321static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1322 .num_chipselect = 2,
1323};
1324
1325static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1326 .name = "mcspi3",
1327 .class = &dra7xx_mcspi_hwmod_class,
1328 .clkdm_name = "l4per_clkdm",
1329 .main_clk = "func_48m_fclk",
1330 .prcm = {
1331 .omap4 = {
1332 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1333 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1334 .modulemode = MODULEMODE_SWCTRL,
1335 },
1336 },
1337 .dev_attr = &mcspi3_dev_attr,
1338};
1339
1340/* mcspi4 */
1341/* mcspi4 dev_attr */
1342static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1343 .num_chipselect = 1,
1344};
1345
1346static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1347 .name = "mcspi4",
1348 .class = &dra7xx_mcspi_hwmod_class,
1349 .clkdm_name = "l4per_clkdm",
1350 .main_clk = "func_48m_fclk",
1351 .prcm = {
1352 .omap4 = {
1353 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1354 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1355 .modulemode = MODULEMODE_SWCTRL,
1356 },
1357 },
1358 .dev_attr = &mcspi4_dev_attr,
1359};
1360
1361/*
1362 * 'mcasp' class
1363 *
1364 */
1365static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1366 .sysc_offs = 0x0004,
1367 .sysc_flags = SYSC_HAS_SIDLEMODE,
1368 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1369 .sysc_fields = &omap_hwmod_sysc_type3,
1370};
1371
1372static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1373 .name = "mcasp",
1374 .sysc = &dra7xx_mcasp_sysc,
1375};
1376
1377/* mcasp3 */
1378static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1379 { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1380};
1381
1382static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1383 .name = "mcasp3",
1384 .class = &dra7xx_mcasp_hwmod_class,
1385 .clkdm_name = "l4per2_clkdm",
1386 .main_clk = "mcasp3_aux_gfclk_mux",
1387 .flags = HWMOD_OPT_CLKS_NEEDED,
1388 .prcm = {
1389 .omap4 = {
1390 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1391 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1392 .modulemode = MODULEMODE_SWCTRL,
1393 },
1394 },
1395 .opt_clks = mcasp3_opt_clks,
1396 .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks),
1397};
1398
1399/*
1400 * 'mmc' class
1401 *
1402 */
1403
1404static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1405 .rev_offs = 0x0000,
1406 .sysc_offs = 0x0010,
1407 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1408 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1409 SYSC_HAS_SOFTRESET),
1410 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1411 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1412 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1413 .sysc_fields = &omap_hwmod_sysc_type2,
1414};
1415
1416static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1417 .name = "mmc",
1418 .sysc = &dra7xx_mmc_sysc,
1419};
1420
1421/* mmc1 */
1422static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1423 { .role = "clk32k", .clk = "mmc1_clk32k" },
1424};
1425
1426/* mmc1 dev_attr */
1427static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1428 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1429};
1430
1431static struct omap_hwmod dra7xx_mmc1_hwmod = {
1432 .name = "mmc1",
1433 .class = &dra7xx_mmc_hwmod_class,
1434 .clkdm_name = "l3init_clkdm",
1435 .main_clk = "mmc1_fclk_div",
1436 .prcm = {
1437 .omap4 = {
1438 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1439 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1440 .modulemode = MODULEMODE_SWCTRL,
1441 },
1442 },
1443 .opt_clks = mmc1_opt_clks,
1444 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1445 .dev_attr = &mmc1_dev_attr,
1446};
1447
1448/* mmc2 */
1449static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1450 { .role = "clk32k", .clk = "mmc2_clk32k" },
1451};
1452
1453static struct omap_hwmod dra7xx_mmc2_hwmod = {
1454 .name = "mmc2",
1455 .class = &dra7xx_mmc_hwmod_class,
1456 .clkdm_name = "l3init_clkdm",
1457 .main_clk = "mmc2_fclk_div",
1458 .prcm = {
1459 .omap4 = {
1460 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1461 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1462 .modulemode = MODULEMODE_SWCTRL,
1463 },
1464 },
1465 .opt_clks = mmc2_opt_clks,
1466 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1467};
1468
1469/* mmc3 */
1470static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1471 { .role = "clk32k", .clk = "mmc3_clk32k" },
1472};
1473
1474static struct omap_hwmod dra7xx_mmc3_hwmod = {
1475 .name = "mmc3",
1476 .class = &dra7xx_mmc_hwmod_class,
1477 .clkdm_name = "l4per_clkdm",
1478 .main_clk = "mmc3_gfclk_div",
1479 .prcm = {
1480 .omap4 = {
1481 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1482 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1483 .modulemode = MODULEMODE_SWCTRL,
1484 },
1485 },
1486 .opt_clks = mmc3_opt_clks,
1487 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1488};
1489
1490/* mmc4 */
1491static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1492 { .role = "clk32k", .clk = "mmc4_clk32k" },
1493};
1494
1495static struct omap_hwmod dra7xx_mmc4_hwmod = {
1496 .name = "mmc4",
1497 .class = &dra7xx_mmc_hwmod_class,
1498 .clkdm_name = "l4per_clkdm",
1499 .main_clk = "mmc4_gfclk_div",
1500 .prcm = {
1501 .omap4 = {
1502 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1503 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1504 .modulemode = MODULEMODE_SWCTRL,
1505 },
1506 },
1507 .opt_clks = mmc4_opt_clks,
1508 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1509};
1510
1511/*
1512 * 'mpu' class
1513 *
1514 */
1515
1516static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1517 .name = "mpu",
1518};
1519
1520/* mpu */
1521static struct omap_hwmod dra7xx_mpu_hwmod = {
1522 .name = "mpu",
1523 .class = &dra7xx_mpu_hwmod_class,
1524 .clkdm_name = "mpu_clkdm",
1525 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1526 .main_clk = "dpll_mpu_m2_ck",
1527 .prcm = {
1528 .omap4 = {
1529 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1530 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1531 },
1532 },
1533};
1534
1535/*
1536 * 'ocp2scp' class
1537 *
1538 */
1539
1540static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1541 .rev_offs = 0x0000,
1542 .sysc_offs = 0x0010,
1543 .syss_offs = 0x0014,
1544 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1545 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1546 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1547 .sysc_fields = &omap_hwmod_sysc_type1,
1548};
1549
1550static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1551 .name = "ocp2scp",
1552 .sysc = &dra7xx_ocp2scp_sysc,
1553};
1554
1555/* ocp2scp1 */
1556static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1557 .name = "ocp2scp1",
1558 .class = &dra7xx_ocp2scp_hwmod_class,
1559 .clkdm_name = "l3init_clkdm",
1560 .main_clk = "l4_root_clk_div",
1561 .prcm = {
1562 .omap4 = {
1563 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1564 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1565 .modulemode = MODULEMODE_HWCTRL,
1566 },
1567 },
1568};
1569
1570/* ocp2scp3 */
1571static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1572 .name = "ocp2scp3",
1573 .class = &dra7xx_ocp2scp_hwmod_class,
1574 .clkdm_name = "l3init_clkdm",
1575 .main_clk = "l4_root_clk_div",
1576 .prcm = {
1577 .omap4 = {
1578 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1579 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1580 .modulemode = MODULEMODE_HWCTRL,
1581 },
1582 },
1583};
1584
1585/*
1586 * 'PCIE' class
1587 *
1588 */
1589
1590/*
1591 * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1592 * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1593 * associated with an IP automatically leaving the driver to handle that
1594 * by itself. This does not work for PCIeSS which needs the reset lines
1595 * deasserted for the driver to start accessing registers.
1596 *
1597 * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1598 * lines after asserting them.
1599 */
1600static int dra7xx_pciess_reset(struct omap_hwmod *oh)
1601{
1602 int i;
1603
1604 for (i = 0; i < oh->rst_lines_cnt; i++) {
1605 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1606 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1607 }
1608
1609 return 0;
1610}
1611
1612static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1613 .name = "pcie",
1614 .reset = dra7xx_pciess_reset,
1615};
1616
1617/* pcie1 */
1618static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1619 { .name = "pcie", .rst_shift = 0 },
1620};
1621
1622static struct omap_hwmod dra7xx_pciess1_hwmod = {
1623 .name = "pcie1",
1624 .class = &dra7xx_pciess_hwmod_class,
1625 .clkdm_name = "pcie_clkdm",
1626 .rst_lines = dra7xx_pciess1_resets,
1627 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
1628 .main_clk = "l4_root_clk_div",
1629 .prcm = {
1630 .omap4 = {
1631 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1632 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1633 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1634 .modulemode = MODULEMODE_SWCTRL,
1635 },
1636 },
1637};
1638
1639/* pcie2 */
1640static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1641 { .name = "pcie", .rst_shift = 1 },
1642};
1643
1644/* pcie2 */
1645static struct omap_hwmod dra7xx_pciess2_hwmod = {
1646 .name = "pcie2",
1647 .class = &dra7xx_pciess_hwmod_class,
1648 .clkdm_name = "pcie_clkdm",
1649 .rst_lines = dra7xx_pciess2_resets,
1650 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
1651 .main_clk = "l4_root_clk_div",
1652 .prcm = {
1653 .omap4 = {
1654 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1655 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1656 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1657 .modulemode = MODULEMODE_SWCTRL,
1658 },
1659 },
1660};
1661
1662/*
1663 * 'qspi' class
1664 *
1665 */
1666
1667static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1668 .sysc_offs = 0x0010,
1669 .sysc_flags = SYSC_HAS_SIDLEMODE,
1670 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1671 SIDLE_SMART_WKUP),
1672 .sysc_fields = &omap_hwmod_sysc_type2,
1673};
1674
1675static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1676 .name = "qspi",
1677 .sysc = &dra7xx_qspi_sysc,
1678};
1679
1680/* qspi */
1681static struct omap_hwmod dra7xx_qspi_hwmod = {
1682 .name = "qspi",
1683 .class = &dra7xx_qspi_hwmod_class,
1684 .clkdm_name = "l4per2_clkdm",
1685 .main_clk = "qspi_gfclk_div",
1686 .prcm = {
1687 .omap4 = {
1688 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1689 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1690 .modulemode = MODULEMODE_SWCTRL,
1691 },
1692 },
1693};
1694
1695/*
1696 * 'rtcss' class
1697 *
1698 */
1699static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1700 .sysc_offs = 0x0078,
1701 .sysc_flags = SYSC_HAS_SIDLEMODE,
1702 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1703 SIDLE_SMART_WKUP),
1704 .sysc_fields = &omap_hwmod_sysc_type3,
1705};
1706
1707static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1708 .name = "rtcss",
1709 .sysc = &dra7xx_rtcss_sysc,
1710};
1711
1712/* rtcss */
1713static struct omap_hwmod dra7xx_rtcss_hwmod = {
1714 .name = "rtcss",
1715 .class = &dra7xx_rtcss_hwmod_class,
1716 .clkdm_name = "rtc_clkdm",
1717 .main_clk = "sys_32k_ck",
1718 .prcm = {
1719 .omap4 = {
1720 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1721 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1722 .modulemode = MODULEMODE_SWCTRL,
1723 },
1724 },
1725};
1726
1727/*
1728 * 'sata' class
1729 *
1730 */
1731
1732static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1733 .sysc_offs = 0x0000,
1734 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1735 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1736 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1737 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1738 .sysc_fields = &omap_hwmod_sysc_type2,
1739};
1740
1741static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1742 .name = "sata",
1743 .sysc = &dra7xx_sata_sysc,
1744};
1745
1746/* sata */
1747
1748static struct omap_hwmod dra7xx_sata_hwmod = {
1749 .name = "sata",
1750 .class = &dra7xx_sata_hwmod_class,
1751 .clkdm_name = "l3init_clkdm",
1752 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1753 .main_clk = "func_48m_fclk",
1754 .mpu_rt_idx = 1,
1755 .prcm = {
1756 .omap4 = {
1757 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1758 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1759 .modulemode = MODULEMODE_SWCTRL,
1760 },
1761 },
1762};
1763
1764/*
1765 * 'smartreflex' class
1766 *
1767 */
1768
1769/* The IP is not compliant to type1 / type2 scheme */
1770static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1771 .sidle_shift = 24,
1772 .enwkup_shift = 26,
1773};
1774
1775static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1776 .sysc_offs = 0x0038,
1777 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1778 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1779 SIDLE_SMART_WKUP),
1780 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1781};
1782
1783static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1784 .name = "smartreflex",
1785 .sysc = &dra7xx_smartreflex_sysc,
1786 .rev = 2,
1787};
1788
1789/* smartreflex_core */
1790/* smartreflex_core dev_attr */
1791static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1792 .sensor_voltdm_name = "core",
1793};
1794
1795static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1796 .name = "smartreflex_core",
1797 .class = &dra7xx_smartreflex_hwmod_class,
1798 .clkdm_name = "coreaon_clkdm",
1799 .main_clk = "wkupaon_iclk_mux",
1800 .prcm = {
1801 .omap4 = {
1802 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1803 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1804 .modulemode = MODULEMODE_SWCTRL,
1805 },
1806 },
1807 .dev_attr = &smartreflex_core_dev_attr,
1808};
1809
1810/* smartreflex_mpu */
1811/* smartreflex_mpu dev_attr */
1812static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1813 .sensor_voltdm_name = "mpu",
1814};
1815
1816static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1817 .name = "smartreflex_mpu",
1818 .class = &dra7xx_smartreflex_hwmod_class,
1819 .clkdm_name = "coreaon_clkdm",
1820 .main_clk = "wkupaon_iclk_mux",
1821 .prcm = {
1822 .omap4 = {
1823 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1824 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1825 .modulemode = MODULEMODE_SWCTRL,
1826 },
1827 },
1828 .dev_attr = &smartreflex_mpu_dev_attr,
1829};
1830
1831/*
1832 * 'spinlock' class
1833 *
1834 */
1835
1836static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1837 .rev_offs = 0x0000,
1838 .sysc_offs = 0x0010,
1839 .syss_offs = 0x0014,
1840 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1841 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1842 SYSS_HAS_RESET_STATUS),
1843 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1844 .sysc_fields = &omap_hwmod_sysc_type1,
1845};
1846
1847static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1848 .name = "spinlock",
1849 .sysc = &dra7xx_spinlock_sysc,
1850};
1851
1852/* spinlock */
1853static struct omap_hwmod dra7xx_spinlock_hwmod = {
1854 .name = "spinlock",
1855 .class = &dra7xx_spinlock_hwmod_class,
1856 .clkdm_name = "l4cfg_clkdm",
1857 .main_clk = "l3_iclk_div",
1858 .prcm = {
1859 .omap4 = {
1860 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1861 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1862 },
1863 },
1864};
1865
1866/*
1867 * 'timer' class
1868 *
1869 * This class contains several variants: ['timer_1ms', 'timer_secure',
1870 * 'timer']
1871 */
1872
1873static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1874 .rev_offs = 0x0000,
1875 .sysc_offs = 0x0010,
1876 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1877 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1878 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1879 SIDLE_SMART_WKUP),
1880 .sysc_fields = &omap_hwmod_sysc_type2,
1881};
1882
1883static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1884 .name = "timer",
1885 .sysc = &dra7xx_timer_1ms_sysc,
1886};
1887
1888static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1889 .rev_offs = 0x0000,
1890 .sysc_offs = 0x0010,
1891 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1892 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1893 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1894 SIDLE_SMART_WKUP),
1895 .sysc_fields = &omap_hwmod_sysc_type2,
1896};
1897
1898static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1899 .name = "timer",
1900 .sysc = &dra7xx_timer_sysc,
1901};
1902
1903/* timer1 */
1904static struct omap_hwmod dra7xx_timer1_hwmod = {
1905 .name = "timer1",
1906 .class = &dra7xx_timer_1ms_hwmod_class,
1907 .clkdm_name = "wkupaon_clkdm",
1908 .main_clk = "timer1_gfclk_mux",
1909 .prcm = {
1910 .omap4 = {
1911 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1912 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1913 .modulemode = MODULEMODE_SWCTRL,
1914 },
1915 },
1916};
1917
1918/* timer2 */
1919static struct omap_hwmod dra7xx_timer2_hwmod = {
1920 .name = "timer2",
1921 .class = &dra7xx_timer_1ms_hwmod_class,
1922 .clkdm_name = "l4per_clkdm",
1923 .main_clk = "timer2_gfclk_mux",
1924 .prcm = {
1925 .omap4 = {
1926 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1927 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1928 .modulemode = MODULEMODE_SWCTRL,
1929 },
1930 },
1931};
1932
1933/* timer3 */
1934static struct omap_hwmod dra7xx_timer3_hwmod = {
1935 .name = "timer3",
1936 .class = &dra7xx_timer_hwmod_class,
1937 .clkdm_name = "l4per_clkdm",
1938 .main_clk = "timer3_gfclk_mux",
1939 .prcm = {
1940 .omap4 = {
1941 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1942 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1943 .modulemode = MODULEMODE_SWCTRL,
1944 },
1945 },
1946};
1947
1948/* timer4 */
1949static struct omap_hwmod dra7xx_timer4_hwmod = {
1950 .name = "timer4",
1951 .class = &dra7xx_timer_hwmod_class,
1952 .clkdm_name = "l4per_clkdm",
1953 .main_clk = "timer4_gfclk_mux",
1954 .prcm = {
1955 .omap4 = {
1956 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1957 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1958 .modulemode = MODULEMODE_SWCTRL,
1959 },
1960 },
1961};
1962
1963/* timer5 */
1964static struct omap_hwmod dra7xx_timer5_hwmod = {
1965 .name = "timer5",
1966 .class = &dra7xx_timer_hwmod_class,
1967 .clkdm_name = "ipu_clkdm",
1968 .main_clk = "timer5_gfclk_mux",
1969 .prcm = {
1970 .omap4 = {
1971 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1972 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1973 .modulemode = MODULEMODE_SWCTRL,
1974 },
1975 },
1976};
1977
1978/* timer6 */
1979static struct omap_hwmod dra7xx_timer6_hwmod = {
1980 .name = "timer6",
1981 .class = &dra7xx_timer_hwmod_class,
1982 .clkdm_name = "ipu_clkdm",
1983 .main_clk = "timer6_gfclk_mux",
1984 .prcm = {
1985 .omap4 = {
1986 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1987 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1988 .modulemode = MODULEMODE_SWCTRL,
1989 },
1990 },
1991};
1992
1993/* timer7 */
1994static struct omap_hwmod dra7xx_timer7_hwmod = {
1995 .name = "timer7",
1996 .class = &dra7xx_timer_hwmod_class,
1997 .clkdm_name = "ipu_clkdm",
1998 .main_clk = "timer7_gfclk_mux",
1999 .prcm = {
2000 .omap4 = {
2001 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2002 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2003 .modulemode = MODULEMODE_SWCTRL,
2004 },
2005 },
2006};
2007
2008/* timer8 */
2009static struct omap_hwmod dra7xx_timer8_hwmod = {
2010 .name = "timer8",
2011 .class = &dra7xx_timer_hwmod_class,
2012 .clkdm_name = "ipu_clkdm",
2013 .main_clk = "timer8_gfclk_mux",
2014 .prcm = {
2015 .omap4 = {
2016 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2017 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2018 .modulemode = MODULEMODE_SWCTRL,
2019 },
2020 },
2021};
2022
2023/* timer9 */
2024static struct omap_hwmod dra7xx_timer9_hwmod = {
2025 .name = "timer9",
2026 .class = &dra7xx_timer_hwmod_class,
2027 .clkdm_name = "l4per_clkdm",
2028 .main_clk = "timer9_gfclk_mux",
2029 .prcm = {
2030 .omap4 = {
2031 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2032 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2033 .modulemode = MODULEMODE_SWCTRL,
2034 },
2035 },
2036};
2037
2038/* timer10 */
2039static struct omap_hwmod dra7xx_timer10_hwmod = {
2040 .name = "timer10",
2041 .class = &dra7xx_timer_1ms_hwmod_class,
2042 .clkdm_name = "l4per_clkdm",
2043 .main_clk = "timer10_gfclk_mux",
2044 .prcm = {
2045 .omap4 = {
2046 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2047 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2048 .modulemode = MODULEMODE_SWCTRL,
2049 },
2050 },
2051};
2052
2053/* timer11 */
2054static struct omap_hwmod dra7xx_timer11_hwmod = {
2055 .name = "timer11",
2056 .class = &dra7xx_timer_hwmod_class,
2057 .clkdm_name = "l4per_clkdm",
2058 .main_clk = "timer11_gfclk_mux",
2059 .prcm = {
2060 .omap4 = {
2061 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2062 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2063 .modulemode = MODULEMODE_SWCTRL,
2064 },
2065 },
2066};
2067
2068/* timer13 */
2069static struct omap_hwmod dra7xx_timer13_hwmod = {
2070 .name = "timer13",
2071 .class = &dra7xx_timer_hwmod_class,
2072 .clkdm_name = "l4per3_clkdm",
2073 .main_clk = "timer13_gfclk_mux",
2074 .prcm = {
2075 .omap4 = {
2076 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2077 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2078 .modulemode = MODULEMODE_SWCTRL,
2079 },
2080 },
2081};
2082
2083/* timer14 */
2084static struct omap_hwmod dra7xx_timer14_hwmod = {
2085 .name = "timer14",
2086 .class = &dra7xx_timer_hwmod_class,
2087 .clkdm_name = "l4per3_clkdm",
2088 .main_clk = "timer14_gfclk_mux",
2089 .prcm = {
2090 .omap4 = {
2091 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2092 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2093 .modulemode = MODULEMODE_SWCTRL,
2094 },
2095 },
2096};
2097
2098/* timer15 */
2099static struct omap_hwmod dra7xx_timer15_hwmod = {
2100 .name = "timer15",
2101 .class = &dra7xx_timer_hwmod_class,
2102 .clkdm_name = "l4per3_clkdm",
2103 .main_clk = "timer15_gfclk_mux",
2104 .prcm = {
2105 .omap4 = {
2106 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2107 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2108 .modulemode = MODULEMODE_SWCTRL,
2109 },
2110 },
2111};
2112
2113/* timer16 */
2114static struct omap_hwmod dra7xx_timer16_hwmod = {
2115 .name = "timer16",
2116 .class = &dra7xx_timer_hwmod_class,
2117 .clkdm_name = "l4per3_clkdm",
2118 .main_clk = "timer16_gfclk_mux",
2119 .prcm = {
2120 .omap4 = {
2121 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2122 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2123 .modulemode = MODULEMODE_SWCTRL,
2124 },
2125 },
2126};
2127
2128/*
2129 * 'uart' class
2130 *
2131 */
2132
2133static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2134 .rev_offs = 0x0050,
2135 .sysc_offs = 0x0054,
2136 .syss_offs = 0x0058,
2137 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2138 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2139 SYSS_HAS_RESET_STATUS),
2140 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2141 SIDLE_SMART_WKUP),
2142 .sysc_fields = &omap_hwmod_sysc_type1,
2143};
2144
2145static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2146 .name = "uart",
2147 .sysc = &dra7xx_uart_sysc,
2148};
2149
2150/* uart1 */
2151static struct omap_hwmod dra7xx_uart1_hwmod = {
2152 .name = "uart1",
2153 .class = &dra7xx_uart_hwmod_class,
2154 .clkdm_name = "l4per_clkdm",
2155 .main_clk = "uart1_gfclk_mux",
2156 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2157 .prcm = {
2158 .omap4 = {
2159 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2160 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2161 .modulemode = MODULEMODE_SWCTRL,
2162 },
2163 },
2164};
2165
2166/* uart2 */
2167static struct omap_hwmod dra7xx_uart2_hwmod = {
2168 .name = "uart2",
2169 .class = &dra7xx_uart_hwmod_class,
2170 .clkdm_name = "l4per_clkdm",
2171 .main_clk = "uart2_gfclk_mux",
2172 .flags = HWMOD_SWSUP_SIDLE_ACT,
2173 .prcm = {
2174 .omap4 = {
2175 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2176 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2177 .modulemode = MODULEMODE_SWCTRL,
2178 },
2179 },
2180};
2181
2182/* uart3 */
2183static struct omap_hwmod dra7xx_uart3_hwmod = {
2184 .name = "uart3",
2185 .class = &dra7xx_uart_hwmod_class,
2186 .clkdm_name = "l4per_clkdm",
2187 .main_clk = "uart3_gfclk_mux",
2188 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2189 .prcm = {
2190 .omap4 = {
2191 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2192 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2193 .modulemode = MODULEMODE_SWCTRL,
2194 },
2195 },
2196};
2197
2198/* uart4 */
2199static struct omap_hwmod dra7xx_uart4_hwmod = {
2200 .name = "uart4",
2201 .class = &dra7xx_uart_hwmod_class,
2202 .clkdm_name = "l4per_clkdm",
2203 .main_clk = "uart4_gfclk_mux",
2204 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
2205 .prcm = {
2206 .omap4 = {
2207 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2208 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2209 .modulemode = MODULEMODE_SWCTRL,
2210 },
2211 },
2212};
2213
2214/* uart5 */
2215static struct omap_hwmod dra7xx_uart5_hwmod = {
2216 .name = "uart5",
2217 .class = &dra7xx_uart_hwmod_class,
2218 .clkdm_name = "l4per_clkdm",
2219 .main_clk = "uart5_gfclk_mux",
2220 .flags = HWMOD_SWSUP_SIDLE_ACT,
2221 .prcm = {
2222 .omap4 = {
2223 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2224 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2225 .modulemode = MODULEMODE_SWCTRL,
2226 },
2227 },
2228};
2229
2230/* uart6 */
2231static struct omap_hwmod dra7xx_uart6_hwmod = {
2232 .name = "uart6",
2233 .class = &dra7xx_uart_hwmod_class,
2234 .clkdm_name = "ipu_clkdm",
2235 .main_clk = "uart6_gfclk_mux",
2236 .flags = HWMOD_SWSUP_SIDLE_ACT,
2237 .prcm = {
2238 .omap4 = {
2239 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2240 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2241 .modulemode = MODULEMODE_SWCTRL,
2242 },
2243 },
2244};
2245
2246/* uart7 */
2247static struct omap_hwmod dra7xx_uart7_hwmod = {
2248 .name = "uart7",
2249 .class = &dra7xx_uart_hwmod_class,
2250 .clkdm_name = "l4per2_clkdm",
2251 .main_clk = "uart7_gfclk_mux",
2252 .flags = HWMOD_SWSUP_SIDLE_ACT,
2253 .prcm = {
2254 .omap4 = {
2255 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2256 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2257 .modulemode = MODULEMODE_SWCTRL,
2258 },
2259 },
2260};
2261
2262/* uart8 */
2263static struct omap_hwmod dra7xx_uart8_hwmod = {
2264 .name = "uart8",
2265 .class = &dra7xx_uart_hwmod_class,
2266 .clkdm_name = "l4per2_clkdm",
2267 .main_clk = "uart8_gfclk_mux",
2268 .flags = HWMOD_SWSUP_SIDLE_ACT,
2269 .prcm = {
2270 .omap4 = {
2271 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2272 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2273 .modulemode = MODULEMODE_SWCTRL,
2274 },
2275 },
2276};
2277
2278/* uart9 */
2279static struct omap_hwmod dra7xx_uart9_hwmod = {
2280 .name = "uart9",
2281 .class = &dra7xx_uart_hwmod_class,
2282 .clkdm_name = "l4per2_clkdm",
2283 .main_clk = "uart9_gfclk_mux",
2284 .flags = HWMOD_SWSUP_SIDLE_ACT,
2285 .prcm = {
2286 .omap4 = {
2287 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2288 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2289 .modulemode = MODULEMODE_SWCTRL,
2290 },
2291 },
2292};
2293
2294/* uart10 */
2295static struct omap_hwmod dra7xx_uart10_hwmod = {
2296 .name = "uart10",
2297 .class = &dra7xx_uart_hwmod_class,
2298 .clkdm_name = "wkupaon_clkdm",
2299 .main_clk = "uart10_gfclk_mux",
2300 .flags = HWMOD_SWSUP_SIDLE_ACT,
2301 .prcm = {
2302 .omap4 = {
2303 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2304 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2305 .modulemode = MODULEMODE_SWCTRL,
2306 },
2307 },
2308};
2309
2310/*
2311 * 'usb_otg_ss' class
2312 *
2313 */
2314
2315static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2316 .rev_offs = 0x0000,
2317 .sysc_offs = 0x0010,
2318 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2319 SYSC_HAS_SIDLEMODE),
2320 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2321 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2322 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2323 .sysc_fields = &omap_hwmod_sysc_type2,
2324};
2325
2326static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2327 .name = "usb_otg_ss",
2328 .sysc = &dra7xx_usb_otg_ss_sysc,
2329};
2330
2331/* usb_otg_ss1 */
2332static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2333 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2334};
2335
2336static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2337 .name = "usb_otg_ss1",
2338 .class = &dra7xx_usb_otg_ss_hwmod_class,
2339 .clkdm_name = "l3init_clkdm",
2340 .main_clk = "dpll_core_h13x2_ck",
2341 .prcm = {
2342 .omap4 = {
2343 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2344 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2345 .modulemode = MODULEMODE_HWCTRL,
2346 },
2347 },
2348 .opt_clks = usb_otg_ss1_opt_clks,
2349 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2350};
2351
2352/* usb_otg_ss2 */
2353static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2354 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2355};
2356
2357static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2358 .name = "usb_otg_ss2",
2359 .class = &dra7xx_usb_otg_ss_hwmod_class,
2360 .clkdm_name = "l3init_clkdm",
2361 .main_clk = "dpll_core_h13x2_ck",
2362 .prcm = {
2363 .omap4 = {
2364 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2365 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2366 .modulemode = MODULEMODE_HWCTRL,
2367 },
2368 },
2369 .opt_clks = usb_otg_ss2_opt_clks,
2370 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2371};
2372
2373/* usb_otg_ss3 */
2374static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2375 .name = "usb_otg_ss3",
2376 .class = &dra7xx_usb_otg_ss_hwmod_class,
2377 .clkdm_name = "l3init_clkdm",
2378 .main_clk = "dpll_core_h13x2_ck",
2379 .prcm = {
2380 .omap4 = {
2381 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2382 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2383 .modulemode = MODULEMODE_HWCTRL,
2384 },
2385 },
2386};
2387
2388/* usb_otg_ss4 */
2389static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2390 .name = "usb_otg_ss4",
2391 .class = &dra7xx_usb_otg_ss_hwmod_class,
2392 .clkdm_name = "l3init_clkdm",
2393 .main_clk = "dpll_core_h13x2_ck",
2394 .prcm = {
2395 .omap4 = {
2396 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2397 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2398 .modulemode = MODULEMODE_HWCTRL,
2399 },
2400 },
2401};
2402
2403/*
2404 * 'vcp' class
2405 *
2406 */
2407
2408static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2409 .name = "vcp",
2410};
2411
2412/* vcp1 */
2413static struct omap_hwmod dra7xx_vcp1_hwmod = {
2414 .name = "vcp1",
2415 .class = &dra7xx_vcp_hwmod_class,
2416 .clkdm_name = "l3main1_clkdm",
2417 .main_clk = "l3_iclk_div",
2418 .prcm = {
2419 .omap4 = {
2420 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2421 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2422 },
2423 },
2424};
2425
2426/* vcp2 */
2427static struct omap_hwmod dra7xx_vcp2_hwmod = {
2428 .name = "vcp2",
2429 .class = &dra7xx_vcp_hwmod_class,
2430 .clkdm_name = "l3main1_clkdm",
2431 .main_clk = "l3_iclk_div",
2432 .prcm = {
2433 .omap4 = {
2434 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2435 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2436 },
2437 },
2438};
2439
2440/*
2441 * 'wd_timer' class
2442 *
2443 */
2444
2445static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2446 .rev_offs = 0x0000,
2447 .sysc_offs = 0x0010,
2448 .syss_offs = 0x0014,
2449 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2450 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2451 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2452 SIDLE_SMART_WKUP),
2453 .sysc_fields = &omap_hwmod_sysc_type1,
2454};
2455
2456static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2457 .name = "wd_timer",
2458 .sysc = &dra7xx_wd_timer_sysc,
2459 .pre_shutdown = &omap2_wd_timer_disable,
2460 .reset = &omap2_wd_timer_reset,
2461};
2462
2463/* wd_timer2 */
2464static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2465 .name = "wd_timer2",
2466 .class = &dra7xx_wd_timer_hwmod_class,
2467 .clkdm_name = "wkupaon_clkdm",
2468 .main_clk = "sys_32k_ck",
2469 .prcm = {
2470 .omap4 = {
2471 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2472 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2473 .modulemode = MODULEMODE_SWCTRL,
2474 },
2475 },
2476};
2477
2478
2479/*
2480 * Interfaces
2481 */
2482
2483/* l3_main_1 -> dmm */
2484static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2485 .master = &dra7xx_l3_main_1_hwmod,
2486 .slave = &dra7xx_dmm_hwmod,
2487 .clk = "l3_iclk_div",
2488 .user = OCP_USER_SDMA,
2489};
2490
2491/* l3_main_2 -> l3_instr */
2492static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2493 .master = &dra7xx_l3_main_2_hwmod,
2494 .slave = &dra7xx_l3_instr_hwmod,
2495 .clk = "l3_iclk_div",
2496 .user = OCP_USER_MPU | OCP_USER_SDMA,
2497};
2498
2499/* l4_cfg -> l3_main_1 */
2500static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2501 .master = &dra7xx_l4_cfg_hwmod,
2502 .slave = &dra7xx_l3_main_1_hwmod,
2503 .clk = "l3_iclk_div",
2504 .user = OCP_USER_MPU | OCP_USER_SDMA,
2505};
2506
2507/* mpu -> l3_main_1 */
2508static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2509 .master = &dra7xx_mpu_hwmod,
2510 .slave = &dra7xx_l3_main_1_hwmod,
2511 .clk = "l3_iclk_div",
2512 .user = OCP_USER_MPU,
2513};
2514
2515/* l3_main_1 -> l3_main_2 */
2516static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2517 .master = &dra7xx_l3_main_1_hwmod,
2518 .slave = &dra7xx_l3_main_2_hwmod,
2519 .clk = "l3_iclk_div",
2520 .user = OCP_USER_MPU,
2521};
2522
2523/* l4_cfg -> l3_main_2 */
2524static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2525 .master = &dra7xx_l4_cfg_hwmod,
2526 .slave = &dra7xx_l3_main_2_hwmod,
2527 .clk = "l3_iclk_div",
2528 .user = OCP_USER_MPU | OCP_USER_SDMA,
2529};
2530
2531/* l3_main_1 -> l4_cfg */
2532static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2533 .master = &dra7xx_l3_main_1_hwmod,
2534 .slave = &dra7xx_l4_cfg_hwmod,
2535 .clk = "l3_iclk_div",
2536 .user = OCP_USER_MPU | OCP_USER_SDMA,
2537};
2538
2539/* l3_main_1 -> l4_per1 */
2540static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2541 .master = &dra7xx_l3_main_1_hwmod,
2542 .slave = &dra7xx_l4_per1_hwmod,
2543 .clk = "l3_iclk_div",
2544 .user = OCP_USER_MPU | OCP_USER_SDMA,
2545};
2546
2547/* l3_main_1 -> l4_per2 */
2548static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2549 .master = &dra7xx_l3_main_1_hwmod,
2550 .slave = &dra7xx_l4_per2_hwmod,
2551 .clk = "l3_iclk_div",
2552 .user = OCP_USER_MPU | OCP_USER_SDMA,
2553};
2554
2555/* l3_main_1 -> l4_per3 */
2556static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2557 .master = &dra7xx_l3_main_1_hwmod,
2558 .slave = &dra7xx_l4_per3_hwmod,
2559 .clk = "l3_iclk_div",
2560 .user = OCP_USER_MPU | OCP_USER_SDMA,
2561};
2562
2563/* l3_main_1 -> l4_wkup */
2564static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2565 .master = &dra7xx_l3_main_1_hwmod,
2566 .slave = &dra7xx_l4_wkup_hwmod,
2567 .clk = "wkupaon_iclk_mux",
2568 .user = OCP_USER_MPU | OCP_USER_SDMA,
2569};
2570
2571/* l4_per2 -> atl */
2572static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2573 .master = &dra7xx_l4_per2_hwmod,
2574 .slave = &dra7xx_atl_hwmod,
2575 .clk = "l3_iclk_div",
2576 .user = OCP_USER_MPU | OCP_USER_SDMA,
2577};
2578
2579/* l3_main_1 -> bb2d */
2580static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2581 .master = &dra7xx_l3_main_1_hwmod,
2582 .slave = &dra7xx_bb2d_hwmod,
2583 .clk = "l3_iclk_div",
2584 .user = OCP_USER_MPU | OCP_USER_SDMA,
2585};
2586
2587/* l4_wkup -> counter_32k */
2588static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2589 .master = &dra7xx_l4_wkup_hwmod,
2590 .slave = &dra7xx_counter_32k_hwmod,
2591 .clk = "wkupaon_iclk_mux",
2592 .user = OCP_USER_MPU | OCP_USER_SDMA,
2593};
2594
2595/* l4_wkup -> ctrl_module_wkup */
2596static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2597 .master = &dra7xx_l4_wkup_hwmod,
2598 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2599 .clk = "wkupaon_iclk_mux",
2600 .user = OCP_USER_MPU | OCP_USER_SDMA,
2601};
2602
2603static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2604 .master = &dra7xx_l4_per2_hwmod,
2605 .slave = &dra7xx_gmac_hwmod,
2606 .clk = "dpll_gmac_ck",
2607 .user = OCP_USER_MPU,
2608};
2609
2610static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2611 .master = &dra7xx_gmac_hwmod,
2612 .slave = &dra7xx_mdio_hwmod,
2613 .user = OCP_USER_MPU,
2614};
2615
2616/* l4_wkup -> dcan1 */
2617static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2618 .master = &dra7xx_l4_wkup_hwmod,
2619 .slave = &dra7xx_dcan1_hwmod,
2620 .clk = "wkupaon_iclk_mux",
2621 .user = OCP_USER_MPU | OCP_USER_SDMA,
2622};
2623
2624/* l4_per2 -> dcan2 */
2625static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2626 .master = &dra7xx_l4_per2_hwmod,
2627 .slave = &dra7xx_dcan2_hwmod,
2628 .clk = "l3_iclk_div",
2629 .user = OCP_USER_MPU | OCP_USER_SDMA,
2630};
2631
2632static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2633 {
2634 .pa_start = 0x4a056000,
2635 .pa_end = 0x4a056fff,
2636 .flags = ADDR_TYPE_RT
2637 },
2638 { }
2639};
2640
2641/* l4_cfg -> dma_system */
2642static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2643 .master = &dra7xx_l4_cfg_hwmod,
2644 .slave = &dra7xx_dma_system_hwmod,
2645 .clk = "l3_iclk_div",
2646 .addr = dra7xx_dma_system_addrs,
2647 .user = OCP_USER_MPU | OCP_USER_SDMA,
2648};
2649
2650/* l3_main_1 -> tpcc */
2651static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
2652 .master = &dra7xx_l3_main_1_hwmod,
2653 .slave = &dra7xx_tpcc_hwmod,
2654 .clk = "l3_iclk_div",
2655 .user = OCP_USER_MPU,
2656};
2657
2658/* l3_main_1 -> tptc0 */
2659static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
2660 .master = &dra7xx_l3_main_1_hwmod,
2661 .slave = &dra7xx_tptc0_hwmod,
2662 .clk = "l3_iclk_div",
2663 .user = OCP_USER_MPU,
2664};
2665
2666/* l3_main_1 -> tptc1 */
2667static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
2668 .master = &dra7xx_l3_main_1_hwmod,
2669 .slave = &dra7xx_tptc1_hwmod,
2670 .clk = "l3_iclk_div",
2671 .user = OCP_USER_MPU,
2672};
2673
2674static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2675 {
2676 .name = "family",
2677 .pa_start = 0x58000000,
2678 .pa_end = 0x5800007f,
2679 .flags = ADDR_TYPE_RT
2680 },
2681};
2682
2683/* l3_main_1 -> dss */
2684static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2685 .master = &dra7xx_l3_main_1_hwmod,
2686 .slave = &dra7xx_dss_hwmod,
2687 .clk = "l3_iclk_div",
2688 .addr = dra7xx_dss_addrs,
2689 .user = OCP_USER_MPU | OCP_USER_SDMA,
2690};
2691
2692static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2693 {
2694 .name = "dispc",
2695 .pa_start = 0x58001000,
2696 .pa_end = 0x58001fff,
2697 .flags = ADDR_TYPE_RT
2698 },
2699};
2700
2701/* l3_main_1 -> dispc */
2702static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2703 .master = &dra7xx_l3_main_1_hwmod,
2704 .slave = &dra7xx_dss_dispc_hwmod,
2705 .clk = "l3_iclk_div",
2706 .addr = dra7xx_dss_dispc_addrs,
2707 .user = OCP_USER_MPU | OCP_USER_SDMA,
2708};
2709
2710static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2711 {
2712 .name = "hdmi_wp",
2713 .pa_start = 0x58040000,
2714 .pa_end = 0x580400ff,
2715 .flags = ADDR_TYPE_RT
2716 },
2717 { }
2718};
2719
2720/* l3_main_1 -> dispc */
2721static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2722 .master = &dra7xx_l3_main_1_hwmod,
2723 .slave = &dra7xx_dss_hdmi_hwmod,
2724 .clk = "l3_iclk_div",
2725 .addr = dra7xx_dss_hdmi_addrs,
2726 .user = OCP_USER_MPU | OCP_USER_SDMA,
2727};
2728
2729/* l4_per2 -> mcasp3 */
2730static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
2731 .master = &dra7xx_l4_per2_hwmod,
2732 .slave = &dra7xx_mcasp3_hwmod,
2733 .clk = "l4_root_clk_div",
2734 .user = OCP_USER_MPU | OCP_USER_SDMA,
2735};
2736
2737/* l3_main_1 -> mcasp3 */
2738static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
2739 .master = &dra7xx_l3_main_1_hwmod,
2740 .slave = &dra7xx_mcasp3_hwmod,
2741 .clk = "l3_iclk_div",
2742 .user = OCP_USER_MPU | OCP_USER_SDMA,
2743};
2744
2745/* l4_per1 -> elm */
2746static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2747 .master = &dra7xx_l4_per1_hwmod,
2748 .slave = &dra7xx_elm_hwmod,
2749 .clk = "l3_iclk_div",
2750 .user = OCP_USER_MPU | OCP_USER_SDMA,
2751};
2752
2753/* l4_wkup -> gpio1 */
2754static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2755 .master = &dra7xx_l4_wkup_hwmod,
2756 .slave = &dra7xx_gpio1_hwmod,
2757 .clk = "wkupaon_iclk_mux",
2758 .user = OCP_USER_MPU | OCP_USER_SDMA,
2759};
2760
2761/* l4_per1 -> gpio2 */
2762static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2763 .master = &dra7xx_l4_per1_hwmod,
2764 .slave = &dra7xx_gpio2_hwmod,
2765 .clk = "l3_iclk_div",
2766 .user = OCP_USER_MPU | OCP_USER_SDMA,
2767};
2768
2769/* l4_per1 -> gpio3 */
2770static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2771 .master = &dra7xx_l4_per1_hwmod,
2772 .slave = &dra7xx_gpio3_hwmod,
2773 .clk = "l3_iclk_div",
2774 .user = OCP_USER_MPU | OCP_USER_SDMA,
2775};
2776
2777/* l4_per1 -> gpio4 */
2778static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2779 .master = &dra7xx_l4_per1_hwmod,
2780 .slave = &dra7xx_gpio4_hwmod,
2781 .clk = "l3_iclk_div",
2782 .user = OCP_USER_MPU | OCP_USER_SDMA,
2783};
2784
2785/* l4_per1 -> gpio5 */
2786static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2787 .master = &dra7xx_l4_per1_hwmod,
2788 .slave = &dra7xx_gpio5_hwmod,
2789 .clk = "l3_iclk_div",
2790 .user = OCP_USER_MPU | OCP_USER_SDMA,
2791};
2792
2793/* l4_per1 -> gpio6 */
2794static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2795 .master = &dra7xx_l4_per1_hwmod,
2796 .slave = &dra7xx_gpio6_hwmod,
2797 .clk = "l3_iclk_div",
2798 .user = OCP_USER_MPU | OCP_USER_SDMA,
2799};
2800
2801/* l4_per1 -> gpio7 */
2802static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2803 .master = &dra7xx_l4_per1_hwmod,
2804 .slave = &dra7xx_gpio7_hwmod,
2805 .clk = "l3_iclk_div",
2806 .user = OCP_USER_MPU | OCP_USER_SDMA,
2807};
2808
2809/* l4_per1 -> gpio8 */
2810static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2811 .master = &dra7xx_l4_per1_hwmod,
2812 .slave = &dra7xx_gpio8_hwmod,
2813 .clk = "l3_iclk_div",
2814 .user = OCP_USER_MPU | OCP_USER_SDMA,
2815};
2816
2817/* l3_main_1 -> gpmc */
2818static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2819 .master = &dra7xx_l3_main_1_hwmod,
2820 .slave = &dra7xx_gpmc_hwmod,
2821 .clk = "l3_iclk_div",
2822 .user = OCP_USER_MPU | OCP_USER_SDMA,
2823};
2824
2825static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2826 {
2827 .pa_start = 0x480b2000,
2828 .pa_end = 0x480b201f,
2829 .flags = ADDR_TYPE_RT
2830 },
2831 { }
2832};
2833
2834/* l4_per1 -> hdq1w */
2835static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2836 .master = &dra7xx_l4_per1_hwmod,
2837 .slave = &dra7xx_hdq1w_hwmod,
2838 .clk = "l3_iclk_div",
2839 .addr = dra7xx_hdq1w_addrs,
2840 .user = OCP_USER_MPU | OCP_USER_SDMA,
2841};
2842
2843/* l4_per1 -> i2c1 */
2844static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2845 .master = &dra7xx_l4_per1_hwmod,
2846 .slave = &dra7xx_i2c1_hwmod,
2847 .clk = "l3_iclk_div",
2848 .user = OCP_USER_MPU | OCP_USER_SDMA,
2849};
2850
2851/* l4_per1 -> i2c2 */
2852static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2853 .master = &dra7xx_l4_per1_hwmod,
2854 .slave = &dra7xx_i2c2_hwmod,
2855 .clk = "l3_iclk_div",
2856 .user = OCP_USER_MPU | OCP_USER_SDMA,
2857};
2858
2859/* l4_per1 -> i2c3 */
2860static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2861 .master = &dra7xx_l4_per1_hwmod,
2862 .slave = &dra7xx_i2c3_hwmod,
2863 .clk = "l3_iclk_div",
2864 .user = OCP_USER_MPU | OCP_USER_SDMA,
2865};
2866
2867/* l4_per1 -> i2c4 */
2868static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2869 .master = &dra7xx_l4_per1_hwmod,
2870 .slave = &dra7xx_i2c4_hwmod,
2871 .clk = "l3_iclk_div",
2872 .user = OCP_USER_MPU | OCP_USER_SDMA,
2873};
2874
2875/* l4_per1 -> i2c5 */
2876static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2877 .master = &dra7xx_l4_per1_hwmod,
2878 .slave = &dra7xx_i2c5_hwmod,
2879 .clk = "l3_iclk_div",
2880 .user = OCP_USER_MPU | OCP_USER_SDMA,
2881};
2882
2883/* l4_cfg -> mailbox1 */
2884static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2885 .master = &dra7xx_l4_cfg_hwmod,
2886 .slave = &dra7xx_mailbox1_hwmod,
2887 .clk = "l3_iclk_div",
2888 .user = OCP_USER_MPU | OCP_USER_SDMA,
2889};
2890
2891/* l4_per3 -> mailbox2 */
2892static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2893 .master = &dra7xx_l4_per3_hwmod,
2894 .slave = &dra7xx_mailbox2_hwmod,
2895 .clk = "l3_iclk_div",
2896 .user = OCP_USER_MPU | OCP_USER_SDMA,
2897};
2898
2899/* l4_per3 -> mailbox3 */
2900static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2901 .master = &dra7xx_l4_per3_hwmod,
2902 .slave = &dra7xx_mailbox3_hwmod,
2903 .clk = "l3_iclk_div",
2904 .user = OCP_USER_MPU | OCP_USER_SDMA,
2905};
2906
2907/* l4_per3 -> mailbox4 */
2908static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2909 .master = &dra7xx_l4_per3_hwmod,
2910 .slave = &dra7xx_mailbox4_hwmod,
2911 .clk = "l3_iclk_div",
2912 .user = OCP_USER_MPU | OCP_USER_SDMA,
2913};
2914
2915/* l4_per3 -> mailbox5 */
2916static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2917 .master = &dra7xx_l4_per3_hwmod,
2918 .slave = &dra7xx_mailbox5_hwmod,
2919 .clk = "l3_iclk_div",
2920 .user = OCP_USER_MPU | OCP_USER_SDMA,
2921};
2922
2923/* l4_per3 -> mailbox6 */
2924static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2925 .master = &dra7xx_l4_per3_hwmod,
2926 .slave = &dra7xx_mailbox6_hwmod,
2927 .clk = "l3_iclk_div",
2928 .user = OCP_USER_MPU | OCP_USER_SDMA,
2929};
2930
2931/* l4_per3 -> mailbox7 */
2932static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2933 .master = &dra7xx_l4_per3_hwmod,
2934 .slave = &dra7xx_mailbox7_hwmod,
2935 .clk = "l3_iclk_div",
2936 .user = OCP_USER_MPU | OCP_USER_SDMA,
2937};
2938
2939/* l4_per3 -> mailbox8 */
2940static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2941 .master = &dra7xx_l4_per3_hwmod,
2942 .slave = &dra7xx_mailbox8_hwmod,
2943 .clk = "l3_iclk_div",
2944 .user = OCP_USER_MPU | OCP_USER_SDMA,
2945};
2946
2947/* l4_per3 -> mailbox9 */
2948static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2949 .master = &dra7xx_l4_per3_hwmod,
2950 .slave = &dra7xx_mailbox9_hwmod,
2951 .clk = "l3_iclk_div",
2952 .user = OCP_USER_MPU | OCP_USER_SDMA,
2953};
2954
2955/* l4_per3 -> mailbox10 */
2956static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2957 .master = &dra7xx_l4_per3_hwmod,
2958 .slave = &dra7xx_mailbox10_hwmod,
2959 .clk = "l3_iclk_div",
2960 .user = OCP_USER_MPU | OCP_USER_SDMA,
2961};
2962
2963/* l4_per3 -> mailbox11 */
2964static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2965 .master = &dra7xx_l4_per3_hwmod,
2966 .slave = &dra7xx_mailbox11_hwmod,
2967 .clk = "l3_iclk_div",
2968 .user = OCP_USER_MPU | OCP_USER_SDMA,
2969};
2970
2971/* l4_per3 -> mailbox12 */
2972static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2973 .master = &dra7xx_l4_per3_hwmod,
2974 .slave = &dra7xx_mailbox12_hwmod,
2975 .clk = "l3_iclk_div",
2976 .user = OCP_USER_MPU | OCP_USER_SDMA,
2977};
2978
2979/* l4_per3 -> mailbox13 */
2980static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2981 .master = &dra7xx_l4_per3_hwmod,
2982 .slave = &dra7xx_mailbox13_hwmod,
2983 .clk = "l3_iclk_div",
2984 .user = OCP_USER_MPU | OCP_USER_SDMA,
2985};
2986
2987/* l4_per1 -> mcspi1 */
2988static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2989 .master = &dra7xx_l4_per1_hwmod,
2990 .slave = &dra7xx_mcspi1_hwmod,
2991 .clk = "l3_iclk_div",
2992 .user = OCP_USER_MPU | OCP_USER_SDMA,
2993};
2994
2995/* l4_per1 -> mcspi2 */
2996static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2997 .master = &dra7xx_l4_per1_hwmod,
2998 .slave = &dra7xx_mcspi2_hwmod,
2999 .clk = "l3_iclk_div",
3000 .user = OCP_USER_MPU | OCP_USER_SDMA,
3001};
3002
3003/* l4_per1 -> mcspi3 */
3004static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3005 .master = &dra7xx_l4_per1_hwmod,
3006 .slave = &dra7xx_mcspi3_hwmod,
3007 .clk = "l3_iclk_div",
3008 .user = OCP_USER_MPU | OCP_USER_SDMA,
3009};
3010
3011/* l4_per1 -> mcspi4 */
3012static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3013 .master = &dra7xx_l4_per1_hwmod,
3014 .slave = &dra7xx_mcspi4_hwmod,
3015 .clk = "l3_iclk_div",
3016 .user = OCP_USER_MPU | OCP_USER_SDMA,
3017};
3018
3019/* l4_per1 -> mmc1 */
3020static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3021 .master = &dra7xx_l4_per1_hwmod,
3022 .slave = &dra7xx_mmc1_hwmod,
3023 .clk = "l3_iclk_div",
3024 .user = OCP_USER_MPU | OCP_USER_SDMA,
3025};
3026
3027/* l4_per1 -> mmc2 */
3028static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3029 .master = &dra7xx_l4_per1_hwmod,
3030 .slave = &dra7xx_mmc2_hwmod,
3031 .clk = "l3_iclk_div",
3032 .user = OCP_USER_MPU | OCP_USER_SDMA,
3033};
3034
3035/* l4_per1 -> mmc3 */
3036static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3037 .master = &dra7xx_l4_per1_hwmod,
3038 .slave = &dra7xx_mmc3_hwmod,
3039 .clk = "l3_iclk_div",
3040 .user = OCP_USER_MPU | OCP_USER_SDMA,
3041};
3042
3043/* l4_per1 -> mmc4 */
3044static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3045 .master = &dra7xx_l4_per1_hwmod,
3046 .slave = &dra7xx_mmc4_hwmod,
3047 .clk = "l3_iclk_div",
3048 .user = OCP_USER_MPU | OCP_USER_SDMA,
3049};
3050
3051/* l4_cfg -> mpu */
3052static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3053 .master = &dra7xx_l4_cfg_hwmod,
3054 .slave = &dra7xx_mpu_hwmod,
3055 .clk = "l3_iclk_div",
3056 .user = OCP_USER_MPU | OCP_USER_SDMA,
3057};
3058
3059/* l4_cfg -> ocp2scp1 */
3060static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3061 .master = &dra7xx_l4_cfg_hwmod,
3062 .slave = &dra7xx_ocp2scp1_hwmod,
3063 .clk = "l4_root_clk_div",
3064 .user = OCP_USER_MPU | OCP_USER_SDMA,
3065};
3066
3067/* l4_cfg -> ocp2scp3 */
3068static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
3069 .master = &dra7xx_l4_cfg_hwmod,
3070 .slave = &dra7xx_ocp2scp3_hwmod,
3071 .clk = "l4_root_clk_div",
3072 .user = OCP_USER_MPU | OCP_USER_SDMA,
3073};
3074
3075/* l3_main_1 -> pciess1 */
3076static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
3077 .master = &dra7xx_l3_main_1_hwmod,
3078 .slave = &dra7xx_pciess1_hwmod,
3079 .clk = "l3_iclk_div",
3080 .user = OCP_USER_MPU | OCP_USER_SDMA,
3081};
3082
3083/* l4_cfg -> pciess1 */
3084static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
3085 .master = &dra7xx_l4_cfg_hwmod,
3086 .slave = &dra7xx_pciess1_hwmod,
3087 .clk = "l4_root_clk_div",
3088 .user = OCP_USER_MPU | OCP_USER_SDMA,
3089};
3090
3091/* l3_main_1 -> pciess2 */
3092static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
3093 .master = &dra7xx_l3_main_1_hwmod,
3094 .slave = &dra7xx_pciess2_hwmod,
3095 .clk = "l3_iclk_div",
3096 .user = OCP_USER_MPU | OCP_USER_SDMA,
3097};
3098
3099/* l4_cfg -> pciess2 */
3100static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
3101 .master = &dra7xx_l4_cfg_hwmod,
3102 .slave = &dra7xx_pciess2_hwmod,
3103 .clk = "l4_root_clk_div",
3104 .user = OCP_USER_MPU | OCP_USER_SDMA,
3105};
3106
3107static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
3108 {
3109 .pa_start = 0x4b300000,
3110 .pa_end = 0x4b30007f,
3111 .flags = ADDR_TYPE_RT
3112 },
3113 { }
3114};
3115
3116/* l3_main_1 -> qspi */
3117static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3118 .master = &dra7xx_l3_main_1_hwmod,
3119 .slave = &dra7xx_qspi_hwmod,
3120 .clk = "l3_iclk_div",
3121 .addr = dra7xx_qspi_addrs,
3122 .user = OCP_USER_MPU | OCP_USER_SDMA,
3123};
3124
3125/* l4_per3 -> rtcss */
3126static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3127 .master = &dra7xx_l4_per3_hwmod,
3128 .slave = &dra7xx_rtcss_hwmod,
3129 .clk = "l4_root_clk_div",
3130 .user = OCP_USER_MPU | OCP_USER_SDMA,
3131};
3132
3133static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
3134 {
3135 .name = "sysc",
3136 .pa_start = 0x4a141100,
3137 .pa_end = 0x4a141107,
3138 .flags = ADDR_TYPE_RT
3139 },
3140 { }
3141};
3142
3143/* l4_cfg -> sata */
3144static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3145 .master = &dra7xx_l4_cfg_hwmod,
3146 .slave = &dra7xx_sata_hwmod,
3147 .clk = "l3_iclk_div",
3148 .addr = dra7xx_sata_addrs,
3149 .user = OCP_USER_MPU | OCP_USER_SDMA,
3150};
3151
3152static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
3153 {
3154 .pa_start = 0x4a0dd000,
3155 .pa_end = 0x4a0dd07f,
3156 .flags = ADDR_TYPE_RT
3157 },
3158 { }
3159};
3160
3161/* l4_cfg -> smartreflex_core */
3162static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3163 .master = &dra7xx_l4_cfg_hwmod,
3164 .slave = &dra7xx_smartreflex_core_hwmod,
3165 .clk = "l4_root_clk_div",
3166 .addr = dra7xx_smartreflex_core_addrs,
3167 .user = OCP_USER_MPU | OCP_USER_SDMA,
3168};
3169
3170static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
3171 {
3172 .pa_start = 0x4a0d9000,
3173 .pa_end = 0x4a0d907f,
3174 .flags = ADDR_TYPE_RT
3175 },
3176 { }
3177};
3178
3179/* l4_cfg -> smartreflex_mpu */
3180static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3181 .master = &dra7xx_l4_cfg_hwmod,
3182 .slave = &dra7xx_smartreflex_mpu_hwmod,
3183 .clk = "l4_root_clk_div",
3184 .addr = dra7xx_smartreflex_mpu_addrs,
3185 .user = OCP_USER_MPU | OCP_USER_SDMA,
3186};
3187
3188/* l4_cfg -> spinlock */
3189static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3190 .master = &dra7xx_l4_cfg_hwmod,
3191 .slave = &dra7xx_spinlock_hwmod,
3192 .clk = "l3_iclk_div",
3193 .user = OCP_USER_MPU | OCP_USER_SDMA,
3194};
3195
3196/* l4_wkup -> timer1 */
3197static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3198 .master = &dra7xx_l4_wkup_hwmod,
3199 .slave = &dra7xx_timer1_hwmod,
3200 .clk = "wkupaon_iclk_mux",
3201 .user = OCP_USER_MPU | OCP_USER_SDMA,
3202};
3203
3204/* l4_per1 -> timer2 */
3205static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3206 .master = &dra7xx_l4_per1_hwmod,
3207 .slave = &dra7xx_timer2_hwmod,
3208 .clk = "l3_iclk_div",
3209 .user = OCP_USER_MPU | OCP_USER_SDMA,
3210};
3211
3212/* l4_per1 -> timer3 */
3213static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3214 .master = &dra7xx_l4_per1_hwmod,
3215 .slave = &dra7xx_timer3_hwmod,
3216 .clk = "l3_iclk_div",
3217 .user = OCP_USER_MPU | OCP_USER_SDMA,
3218};
3219
3220/* l4_per1 -> timer4 */
3221static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3222 .master = &dra7xx_l4_per1_hwmod,
3223 .slave = &dra7xx_timer4_hwmod,
3224 .clk = "l3_iclk_div",
3225 .user = OCP_USER_MPU | OCP_USER_SDMA,
3226};
3227
3228/* l4_per3 -> timer5 */
3229static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3230 .master = &dra7xx_l4_per3_hwmod,
3231 .slave = &dra7xx_timer5_hwmod,
3232 .clk = "l3_iclk_div",
3233 .user = OCP_USER_MPU | OCP_USER_SDMA,
3234};
3235
3236/* l4_per3 -> timer6 */
3237static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3238 .master = &dra7xx_l4_per3_hwmod,
3239 .slave = &dra7xx_timer6_hwmod,
3240 .clk = "l3_iclk_div",
3241 .user = OCP_USER_MPU | OCP_USER_SDMA,
3242};
3243
3244/* l4_per3 -> timer7 */
3245static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3246 .master = &dra7xx_l4_per3_hwmod,
3247 .slave = &dra7xx_timer7_hwmod,
3248 .clk = "l3_iclk_div",
3249 .user = OCP_USER_MPU | OCP_USER_SDMA,
3250};
3251
3252/* l4_per3 -> timer8 */
3253static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3254 .master = &dra7xx_l4_per3_hwmod,
3255 .slave = &dra7xx_timer8_hwmod,
3256 .clk = "l3_iclk_div",
3257 .user = OCP_USER_MPU | OCP_USER_SDMA,
3258};
3259
3260/* l4_per1 -> timer9 */
3261static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3262 .master = &dra7xx_l4_per1_hwmod,
3263 .slave = &dra7xx_timer9_hwmod,
3264 .clk = "l3_iclk_div",
3265 .user = OCP_USER_MPU | OCP_USER_SDMA,
3266};
3267
3268/* l4_per1 -> timer10 */
3269static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3270 .master = &dra7xx_l4_per1_hwmod,
3271 .slave = &dra7xx_timer10_hwmod,
3272 .clk = "l3_iclk_div",
3273 .user = OCP_USER_MPU | OCP_USER_SDMA,
3274};
3275
3276/* l4_per1 -> timer11 */
3277static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3278 .master = &dra7xx_l4_per1_hwmod,
3279 .slave = &dra7xx_timer11_hwmod,
3280 .clk = "l3_iclk_div",
3281 .user = OCP_USER_MPU | OCP_USER_SDMA,
3282};
3283
3284/* l4_per3 -> timer13 */
3285static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3286 .master = &dra7xx_l4_per3_hwmod,
3287 .slave = &dra7xx_timer13_hwmod,
3288 .clk = "l3_iclk_div",
3289 .user = OCP_USER_MPU | OCP_USER_SDMA,
3290};
3291
3292/* l4_per3 -> timer14 */
3293static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3294 .master = &dra7xx_l4_per3_hwmod,
3295 .slave = &dra7xx_timer14_hwmod,
3296 .clk = "l3_iclk_div",
3297 .user = OCP_USER_MPU | OCP_USER_SDMA,
3298};
3299
3300/* l4_per3 -> timer15 */
3301static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3302 .master = &dra7xx_l4_per3_hwmod,
3303 .slave = &dra7xx_timer15_hwmod,
3304 .clk = "l3_iclk_div",
3305 .user = OCP_USER_MPU | OCP_USER_SDMA,
3306};
3307
3308/* l4_per3 -> timer16 */
3309static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3310 .master = &dra7xx_l4_per3_hwmod,
3311 .slave = &dra7xx_timer16_hwmod,
3312 .clk = "l3_iclk_div",
3313 .user = OCP_USER_MPU | OCP_USER_SDMA,
3314};
3315
3316/* l4_per1 -> uart1 */
3317static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3318 .master = &dra7xx_l4_per1_hwmod,
3319 .slave = &dra7xx_uart1_hwmod,
3320 .clk = "l3_iclk_div",
3321 .user = OCP_USER_MPU | OCP_USER_SDMA,
3322};
3323
3324/* l4_per1 -> uart2 */
3325static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3326 .master = &dra7xx_l4_per1_hwmod,
3327 .slave = &dra7xx_uart2_hwmod,
3328 .clk = "l3_iclk_div",
3329 .user = OCP_USER_MPU | OCP_USER_SDMA,
3330};
3331
3332/* l4_per1 -> uart3 */
3333static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3334 .master = &dra7xx_l4_per1_hwmod,
3335 .slave = &dra7xx_uart3_hwmod,
3336 .clk = "l3_iclk_div",
3337 .user = OCP_USER_MPU | OCP_USER_SDMA,
3338};
3339
3340/* l4_per1 -> uart4 */
3341static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3342 .master = &dra7xx_l4_per1_hwmod,
3343 .slave = &dra7xx_uart4_hwmod,
3344 .clk = "l3_iclk_div",
3345 .user = OCP_USER_MPU | OCP_USER_SDMA,
3346};
3347
3348/* l4_per1 -> uart5 */
3349static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3350 .master = &dra7xx_l4_per1_hwmod,
3351 .slave = &dra7xx_uart5_hwmod,
3352 .clk = "l3_iclk_div",
3353 .user = OCP_USER_MPU | OCP_USER_SDMA,
3354};
3355
3356/* l4_per1 -> uart6 */
3357static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3358 .master = &dra7xx_l4_per1_hwmod,
3359 .slave = &dra7xx_uart6_hwmod,
3360 .clk = "l3_iclk_div",
3361 .user = OCP_USER_MPU | OCP_USER_SDMA,
3362};
3363
3364/* l4_per2 -> uart7 */
3365static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3366 .master = &dra7xx_l4_per2_hwmod,
3367 .slave = &dra7xx_uart7_hwmod,
3368 .clk = "l3_iclk_div",
3369 .user = OCP_USER_MPU | OCP_USER_SDMA,
3370};
3371
3372/* l4_per2 -> uart8 */
3373static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3374 .master = &dra7xx_l4_per2_hwmod,
3375 .slave = &dra7xx_uart8_hwmod,
3376 .clk = "l3_iclk_div",
3377 .user = OCP_USER_MPU | OCP_USER_SDMA,
3378};
3379
3380/* l4_per2 -> uart9 */
3381static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3382 .master = &dra7xx_l4_per2_hwmod,
3383 .slave = &dra7xx_uart9_hwmod,
3384 .clk = "l3_iclk_div",
3385 .user = OCP_USER_MPU | OCP_USER_SDMA,
3386};
3387
3388/* l4_wkup -> uart10 */
3389static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3390 .master = &dra7xx_l4_wkup_hwmod,
3391 .slave = &dra7xx_uart10_hwmod,
3392 .clk = "wkupaon_iclk_mux",
3393 .user = OCP_USER_MPU | OCP_USER_SDMA,
3394};
3395
3396/* l4_per3 -> usb_otg_ss1 */
3397static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3398 .master = &dra7xx_l4_per3_hwmod,
3399 .slave = &dra7xx_usb_otg_ss1_hwmod,
3400 .clk = "dpll_core_h13x2_ck",
3401 .user = OCP_USER_MPU | OCP_USER_SDMA,
3402};
3403
3404/* l4_per3 -> usb_otg_ss2 */
3405static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3406 .master = &dra7xx_l4_per3_hwmod,
3407 .slave = &dra7xx_usb_otg_ss2_hwmod,
3408 .clk = "dpll_core_h13x2_ck",
3409 .user = OCP_USER_MPU | OCP_USER_SDMA,
3410};
3411
3412/* l4_per3 -> usb_otg_ss3 */
3413static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3414 .master = &dra7xx_l4_per3_hwmod,
3415 .slave = &dra7xx_usb_otg_ss3_hwmod,
3416 .clk = "dpll_core_h13x2_ck",
3417 .user = OCP_USER_MPU | OCP_USER_SDMA,
3418};
3419
3420/* l4_per3 -> usb_otg_ss4 */
3421static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3422 .master = &dra7xx_l4_per3_hwmod,
3423 .slave = &dra7xx_usb_otg_ss4_hwmod,
3424 .clk = "dpll_core_h13x2_ck",
3425 .user = OCP_USER_MPU | OCP_USER_SDMA,
3426};
3427
3428/* l3_main_1 -> vcp1 */
3429static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3430 .master = &dra7xx_l3_main_1_hwmod,
3431 .slave = &dra7xx_vcp1_hwmod,
3432 .clk = "l3_iclk_div",
3433 .user = OCP_USER_MPU | OCP_USER_SDMA,
3434};
3435
3436/* l4_per2 -> vcp1 */
3437static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3438 .master = &dra7xx_l4_per2_hwmod,
3439 .slave = &dra7xx_vcp1_hwmod,
3440 .clk = "l3_iclk_div",
3441 .user = OCP_USER_MPU | OCP_USER_SDMA,
3442};
3443
3444/* l3_main_1 -> vcp2 */
3445static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3446 .master = &dra7xx_l3_main_1_hwmod,
3447 .slave = &dra7xx_vcp2_hwmod,
3448 .clk = "l3_iclk_div",
3449 .user = OCP_USER_MPU | OCP_USER_SDMA,
3450};
3451
3452/* l4_per2 -> vcp2 */
3453static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3454 .master = &dra7xx_l4_per2_hwmod,
3455 .slave = &dra7xx_vcp2_hwmod,
3456 .clk = "l3_iclk_div",
3457 .user = OCP_USER_MPU | OCP_USER_SDMA,
3458};
3459
3460/* l4_wkup -> wd_timer2 */
3461static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3462 .master = &dra7xx_l4_wkup_hwmod,
3463 .slave = &dra7xx_wd_timer2_hwmod,
3464 .clk = "wkupaon_iclk_mux",
3465 .user = OCP_USER_MPU | OCP_USER_SDMA,
3466};
3467
3468static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3469 &dra7xx_l3_main_1__dmm,
3470 &dra7xx_l3_main_2__l3_instr,
3471 &dra7xx_l4_cfg__l3_main_1,
3472 &dra7xx_mpu__l3_main_1,
3473 &dra7xx_l3_main_1__l3_main_2,
3474 &dra7xx_l4_cfg__l3_main_2,
3475 &dra7xx_l3_main_1__l4_cfg,
3476 &dra7xx_l3_main_1__l4_per1,
3477 &dra7xx_l3_main_1__l4_per2,
3478 &dra7xx_l3_main_1__l4_per3,
3479 &dra7xx_l3_main_1__l4_wkup,
3480 &dra7xx_l4_per2__atl,
3481 &dra7xx_l3_main_1__bb2d,
3482 &dra7xx_l4_wkup__counter_32k,
3483 &dra7xx_l4_wkup__ctrl_module_wkup,
3484 &dra7xx_l4_wkup__dcan1,
3485 &dra7xx_l4_per2__dcan2,
3486 &dra7xx_l4_per2__cpgmac0,
3487 &dra7xx_l4_per2__mcasp3,
3488 &dra7xx_l3_main_1__mcasp3,
3489 &dra7xx_gmac__mdio,
3490 &dra7xx_l4_cfg__dma_system,
3491 &dra7xx_l3_main_1__tpcc,
3492 &dra7xx_l3_main_1__tptc0,
3493 &dra7xx_l3_main_1__tptc1,
3494 &dra7xx_l3_main_1__dss,
3495 &dra7xx_l3_main_1__dispc,
3496 &dra7xx_l3_main_1__hdmi,
3497 &dra7xx_l4_per1__elm,
3498 &dra7xx_l4_wkup__gpio1,
3499 &dra7xx_l4_per1__gpio2,
3500 &dra7xx_l4_per1__gpio3,
3501 &dra7xx_l4_per1__gpio4,
3502 &dra7xx_l4_per1__gpio5,
3503 &dra7xx_l4_per1__gpio6,
3504 &dra7xx_l4_per1__gpio7,
3505 &dra7xx_l4_per1__gpio8,
3506 &dra7xx_l3_main_1__gpmc,
3507 &dra7xx_l4_per1__hdq1w,
3508 &dra7xx_l4_per1__i2c1,
3509 &dra7xx_l4_per1__i2c2,
3510 &dra7xx_l4_per1__i2c3,
3511 &dra7xx_l4_per1__i2c4,
3512 &dra7xx_l4_per1__i2c5,
3513 &dra7xx_l4_cfg__mailbox1,
3514 &dra7xx_l4_per3__mailbox2,
3515 &dra7xx_l4_per3__mailbox3,
3516 &dra7xx_l4_per3__mailbox4,
3517 &dra7xx_l4_per3__mailbox5,
3518 &dra7xx_l4_per3__mailbox6,
3519 &dra7xx_l4_per3__mailbox7,
3520 &dra7xx_l4_per3__mailbox8,
3521 &dra7xx_l4_per3__mailbox9,
3522 &dra7xx_l4_per3__mailbox10,
3523 &dra7xx_l4_per3__mailbox11,
3524 &dra7xx_l4_per3__mailbox12,
3525 &dra7xx_l4_per3__mailbox13,
3526 &dra7xx_l4_per1__mcspi1,
3527 &dra7xx_l4_per1__mcspi2,
3528 &dra7xx_l4_per1__mcspi3,
3529 &dra7xx_l4_per1__mcspi4,
3530 &dra7xx_l4_per1__mmc1,
3531 &dra7xx_l4_per1__mmc2,
3532 &dra7xx_l4_per1__mmc3,
3533 &dra7xx_l4_per1__mmc4,
3534 &dra7xx_l4_cfg__mpu,
3535 &dra7xx_l4_cfg__ocp2scp1,
3536 &dra7xx_l4_cfg__ocp2scp3,
3537 &dra7xx_l3_main_1__pciess1,
3538 &dra7xx_l4_cfg__pciess1,
3539 &dra7xx_l3_main_1__pciess2,
3540 &dra7xx_l4_cfg__pciess2,
3541 &dra7xx_l3_main_1__qspi,
3542 &dra7xx_l4_per3__rtcss,
3543 &dra7xx_l4_cfg__sata,
3544 &dra7xx_l4_cfg__smartreflex_core,
3545 &dra7xx_l4_cfg__smartreflex_mpu,
3546 &dra7xx_l4_cfg__spinlock,
3547 &dra7xx_l4_wkup__timer1,
3548 &dra7xx_l4_per1__timer2,
3549 &dra7xx_l4_per1__timer3,
3550 &dra7xx_l4_per1__timer4,
3551 &dra7xx_l4_per3__timer5,
3552 &dra7xx_l4_per3__timer6,
3553 &dra7xx_l4_per3__timer7,
3554 &dra7xx_l4_per3__timer8,
3555 &dra7xx_l4_per1__timer9,
3556 &dra7xx_l4_per1__timer10,
3557 &dra7xx_l4_per1__timer11,
3558 &dra7xx_l4_per3__timer13,
3559 &dra7xx_l4_per3__timer14,
3560 &dra7xx_l4_per3__timer15,
3561 &dra7xx_l4_per3__timer16,
3562 &dra7xx_l4_per1__uart1,
3563 &dra7xx_l4_per1__uart2,
3564 &dra7xx_l4_per1__uart3,
3565 &dra7xx_l4_per1__uart4,
3566 &dra7xx_l4_per1__uart5,
3567 &dra7xx_l4_per1__uart6,
3568 &dra7xx_l4_per2__uart7,
3569 &dra7xx_l4_per2__uart8,
3570 &dra7xx_l4_per2__uart9,
3571 &dra7xx_l4_wkup__uart10,
3572 &dra7xx_l4_per3__usb_otg_ss1,
3573 &dra7xx_l4_per3__usb_otg_ss2,
3574 &dra7xx_l4_per3__usb_otg_ss3,
3575 &dra7xx_l3_main_1__vcp1,
3576 &dra7xx_l4_per2__vcp1,
3577 &dra7xx_l3_main_1__vcp2,
3578 &dra7xx_l4_per2__vcp2,
3579 &dra7xx_l4_wkup__wd_timer2,
3580 NULL,
3581};
3582
3583static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3584 &dra7xx_l4_per3__usb_otg_ss4,
3585 NULL,
3586};
3587
3588static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3589 NULL,
3590};
3591
3592int __init dra7xx_hwmod_init(void)
3593{
3594 int ret;
3595
3596 omap_hwmod_init();
3597 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3598
3599 if (!ret && soc_is_dra74x())
3600 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3601 else if (!ret && soc_is_dra72x())
3602 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3603
3604 return ret;
3605}