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1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated
3 *
4 * Hwmod present only in AM43x and those that differ other than register
5 * offsets as compared to AM335x.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/platform_data/gpio-omap.h>
18#include <linux/platform_data/spi-omap2-mcspi.h>
19#include "omap_hwmod.h"
20#include "omap_hwmod_33xx_43xx_common_data.h"
21#include "prcm43xx.h"
22
23/* IP blocks */
24static struct omap_hwmod am43xx_l4_hs_hwmod = {
25 .name = "l4_hs",
26 .class = &am33xx_l4_hwmod_class,
27 .clkdm_name = "l3_clkdm",
28 .flags = HWMOD_INIT_NO_IDLE,
29 .main_clk = "l4hs_gclk",
30 .prcm = {
31 .omap4 = {
32 .clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
33 .modulemode = MODULEMODE_SWCTRL,
34 },
35 },
36};
37
38static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
39 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
40};
41
42static struct omap_hwmod am43xx_wkup_m3_hwmod = {
43 .name = "wkup_m3",
44 .class = &am33xx_wkup_m3_hwmod_class,
45 .clkdm_name = "l4_wkup_aon_clkdm",
46 /* Keep hardreset asserted */
47 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
48 .main_clk = "sys_clkin_ck",
49 .prcm = {
50 .omap4 = {
51 .clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
52 .rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
53 .rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET,
54 .modulemode = MODULEMODE_SWCTRL,
55 },
56 },
57 .rst_lines = am33xx_wkup_m3_resets,
58 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
59};
60
61static struct omap_hwmod am43xx_control_hwmod = {
62 .name = "control",
63 .class = &am33xx_control_hwmod_class,
64 .clkdm_name = "l4_wkup_clkdm",
65 .flags = HWMOD_INIT_NO_IDLE,
66 .main_clk = "sys_clkin_ck",
67 .prcm = {
68 .omap4 = {
69 .clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
70 .modulemode = MODULEMODE_SWCTRL,
71 },
72 },
73};
74
75static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
76 { .role = "dbclk", .clk = "gpio0_dbclk" },
77};
78
79static struct omap_hwmod am43xx_gpio0_hwmod = {
80 .name = "gpio1",
81 .class = &am33xx_gpio_hwmod_class,
82 .clkdm_name = "l4_wkup_clkdm",
83 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
84 .main_clk = "sys_clkin_ck",
85 .prcm = {
86 .omap4 = {
87 .clkctrl_offs = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
88 .modulemode = MODULEMODE_SWCTRL,
89 },
90 },
91 .opt_clks = gpio0_opt_clks,
92 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
93 .dev_attr = &gpio_dev_attr,
94};
95
96static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
97 .rev_offs = 0x0,
98 .sysc_offs = 0x4,
99 .sysc_flags = SYSC_HAS_SIDLEMODE,
100 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
101 .sysc_fields = &omap_hwmod_sysc_type1,
102};
103
104static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
105 .name = "synctimer",
106 .sysc = &am43xx_synctimer_sysc,
107};
108
109static struct omap_hwmod am43xx_synctimer_hwmod = {
110 .name = "counter_32k",
111 .class = &am43xx_synctimer_hwmod_class,
112 .clkdm_name = "l4_wkup_aon_clkdm",
113 .flags = HWMOD_SWSUP_SIDLE,
114 .main_clk = "synctimer_32kclk",
115 .prcm = {
116 .omap4 = {
117 .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
118 .modulemode = MODULEMODE_SWCTRL,
119 },
120 },
121};
122
123static struct omap_hwmod am43xx_timer8_hwmod = {
124 .name = "timer8",
125 .class = &am33xx_timer_hwmod_class,
126 .clkdm_name = "l4ls_clkdm",
127 .main_clk = "timer8_fck",
128 .prcm = {
129 .omap4 = {
130 .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
131 .modulemode = MODULEMODE_SWCTRL,
132 },
133 },
134};
135
136static struct omap_hwmod am43xx_timer9_hwmod = {
137 .name = "timer9",
138 .class = &am33xx_timer_hwmod_class,
139 .clkdm_name = "l4ls_clkdm",
140 .main_clk = "timer9_fck",
141 .prcm = {
142 .omap4 = {
143 .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
144 .modulemode = MODULEMODE_SWCTRL,
145 },
146 },
147};
148
149static struct omap_hwmod am43xx_timer10_hwmod = {
150 .name = "timer10",
151 .class = &am33xx_timer_hwmod_class,
152 .clkdm_name = "l4ls_clkdm",
153 .main_clk = "timer10_fck",
154 .prcm = {
155 .omap4 = {
156 .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
157 .modulemode = MODULEMODE_SWCTRL,
158 },
159 },
160};
161
162static struct omap_hwmod am43xx_timer11_hwmod = {
163 .name = "timer11",
164 .class = &am33xx_timer_hwmod_class,
165 .clkdm_name = "l4ls_clkdm",
166 .main_clk = "timer11_fck",
167 .prcm = {
168 .omap4 = {
169 .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
170 .modulemode = MODULEMODE_SWCTRL,
171 },
172 },
173};
174
175static struct omap_hwmod am43xx_epwmss3_hwmod = {
176 .name = "epwmss3",
177 .class = &am33xx_epwmss_hwmod_class,
178 .clkdm_name = "l4ls_clkdm",
179 .main_clk = "l4ls_gclk",
180 .prcm = {
181 .omap4 = {
182 .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
183 .modulemode = MODULEMODE_SWCTRL,
184 },
185 },
186};
187
188static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
189 .name = "ehrpwm3",
190 .class = &am33xx_ehrpwm_hwmod_class,
191 .clkdm_name = "l4ls_clkdm",
192 .main_clk = "l4ls_gclk",
193};
194
195static struct omap_hwmod am43xx_epwmss4_hwmod = {
196 .name = "epwmss4",
197 .class = &am33xx_epwmss_hwmod_class,
198 .clkdm_name = "l4ls_clkdm",
199 .main_clk = "l4ls_gclk",
200 .prcm = {
201 .omap4 = {
202 .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
203 .modulemode = MODULEMODE_SWCTRL,
204 },
205 },
206};
207
208static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
209 .name = "ehrpwm4",
210 .class = &am33xx_ehrpwm_hwmod_class,
211 .clkdm_name = "l4ls_clkdm",
212 .main_clk = "l4ls_gclk",
213};
214
215static struct omap_hwmod am43xx_epwmss5_hwmod = {
216 .name = "epwmss5",
217 .class = &am33xx_epwmss_hwmod_class,
218 .clkdm_name = "l4ls_clkdm",
219 .main_clk = "l4ls_gclk",
220 .prcm = {
221 .omap4 = {
222 .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
223 .modulemode = MODULEMODE_SWCTRL,
224 },
225 },
226};
227
228static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
229 .name = "ehrpwm5",
230 .class = &am33xx_ehrpwm_hwmod_class,
231 .clkdm_name = "l4ls_clkdm",
232 .main_clk = "l4ls_gclk",
233};
234
235static struct omap_hwmod am43xx_spi2_hwmod = {
236 .name = "spi2",
237 .class = &am33xx_spi_hwmod_class,
238 .clkdm_name = "l4ls_clkdm",
239 .main_clk = "dpll_per_m2_div4_ck",
240 .prcm = {
241 .omap4 = {
242 .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
243 .modulemode = MODULEMODE_SWCTRL,
244 },
245 },
246 .dev_attr = &mcspi_attrib,
247};
248
249static struct omap_hwmod am43xx_spi3_hwmod = {
250 .name = "spi3",
251 .class = &am33xx_spi_hwmod_class,
252 .clkdm_name = "l4ls_clkdm",
253 .main_clk = "dpll_per_m2_div4_ck",
254 .prcm = {
255 .omap4 = {
256 .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
257 .modulemode = MODULEMODE_SWCTRL,
258 },
259 },
260 .dev_attr = &mcspi_attrib,
261};
262
263static struct omap_hwmod am43xx_spi4_hwmod = {
264 .name = "spi4",
265 .class = &am33xx_spi_hwmod_class,
266 .clkdm_name = "l4ls_clkdm",
267 .main_clk = "dpll_per_m2_div4_ck",
268 .prcm = {
269 .omap4 = {
270 .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
271 .modulemode = MODULEMODE_SWCTRL,
272 },
273 },
274 .dev_attr = &mcspi_attrib,
275};
276
277static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
278 { .role = "dbclk", .clk = "gpio4_dbclk" },
279};
280
281static struct omap_hwmod am43xx_gpio4_hwmod = {
282 .name = "gpio5",
283 .class = &am33xx_gpio_hwmod_class,
284 .clkdm_name = "l4ls_clkdm",
285 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
286 .main_clk = "l4ls_gclk",
287 .prcm = {
288 .omap4 = {
289 .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
290 .modulemode = MODULEMODE_SWCTRL,
291 },
292 },
293 .opt_clks = gpio4_opt_clks,
294 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
295 .dev_attr = &gpio_dev_attr,
296};
297
298static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
299 { .role = "dbclk", .clk = "gpio5_dbclk" },
300};
301
302static struct omap_hwmod am43xx_gpio5_hwmod = {
303 .name = "gpio6",
304 .class = &am33xx_gpio_hwmod_class,
305 .clkdm_name = "l4ls_clkdm",
306 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
307 .main_clk = "l4ls_gclk",
308 .prcm = {
309 .omap4 = {
310 .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
311 .modulemode = MODULEMODE_SWCTRL,
312 },
313 },
314 .opt_clks = gpio5_opt_clks,
315 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
316 .dev_attr = &gpio_dev_attr,
317};
318
319static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
320 .name = "ocp2scp",
321};
322
323static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
324 .name = "ocp2scp0",
325 .class = &am43xx_ocp2scp_hwmod_class,
326 .clkdm_name = "l4ls_clkdm",
327 .main_clk = "l4ls_gclk",
328 .prcm = {
329 .omap4 = {
330 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
331 .modulemode = MODULEMODE_SWCTRL,
332 },
333 },
334};
335
336static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
337 .name = "ocp2scp1",
338 .class = &am43xx_ocp2scp_hwmod_class,
339 .clkdm_name = "l4ls_clkdm",
340 .main_clk = "l4ls_gclk",
341 .prcm = {
342 .omap4 = {
343 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
344 .modulemode = MODULEMODE_SWCTRL,
345 },
346 },
347};
348
349static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
350 .rev_offs = 0x0000,
351 .sysc_offs = 0x0010,
352 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
353 SYSC_HAS_SIDLEMODE),
354 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
355 SIDLE_SMART_WKUP | MSTANDBY_FORCE |
356 MSTANDBY_NO | MSTANDBY_SMART |
357 MSTANDBY_SMART_WKUP),
358 .sysc_fields = &omap_hwmod_sysc_type2,
359};
360
361static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
362 .name = "usb_otg_ss",
363 .sysc = &am43xx_usb_otg_ss_sysc,
364};
365
366static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
367 .name = "usb_otg_ss0",
368 .class = &am43xx_usb_otg_ss_hwmod_class,
369 .clkdm_name = "l3s_clkdm",
370 .main_clk = "l3s_gclk",
371 .prcm = {
372 .omap4 = {
373 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
374 .modulemode = MODULEMODE_SWCTRL,
375 },
376 },
377};
378
379static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
380 .name = "usb_otg_ss1",
381 .class = &am43xx_usb_otg_ss_hwmod_class,
382 .clkdm_name = "l3s_clkdm",
383 .main_clk = "l3s_gclk",
384 .prcm = {
385 .omap4 = {
386 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
387 .modulemode = MODULEMODE_SWCTRL,
388 },
389 },
390};
391
392static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
393 .sysc_offs = 0x0010,
394 .sysc_flags = SYSC_HAS_SIDLEMODE,
395 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
396 SIDLE_SMART_WKUP),
397 .sysc_fields = &omap_hwmod_sysc_type2,
398};
399
400static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
401 .name = "qspi",
402 .sysc = &am43xx_qspi_sysc,
403};
404
405static struct omap_hwmod am43xx_qspi_hwmod = {
406 .name = "qspi",
407 .class = &am43xx_qspi_hwmod_class,
408 .clkdm_name = "l3s_clkdm",
409 .main_clk = "l3s_gclk",
410 .prcm = {
411 .omap4 = {
412 .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
413 .modulemode = MODULEMODE_SWCTRL,
414 },
415 },
416};
417
418/* Interfaces */
419static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
420 .master = &am33xx_l3_main_hwmod,
421 .slave = &am43xx_l4_hs_hwmod,
422 .clk = "l3s_gclk",
423 .user = OCP_USER_MPU | OCP_USER_SDMA,
424};
425
426static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
427 .master = &am43xx_wkup_m3_hwmod,
428 .slave = &am33xx_l4_wkup_hwmod,
429 .clk = "sys_clkin_ck",
430 .user = OCP_USER_MPU | OCP_USER_SDMA,
431};
432
433static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
434 .master = &am33xx_l4_wkup_hwmod,
435 .slave = &am43xx_wkup_m3_hwmod,
436 .clk = "sys_clkin_ck",
437 .user = OCP_USER_MPU | OCP_USER_SDMA,
438};
439
440static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
441 .master = &am33xx_l3_main_hwmod,
442 .slave = &am33xx_pruss_hwmod,
443 .clk = "dpll_core_m4_ck",
444 .user = OCP_USER_MPU,
445};
446
447static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
448 .master = &am33xx_l4_wkup_hwmod,
449 .slave = &am33xx_smartreflex0_hwmod,
450 .clk = "sys_clkin_ck",
451 .user = OCP_USER_MPU,
452};
453
454static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
455 .master = &am33xx_l4_wkup_hwmod,
456 .slave = &am33xx_smartreflex1_hwmod,
457 .clk = "sys_clkin_ck",
458 .user = OCP_USER_MPU,
459};
460
461static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
462 .master = &am33xx_l4_wkup_hwmod,
463 .slave = &am43xx_control_hwmod,
464 .clk = "sys_clkin_ck",
465 .user = OCP_USER_MPU,
466};
467
468static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
469 .master = &am33xx_l4_wkup_hwmod,
470 .slave = &am33xx_i2c1_hwmod,
471 .clk = "sys_clkin_ck",
472 .user = OCP_USER_MPU,
473};
474
475static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
476 .master = &am33xx_l4_wkup_hwmod,
477 .slave = &am43xx_gpio0_hwmod,
478 .clk = "sys_clkin_ck",
479 .user = OCP_USER_MPU | OCP_USER_SDMA,
480};
481
482static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
483 .master = &am43xx_l4_hs_hwmod,
484 .slave = &am33xx_cpgmac0_hwmod,
485 .clk = "cpsw_125mhz_gclk",
486 .user = OCP_USER_MPU,
487};
488
489static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
490 .master = &am33xx_l4_wkup_hwmod,
491 .slave = &am33xx_timer1_hwmod,
492 .clk = "sys_clkin_ck",
493 .user = OCP_USER_MPU,
494};
495
496static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
497 .master = &am33xx_l4_wkup_hwmod,
498 .slave = &am33xx_uart1_hwmod,
499 .clk = "sys_clkin_ck",
500 .user = OCP_USER_MPU,
501};
502
503static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
504 .master = &am33xx_l4_wkup_hwmod,
505 .slave = &am33xx_wd_timer1_hwmod,
506 .clk = "sys_clkin_ck",
507 .user = OCP_USER_MPU,
508};
509
510static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
511 .master = &am33xx_l4_wkup_hwmod,
512 .slave = &am43xx_synctimer_hwmod,
513 .clk = "sys_clkin_ck",
514 .user = OCP_USER_MPU,
515};
516
517static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
518 .master = &am33xx_l4_ls_hwmod,
519 .slave = &am43xx_timer8_hwmod,
520 .clk = "l4ls_gclk",
521 .user = OCP_USER_MPU,
522};
523
524static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
525 .master = &am33xx_l4_ls_hwmod,
526 .slave = &am43xx_timer9_hwmod,
527 .clk = "l4ls_gclk",
528 .user = OCP_USER_MPU,
529};
530
531static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
532 .master = &am33xx_l4_ls_hwmod,
533 .slave = &am43xx_timer10_hwmod,
534 .clk = "l4ls_gclk",
535 .user = OCP_USER_MPU,
536};
537
538static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
539 .master = &am33xx_l4_ls_hwmod,
540 .slave = &am43xx_timer11_hwmod,
541 .clk = "l4ls_gclk",
542 .user = OCP_USER_MPU,
543};
544
545static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
546 .master = &am33xx_l4_ls_hwmod,
547 .slave = &am43xx_epwmss3_hwmod,
548 .clk = "l4ls_gclk",
549 .user = OCP_USER_MPU,
550};
551
552static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
553 .master = &am43xx_epwmss3_hwmod,
554 .slave = &am43xx_ehrpwm3_hwmod,
555 .clk = "l4ls_gclk",
556 .user = OCP_USER_MPU,
557};
558
559static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
560 .master = &am33xx_l4_ls_hwmod,
561 .slave = &am43xx_epwmss4_hwmod,
562 .clk = "l4ls_gclk",
563 .user = OCP_USER_MPU,
564};
565
566static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
567 .master = &am43xx_epwmss4_hwmod,
568 .slave = &am43xx_ehrpwm4_hwmod,
569 .clk = "l4ls_gclk",
570 .user = OCP_USER_MPU,
571};
572
573static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
574 .master = &am33xx_l4_ls_hwmod,
575 .slave = &am43xx_epwmss5_hwmod,
576 .clk = "l4ls_gclk",
577 .user = OCP_USER_MPU,
578};
579
580static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
581 .master = &am43xx_epwmss5_hwmod,
582 .slave = &am43xx_ehrpwm5_hwmod,
583 .clk = "l4ls_gclk",
584 .user = OCP_USER_MPU,
585};
586
587static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
588 .master = &am33xx_l4_ls_hwmod,
589 .slave = &am43xx_spi2_hwmod,
590 .clk = "l4ls_gclk",
591 .user = OCP_USER_MPU,
592};
593
594static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
595 .master = &am33xx_l4_ls_hwmod,
596 .slave = &am43xx_spi3_hwmod,
597 .clk = "l4ls_gclk",
598 .user = OCP_USER_MPU,
599};
600
601static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
602 .master = &am33xx_l4_ls_hwmod,
603 .slave = &am43xx_spi4_hwmod,
604 .clk = "l4ls_gclk",
605 .user = OCP_USER_MPU,
606};
607
608static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
609 .master = &am33xx_l4_ls_hwmod,
610 .slave = &am43xx_gpio4_hwmod,
611 .clk = "l4ls_gclk",
612 .user = OCP_USER_MPU | OCP_USER_SDMA,
613};
614
615static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
616 .master = &am33xx_l4_ls_hwmod,
617 .slave = &am43xx_gpio5_hwmod,
618 .clk = "l4ls_gclk",
619 .user = OCP_USER_MPU | OCP_USER_SDMA,
620};
621
622static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
623 .master = &am33xx_l4_ls_hwmod,
624 .slave = &am43xx_ocp2scp0_hwmod,
625 .clk = "l4ls_gclk",
626 .user = OCP_USER_MPU,
627};
628
629static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
630 .master = &am33xx_l4_ls_hwmod,
631 .slave = &am43xx_ocp2scp1_hwmod,
632 .clk = "l4ls_gclk",
633 .user = OCP_USER_MPU,
634};
635
636static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
637 .master = &am33xx_l3_s_hwmod,
638 .slave = &am43xx_usb_otg_ss0_hwmod,
639 .clk = "l3s_gclk",
640 .user = OCP_USER_MPU | OCP_USER_SDMA,
641};
642
643static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
644 .master = &am33xx_l3_s_hwmod,
645 .slave = &am43xx_usb_otg_ss1_hwmod,
646 .clk = "l3s_gclk",
647 .user = OCP_USER_MPU | OCP_USER_SDMA,
648};
649
650static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
651 .master = &am33xx_l3_s_hwmod,
652 .slave = &am43xx_qspi_hwmod,
653 .clk = "l3s_gclk",
654 .user = OCP_USER_MPU | OCP_USER_SDMA,
655};
656
657static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
658 &am33xx_l4_wkup__synctimer,
659 &am43xx_l4_ls__timer8,
660 &am43xx_l4_ls__timer9,
661 &am43xx_l4_ls__timer10,
662 &am43xx_l4_ls__timer11,
663 &am43xx_l4_ls__epwmss3,
664 &am43xx_epwmss3__ehrpwm3,
665 &am43xx_l4_ls__epwmss4,
666 &am43xx_epwmss4__ehrpwm4,
667 &am43xx_l4_ls__epwmss5,
668 &am43xx_epwmss5__ehrpwm5,
669 &am43xx_l4_ls__mcspi2,
670 &am43xx_l4_ls__mcspi3,
671 &am43xx_l4_ls__mcspi4,
672 &am43xx_l4_ls__gpio4,
673 &am43xx_l4_ls__gpio5,
674 &am43xx_l3_main__pruss,
675 &am33xx_mpu__l3_main,
676 &am33xx_mpu__prcm,
677 &am33xx_l3_s__l4_ls,
678 &am33xx_l3_s__l4_wkup,
679 &am43xx_l3_main__l4_hs,
680 &am33xx_l3_main__l3_s,
681 &am33xx_l3_main__l3_instr,
682 &am33xx_l3_main__gfx,
683 &am33xx_l3_s__l3_main,
684 &am33xx_pruss__l3_main,
685 &am43xx_wkup_m3__l4_wkup,
686 &am33xx_gfx__l3_main,
687 &am43xx_l4_wkup__wkup_m3,
688 &am43xx_l4_wkup__control,
689 &am43xx_l4_wkup__smartreflex0,
690 &am43xx_l4_wkup__smartreflex1,
691 &am43xx_l4_wkup__uart1,
692 &am43xx_l4_wkup__timer1,
693 &am43xx_l4_wkup__i2c1,
694 &am43xx_l4_wkup__gpio0,
695 &am43xx_l4_wkup__wd_timer1,
696 &am43xx_l3_s__qspi,
697 &am33xx_l4_per__dcan0,
698 &am33xx_l4_per__dcan1,
699 &am33xx_l4_per__gpio1,
700 &am33xx_l4_per__gpio2,
701 &am33xx_l4_per__gpio3,
702 &am33xx_l4_per__i2c2,
703 &am33xx_l4_per__i2c3,
704 &am33xx_l4_per__mailbox,
705 &am33xx_l4_ls__mcasp0,
706 &am33xx_l4_ls__mcasp1,
707 &am33xx_l4_ls__mmc0,
708 &am33xx_l4_ls__mmc1,
709 &am33xx_l3_s__mmc2,
710 &am33xx_l4_ls__timer2,
711 &am33xx_l4_ls__timer3,
712 &am33xx_l4_ls__timer4,
713 &am33xx_l4_ls__timer5,
714 &am33xx_l4_ls__timer6,
715 &am33xx_l4_ls__timer7,
716 &am33xx_l3_main__tpcc,
717 &am33xx_l4_ls__uart2,
718 &am33xx_l4_ls__uart3,
719 &am33xx_l4_ls__uart4,
720 &am33xx_l4_ls__uart5,
721 &am33xx_l4_ls__uart6,
722 &am33xx_l4_ls__spinlock,
723 &am33xx_l4_ls__elm,
724 &am33xx_l4_ls__epwmss0,
725 &am33xx_epwmss0__ecap0,
726 &am33xx_epwmss0__eqep0,
727 &am33xx_epwmss0__ehrpwm0,
728 &am33xx_l4_ls__epwmss1,
729 &am33xx_epwmss1__ecap1,
730 &am33xx_epwmss1__eqep1,
731 &am33xx_epwmss1__ehrpwm1,
732 &am33xx_l4_ls__epwmss2,
733 &am33xx_epwmss2__ecap2,
734 &am33xx_epwmss2__eqep2,
735 &am33xx_epwmss2__ehrpwm2,
736 &am33xx_l3_s__gpmc,
737 &am33xx_l4_ls__mcspi0,
738 &am33xx_l4_ls__mcspi1,
739 &am33xx_l3_main__tptc0,
740 &am33xx_l3_main__tptc1,
741 &am33xx_l3_main__tptc2,
742 &am33xx_l3_main__ocmc,
743 &am43xx_l4_hs__cpgmac0,
744 &am33xx_cpgmac0__mdio,
745 &am33xx_l3_main__sha0,
746 &am33xx_l3_main__aes0,
747 &am43xx_l4_ls__ocp2scp0,
748 &am43xx_l4_ls__ocp2scp1,
749 &am43xx_l3_s__usbotgss0,
750 &am43xx_l3_s__usbotgss1,
751 NULL,
752};
753
754int __init am43xx_hwmod_init(void)
755{
756 omap_hwmod_am43xx_reg();
757 omap_hwmod_init();
758 return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
759}
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated
3 *
4 * Hwmod present only in AM43x and those that differ other than register
5 * offsets as compared to AM335x.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/platform_data/gpio-omap.h>
18#include <linux/platform_data/spi-omap2-mcspi.h>
19#include "omap_hwmod.h"
20#include "omap_hwmod_33xx_43xx_common_data.h"
21#include "prcm43xx.h"
22#include "omap_hwmod_common_data.h"
23#include "hdq1w.h"
24
25
26/* IP blocks */
27static struct omap_hwmod am43xx_emif_hwmod = {
28 .name = "emif",
29 .class = &am33xx_emif_hwmod_class,
30 .clkdm_name = "emif_clkdm",
31 .flags = HWMOD_INIT_NO_IDLE,
32 .main_clk = "dpll_ddr_m2_ck",
33 .prcm = {
34 .omap4 = {
35 .clkctrl_offs = AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET,
36 .modulemode = MODULEMODE_SWCTRL,
37 },
38 },
39};
40
41static struct omap_hwmod am43xx_l4_hs_hwmod = {
42 .name = "l4_hs",
43 .class = &am33xx_l4_hwmod_class,
44 .clkdm_name = "l3_clkdm",
45 .flags = HWMOD_INIT_NO_IDLE,
46 .main_clk = "l4hs_gclk",
47 .prcm = {
48 .omap4 = {
49 .clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
50 .modulemode = MODULEMODE_SWCTRL,
51 },
52 },
53};
54
55static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
56 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
57};
58
59static struct omap_hwmod am43xx_wkup_m3_hwmod = {
60 .name = "wkup_m3",
61 .class = &am33xx_wkup_m3_hwmod_class,
62 .clkdm_name = "l4_wkup_aon_clkdm",
63 /* Keep hardreset asserted */
64 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
65 .main_clk = "sys_clkin_ck",
66 .prcm = {
67 .omap4 = {
68 .clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
69 .rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
70 .rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET,
71 .modulemode = MODULEMODE_SWCTRL,
72 },
73 },
74 .rst_lines = am33xx_wkup_m3_resets,
75 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
76};
77
78static struct omap_hwmod am43xx_control_hwmod = {
79 .name = "control",
80 .class = &am33xx_control_hwmod_class,
81 .clkdm_name = "l4_wkup_clkdm",
82 .flags = HWMOD_INIT_NO_IDLE,
83 .main_clk = "sys_clkin_ck",
84 .prcm = {
85 .omap4 = {
86 .clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
87 .modulemode = MODULEMODE_SWCTRL,
88 },
89 },
90};
91
92static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
93 { .role = "dbclk", .clk = "gpio0_dbclk" },
94};
95
96static struct omap_hwmod am43xx_gpio0_hwmod = {
97 .name = "gpio1",
98 .class = &am33xx_gpio_hwmod_class,
99 .clkdm_name = "l4_wkup_clkdm",
100 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
101 .main_clk = "sys_clkin_ck",
102 .prcm = {
103 .omap4 = {
104 .clkctrl_offs = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
105 .modulemode = MODULEMODE_SWCTRL,
106 },
107 },
108 .opt_clks = gpio0_opt_clks,
109 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
110 .dev_attr = &gpio_dev_attr,
111};
112
113static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
114 .rev_offs = 0x0,
115 .sysc_offs = 0x4,
116 .sysc_flags = SYSC_HAS_SIDLEMODE,
117 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
118 .sysc_fields = &omap_hwmod_sysc_type1,
119};
120
121static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
122 .name = "synctimer",
123 .sysc = &am43xx_synctimer_sysc,
124};
125
126static struct omap_hwmod am43xx_synctimer_hwmod = {
127 .name = "counter_32k",
128 .class = &am43xx_synctimer_hwmod_class,
129 .clkdm_name = "l4_wkup_aon_clkdm",
130 .flags = HWMOD_SWSUP_SIDLE,
131 .main_clk = "synctimer_32kclk",
132 .prcm = {
133 .omap4 = {
134 .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
135 .modulemode = MODULEMODE_SWCTRL,
136 },
137 },
138};
139
140static struct omap_hwmod am43xx_timer8_hwmod = {
141 .name = "timer8",
142 .class = &am33xx_timer_hwmod_class,
143 .clkdm_name = "l4ls_clkdm",
144 .main_clk = "timer8_fck",
145 .prcm = {
146 .omap4 = {
147 .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
148 .modulemode = MODULEMODE_SWCTRL,
149 },
150 },
151};
152
153static struct omap_hwmod am43xx_timer9_hwmod = {
154 .name = "timer9",
155 .class = &am33xx_timer_hwmod_class,
156 .clkdm_name = "l4ls_clkdm",
157 .main_clk = "timer9_fck",
158 .prcm = {
159 .omap4 = {
160 .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
161 .modulemode = MODULEMODE_SWCTRL,
162 },
163 },
164};
165
166static struct omap_hwmod am43xx_timer10_hwmod = {
167 .name = "timer10",
168 .class = &am33xx_timer_hwmod_class,
169 .clkdm_name = "l4ls_clkdm",
170 .main_clk = "timer10_fck",
171 .prcm = {
172 .omap4 = {
173 .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
174 .modulemode = MODULEMODE_SWCTRL,
175 },
176 },
177};
178
179static struct omap_hwmod am43xx_timer11_hwmod = {
180 .name = "timer11",
181 .class = &am33xx_timer_hwmod_class,
182 .clkdm_name = "l4ls_clkdm",
183 .main_clk = "timer11_fck",
184 .prcm = {
185 .omap4 = {
186 .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
187 .modulemode = MODULEMODE_SWCTRL,
188 },
189 },
190};
191
192static struct omap_hwmod am43xx_epwmss3_hwmod = {
193 .name = "epwmss3",
194 .class = &am33xx_epwmss_hwmod_class,
195 .clkdm_name = "l4ls_clkdm",
196 .main_clk = "l4ls_gclk",
197 .prcm = {
198 .omap4 = {
199 .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
200 .modulemode = MODULEMODE_SWCTRL,
201 },
202 },
203};
204
205static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
206 .name = "ehrpwm3",
207 .class = &am33xx_ehrpwm_hwmod_class,
208 .clkdm_name = "l4ls_clkdm",
209 .main_clk = "l4ls_gclk",
210};
211
212static struct omap_hwmod am43xx_epwmss4_hwmod = {
213 .name = "epwmss4",
214 .class = &am33xx_epwmss_hwmod_class,
215 .clkdm_name = "l4ls_clkdm",
216 .main_clk = "l4ls_gclk",
217 .prcm = {
218 .omap4 = {
219 .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
220 .modulemode = MODULEMODE_SWCTRL,
221 },
222 },
223};
224
225static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
226 .name = "ehrpwm4",
227 .class = &am33xx_ehrpwm_hwmod_class,
228 .clkdm_name = "l4ls_clkdm",
229 .main_clk = "l4ls_gclk",
230};
231
232static struct omap_hwmod am43xx_epwmss5_hwmod = {
233 .name = "epwmss5",
234 .class = &am33xx_epwmss_hwmod_class,
235 .clkdm_name = "l4ls_clkdm",
236 .main_clk = "l4ls_gclk",
237 .prcm = {
238 .omap4 = {
239 .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
240 .modulemode = MODULEMODE_SWCTRL,
241 },
242 },
243};
244
245static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
246 .name = "ehrpwm5",
247 .class = &am33xx_ehrpwm_hwmod_class,
248 .clkdm_name = "l4ls_clkdm",
249 .main_clk = "l4ls_gclk",
250};
251
252static struct omap_hwmod am43xx_spi2_hwmod = {
253 .name = "spi2",
254 .class = &am33xx_spi_hwmod_class,
255 .clkdm_name = "l4ls_clkdm",
256 .main_clk = "dpll_per_m2_div4_ck",
257 .prcm = {
258 .omap4 = {
259 .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
260 .modulemode = MODULEMODE_SWCTRL,
261 },
262 },
263 .dev_attr = &mcspi_attrib,
264};
265
266static struct omap_hwmod am43xx_spi3_hwmod = {
267 .name = "spi3",
268 .class = &am33xx_spi_hwmod_class,
269 .clkdm_name = "l4ls_clkdm",
270 .main_clk = "dpll_per_m2_div4_ck",
271 .prcm = {
272 .omap4 = {
273 .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
274 .modulemode = MODULEMODE_SWCTRL,
275 },
276 },
277 .dev_attr = &mcspi_attrib,
278};
279
280static struct omap_hwmod am43xx_spi4_hwmod = {
281 .name = "spi4",
282 .class = &am33xx_spi_hwmod_class,
283 .clkdm_name = "l4ls_clkdm",
284 .main_clk = "dpll_per_m2_div4_ck",
285 .prcm = {
286 .omap4 = {
287 .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
288 .modulemode = MODULEMODE_SWCTRL,
289 },
290 },
291 .dev_attr = &mcspi_attrib,
292};
293
294static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
295 { .role = "dbclk", .clk = "gpio4_dbclk" },
296};
297
298static struct omap_hwmod am43xx_gpio4_hwmod = {
299 .name = "gpio5",
300 .class = &am33xx_gpio_hwmod_class,
301 .clkdm_name = "l4ls_clkdm",
302 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
303 .main_clk = "l4ls_gclk",
304 .prcm = {
305 .omap4 = {
306 .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
307 .modulemode = MODULEMODE_SWCTRL,
308 },
309 },
310 .opt_clks = gpio4_opt_clks,
311 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
312 .dev_attr = &gpio_dev_attr,
313};
314
315static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
316 { .role = "dbclk", .clk = "gpio5_dbclk" },
317};
318
319static struct omap_hwmod am43xx_gpio5_hwmod = {
320 .name = "gpio6",
321 .class = &am33xx_gpio_hwmod_class,
322 .clkdm_name = "l4ls_clkdm",
323 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
324 .main_clk = "l4ls_gclk",
325 .prcm = {
326 .omap4 = {
327 .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
328 .modulemode = MODULEMODE_SWCTRL,
329 },
330 },
331 .opt_clks = gpio5_opt_clks,
332 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
333 .dev_attr = &gpio_dev_attr,
334};
335
336static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
337 .name = "ocp2scp",
338};
339
340static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
341 .name = "ocp2scp0",
342 .class = &am43xx_ocp2scp_hwmod_class,
343 .clkdm_name = "l4ls_clkdm",
344 .main_clk = "l4ls_gclk",
345 .prcm = {
346 .omap4 = {
347 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
348 .modulemode = MODULEMODE_SWCTRL,
349 },
350 },
351};
352
353static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
354 .name = "ocp2scp1",
355 .class = &am43xx_ocp2scp_hwmod_class,
356 .clkdm_name = "l4ls_clkdm",
357 .main_clk = "l4ls_gclk",
358 .prcm = {
359 .omap4 = {
360 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
361 .modulemode = MODULEMODE_SWCTRL,
362 },
363 },
364};
365
366static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
367 .rev_offs = 0x0000,
368 .sysc_offs = 0x0010,
369 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
370 SYSC_HAS_SIDLEMODE),
371 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
372 SIDLE_SMART_WKUP | MSTANDBY_FORCE |
373 MSTANDBY_NO | MSTANDBY_SMART |
374 MSTANDBY_SMART_WKUP),
375 .sysc_fields = &omap_hwmod_sysc_type2,
376};
377
378static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
379 .name = "usb_otg_ss",
380 .sysc = &am43xx_usb_otg_ss_sysc,
381};
382
383static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
384 .name = "usb_otg_ss0",
385 .class = &am43xx_usb_otg_ss_hwmod_class,
386 .clkdm_name = "l3s_clkdm",
387 .main_clk = "l3s_gclk",
388 .prcm = {
389 .omap4 = {
390 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
391 .modulemode = MODULEMODE_SWCTRL,
392 },
393 },
394};
395
396static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
397 .name = "usb_otg_ss1",
398 .class = &am43xx_usb_otg_ss_hwmod_class,
399 .clkdm_name = "l3s_clkdm",
400 .main_clk = "l3s_gclk",
401 .prcm = {
402 .omap4 = {
403 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
404 .modulemode = MODULEMODE_SWCTRL,
405 },
406 },
407};
408
409static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
410 .sysc_offs = 0x0010,
411 .sysc_flags = SYSC_HAS_SIDLEMODE,
412 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
413 SIDLE_SMART_WKUP),
414 .sysc_fields = &omap_hwmod_sysc_type2,
415};
416
417static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
418 .name = "qspi",
419 .sysc = &am43xx_qspi_sysc,
420};
421
422static struct omap_hwmod am43xx_qspi_hwmod = {
423 .name = "qspi",
424 .class = &am43xx_qspi_hwmod_class,
425 .clkdm_name = "l3s_clkdm",
426 .main_clk = "l3s_gclk",
427 .prcm = {
428 .omap4 = {
429 .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
430 .modulemode = MODULEMODE_SWCTRL,
431 },
432 },
433};
434
435/*
436 * 'adc/tsc' class
437 * TouchScreen Controller (Analog-To-Digital Converter)
438 */
439static struct omap_hwmod_class_sysconfig am43xx_adc_tsc_sysc = {
440 .rev_offs = 0x00,
441 .sysc_offs = 0x10,
442 .sysc_flags = SYSC_HAS_SIDLEMODE,
443 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
444 SIDLE_SMART_WKUP),
445 .sysc_fields = &omap_hwmod_sysc_type2,
446};
447
448static struct omap_hwmod_class am43xx_adc_tsc_hwmod_class = {
449 .name = "adc_tsc",
450 .sysc = &am43xx_adc_tsc_sysc,
451};
452
453static struct omap_hwmod am43xx_adc_tsc_hwmod = {
454 .name = "adc_tsc",
455 .class = &am43xx_adc_tsc_hwmod_class,
456 .clkdm_name = "l3s_tsc_clkdm",
457 .main_clk = "adc_tsc_fck",
458 .prcm = {
459 .omap4 = {
460 .clkctrl_offs = AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
461 .modulemode = MODULEMODE_SWCTRL,
462 },
463 },
464};
465
466/* dss */
467
468static struct omap_hwmod am43xx_dss_core_hwmod = {
469 .name = "dss_core",
470 .class = &omap2_dss_hwmod_class,
471 .clkdm_name = "dss_clkdm",
472 .main_clk = "disp_clk",
473 .prcm = {
474 .omap4 = {
475 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
476 .modulemode = MODULEMODE_SWCTRL,
477 },
478 },
479};
480
481/* dispc */
482
483static struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
484 .manager_count = 1,
485 .has_framedonetv_irq = 0
486};
487
488static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
489 .rev_offs = 0x0000,
490 .sysc_offs = 0x0010,
491 .syss_offs = 0x0014,
492 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
493 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
494 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
495 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
496 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
497 .sysc_fields = &omap_hwmod_sysc_type1,
498};
499
500static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
501 .name = "dispc",
502 .sysc = &am43xx_dispc_sysc,
503};
504
505static struct omap_hwmod am43xx_dss_dispc_hwmod = {
506 .name = "dss_dispc",
507 .class = &am43xx_dispc_hwmod_class,
508 .clkdm_name = "dss_clkdm",
509 .main_clk = "disp_clk",
510 .prcm = {
511 .omap4 = {
512 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
513 },
514 },
515 .dev_attr = &am43xx_dss_dispc_dev_attr,
516 .parent_hwmod = &am43xx_dss_core_hwmod,
517};
518
519/* rfbi */
520
521static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
522 .name = "dss_rfbi",
523 .class = &omap2_rfbi_hwmod_class,
524 .clkdm_name = "dss_clkdm",
525 .main_clk = "disp_clk",
526 .prcm = {
527 .omap4 = {
528 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
529 },
530 },
531 .parent_hwmod = &am43xx_dss_core_hwmod,
532};
533
534/* HDQ1W */
535static struct omap_hwmod_class_sysconfig am43xx_hdq1w_sysc = {
536 .rev_offs = 0x0000,
537 .sysc_offs = 0x0014,
538 .syss_offs = 0x0018,
539 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
540 .sysc_fields = &omap_hwmod_sysc_type1,
541};
542
543static struct omap_hwmod_class am43xx_hdq1w_hwmod_class = {
544 .name = "hdq1w",
545 .sysc = &am43xx_hdq1w_sysc,
546 .reset = &omap_hdq1w_reset,
547};
548
549static struct omap_hwmod am43xx_hdq1w_hwmod = {
550 .name = "hdq1w",
551 .class = &am43xx_hdq1w_hwmod_class,
552 .clkdm_name = "l4ls_clkdm",
553 .prcm = {
554 .omap4 = {
555 .clkctrl_offs = AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET,
556 .modulemode = MODULEMODE_SWCTRL,
557 },
558 },
559};
560
561static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = {
562 .rev_offs = 0x0,
563 .sysc_offs = 0x104,
564 .sysc_flags = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE,
565 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
566 MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO),
567 .sysc_fields = &omap_hwmod_sysc_type2,
568};
569
570static struct omap_hwmod_class am43xx_vpfe_hwmod_class = {
571 .name = "vpfe",
572 .sysc = &am43xx_vpfe_sysc,
573};
574
575static struct omap_hwmod am43xx_vpfe0_hwmod = {
576 .name = "vpfe0",
577 .class = &am43xx_vpfe_hwmod_class,
578 .clkdm_name = "l3s_clkdm",
579 .prcm = {
580 .omap4 = {
581 .modulemode = MODULEMODE_SWCTRL,
582 .clkctrl_offs = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET,
583 },
584 },
585};
586
587static struct omap_hwmod am43xx_vpfe1_hwmod = {
588 .name = "vpfe1",
589 .class = &am43xx_vpfe_hwmod_class,
590 .clkdm_name = "l3s_clkdm",
591 .prcm = {
592 .omap4 = {
593 .modulemode = MODULEMODE_SWCTRL,
594 .clkctrl_offs = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET,
595 },
596 },
597};
598
599/* Interfaces */
600static struct omap_hwmod_ocp_if am43xx_l3_main__emif = {
601 .master = &am33xx_l3_main_hwmod,
602 .slave = &am43xx_emif_hwmod,
603 .clk = "dpll_core_m4_ck",
604 .user = OCP_USER_MPU | OCP_USER_SDMA,
605};
606
607static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
608 .master = &am33xx_l3_main_hwmod,
609 .slave = &am43xx_l4_hs_hwmod,
610 .clk = "l3s_gclk",
611 .user = OCP_USER_MPU | OCP_USER_SDMA,
612};
613
614static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
615 .master = &am43xx_wkup_m3_hwmod,
616 .slave = &am33xx_l4_wkup_hwmod,
617 .clk = "sys_clkin_ck",
618 .user = OCP_USER_MPU | OCP_USER_SDMA,
619};
620
621static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
622 .master = &am33xx_l4_wkup_hwmod,
623 .slave = &am43xx_wkup_m3_hwmod,
624 .clk = "sys_clkin_ck",
625 .user = OCP_USER_MPU | OCP_USER_SDMA,
626};
627
628static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
629 .master = &am33xx_l3_main_hwmod,
630 .slave = &am33xx_pruss_hwmod,
631 .clk = "dpll_core_m4_ck",
632 .user = OCP_USER_MPU,
633};
634
635static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
636 .master = &am33xx_l4_wkup_hwmod,
637 .slave = &am33xx_smartreflex0_hwmod,
638 .clk = "sys_clkin_ck",
639 .user = OCP_USER_MPU,
640};
641
642static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
643 .master = &am33xx_l4_wkup_hwmod,
644 .slave = &am33xx_smartreflex1_hwmod,
645 .clk = "sys_clkin_ck",
646 .user = OCP_USER_MPU,
647};
648
649static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
650 .master = &am33xx_l4_wkup_hwmod,
651 .slave = &am43xx_control_hwmod,
652 .clk = "sys_clkin_ck",
653 .user = OCP_USER_MPU,
654};
655
656static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
657 .master = &am33xx_l4_wkup_hwmod,
658 .slave = &am33xx_i2c1_hwmod,
659 .clk = "sys_clkin_ck",
660 .user = OCP_USER_MPU,
661};
662
663static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
664 .master = &am33xx_l4_wkup_hwmod,
665 .slave = &am43xx_gpio0_hwmod,
666 .clk = "sys_clkin_ck",
667 .user = OCP_USER_MPU | OCP_USER_SDMA,
668};
669
670static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
671 .master = &am33xx_l4_wkup_hwmod,
672 .slave = &am43xx_adc_tsc_hwmod,
673 .clk = "dpll_core_m4_div2_ck",
674 .user = OCP_USER_MPU,
675};
676
677static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
678 .master = &am43xx_l4_hs_hwmod,
679 .slave = &am33xx_cpgmac0_hwmod,
680 .clk = "cpsw_125mhz_gclk",
681 .user = OCP_USER_MPU,
682};
683
684static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
685 .master = &am33xx_l4_wkup_hwmod,
686 .slave = &am33xx_timer1_hwmod,
687 .clk = "sys_clkin_ck",
688 .user = OCP_USER_MPU,
689};
690
691static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
692 .master = &am33xx_l4_wkup_hwmod,
693 .slave = &am33xx_uart1_hwmod,
694 .clk = "sys_clkin_ck",
695 .user = OCP_USER_MPU,
696};
697
698static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
699 .master = &am33xx_l4_wkup_hwmod,
700 .slave = &am33xx_wd_timer1_hwmod,
701 .clk = "sys_clkin_ck",
702 .user = OCP_USER_MPU,
703};
704
705static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
706 .master = &am33xx_l4_wkup_hwmod,
707 .slave = &am43xx_synctimer_hwmod,
708 .clk = "sys_clkin_ck",
709 .user = OCP_USER_MPU,
710};
711
712static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
713 .master = &am33xx_l4_ls_hwmod,
714 .slave = &am43xx_timer8_hwmod,
715 .clk = "l4ls_gclk",
716 .user = OCP_USER_MPU,
717};
718
719static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
720 .master = &am33xx_l4_ls_hwmod,
721 .slave = &am43xx_timer9_hwmod,
722 .clk = "l4ls_gclk",
723 .user = OCP_USER_MPU,
724};
725
726static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
727 .master = &am33xx_l4_ls_hwmod,
728 .slave = &am43xx_timer10_hwmod,
729 .clk = "l4ls_gclk",
730 .user = OCP_USER_MPU,
731};
732
733static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
734 .master = &am33xx_l4_ls_hwmod,
735 .slave = &am43xx_timer11_hwmod,
736 .clk = "l4ls_gclk",
737 .user = OCP_USER_MPU,
738};
739
740static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
741 .master = &am33xx_l4_ls_hwmod,
742 .slave = &am43xx_epwmss3_hwmod,
743 .clk = "l4ls_gclk",
744 .user = OCP_USER_MPU,
745};
746
747static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
748 .master = &am43xx_epwmss3_hwmod,
749 .slave = &am43xx_ehrpwm3_hwmod,
750 .clk = "l4ls_gclk",
751 .user = OCP_USER_MPU,
752};
753
754static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
755 .master = &am33xx_l4_ls_hwmod,
756 .slave = &am43xx_epwmss4_hwmod,
757 .clk = "l4ls_gclk",
758 .user = OCP_USER_MPU,
759};
760
761static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
762 .master = &am43xx_epwmss4_hwmod,
763 .slave = &am43xx_ehrpwm4_hwmod,
764 .clk = "l4ls_gclk",
765 .user = OCP_USER_MPU,
766};
767
768static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
769 .master = &am33xx_l4_ls_hwmod,
770 .slave = &am43xx_epwmss5_hwmod,
771 .clk = "l4ls_gclk",
772 .user = OCP_USER_MPU,
773};
774
775static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
776 .master = &am43xx_epwmss5_hwmod,
777 .slave = &am43xx_ehrpwm5_hwmod,
778 .clk = "l4ls_gclk",
779 .user = OCP_USER_MPU,
780};
781
782static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
783 .master = &am33xx_l4_ls_hwmod,
784 .slave = &am43xx_spi2_hwmod,
785 .clk = "l4ls_gclk",
786 .user = OCP_USER_MPU,
787};
788
789static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
790 .master = &am33xx_l4_ls_hwmod,
791 .slave = &am43xx_spi3_hwmod,
792 .clk = "l4ls_gclk",
793 .user = OCP_USER_MPU,
794};
795
796static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
797 .master = &am33xx_l4_ls_hwmod,
798 .slave = &am43xx_spi4_hwmod,
799 .clk = "l4ls_gclk",
800 .user = OCP_USER_MPU,
801};
802
803static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
804 .master = &am33xx_l4_ls_hwmod,
805 .slave = &am43xx_gpio4_hwmod,
806 .clk = "l4ls_gclk",
807 .user = OCP_USER_MPU | OCP_USER_SDMA,
808};
809
810static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
811 .master = &am33xx_l4_ls_hwmod,
812 .slave = &am43xx_gpio5_hwmod,
813 .clk = "l4ls_gclk",
814 .user = OCP_USER_MPU | OCP_USER_SDMA,
815};
816
817static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
818 .master = &am33xx_l4_ls_hwmod,
819 .slave = &am43xx_ocp2scp0_hwmod,
820 .clk = "l4ls_gclk",
821 .user = OCP_USER_MPU,
822};
823
824static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
825 .master = &am33xx_l4_ls_hwmod,
826 .slave = &am43xx_ocp2scp1_hwmod,
827 .clk = "l4ls_gclk",
828 .user = OCP_USER_MPU,
829};
830
831static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
832 .master = &am33xx_l3_s_hwmod,
833 .slave = &am43xx_usb_otg_ss0_hwmod,
834 .clk = "l3s_gclk",
835 .user = OCP_USER_MPU | OCP_USER_SDMA,
836};
837
838static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
839 .master = &am33xx_l3_s_hwmod,
840 .slave = &am43xx_usb_otg_ss1_hwmod,
841 .clk = "l3s_gclk",
842 .user = OCP_USER_MPU | OCP_USER_SDMA,
843};
844
845static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
846 .master = &am33xx_l3_s_hwmod,
847 .slave = &am43xx_qspi_hwmod,
848 .clk = "l3s_gclk",
849 .user = OCP_USER_MPU | OCP_USER_SDMA,
850};
851
852static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
853 .master = &am43xx_dss_core_hwmod,
854 .slave = &am33xx_l3_main_hwmod,
855 .clk = "l3_gclk",
856 .user = OCP_USER_MPU | OCP_USER_SDMA,
857};
858
859static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
860 .master = &am33xx_l4_ls_hwmod,
861 .slave = &am43xx_dss_core_hwmod,
862 .clk = "l4ls_gclk",
863 .user = OCP_USER_MPU | OCP_USER_SDMA,
864};
865
866static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
867 .master = &am33xx_l4_ls_hwmod,
868 .slave = &am43xx_dss_dispc_hwmod,
869 .clk = "l4ls_gclk",
870 .user = OCP_USER_MPU | OCP_USER_SDMA,
871};
872
873static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
874 .master = &am33xx_l4_ls_hwmod,
875 .slave = &am43xx_dss_rfbi_hwmod,
876 .clk = "l4ls_gclk",
877 .user = OCP_USER_MPU | OCP_USER_SDMA,
878};
879
880static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
881 .master = &am33xx_l4_ls_hwmod,
882 .slave = &am43xx_hdq1w_hwmod,
883 .clk = "l4ls_gclk",
884 .user = OCP_USER_MPU | OCP_USER_SDMA,
885};
886
887static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = {
888 .master = &am43xx_vpfe0_hwmod,
889 .slave = &am33xx_l3_main_hwmod,
890 .clk = "l3_gclk",
891 .user = OCP_USER_MPU | OCP_USER_SDMA,
892};
893
894static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = {
895 .master = &am43xx_vpfe1_hwmod,
896 .slave = &am33xx_l3_main_hwmod,
897 .clk = "l3_gclk",
898 .user = OCP_USER_MPU | OCP_USER_SDMA,
899};
900
901static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe0 = {
902 .master = &am33xx_l4_ls_hwmod,
903 .slave = &am43xx_vpfe0_hwmod,
904 .clk = "l4ls_gclk",
905 .user = OCP_USER_MPU | OCP_USER_SDMA,
906};
907
908static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = {
909 .master = &am33xx_l4_ls_hwmod,
910 .slave = &am43xx_vpfe1_hwmod,
911 .clk = "l4ls_gclk",
912 .user = OCP_USER_MPU | OCP_USER_SDMA,
913};
914
915static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
916 &am33xx_l4_wkup__synctimer,
917 &am43xx_l4_ls__timer8,
918 &am43xx_l4_ls__timer9,
919 &am43xx_l4_ls__timer10,
920 &am43xx_l4_ls__timer11,
921 &am43xx_l4_ls__epwmss3,
922 &am43xx_epwmss3__ehrpwm3,
923 &am43xx_l4_ls__epwmss4,
924 &am43xx_epwmss4__ehrpwm4,
925 &am43xx_l4_ls__epwmss5,
926 &am43xx_epwmss5__ehrpwm5,
927 &am43xx_l4_ls__mcspi2,
928 &am43xx_l4_ls__mcspi3,
929 &am43xx_l4_ls__mcspi4,
930 &am43xx_l4_ls__gpio4,
931 &am43xx_l4_ls__gpio5,
932 &am43xx_l3_main__pruss,
933 &am33xx_mpu__l3_main,
934 &am33xx_mpu__prcm,
935 &am33xx_l3_s__l4_ls,
936 &am33xx_l3_s__l4_wkup,
937 &am43xx_l3_main__l4_hs,
938 &am33xx_l3_main__l3_s,
939 &am33xx_l3_main__l3_instr,
940 &am33xx_l3_main__gfx,
941 &am33xx_l3_s__l3_main,
942 &am43xx_l3_main__emif,
943 &am33xx_pruss__l3_main,
944 &am43xx_wkup_m3__l4_wkup,
945 &am33xx_gfx__l3_main,
946 &am43xx_l4_wkup__wkup_m3,
947 &am43xx_l4_wkup__control,
948 &am43xx_l4_wkup__smartreflex0,
949 &am43xx_l4_wkup__smartreflex1,
950 &am43xx_l4_wkup__uart1,
951 &am43xx_l4_wkup__timer1,
952 &am43xx_l4_wkup__i2c1,
953 &am43xx_l4_wkup__gpio0,
954 &am43xx_l4_wkup__wd_timer1,
955 &am43xx_l4_wkup__adc_tsc,
956 &am43xx_l3_s__qspi,
957 &am33xx_l4_per__dcan0,
958 &am33xx_l4_per__dcan1,
959 &am33xx_l4_per__gpio1,
960 &am33xx_l4_per__gpio2,
961 &am33xx_l4_per__gpio3,
962 &am33xx_l4_per__i2c2,
963 &am33xx_l4_per__i2c3,
964 &am33xx_l4_per__mailbox,
965 &am33xx_l4_ls__mcasp0,
966 &am33xx_l4_ls__mcasp1,
967 &am33xx_l4_ls__mmc0,
968 &am33xx_l4_ls__mmc1,
969 &am33xx_l3_s__mmc2,
970 &am33xx_l4_ls__timer2,
971 &am33xx_l4_ls__timer3,
972 &am33xx_l4_ls__timer4,
973 &am33xx_l4_ls__timer5,
974 &am33xx_l4_ls__timer6,
975 &am33xx_l4_ls__timer7,
976 &am33xx_l3_main__tpcc,
977 &am33xx_l4_ls__uart2,
978 &am33xx_l4_ls__uart3,
979 &am33xx_l4_ls__uart4,
980 &am33xx_l4_ls__uart5,
981 &am33xx_l4_ls__uart6,
982 &am33xx_l4_ls__spinlock,
983 &am33xx_l4_ls__elm,
984 &am33xx_l4_ls__epwmss0,
985 &am33xx_epwmss0__ecap0,
986 &am33xx_epwmss0__eqep0,
987 &am33xx_epwmss0__ehrpwm0,
988 &am33xx_l4_ls__epwmss1,
989 &am33xx_epwmss1__ecap1,
990 &am33xx_epwmss1__eqep1,
991 &am33xx_epwmss1__ehrpwm1,
992 &am33xx_l4_ls__epwmss2,
993 &am33xx_epwmss2__ecap2,
994 &am33xx_epwmss2__eqep2,
995 &am33xx_epwmss2__ehrpwm2,
996 &am33xx_l3_s__gpmc,
997 &am33xx_l4_ls__mcspi0,
998 &am33xx_l4_ls__mcspi1,
999 &am33xx_l3_main__tptc0,
1000 &am33xx_l3_main__tptc1,
1001 &am33xx_l3_main__tptc2,
1002 &am33xx_l3_main__ocmc,
1003 &am43xx_l4_hs__cpgmac0,
1004 &am33xx_cpgmac0__mdio,
1005 &am33xx_l3_main__sha0,
1006 &am33xx_l3_main__aes0,
1007 &am43xx_l4_ls__ocp2scp0,
1008 &am43xx_l4_ls__ocp2scp1,
1009 &am43xx_l3_s__usbotgss0,
1010 &am43xx_l3_s__usbotgss1,
1011 &am43xx_dss__l3_main,
1012 &am43xx_l4_ls__dss,
1013 &am43xx_l4_ls__dss_dispc,
1014 &am43xx_l4_ls__dss_rfbi,
1015 &am43xx_l4_ls__hdq1w,
1016 &am43xx_l3__vpfe0,
1017 &am43xx_l3__vpfe1,
1018 &am43xx_l4_ls__vpfe0,
1019 &am43xx_l4_ls__vpfe1,
1020 NULL,
1021};
1022
1023static struct omap_hwmod_ocp_if *am43xx_rtc_hwmod_ocp_ifs[] __initdata = {
1024 &am33xx_l4_wkup__rtc,
1025 NULL,
1026};
1027
1028int __init am43xx_hwmod_init(void)
1029{
1030 int ret;
1031
1032 omap_hwmod_am43xx_reg();
1033 omap_hwmod_init();
1034 ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
1035
1036 if (!ret && of_machine_is_compatible("ti,am4372"))
1037 ret = omap_hwmod_register_links(am43xx_rtc_hwmod_ocp_ifs);
1038
1039 return ret;
1040}