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1/*
2 * drivers/net/phy/micrel.c
3 *
4 * Driver for Micrel PHYs
5 *
6 * Author: David J. Choi
7 *
8 * Copyright (c) 2010-2013 Micrel, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * Support : Micrel Phys:
16 * Giga phys: ksz9021, ksz9031
17 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
18 * ksz8021, ksz8031, ksz8051,
19 * ksz8081, ksz8091,
20 * ksz8061,
21 * Switch : ksz8873, ksz886x
22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/phy.h>
27#include <linux/micrel_phy.h>
28#include <linux/of.h>
29
30/* Operation Mode Strap Override */
31#define MII_KSZPHY_OMSO 0x16
32#define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
33#define KSZPHY_OMSO_RMII_OVERRIDE (1 << 1)
34#define KSZPHY_OMSO_MII_OVERRIDE (1 << 0)
35
36/* general Interrupt control/status reg in vendor specific block. */
37#define MII_KSZPHY_INTCS 0x1B
38#define KSZPHY_INTCS_JABBER (1 << 15)
39#define KSZPHY_INTCS_RECEIVE_ERR (1 << 14)
40#define KSZPHY_INTCS_PAGE_RECEIVE (1 << 13)
41#define KSZPHY_INTCS_PARELLEL (1 << 12)
42#define KSZPHY_INTCS_LINK_PARTNER_ACK (1 << 11)
43#define KSZPHY_INTCS_LINK_DOWN (1 << 10)
44#define KSZPHY_INTCS_REMOTE_FAULT (1 << 9)
45#define KSZPHY_INTCS_LINK_UP (1 << 8)
46#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
47 KSZPHY_INTCS_LINK_DOWN)
48
49/* general PHY control reg in vendor specific block. */
50#define MII_KSZPHY_CTRL 0x1F
51/* bitmap of PHY register to set interrupt mode */
52#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9)
53#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14)
54#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
55#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
56
57/* Write/read to/from extended registers */
58#define MII_KSZPHY_EXTREG 0x0b
59#define KSZPHY_EXTREG_WRITE 0x8000
60
61#define MII_KSZPHY_EXTREG_WRITE 0x0c
62#define MII_KSZPHY_EXTREG_READ 0x0d
63
64/* Extended registers */
65#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
66#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
67#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
68
69#define PS_TO_REG 200
70
71static int ksz_config_flags(struct phy_device *phydev)
72{
73 int regval;
74
75 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
76 regval = phy_read(phydev, MII_KSZPHY_CTRL);
77 regval |= KSZ8051_RMII_50MHZ_CLK;
78 return phy_write(phydev, MII_KSZPHY_CTRL, regval);
79 }
80 return 0;
81}
82
83static int kszphy_extended_write(struct phy_device *phydev,
84 u32 regnum, u16 val)
85{
86 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
87 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
88}
89
90static int kszphy_extended_read(struct phy_device *phydev,
91 u32 regnum)
92{
93 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
94 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
95}
96
97static int kszphy_ack_interrupt(struct phy_device *phydev)
98{
99 /* bit[7..0] int status, which is a read and clear register. */
100 int rc;
101
102 rc = phy_read(phydev, MII_KSZPHY_INTCS);
103
104 return (rc < 0) ? rc : 0;
105}
106
107static int kszphy_set_interrupt(struct phy_device *phydev)
108{
109 int temp;
110 temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
111 KSZPHY_INTCS_ALL : 0;
112 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
113}
114
115static int kszphy_config_intr(struct phy_device *phydev)
116{
117 int temp, rc;
118
119 /* set the interrupt pin active low */
120 temp = phy_read(phydev, MII_KSZPHY_CTRL);
121 temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
122 phy_write(phydev, MII_KSZPHY_CTRL, temp);
123 rc = kszphy_set_interrupt(phydev);
124 return rc < 0 ? rc : 0;
125}
126
127static int ksz9021_config_intr(struct phy_device *phydev)
128{
129 int temp, rc;
130
131 /* set the interrupt pin active low */
132 temp = phy_read(phydev, MII_KSZPHY_CTRL);
133 temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
134 phy_write(phydev, MII_KSZPHY_CTRL, temp);
135 rc = kszphy_set_interrupt(phydev);
136 return rc < 0 ? rc : 0;
137}
138
139static int ks8737_config_intr(struct phy_device *phydev)
140{
141 int temp, rc;
142
143 /* set the interrupt pin active low */
144 temp = phy_read(phydev, MII_KSZPHY_CTRL);
145 temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
146 phy_write(phydev, MII_KSZPHY_CTRL, temp);
147 rc = kszphy_set_interrupt(phydev);
148 return rc < 0 ? rc : 0;
149}
150
151static int kszphy_setup_led(struct phy_device *phydev,
152 unsigned int reg, unsigned int shift)
153{
154
155 struct device *dev = &phydev->dev;
156 struct device_node *of_node = dev->of_node;
157 int rc, temp;
158 u32 val;
159
160 if (!of_node && dev->parent->of_node)
161 of_node = dev->parent->of_node;
162
163 if (of_property_read_u32(of_node, "micrel,led-mode", &val))
164 return 0;
165
166 temp = phy_read(phydev, reg);
167 if (temp < 0)
168 return temp;
169
170 temp &= ~(3 << shift);
171 temp |= val << shift;
172 rc = phy_write(phydev, reg, temp);
173
174 return rc < 0 ? rc : 0;
175}
176
177static int kszphy_config_init(struct phy_device *phydev)
178{
179 return 0;
180}
181
182static int kszphy_config_init_led8041(struct phy_device *phydev)
183{
184 /* single led control, register 0x1e bits 15..14 */
185 return kszphy_setup_led(phydev, 0x1e, 14);
186}
187
188static int ksz8021_config_init(struct phy_device *phydev)
189{
190 const u16 val = KSZPHY_OMSO_B_CAST_OFF | KSZPHY_OMSO_RMII_OVERRIDE;
191 int rc;
192
193 rc = kszphy_setup_led(phydev, 0x1f, 4);
194 if (rc)
195 dev_err(&phydev->dev, "failed to set led mode\n");
196
197 phy_write(phydev, MII_KSZPHY_OMSO, val);
198 rc = ksz_config_flags(phydev);
199 return rc < 0 ? rc : 0;
200}
201
202static int ks8051_config_init(struct phy_device *phydev)
203{
204 int rc;
205
206 rc = kszphy_setup_led(phydev, 0x1f, 4);
207 if (rc)
208 dev_err(&phydev->dev, "failed to set led mode\n");
209
210 rc = ksz_config_flags(phydev);
211 return rc < 0 ? rc : 0;
212}
213
214static int ksz9021_load_values_from_of(struct phy_device *phydev,
215 struct device_node *of_node, u16 reg,
216 char *field1, char *field2,
217 char *field3, char *field4)
218{
219 int val1 = -1;
220 int val2 = -2;
221 int val3 = -3;
222 int val4 = -4;
223 int newval;
224 int matches = 0;
225
226 if (!of_property_read_u32(of_node, field1, &val1))
227 matches++;
228
229 if (!of_property_read_u32(of_node, field2, &val2))
230 matches++;
231
232 if (!of_property_read_u32(of_node, field3, &val3))
233 matches++;
234
235 if (!of_property_read_u32(of_node, field4, &val4))
236 matches++;
237
238 if (!matches)
239 return 0;
240
241 if (matches < 4)
242 newval = kszphy_extended_read(phydev, reg);
243 else
244 newval = 0;
245
246 if (val1 != -1)
247 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
248
249 if (val2 != -2)
250 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
251
252 if (val3 != -3)
253 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
254
255 if (val4 != -4)
256 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
257
258 return kszphy_extended_write(phydev, reg, newval);
259}
260
261static int ksz9021_config_init(struct phy_device *phydev)
262{
263 struct device *dev = &phydev->dev;
264 struct device_node *of_node = dev->of_node;
265
266 if (!of_node && dev->parent->of_node)
267 of_node = dev->parent->of_node;
268
269 if (of_node) {
270 ksz9021_load_values_from_of(phydev, of_node,
271 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
272 "txen-skew-ps", "txc-skew-ps",
273 "rxdv-skew-ps", "rxc-skew-ps");
274 ksz9021_load_values_from_of(phydev, of_node,
275 MII_KSZPHY_RX_DATA_PAD_SKEW,
276 "rxd0-skew-ps", "rxd1-skew-ps",
277 "rxd2-skew-ps", "rxd3-skew-ps");
278 ksz9021_load_values_from_of(phydev, of_node,
279 MII_KSZPHY_TX_DATA_PAD_SKEW,
280 "txd0-skew-ps", "txd1-skew-ps",
281 "txd2-skew-ps", "txd3-skew-ps");
282 }
283 return 0;
284}
285
286#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
287#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX (1 << 6)
288#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED (1 << 4)
289static int ksz8873mll_read_status(struct phy_device *phydev)
290{
291 int regval;
292
293 /* dummy read */
294 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
295
296 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
297
298 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
299 phydev->duplex = DUPLEX_HALF;
300 else
301 phydev->duplex = DUPLEX_FULL;
302
303 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
304 phydev->speed = SPEED_10;
305 else
306 phydev->speed = SPEED_100;
307
308 phydev->link = 1;
309 phydev->pause = phydev->asym_pause = 0;
310
311 return 0;
312}
313
314static int ksz8873mll_config_aneg(struct phy_device *phydev)
315{
316 return 0;
317}
318
319static struct phy_driver ksphy_driver[] = {
320{
321 .phy_id = PHY_ID_KS8737,
322 .phy_id_mask = 0x00fffff0,
323 .name = "Micrel KS8737",
324 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
325 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
326 .config_init = kszphy_config_init,
327 .config_aneg = genphy_config_aneg,
328 .read_status = genphy_read_status,
329 .ack_interrupt = kszphy_ack_interrupt,
330 .config_intr = ks8737_config_intr,
331 .suspend = genphy_suspend,
332 .resume = genphy_resume,
333 .driver = { .owner = THIS_MODULE,},
334}, {
335 .phy_id = PHY_ID_KSZ8021,
336 .phy_id_mask = 0x00ffffff,
337 .name = "Micrel KSZ8021 or KSZ8031",
338 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
339 SUPPORTED_Asym_Pause),
340 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
341 .config_init = ksz8021_config_init,
342 .config_aneg = genphy_config_aneg,
343 .read_status = genphy_read_status,
344 .ack_interrupt = kszphy_ack_interrupt,
345 .config_intr = kszphy_config_intr,
346 .suspend = genphy_suspend,
347 .resume = genphy_resume,
348 .driver = { .owner = THIS_MODULE,},
349}, {
350 .phy_id = PHY_ID_KSZ8031,
351 .phy_id_mask = 0x00ffffff,
352 .name = "Micrel KSZ8031",
353 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
354 SUPPORTED_Asym_Pause),
355 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
356 .config_init = ksz8021_config_init,
357 .config_aneg = genphy_config_aneg,
358 .read_status = genphy_read_status,
359 .ack_interrupt = kszphy_ack_interrupt,
360 .config_intr = kszphy_config_intr,
361 .suspend = genphy_suspend,
362 .resume = genphy_resume,
363 .driver = { .owner = THIS_MODULE,},
364}, {
365 .phy_id = PHY_ID_KSZ8041,
366 .phy_id_mask = 0x00fffff0,
367 .name = "Micrel KSZ8041",
368 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
369 | SUPPORTED_Asym_Pause),
370 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
371 .config_init = kszphy_config_init_led8041,
372 .config_aneg = genphy_config_aneg,
373 .read_status = genphy_read_status,
374 .ack_interrupt = kszphy_ack_interrupt,
375 .config_intr = kszphy_config_intr,
376 .suspend = genphy_suspend,
377 .resume = genphy_resume,
378 .driver = { .owner = THIS_MODULE,},
379}, {
380 .phy_id = PHY_ID_KSZ8041RNLI,
381 .phy_id_mask = 0x00fffff0,
382 .name = "Micrel KSZ8041RNLI",
383 .features = PHY_BASIC_FEATURES |
384 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
385 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
386 .config_init = kszphy_config_init_led8041,
387 .config_aneg = genphy_config_aneg,
388 .read_status = genphy_read_status,
389 .ack_interrupt = kszphy_ack_interrupt,
390 .config_intr = kszphy_config_intr,
391 .suspend = genphy_suspend,
392 .resume = genphy_resume,
393 .driver = { .owner = THIS_MODULE,},
394}, {
395 .phy_id = PHY_ID_KSZ8051,
396 .phy_id_mask = 0x00fffff0,
397 .name = "Micrel KSZ8051",
398 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
399 | SUPPORTED_Asym_Pause),
400 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
401 .config_init = ks8051_config_init,
402 .config_aneg = genphy_config_aneg,
403 .read_status = genphy_read_status,
404 .ack_interrupt = kszphy_ack_interrupt,
405 .config_intr = kszphy_config_intr,
406 .suspend = genphy_suspend,
407 .resume = genphy_resume,
408 .driver = { .owner = THIS_MODULE,},
409}, {
410 .phy_id = PHY_ID_KSZ8001,
411 .name = "Micrel KSZ8001 or KS8721",
412 .phy_id_mask = 0x00ffffff,
413 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
414 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
415 .config_init = kszphy_config_init_led8041,
416 .config_aneg = genphy_config_aneg,
417 .read_status = genphy_read_status,
418 .ack_interrupt = kszphy_ack_interrupt,
419 .config_intr = kszphy_config_intr,
420 .suspend = genphy_suspend,
421 .resume = genphy_resume,
422 .driver = { .owner = THIS_MODULE,},
423}, {
424 .phy_id = PHY_ID_KSZ8081,
425 .name = "Micrel KSZ8081 or KSZ8091",
426 .phy_id_mask = 0x00fffff0,
427 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
428 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
429 .config_init = kszphy_config_init,
430 .config_aneg = genphy_config_aneg,
431 .read_status = genphy_read_status,
432 .ack_interrupt = kszphy_ack_interrupt,
433 .config_intr = kszphy_config_intr,
434 .suspend = genphy_suspend,
435 .resume = genphy_resume,
436 .driver = { .owner = THIS_MODULE,},
437}, {
438 .phy_id = PHY_ID_KSZ8061,
439 .name = "Micrel KSZ8061",
440 .phy_id_mask = 0x00fffff0,
441 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
442 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
443 .config_init = kszphy_config_init,
444 .config_aneg = genphy_config_aneg,
445 .read_status = genphy_read_status,
446 .ack_interrupt = kszphy_ack_interrupt,
447 .config_intr = kszphy_config_intr,
448 .suspend = genphy_suspend,
449 .resume = genphy_resume,
450 .driver = { .owner = THIS_MODULE,},
451}, {
452 .phy_id = PHY_ID_KSZ9021,
453 .phy_id_mask = 0x000ffffe,
454 .name = "Micrel KSZ9021 Gigabit PHY",
455 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
456 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
457 .config_init = ksz9021_config_init,
458 .config_aneg = genphy_config_aneg,
459 .read_status = genphy_read_status,
460 .ack_interrupt = kszphy_ack_interrupt,
461 .config_intr = ksz9021_config_intr,
462 .suspend = genphy_suspend,
463 .resume = genphy_resume,
464 .driver = { .owner = THIS_MODULE, },
465}, {
466 .phy_id = PHY_ID_KSZ9031,
467 .phy_id_mask = 0x00fffff0,
468 .name = "Micrel KSZ9031 Gigabit PHY",
469 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause
470 | SUPPORTED_Asym_Pause),
471 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
472 .config_init = kszphy_config_init,
473 .config_aneg = genphy_config_aneg,
474 .read_status = genphy_read_status,
475 .ack_interrupt = kszphy_ack_interrupt,
476 .config_intr = ksz9021_config_intr,
477 .suspend = genphy_suspend,
478 .resume = genphy_resume,
479 .driver = { .owner = THIS_MODULE, },
480}, {
481 .phy_id = PHY_ID_KSZ8873MLL,
482 .phy_id_mask = 0x00fffff0,
483 .name = "Micrel KSZ8873MLL Switch",
484 .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
485 .flags = PHY_HAS_MAGICANEG,
486 .config_init = kszphy_config_init,
487 .config_aneg = ksz8873mll_config_aneg,
488 .read_status = ksz8873mll_read_status,
489 .suspend = genphy_suspend,
490 .resume = genphy_resume,
491 .driver = { .owner = THIS_MODULE, },
492}, {
493 .phy_id = PHY_ID_KSZ886X,
494 .phy_id_mask = 0x00fffff0,
495 .name = "Micrel KSZ886X Switch",
496 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
497 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
498 .config_init = kszphy_config_init,
499 .config_aneg = genphy_config_aneg,
500 .read_status = genphy_read_status,
501 .suspend = genphy_suspend,
502 .resume = genphy_resume,
503 .driver = { .owner = THIS_MODULE, },
504} };
505
506static int __init ksphy_init(void)
507{
508 return phy_drivers_register(ksphy_driver,
509 ARRAY_SIZE(ksphy_driver));
510}
511
512static void __exit ksphy_exit(void)
513{
514 phy_drivers_unregister(ksphy_driver,
515 ARRAY_SIZE(ksphy_driver));
516}
517
518module_init(ksphy_init);
519module_exit(ksphy_exit);
520
521MODULE_DESCRIPTION("Micrel PHY driver");
522MODULE_AUTHOR("David J. Choi");
523MODULE_LICENSE("GPL");
524
525static struct mdio_device_id __maybe_unused micrel_tbl[] = {
526 { PHY_ID_KSZ9021, 0x000ffffe },
527 { PHY_ID_KSZ9031, 0x00fffff0 },
528 { PHY_ID_KSZ8001, 0x00ffffff },
529 { PHY_ID_KS8737, 0x00fffff0 },
530 { PHY_ID_KSZ8021, 0x00ffffff },
531 { PHY_ID_KSZ8031, 0x00ffffff },
532 { PHY_ID_KSZ8041, 0x00fffff0 },
533 { PHY_ID_KSZ8051, 0x00fffff0 },
534 { PHY_ID_KSZ8061, 0x00fffff0 },
535 { PHY_ID_KSZ8081, 0x00fffff0 },
536 { PHY_ID_KSZ8873MLL, 0x00fffff0 },
537 { PHY_ID_KSZ886X, 0x00fffff0 },
538 { }
539};
540
541MODULE_DEVICE_TABLE(mdio, micrel_tbl);
1/*
2 * drivers/net/phy/micrel.c
3 *
4 * Driver for Micrel PHYs
5 *
6 * Author: David J. Choi
7 *
8 * Copyright (c) 2010-2013 Micrel, Inc.
9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * Support : Micrel Phys:
17 * Giga phys: ksz9021, ksz9031
18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
19 * ksz8021, ksz8031, ksz8051,
20 * ksz8081, ksz8091,
21 * ksz8061,
22 * Switch : ksz8873, ksz886x
23 * ksz9477
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/phy.h>
29#include <linux/micrel_phy.h>
30#include <linux/of.h>
31#include <linux/clk.h>
32
33/* Operation Mode Strap Override */
34#define MII_KSZPHY_OMSO 0x16
35#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
36#define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
37#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
38#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
39
40/* general Interrupt control/status reg in vendor specific block. */
41#define MII_KSZPHY_INTCS 0x1B
42#define KSZPHY_INTCS_JABBER BIT(15)
43#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
44#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
45#define KSZPHY_INTCS_PARELLEL BIT(12)
46#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
47#define KSZPHY_INTCS_LINK_DOWN BIT(10)
48#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
49#define KSZPHY_INTCS_LINK_UP BIT(8)
50#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
51 KSZPHY_INTCS_LINK_DOWN)
52
53/* PHY Control 1 */
54#define MII_KSZPHY_CTRL_1 0x1e
55
56/* PHY Control 2 / PHY Control (if no PHY Control 1) */
57#define MII_KSZPHY_CTRL_2 0x1f
58#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
59/* bitmap of PHY register to set interrupt mode */
60#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
61#define KSZPHY_RMII_REF_CLK_SEL BIT(7)
62
63/* Write/read to/from extended registers */
64#define MII_KSZPHY_EXTREG 0x0b
65#define KSZPHY_EXTREG_WRITE 0x8000
66
67#define MII_KSZPHY_EXTREG_WRITE 0x0c
68#define MII_KSZPHY_EXTREG_READ 0x0d
69
70/* Extended registers */
71#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
72#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
73#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
74
75#define PS_TO_REG 200
76
77struct kszphy_hw_stat {
78 const char *string;
79 u8 reg;
80 u8 bits;
81};
82
83static struct kszphy_hw_stat kszphy_hw_stats[] = {
84 { "phy_receive_errors", 21, 16},
85 { "phy_idle_errors", 10, 8 },
86};
87
88struct kszphy_type {
89 u32 led_mode_reg;
90 u16 interrupt_level_mask;
91 bool has_broadcast_disable;
92 bool has_nand_tree_disable;
93 bool has_rmii_ref_clk_sel;
94};
95
96struct kszphy_priv {
97 const struct kszphy_type *type;
98 int led_mode;
99 bool rmii_ref_clk_sel;
100 bool rmii_ref_clk_sel_val;
101 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
102};
103
104static const struct kszphy_type ksz8021_type = {
105 .led_mode_reg = MII_KSZPHY_CTRL_2,
106 .has_broadcast_disable = true,
107 .has_nand_tree_disable = true,
108 .has_rmii_ref_clk_sel = true,
109};
110
111static const struct kszphy_type ksz8041_type = {
112 .led_mode_reg = MII_KSZPHY_CTRL_1,
113};
114
115static const struct kszphy_type ksz8051_type = {
116 .led_mode_reg = MII_KSZPHY_CTRL_2,
117 .has_nand_tree_disable = true,
118};
119
120static const struct kszphy_type ksz8081_type = {
121 .led_mode_reg = MII_KSZPHY_CTRL_2,
122 .has_broadcast_disable = true,
123 .has_nand_tree_disable = true,
124 .has_rmii_ref_clk_sel = true,
125};
126
127static const struct kszphy_type ks8737_type = {
128 .interrupt_level_mask = BIT(14),
129};
130
131static const struct kszphy_type ksz9021_type = {
132 .interrupt_level_mask = BIT(14),
133};
134
135static int kszphy_extended_write(struct phy_device *phydev,
136 u32 regnum, u16 val)
137{
138 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
139 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
140}
141
142static int kszphy_extended_read(struct phy_device *phydev,
143 u32 regnum)
144{
145 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
146 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
147}
148
149static int kszphy_ack_interrupt(struct phy_device *phydev)
150{
151 /* bit[7..0] int status, which is a read and clear register. */
152 int rc;
153
154 rc = phy_read(phydev, MII_KSZPHY_INTCS);
155
156 return (rc < 0) ? rc : 0;
157}
158
159static int kszphy_config_intr(struct phy_device *phydev)
160{
161 const struct kszphy_type *type = phydev->drv->driver_data;
162 int temp;
163 u16 mask;
164
165 if (type && type->interrupt_level_mask)
166 mask = type->interrupt_level_mask;
167 else
168 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
169
170 /* set the interrupt pin active low */
171 temp = phy_read(phydev, MII_KSZPHY_CTRL);
172 if (temp < 0)
173 return temp;
174 temp &= ~mask;
175 phy_write(phydev, MII_KSZPHY_CTRL, temp);
176
177 /* enable / disable interrupts */
178 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
179 temp = KSZPHY_INTCS_ALL;
180 else
181 temp = 0;
182
183 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
184}
185
186static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
187{
188 int ctrl;
189
190 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
191 if (ctrl < 0)
192 return ctrl;
193
194 if (val)
195 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
196 else
197 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
198
199 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
200}
201
202static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
203{
204 int rc, temp, shift;
205
206 switch (reg) {
207 case MII_KSZPHY_CTRL_1:
208 shift = 14;
209 break;
210 case MII_KSZPHY_CTRL_2:
211 shift = 4;
212 break;
213 default:
214 return -EINVAL;
215 }
216
217 temp = phy_read(phydev, reg);
218 if (temp < 0) {
219 rc = temp;
220 goto out;
221 }
222
223 temp &= ~(3 << shift);
224 temp |= val << shift;
225 rc = phy_write(phydev, reg, temp);
226out:
227 if (rc < 0)
228 phydev_err(phydev, "failed to set led mode\n");
229
230 return rc;
231}
232
233/* Disable PHY address 0 as the broadcast address, so that it can be used as a
234 * unique (non-broadcast) address on a shared bus.
235 */
236static int kszphy_broadcast_disable(struct phy_device *phydev)
237{
238 int ret;
239
240 ret = phy_read(phydev, MII_KSZPHY_OMSO);
241 if (ret < 0)
242 goto out;
243
244 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
245out:
246 if (ret)
247 phydev_err(phydev, "failed to disable broadcast address\n");
248
249 return ret;
250}
251
252static int kszphy_nand_tree_disable(struct phy_device *phydev)
253{
254 int ret;
255
256 ret = phy_read(phydev, MII_KSZPHY_OMSO);
257 if (ret < 0)
258 goto out;
259
260 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
261 return 0;
262
263 ret = phy_write(phydev, MII_KSZPHY_OMSO,
264 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
265out:
266 if (ret)
267 phydev_err(phydev, "failed to disable NAND tree mode\n");
268
269 return ret;
270}
271
272/* Some config bits need to be set again on resume, handle them here. */
273static int kszphy_config_reset(struct phy_device *phydev)
274{
275 struct kszphy_priv *priv = phydev->priv;
276 int ret;
277
278 if (priv->rmii_ref_clk_sel) {
279 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
280 if (ret) {
281 phydev_err(phydev,
282 "failed to set rmii reference clock\n");
283 return ret;
284 }
285 }
286
287 if (priv->led_mode >= 0)
288 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
289
290 return 0;
291}
292
293static int kszphy_config_init(struct phy_device *phydev)
294{
295 struct kszphy_priv *priv = phydev->priv;
296 const struct kszphy_type *type;
297
298 if (!priv)
299 return 0;
300
301 type = priv->type;
302
303 if (type->has_broadcast_disable)
304 kszphy_broadcast_disable(phydev);
305
306 if (type->has_nand_tree_disable)
307 kszphy_nand_tree_disable(phydev);
308
309 return kszphy_config_reset(phydev);
310}
311
312static int ksz8041_config_init(struct phy_device *phydev)
313{
314 struct device_node *of_node = phydev->mdio.dev.of_node;
315
316 /* Limit supported and advertised modes in fiber mode */
317 if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
318 phydev->dev_flags |= MICREL_PHY_FXEN;
319 phydev->supported &= SUPPORTED_100baseT_Full |
320 SUPPORTED_100baseT_Half;
321 phydev->supported |= SUPPORTED_FIBRE;
322 phydev->advertising &= ADVERTISED_100baseT_Full |
323 ADVERTISED_100baseT_Half;
324 phydev->advertising |= ADVERTISED_FIBRE;
325 phydev->autoneg = AUTONEG_DISABLE;
326 }
327
328 return kszphy_config_init(phydev);
329}
330
331static int ksz8041_config_aneg(struct phy_device *phydev)
332{
333 /* Skip auto-negotiation in fiber mode */
334 if (phydev->dev_flags & MICREL_PHY_FXEN) {
335 phydev->speed = SPEED_100;
336 return 0;
337 }
338
339 return genphy_config_aneg(phydev);
340}
341
342static int ksz9021_load_values_from_of(struct phy_device *phydev,
343 const struct device_node *of_node,
344 u16 reg,
345 const char *field1, const char *field2,
346 const char *field3, const char *field4)
347{
348 int val1 = -1;
349 int val2 = -2;
350 int val3 = -3;
351 int val4 = -4;
352 int newval;
353 int matches = 0;
354
355 if (!of_property_read_u32(of_node, field1, &val1))
356 matches++;
357
358 if (!of_property_read_u32(of_node, field2, &val2))
359 matches++;
360
361 if (!of_property_read_u32(of_node, field3, &val3))
362 matches++;
363
364 if (!of_property_read_u32(of_node, field4, &val4))
365 matches++;
366
367 if (!matches)
368 return 0;
369
370 if (matches < 4)
371 newval = kszphy_extended_read(phydev, reg);
372 else
373 newval = 0;
374
375 if (val1 != -1)
376 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
377
378 if (val2 != -2)
379 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
380
381 if (val3 != -3)
382 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
383
384 if (val4 != -4)
385 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
386
387 return kszphy_extended_write(phydev, reg, newval);
388}
389
390static int ksz9021_config_init(struct phy_device *phydev)
391{
392 const struct device *dev = &phydev->mdio.dev;
393 const struct device_node *of_node = dev->of_node;
394 const struct device *dev_walker;
395
396 /* The Micrel driver has a deprecated option to place phy OF
397 * properties in the MAC node. Walk up the tree of devices to
398 * find a device with an OF node.
399 */
400 dev_walker = &phydev->mdio.dev;
401 do {
402 of_node = dev_walker->of_node;
403 dev_walker = dev_walker->parent;
404
405 } while (!of_node && dev_walker);
406
407 if (of_node) {
408 ksz9021_load_values_from_of(phydev, of_node,
409 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
410 "txen-skew-ps", "txc-skew-ps",
411 "rxdv-skew-ps", "rxc-skew-ps");
412 ksz9021_load_values_from_of(phydev, of_node,
413 MII_KSZPHY_RX_DATA_PAD_SKEW,
414 "rxd0-skew-ps", "rxd1-skew-ps",
415 "rxd2-skew-ps", "rxd3-skew-ps");
416 ksz9021_load_values_from_of(phydev, of_node,
417 MII_KSZPHY_TX_DATA_PAD_SKEW,
418 "txd0-skew-ps", "txd1-skew-ps",
419 "txd2-skew-ps", "txd3-skew-ps");
420 }
421 return 0;
422}
423
424#define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
425#define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
426#define OP_DATA 1
427#define KSZ9031_PS_TO_REG 60
428
429/* Extended registers */
430/* MMD Address 0x0 */
431#define MII_KSZ9031RN_FLP_BURST_TX_LO 3
432#define MII_KSZ9031RN_FLP_BURST_TX_HI 4
433
434/* MMD Address 0x2 */
435#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
436#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
437#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
438#define MII_KSZ9031RN_CLK_PAD_SKEW 8
439
440/* MMD Address 0x1C */
441#define MII_KSZ9031RN_EDPD 0x23
442#define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
443
444static int ksz9031_extended_write(struct phy_device *phydev,
445 u8 mode, u32 dev_addr, u32 regnum, u16 val)
446{
447 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
448 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
449 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
450 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
451}
452
453static int ksz9031_extended_read(struct phy_device *phydev,
454 u8 mode, u32 dev_addr, u32 regnum)
455{
456 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
457 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
458 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
459 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
460}
461
462static int ksz9031_of_load_skew_values(struct phy_device *phydev,
463 const struct device_node *of_node,
464 u16 reg, size_t field_sz,
465 const char *field[], u8 numfields)
466{
467 int val[4] = {-1, -2, -3, -4};
468 int matches = 0;
469 u16 mask;
470 u16 maxval;
471 u16 newval;
472 int i;
473
474 for (i = 0; i < numfields; i++)
475 if (!of_property_read_u32(of_node, field[i], val + i))
476 matches++;
477
478 if (!matches)
479 return 0;
480
481 if (matches < numfields)
482 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
483 else
484 newval = 0;
485
486 maxval = (field_sz == 4) ? 0xf : 0x1f;
487 for (i = 0; i < numfields; i++)
488 if (val[i] != -(i + 1)) {
489 mask = 0xffff;
490 mask ^= maxval << (field_sz * i);
491 newval = (newval & mask) |
492 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
493 << (field_sz * i));
494 }
495
496 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
497}
498
499/* Center KSZ9031RNX FLP timing at 16ms. */
500static int ksz9031_center_flp_timing(struct phy_device *phydev)
501{
502 int result;
503
504 result = ksz9031_extended_write(phydev, OP_DATA, 0,
505 MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
506 if (result)
507 return result;
508
509 result = ksz9031_extended_write(phydev, OP_DATA, 0,
510 MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
511 if (result)
512 return result;
513
514 return genphy_restart_aneg(phydev);
515}
516
517/* Enable energy-detect power-down mode */
518static int ksz9031_enable_edpd(struct phy_device *phydev)
519{
520 int reg;
521
522 reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD);
523 if (reg < 0)
524 return reg;
525 return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD,
526 reg | MII_KSZ9031RN_EDPD_ENABLE);
527}
528
529static int ksz9031_config_init(struct phy_device *phydev)
530{
531 const struct device *dev = &phydev->mdio.dev;
532 const struct device_node *of_node = dev->of_node;
533 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
534 static const char *rx_data_skews[4] = {
535 "rxd0-skew-ps", "rxd1-skew-ps",
536 "rxd2-skew-ps", "rxd3-skew-ps"
537 };
538 static const char *tx_data_skews[4] = {
539 "txd0-skew-ps", "txd1-skew-ps",
540 "txd2-skew-ps", "txd3-skew-ps"
541 };
542 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
543 const struct device *dev_walker;
544 int result;
545
546 result = ksz9031_enable_edpd(phydev);
547 if (result < 0)
548 return result;
549
550 /* The Micrel driver has a deprecated option to place phy OF
551 * properties in the MAC node. Walk up the tree of devices to
552 * find a device with an OF node.
553 */
554 dev_walker = &phydev->mdio.dev;
555 do {
556 of_node = dev_walker->of_node;
557 dev_walker = dev_walker->parent;
558 } while (!of_node && dev_walker);
559
560 if (of_node) {
561 ksz9031_of_load_skew_values(phydev, of_node,
562 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
563 clk_skews, 2);
564
565 ksz9031_of_load_skew_values(phydev, of_node,
566 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
567 control_skews, 2);
568
569 ksz9031_of_load_skew_values(phydev, of_node,
570 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
571 rx_data_skews, 4);
572
573 ksz9031_of_load_skew_values(phydev, of_node,
574 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
575 tx_data_skews, 4);
576
577 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
578 * When the device links in the 1000BASE-T slave mode only,
579 * the optional 125MHz reference output clock (CLK125_NDO)
580 * has wide duty cycle variation.
581 *
582 * The optional CLK125_NDO clock does not meet the RGMII
583 * 45/55 percent (min/max) duty cycle requirement and therefore
584 * cannot be used directly by the MAC side for clocking
585 * applications that have setup/hold time requirements on
586 * rising and falling clock edges.
587 *
588 * Workaround:
589 * Force the phy to be the master to receive a stable clock
590 * which meets the duty cycle requirement.
591 */
592 if (of_property_read_bool(of_node, "micrel,force-master")) {
593 result = phy_read(phydev, MII_CTRL1000);
594 if (result < 0)
595 goto err_force_master;
596
597 /* enable master mode, config & prefer master */
598 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
599 result = phy_write(phydev, MII_CTRL1000, result);
600 if (result < 0)
601 goto err_force_master;
602 }
603 }
604
605 return ksz9031_center_flp_timing(phydev);
606
607err_force_master:
608 phydev_err(phydev, "failed to force the phy to master mode\n");
609 return result;
610}
611
612#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
613#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
614#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
615static int ksz8873mll_read_status(struct phy_device *phydev)
616{
617 int regval;
618
619 /* dummy read */
620 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
621
622 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
623
624 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
625 phydev->duplex = DUPLEX_HALF;
626 else
627 phydev->duplex = DUPLEX_FULL;
628
629 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
630 phydev->speed = SPEED_10;
631 else
632 phydev->speed = SPEED_100;
633
634 phydev->link = 1;
635 phydev->pause = phydev->asym_pause = 0;
636
637 return 0;
638}
639
640static int ksz9031_read_status(struct phy_device *phydev)
641{
642 int err;
643 int regval;
644
645 err = genphy_read_status(phydev);
646 if (err)
647 return err;
648
649 /* Make sure the PHY is not broken. Read idle error count,
650 * and reset the PHY if it is maxed out.
651 */
652 regval = phy_read(phydev, MII_STAT1000);
653 if ((regval & 0xFF) == 0xFF) {
654 phy_init_hw(phydev);
655 phydev->link = 0;
656 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
657 phydev->drv->config_intr(phydev);
658 return genphy_config_aneg(phydev);
659 }
660
661 return 0;
662}
663
664static int ksz8873mll_config_aneg(struct phy_device *phydev)
665{
666 return 0;
667}
668
669static int kszphy_get_sset_count(struct phy_device *phydev)
670{
671 return ARRAY_SIZE(kszphy_hw_stats);
672}
673
674static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
675{
676 int i;
677
678 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
679 strlcpy(data + i * ETH_GSTRING_LEN,
680 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
681 }
682}
683
684#ifndef UINT64_MAX
685#define UINT64_MAX (u64)(~((u64)0))
686#endif
687static u64 kszphy_get_stat(struct phy_device *phydev, int i)
688{
689 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
690 struct kszphy_priv *priv = phydev->priv;
691 int val;
692 u64 ret;
693
694 val = phy_read(phydev, stat.reg);
695 if (val < 0) {
696 ret = UINT64_MAX;
697 } else {
698 val = val & ((1 << stat.bits) - 1);
699 priv->stats[i] += val;
700 ret = priv->stats[i];
701 }
702
703 return ret;
704}
705
706static void kszphy_get_stats(struct phy_device *phydev,
707 struct ethtool_stats *stats, u64 *data)
708{
709 int i;
710
711 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
712 data[i] = kszphy_get_stat(phydev, i);
713}
714
715static int kszphy_suspend(struct phy_device *phydev)
716{
717 /* Disable PHY Interrupts */
718 if (phy_interrupt_is_valid(phydev)) {
719 phydev->interrupts = PHY_INTERRUPT_DISABLED;
720 if (phydev->drv->config_intr)
721 phydev->drv->config_intr(phydev);
722 }
723
724 return genphy_suspend(phydev);
725}
726
727static int kszphy_resume(struct phy_device *phydev)
728{
729 int ret;
730
731 genphy_resume(phydev);
732
733 ret = kszphy_config_reset(phydev);
734 if (ret)
735 return ret;
736
737 /* Enable PHY Interrupts */
738 if (phy_interrupt_is_valid(phydev)) {
739 phydev->interrupts = PHY_INTERRUPT_ENABLED;
740 if (phydev->drv->config_intr)
741 phydev->drv->config_intr(phydev);
742 }
743
744 return 0;
745}
746
747static int kszphy_probe(struct phy_device *phydev)
748{
749 const struct kszphy_type *type = phydev->drv->driver_data;
750 const struct device_node *np = phydev->mdio.dev.of_node;
751 struct kszphy_priv *priv;
752 struct clk *clk;
753 int ret;
754
755 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
756 if (!priv)
757 return -ENOMEM;
758
759 phydev->priv = priv;
760
761 priv->type = type;
762
763 if (type->led_mode_reg) {
764 ret = of_property_read_u32(np, "micrel,led-mode",
765 &priv->led_mode);
766 if (ret)
767 priv->led_mode = -1;
768
769 if (priv->led_mode > 3) {
770 phydev_err(phydev, "invalid led mode: 0x%02x\n",
771 priv->led_mode);
772 priv->led_mode = -1;
773 }
774 } else {
775 priv->led_mode = -1;
776 }
777
778 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
779 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
780 if (!IS_ERR_OR_NULL(clk)) {
781 unsigned long rate = clk_get_rate(clk);
782 bool rmii_ref_clk_sel_25_mhz;
783
784 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
785 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
786 "micrel,rmii-reference-clock-select-25-mhz");
787
788 if (rate > 24500000 && rate < 25500000) {
789 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
790 } else if (rate > 49500000 && rate < 50500000) {
791 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
792 } else {
793 phydev_err(phydev, "Clock rate out of range: %ld\n",
794 rate);
795 return -EINVAL;
796 }
797 }
798
799 /* Support legacy board-file configuration */
800 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
801 priv->rmii_ref_clk_sel = true;
802 priv->rmii_ref_clk_sel_val = true;
803 }
804
805 return 0;
806}
807
808static struct phy_driver ksphy_driver[] = {
809{
810 .phy_id = PHY_ID_KS8737,
811 .phy_id_mask = MICREL_PHY_ID_MASK,
812 .name = "Micrel KS8737",
813 .features = PHY_BASIC_FEATURES,
814 .flags = PHY_HAS_INTERRUPT,
815 .driver_data = &ks8737_type,
816 .config_init = kszphy_config_init,
817 .ack_interrupt = kszphy_ack_interrupt,
818 .config_intr = kszphy_config_intr,
819 .suspend = genphy_suspend,
820 .resume = genphy_resume,
821}, {
822 .phy_id = PHY_ID_KSZ8021,
823 .phy_id_mask = 0x00ffffff,
824 .name = "Micrel KSZ8021 or KSZ8031",
825 .features = PHY_BASIC_FEATURES,
826 .flags = PHY_HAS_INTERRUPT,
827 .driver_data = &ksz8021_type,
828 .probe = kszphy_probe,
829 .config_init = kszphy_config_init,
830 .ack_interrupt = kszphy_ack_interrupt,
831 .config_intr = kszphy_config_intr,
832 .get_sset_count = kszphy_get_sset_count,
833 .get_strings = kszphy_get_strings,
834 .get_stats = kszphy_get_stats,
835 .suspend = genphy_suspend,
836 .resume = genphy_resume,
837}, {
838 .phy_id = PHY_ID_KSZ8031,
839 .phy_id_mask = 0x00ffffff,
840 .name = "Micrel KSZ8031",
841 .features = PHY_BASIC_FEATURES,
842 .flags = PHY_HAS_INTERRUPT,
843 .driver_data = &ksz8021_type,
844 .probe = kszphy_probe,
845 .config_init = kszphy_config_init,
846 .ack_interrupt = kszphy_ack_interrupt,
847 .config_intr = kszphy_config_intr,
848 .get_sset_count = kszphy_get_sset_count,
849 .get_strings = kszphy_get_strings,
850 .get_stats = kszphy_get_stats,
851 .suspend = genphy_suspend,
852 .resume = genphy_resume,
853}, {
854 .phy_id = PHY_ID_KSZ8041,
855 .phy_id_mask = MICREL_PHY_ID_MASK,
856 .name = "Micrel KSZ8041",
857 .features = PHY_BASIC_FEATURES,
858 .flags = PHY_HAS_INTERRUPT,
859 .driver_data = &ksz8041_type,
860 .probe = kszphy_probe,
861 .config_init = ksz8041_config_init,
862 .config_aneg = ksz8041_config_aneg,
863 .ack_interrupt = kszphy_ack_interrupt,
864 .config_intr = kszphy_config_intr,
865 .get_sset_count = kszphy_get_sset_count,
866 .get_strings = kszphy_get_strings,
867 .get_stats = kszphy_get_stats,
868 .suspend = genphy_suspend,
869 .resume = genphy_resume,
870}, {
871 .phy_id = PHY_ID_KSZ8041RNLI,
872 .phy_id_mask = MICREL_PHY_ID_MASK,
873 .name = "Micrel KSZ8041RNLI",
874 .features = PHY_BASIC_FEATURES,
875 .flags = PHY_HAS_INTERRUPT,
876 .driver_data = &ksz8041_type,
877 .probe = kszphy_probe,
878 .config_init = kszphy_config_init,
879 .ack_interrupt = kszphy_ack_interrupt,
880 .config_intr = kszphy_config_intr,
881 .get_sset_count = kszphy_get_sset_count,
882 .get_strings = kszphy_get_strings,
883 .get_stats = kszphy_get_stats,
884 .suspend = genphy_suspend,
885 .resume = genphy_resume,
886}, {
887 .phy_id = PHY_ID_KSZ8051,
888 .phy_id_mask = MICREL_PHY_ID_MASK,
889 .name = "Micrel KSZ8051",
890 .features = PHY_BASIC_FEATURES,
891 .flags = PHY_HAS_INTERRUPT,
892 .driver_data = &ksz8051_type,
893 .probe = kszphy_probe,
894 .config_init = kszphy_config_init,
895 .ack_interrupt = kszphy_ack_interrupt,
896 .config_intr = kszphy_config_intr,
897 .get_sset_count = kszphy_get_sset_count,
898 .get_strings = kszphy_get_strings,
899 .get_stats = kszphy_get_stats,
900 .suspend = genphy_suspend,
901 .resume = genphy_resume,
902}, {
903 .phy_id = PHY_ID_KSZ8001,
904 .name = "Micrel KSZ8001 or KS8721",
905 .phy_id_mask = 0x00fffffc,
906 .features = PHY_BASIC_FEATURES,
907 .flags = PHY_HAS_INTERRUPT,
908 .driver_data = &ksz8041_type,
909 .probe = kszphy_probe,
910 .config_init = kszphy_config_init,
911 .ack_interrupt = kszphy_ack_interrupt,
912 .config_intr = kszphy_config_intr,
913 .get_sset_count = kszphy_get_sset_count,
914 .get_strings = kszphy_get_strings,
915 .get_stats = kszphy_get_stats,
916 .suspend = genphy_suspend,
917 .resume = genphy_resume,
918}, {
919 .phy_id = PHY_ID_KSZ8081,
920 .name = "Micrel KSZ8081 or KSZ8091",
921 .phy_id_mask = MICREL_PHY_ID_MASK,
922 .features = PHY_BASIC_FEATURES,
923 .flags = PHY_HAS_INTERRUPT,
924 .driver_data = &ksz8081_type,
925 .probe = kszphy_probe,
926 .config_init = kszphy_config_init,
927 .ack_interrupt = kszphy_ack_interrupt,
928 .config_intr = kszphy_config_intr,
929 .get_sset_count = kszphy_get_sset_count,
930 .get_strings = kszphy_get_strings,
931 .get_stats = kszphy_get_stats,
932 .suspend = kszphy_suspend,
933 .resume = kszphy_resume,
934}, {
935 .phy_id = PHY_ID_KSZ8061,
936 .name = "Micrel KSZ8061",
937 .phy_id_mask = MICREL_PHY_ID_MASK,
938 .features = PHY_BASIC_FEATURES,
939 .flags = PHY_HAS_INTERRUPT,
940 .config_init = kszphy_config_init,
941 .ack_interrupt = kszphy_ack_interrupt,
942 .config_intr = kszphy_config_intr,
943 .suspend = genphy_suspend,
944 .resume = genphy_resume,
945}, {
946 .phy_id = PHY_ID_KSZ9021,
947 .phy_id_mask = 0x000ffffe,
948 .name = "Micrel KSZ9021 Gigabit PHY",
949 .features = PHY_GBIT_FEATURES,
950 .flags = PHY_HAS_INTERRUPT,
951 .driver_data = &ksz9021_type,
952 .probe = kszphy_probe,
953 .config_init = ksz9021_config_init,
954 .ack_interrupt = kszphy_ack_interrupt,
955 .config_intr = kszphy_config_intr,
956 .get_sset_count = kszphy_get_sset_count,
957 .get_strings = kszphy_get_strings,
958 .get_stats = kszphy_get_stats,
959 .suspend = genphy_suspend,
960 .resume = genphy_resume,
961 .read_mmd = genphy_read_mmd_unsupported,
962 .write_mmd = genphy_write_mmd_unsupported,
963}, {
964 .phy_id = PHY_ID_KSZ9031,
965 .phy_id_mask = MICREL_PHY_ID_MASK,
966 .name = "Micrel KSZ9031 Gigabit PHY",
967 .features = PHY_GBIT_FEATURES,
968 .flags = PHY_HAS_INTERRUPT,
969 .driver_data = &ksz9021_type,
970 .probe = kszphy_probe,
971 .config_init = ksz9031_config_init,
972 .read_status = ksz9031_read_status,
973 .ack_interrupt = kszphy_ack_interrupt,
974 .config_intr = kszphy_config_intr,
975 .get_sset_count = kszphy_get_sset_count,
976 .get_strings = kszphy_get_strings,
977 .get_stats = kszphy_get_stats,
978 .suspend = genphy_suspend,
979 .resume = kszphy_resume,
980}, {
981 .phy_id = PHY_ID_KSZ8873MLL,
982 .phy_id_mask = MICREL_PHY_ID_MASK,
983 .name = "Micrel KSZ8873MLL Switch",
984 .config_init = kszphy_config_init,
985 .config_aneg = ksz8873mll_config_aneg,
986 .read_status = ksz8873mll_read_status,
987 .suspend = genphy_suspend,
988 .resume = genphy_resume,
989}, {
990 .phy_id = PHY_ID_KSZ886X,
991 .phy_id_mask = MICREL_PHY_ID_MASK,
992 .name = "Micrel KSZ886X Switch",
993 .features = PHY_BASIC_FEATURES,
994 .flags = PHY_HAS_INTERRUPT,
995 .config_init = kszphy_config_init,
996 .suspend = genphy_suspend,
997 .resume = genphy_resume,
998}, {
999 .phy_id = PHY_ID_KSZ8795,
1000 .phy_id_mask = MICREL_PHY_ID_MASK,
1001 .name = "Micrel KSZ8795",
1002 .features = PHY_BASIC_FEATURES,
1003 .flags = PHY_HAS_INTERRUPT,
1004 .config_init = kszphy_config_init,
1005 .config_aneg = ksz8873mll_config_aneg,
1006 .read_status = ksz8873mll_read_status,
1007 .suspend = genphy_suspend,
1008 .resume = genphy_resume,
1009}, {
1010 .phy_id = PHY_ID_KSZ9477,
1011 .phy_id_mask = MICREL_PHY_ID_MASK,
1012 .name = "Microchip KSZ9477",
1013 .features = PHY_GBIT_FEATURES,
1014 .config_init = kszphy_config_init,
1015 .suspend = genphy_suspend,
1016 .resume = genphy_resume,
1017} };
1018
1019module_phy_driver(ksphy_driver);
1020
1021MODULE_DESCRIPTION("Micrel PHY driver");
1022MODULE_AUTHOR("David J. Choi");
1023MODULE_LICENSE("GPL");
1024
1025static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1026 { PHY_ID_KSZ9021, 0x000ffffe },
1027 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1028 { PHY_ID_KSZ8001, 0x00fffffc },
1029 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1030 { PHY_ID_KSZ8021, 0x00ffffff },
1031 { PHY_ID_KSZ8031, 0x00ffffff },
1032 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1033 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1034 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1035 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1036 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1037 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1038 { }
1039};
1040
1041MODULE_DEVICE_TABLE(mdio, micrel_tbl);