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1/*
2 * drivers/net/phy/broadcom.c
3 *
4 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
5 * transceivers.
6 *
7 * Copyright (c) 2006 Maciej W. Rozycki
8 *
9 * Inspired by code written by Amy Fong.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16
17#include <linux/module.h>
18#include <linux/phy.h>
19#include <linux/brcmphy.h>
20
21
22#define BRCM_PHY_MODEL(phydev) \
23 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
24
25#define BRCM_PHY_REV(phydev) \
26 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
27
28/*
29 * Broadcom LED source encodings. These are used in BCM5461, BCM5481,
30 * BCM5482, and possibly some others.
31 */
32#define BCM_LED_SRC_LINKSPD1 0x0
33#define BCM_LED_SRC_LINKSPD2 0x1
34#define BCM_LED_SRC_XMITLED 0x2
35#define BCM_LED_SRC_ACTIVITYLED 0x3
36#define BCM_LED_SRC_FDXLED 0x4
37#define BCM_LED_SRC_SLAVE 0x5
38#define BCM_LED_SRC_INTR 0x6
39#define BCM_LED_SRC_QUALITY 0x7
40#define BCM_LED_SRC_RCVLED 0x8
41#define BCM_LED_SRC_MULTICOLOR1 0xa
42#define BCM_LED_SRC_OPENSHORT 0xb
43#define BCM_LED_SRC_OFF 0xe /* Tied high */
44#define BCM_LED_SRC_ON 0xf /* Tied low */
45
46
47/*
48 * BCM5482: Shadow registers
49 * Shadow values go into bits [14:10] of register 0x1c to select a shadow
50 * register to access.
51 */
52/* 00101: Spare Control Register 3 */
53#define BCM54XX_SHD_SCR3 0x05
54#define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001
55#define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002
56#define BCM54XX_SHD_SCR3_TRDDAPD 0x0004
57
58/* 01010: Auto Power-Down */
59#define BCM54XX_SHD_APD 0x0a
60#define BCM54XX_SHD_APD_EN 0x0020
61
62#define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */
63 /* LED3 / ~LINKSPD[2] selector */
64#define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4)
65 /* LED1 / ~LINKSPD[1] selector */
66#define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0)
67#define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */
68#define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */
69#define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */
70#define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */
71#define BCM5482_SHD_MODE 0x1f /* 11111: Mode Control Register */
72#define BCM5482_SHD_MODE_1000BX 0x0001 /* Enable 1000BASE-X registers */
73
74
75/*
76 * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17)
77 */
78#define MII_BCM54XX_EXP_AADJ1CH0 0x001f
79#define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200
80#define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100
81#define MII_BCM54XX_EXP_AADJ1CH3 0x601f
82#define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002
83#define MII_BCM54XX_EXP_EXP08 0x0F08
84#define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001
85#define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200
86#define MII_BCM54XX_EXP_EXP75 0x0f75
87#define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c
88#define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001
89#define MII_BCM54XX_EXP_EXP96 0x0f96
90#define MII_BCM54XX_EXP_EXP96_MYST 0x0010
91#define MII_BCM54XX_EXP_EXP97 0x0f97
92#define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c
93
94/*
95 * BCM5482: Secondary SerDes registers
96 */
97#define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */
98#define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */
99#define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */
100#define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
101#define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
102
103
104/*****************************************************************************/
105/* Fast Ethernet Transceiver definitions. */
106/*****************************************************************************/
107
108#define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */
109#define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */
110#define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */
111#define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */
112#define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */
113#define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */
114
115#define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */
116#define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */
117
118
119/*** Shadow register definitions ***/
120
121#define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */
122#define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */
123
124#define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */
125#define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003
126#define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001
127
128#define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */
129#define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */
130
131
132MODULE_DESCRIPTION("Broadcom PHY driver");
133MODULE_AUTHOR("Maciej W. Rozycki");
134MODULE_LICENSE("GPL");
135
136/*
137 * Indirect register access functions for the 1000BASE-T/100BASE-TX/10BASE-T
138 * 0x1c shadow registers.
139 */
140static int bcm54xx_shadow_read(struct phy_device *phydev, u16 shadow)
141{
142 phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
143 return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
144}
145
146static int bcm54xx_shadow_write(struct phy_device *phydev, u16 shadow, u16 val)
147{
148 return phy_write(phydev, MII_BCM54XX_SHD,
149 MII_BCM54XX_SHD_WRITE |
150 MII_BCM54XX_SHD_VAL(shadow) |
151 MII_BCM54XX_SHD_DATA(val));
152}
153
154/* Indirect register access functions for the Expansion Registers */
155static int bcm54xx_exp_read(struct phy_device *phydev, u16 regnum)
156{
157 int val;
158
159 val = phy_write(phydev, MII_BCM54XX_EXP_SEL, regnum);
160 if (val < 0)
161 return val;
162
163 val = phy_read(phydev, MII_BCM54XX_EXP_DATA);
164
165 /* Restore default value. It's O.K. if this write fails. */
166 phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
167
168 return val;
169}
170
171static int bcm54xx_exp_write(struct phy_device *phydev, u16 regnum, u16 val)
172{
173 int ret;
174
175 ret = phy_write(phydev, MII_BCM54XX_EXP_SEL, regnum);
176 if (ret < 0)
177 return ret;
178
179 ret = phy_write(phydev, MII_BCM54XX_EXP_DATA, val);
180
181 /* Restore default value. It's O.K. if this write fails. */
182 phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
183
184 return ret;
185}
186
187static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
188{
189 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
190}
191
192/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
193static int bcm50610_a0_workaround(struct phy_device *phydev)
194{
195 int err;
196
197 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_AADJ1CH0,
198 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
199 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
200 if (err < 0)
201 return err;
202
203 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_AADJ1CH3,
204 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
205 if (err < 0)
206 return err;
207
208 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP75,
209 MII_BCM54XX_EXP_EXP75_VDACCTRL);
210 if (err < 0)
211 return err;
212
213 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP96,
214 MII_BCM54XX_EXP_EXP96_MYST);
215 if (err < 0)
216 return err;
217
218 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP97,
219 MII_BCM54XX_EXP_EXP97_MYST);
220
221 return err;
222}
223
224static int bcm54xx_phydsp_config(struct phy_device *phydev)
225{
226 int err, err2;
227
228 /* Enable the SMDSP clock */
229 err = bcm54xx_auxctl_write(phydev,
230 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
231 MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
232 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
233 if (err < 0)
234 return err;
235
236 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
237 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
238 /* Clear bit 9 to fix a phy interop issue. */
239 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP08,
240 MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
241 if (err < 0)
242 goto error;
243
244 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
245 err = bcm50610_a0_workaround(phydev);
246 if (err < 0)
247 goto error;
248 }
249 }
250
251 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
252 int val;
253
254 val = bcm54xx_exp_read(phydev, MII_BCM54XX_EXP_EXP75);
255 if (val < 0)
256 goto error;
257
258 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
259 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP75, val);
260 }
261
262error:
263 /* Disable the SMDSP clock */
264 err2 = bcm54xx_auxctl_write(phydev,
265 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
266 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
267
268 /* Return the first error reported. */
269 return err ? err : err2;
270}
271
272static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
273{
274 u32 orig;
275 int val;
276 bool clk125en = true;
277
278 /* Abort if we are using an untested phy. */
279 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
280 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
281 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M)
282 return;
283
284 val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_SCR3);
285 if (val < 0)
286 return;
287
288 orig = val;
289
290 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
291 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
292 BRCM_PHY_REV(phydev) >= 0x3) {
293 /*
294 * Here, bit 0 _disables_ CLK125 when set.
295 * This bit is set by default.
296 */
297 clk125en = false;
298 } else {
299 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
300 /* Here, bit 0 _enables_ CLK125 when set */
301 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
302 clk125en = false;
303 }
304 }
305
306 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
307 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
308 else
309 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
310
311 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY)
312 val |= BCM54XX_SHD_SCR3_TRDDAPD;
313
314 if (orig != val)
315 bcm54xx_shadow_write(phydev, BCM54XX_SHD_SCR3, val);
316
317 val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_APD);
318 if (val < 0)
319 return;
320
321 orig = val;
322
323 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
324 val |= BCM54XX_SHD_APD_EN;
325 else
326 val &= ~BCM54XX_SHD_APD_EN;
327
328 if (orig != val)
329 bcm54xx_shadow_write(phydev, BCM54XX_SHD_APD, val);
330}
331
332static int bcm54xx_config_init(struct phy_device *phydev)
333{
334 int reg, err;
335
336 reg = phy_read(phydev, MII_BCM54XX_ECR);
337 if (reg < 0)
338 return reg;
339
340 /* Mask interrupts globally. */
341 reg |= MII_BCM54XX_ECR_IM;
342 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
343 if (err < 0)
344 return err;
345
346 /* Unmask events we are interested in. */
347 reg = ~(MII_BCM54XX_INT_DUPLEX |
348 MII_BCM54XX_INT_SPEED |
349 MII_BCM54XX_INT_LINK);
350 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
351 if (err < 0)
352 return err;
353
354 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
355 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
356 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
357 bcm54xx_shadow_write(phydev, BCM54XX_SHD_RGMII_MODE, 0);
358
359 if ((phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) ||
360 (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) ||
361 (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
362 bcm54xx_adjust_rxrefclk(phydev);
363
364 bcm54xx_phydsp_config(phydev);
365
366 return 0;
367}
368
369static int bcm5482_config_init(struct phy_device *phydev)
370{
371 int err, reg;
372
373 err = bcm54xx_config_init(phydev);
374
375 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
376 /*
377 * Enable secondary SerDes and its use as an LED source
378 */
379 reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_SSD);
380 bcm54xx_shadow_write(phydev, BCM5482_SHD_SSD,
381 reg |
382 BCM5482_SHD_SSD_LEDM |
383 BCM5482_SHD_SSD_EN);
384
385 /*
386 * Enable SGMII slave mode and auto-detection
387 */
388 reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD;
389 err = bcm54xx_exp_read(phydev, reg);
390 if (err < 0)
391 return err;
392 err = bcm54xx_exp_write(phydev, reg, err |
393 BCM5482_SSD_SGMII_SLAVE_EN |
394 BCM5482_SSD_SGMII_SLAVE_AD);
395 if (err < 0)
396 return err;
397
398 /*
399 * Disable secondary SerDes powerdown
400 */
401 reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD;
402 err = bcm54xx_exp_read(phydev, reg);
403 if (err < 0)
404 return err;
405 err = bcm54xx_exp_write(phydev, reg,
406 err & ~BCM5482_SSD_1000BX_CTL_PWRDOWN);
407 if (err < 0)
408 return err;
409
410 /*
411 * Select 1000BASE-X register set (primary SerDes)
412 */
413 reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_MODE);
414 bcm54xx_shadow_write(phydev, BCM5482_SHD_MODE,
415 reg | BCM5482_SHD_MODE_1000BX);
416
417 /*
418 * LED1=ACTIVITYLED, LED3=LINKSPD[2]
419 * (Use LED1 as secondary SerDes ACTIVITY LED)
420 */
421 bcm54xx_shadow_write(phydev, BCM5482_SHD_LEDS1,
422 BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
423 BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
424
425 /*
426 * Auto-negotiation doesn't seem to work quite right
427 * in this mode, so we disable it and force it to the
428 * right speed/duplex setting. Only 'link status'
429 * is important.
430 */
431 phydev->autoneg = AUTONEG_DISABLE;
432 phydev->speed = SPEED_1000;
433 phydev->duplex = DUPLEX_FULL;
434 }
435
436 return err;
437}
438
439static int bcm5482_read_status(struct phy_device *phydev)
440{
441 int err;
442
443 err = genphy_read_status(phydev);
444
445 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
446 /*
447 * Only link status matters for 1000Base-X mode, so force
448 * 1000 Mbit/s full-duplex status
449 */
450 if (phydev->link) {
451 phydev->speed = SPEED_1000;
452 phydev->duplex = DUPLEX_FULL;
453 }
454 }
455
456 return err;
457}
458
459static int bcm54xx_ack_interrupt(struct phy_device *phydev)
460{
461 int reg;
462
463 /* Clear pending interrupts. */
464 reg = phy_read(phydev, MII_BCM54XX_ISR);
465 if (reg < 0)
466 return reg;
467
468 return 0;
469}
470
471static int bcm54xx_config_intr(struct phy_device *phydev)
472{
473 int reg, err;
474
475 reg = phy_read(phydev, MII_BCM54XX_ECR);
476 if (reg < 0)
477 return reg;
478
479 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
480 reg &= ~MII_BCM54XX_ECR_IM;
481 else
482 reg |= MII_BCM54XX_ECR_IM;
483
484 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
485 return err;
486}
487
488static int bcm5481_config_aneg(struct phy_device *phydev)
489{
490 int ret;
491
492 /* Aneg firsly. */
493 ret = genphy_config_aneg(phydev);
494
495 /* Then we can set up the delay. */
496 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
497 u16 reg;
498
499 /*
500 * There is no BCM5481 specification available, so down
501 * here is everything we know about "register 0x18". This
502 * at least helps BCM5481 to successfully receive packets
503 * on MPC8360E-RDK board. Peter Barada <peterb@logicpd.com>
504 * says: "This sets delay between the RXD and RXC signals
505 * instead of using trace lengths to achieve timing".
506 */
507
508 /* Set RDX clk delay. */
509 reg = 0x7 | (0x7 << 12);
510 phy_write(phydev, 0x18, reg);
511
512 reg = phy_read(phydev, 0x18);
513 /* Set RDX-RXC skew. */
514 reg |= (1 << 8);
515 /* Write bits 14:0. */
516 reg |= (1 << 15);
517 phy_write(phydev, 0x18, reg);
518 }
519
520 return ret;
521}
522
523static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
524{
525 int val;
526
527 val = phy_read(phydev, reg);
528 if (val < 0)
529 return val;
530
531 return phy_write(phydev, reg, val | set);
532}
533
534static int brcm_fet_config_init(struct phy_device *phydev)
535{
536 int reg, err, err2, brcmtest;
537
538 /* Reset the PHY to bring it to a known state. */
539 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
540 if (err < 0)
541 return err;
542
543 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
544 if (reg < 0)
545 return reg;
546
547 /* Unmask events we are interested in and mask interrupts globally. */
548 reg = MII_BRCM_FET_IR_DUPLEX_EN |
549 MII_BRCM_FET_IR_SPEED_EN |
550 MII_BRCM_FET_IR_LINK_EN |
551 MII_BRCM_FET_IR_ENABLE |
552 MII_BRCM_FET_IR_MASK;
553
554 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
555 if (err < 0)
556 return err;
557
558 /* Enable shadow register access */
559 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
560 if (brcmtest < 0)
561 return brcmtest;
562
563 reg = brcmtest | MII_BRCM_FET_BT_SRE;
564
565 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
566 if (err < 0)
567 return err;
568
569 /* Set the LED mode */
570 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
571 if (reg < 0) {
572 err = reg;
573 goto done;
574 }
575
576 reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
577 reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
578
579 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
580 if (err < 0)
581 goto done;
582
583 /* Enable auto MDIX */
584 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
585 MII_BRCM_FET_SHDW_MC_FAME);
586 if (err < 0)
587 goto done;
588
589 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
590 /* Enable auto power down */
591 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
592 MII_BRCM_FET_SHDW_AS2_APDE);
593 }
594
595done:
596 /* Disable shadow register access */
597 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
598 if (!err)
599 err = err2;
600
601 return err;
602}
603
604static int brcm_fet_ack_interrupt(struct phy_device *phydev)
605{
606 int reg;
607
608 /* Clear pending interrupts. */
609 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
610 if (reg < 0)
611 return reg;
612
613 return 0;
614}
615
616static int brcm_fet_config_intr(struct phy_device *phydev)
617{
618 int reg, err;
619
620 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
621 if (reg < 0)
622 return reg;
623
624 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
625 reg &= ~MII_BRCM_FET_IR_MASK;
626 else
627 reg |= MII_BRCM_FET_IR_MASK;
628
629 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
630 return err;
631}
632
633static struct phy_driver broadcom_drivers[] = {
634{
635 .phy_id = PHY_ID_BCM5411,
636 .phy_id_mask = 0xfffffff0,
637 .name = "Broadcom BCM5411",
638 .features = PHY_GBIT_FEATURES |
639 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
640 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
641 .config_init = bcm54xx_config_init,
642 .config_aneg = genphy_config_aneg,
643 .read_status = genphy_read_status,
644 .ack_interrupt = bcm54xx_ack_interrupt,
645 .config_intr = bcm54xx_config_intr,
646 .driver = { .owner = THIS_MODULE },
647}, {
648 .phy_id = PHY_ID_BCM5421,
649 .phy_id_mask = 0xfffffff0,
650 .name = "Broadcom BCM5421",
651 .features = PHY_GBIT_FEATURES |
652 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
653 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
654 .config_init = bcm54xx_config_init,
655 .config_aneg = genphy_config_aneg,
656 .read_status = genphy_read_status,
657 .ack_interrupt = bcm54xx_ack_interrupt,
658 .config_intr = bcm54xx_config_intr,
659 .driver = { .owner = THIS_MODULE },
660}, {
661 .phy_id = PHY_ID_BCM5461,
662 .phy_id_mask = 0xfffffff0,
663 .name = "Broadcom BCM5461",
664 .features = PHY_GBIT_FEATURES |
665 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
666 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
667 .config_init = bcm54xx_config_init,
668 .config_aneg = genphy_config_aneg,
669 .read_status = genphy_read_status,
670 .ack_interrupt = bcm54xx_ack_interrupt,
671 .config_intr = bcm54xx_config_intr,
672 .driver = { .owner = THIS_MODULE },
673}, {
674 .phy_id = PHY_ID_BCM5464,
675 .phy_id_mask = 0xfffffff0,
676 .name = "Broadcom BCM5464",
677 .features = PHY_GBIT_FEATURES |
678 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
679 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
680 .config_init = bcm54xx_config_init,
681 .config_aneg = genphy_config_aneg,
682 .read_status = genphy_read_status,
683 .ack_interrupt = bcm54xx_ack_interrupt,
684 .config_intr = bcm54xx_config_intr,
685 .driver = { .owner = THIS_MODULE },
686}, {
687 .phy_id = PHY_ID_BCM5481,
688 .phy_id_mask = 0xfffffff0,
689 .name = "Broadcom BCM5481",
690 .features = PHY_GBIT_FEATURES |
691 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
692 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
693 .config_init = bcm54xx_config_init,
694 .config_aneg = bcm5481_config_aneg,
695 .read_status = genphy_read_status,
696 .ack_interrupt = bcm54xx_ack_interrupt,
697 .config_intr = bcm54xx_config_intr,
698 .driver = { .owner = THIS_MODULE },
699}, {
700 .phy_id = PHY_ID_BCM5482,
701 .phy_id_mask = 0xfffffff0,
702 .name = "Broadcom BCM5482",
703 .features = PHY_GBIT_FEATURES |
704 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
705 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
706 .config_init = bcm5482_config_init,
707 .config_aneg = genphy_config_aneg,
708 .read_status = bcm5482_read_status,
709 .ack_interrupt = bcm54xx_ack_interrupt,
710 .config_intr = bcm54xx_config_intr,
711 .driver = { .owner = THIS_MODULE },
712}, {
713 .phy_id = PHY_ID_BCM50610,
714 .phy_id_mask = 0xfffffff0,
715 .name = "Broadcom BCM50610",
716 .features = PHY_GBIT_FEATURES |
717 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
718 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
719 .config_init = bcm54xx_config_init,
720 .config_aneg = genphy_config_aneg,
721 .read_status = genphy_read_status,
722 .ack_interrupt = bcm54xx_ack_interrupt,
723 .config_intr = bcm54xx_config_intr,
724 .driver = { .owner = THIS_MODULE },
725}, {
726 .phy_id = PHY_ID_BCM50610M,
727 .phy_id_mask = 0xfffffff0,
728 .name = "Broadcom BCM50610M",
729 .features = PHY_GBIT_FEATURES |
730 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
731 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
732 .config_init = bcm54xx_config_init,
733 .config_aneg = genphy_config_aneg,
734 .read_status = genphy_read_status,
735 .ack_interrupt = bcm54xx_ack_interrupt,
736 .config_intr = bcm54xx_config_intr,
737 .driver = { .owner = THIS_MODULE },
738}, {
739 .phy_id = PHY_ID_BCM57780,
740 .phy_id_mask = 0xfffffff0,
741 .name = "Broadcom BCM57780",
742 .features = PHY_GBIT_FEATURES |
743 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
744 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
745 .config_init = bcm54xx_config_init,
746 .config_aneg = genphy_config_aneg,
747 .read_status = genphy_read_status,
748 .ack_interrupt = bcm54xx_ack_interrupt,
749 .config_intr = bcm54xx_config_intr,
750 .driver = { .owner = THIS_MODULE },
751}, {
752 .phy_id = PHY_ID_BCMAC131,
753 .phy_id_mask = 0xfffffff0,
754 .name = "Broadcom BCMAC131",
755 .features = PHY_BASIC_FEATURES |
756 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
757 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
758 .config_init = brcm_fet_config_init,
759 .config_aneg = genphy_config_aneg,
760 .read_status = genphy_read_status,
761 .ack_interrupt = brcm_fet_ack_interrupt,
762 .config_intr = brcm_fet_config_intr,
763 .driver = { .owner = THIS_MODULE },
764}, {
765 .phy_id = PHY_ID_BCM5241,
766 .phy_id_mask = 0xfffffff0,
767 .name = "Broadcom BCM5241",
768 .features = PHY_BASIC_FEATURES |
769 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
770 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
771 .config_init = brcm_fet_config_init,
772 .config_aneg = genphy_config_aneg,
773 .read_status = genphy_read_status,
774 .ack_interrupt = brcm_fet_ack_interrupt,
775 .config_intr = brcm_fet_config_intr,
776 .driver = { .owner = THIS_MODULE },
777} };
778
779static int __init broadcom_init(void)
780{
781 return phy_drivers_register(broadcom_drivers,
782 ARRAY_SIZE(broadcom_drivers));
783}
784
785static void __exit broadcom_exit(void)
786{
787 phy_drivers_unregister(broadcom_drivers,
788 ARRAY_SIZE(broadcom_drivers));
789}
790
791module_init(broadcom_init);
792module_exit(broadcom_exit);
793
794static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
795 { PHY_ID_BCM5411, 0xfffffff0 },
796 { PHY_ID_BCM5421, 0xfffffff0 },
797 { PHY_ID_BCM5461, 0xfffffff0 },
798 { PHY_ID_BCM5464, 0xfffffff0 },
799 { PHY_ID_BCM5482, 0xfffffff0 },
800 { PHY_ID_BCM5482, 0xfffffff0 },
801 { PHY_ID_BCM50610, 0xfffffff0 },
802 { PHY_ID_BCM50610M, 0xfffffff0 },
803 { PHY_ID_BCM57780, 0xfffffff0 },
804 { PHY_ID_BCMAC131, 0xfffffff0 },
805 { PHY_ID_BCM5241, 0xfffffff0 },
806 { }
807};
808
809MODULE_DEVICE_TABLE(mdio, broadcom_tbl);
1/*
2 * drivers/net/phy/broadcom.c
3 *
4 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
5 * transceivers.
6 *
7 * Copyright (c) 2006 Maciej W. Rozycki
8 *
9 * Inspired by code written by Amy Fong.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16
17#include "bcm-phy-lib.h"
18#include <linux/module.h>
19#include <linux/phy.h>
20#include <linux/brcmphy.h>
21#include <linux/of.h>
22
23#define BRCM_PHY_MODEL(phydev) \
24 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
25
26#define BRCM_PHY_REV(phydev) \
27 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
28
29MODULE_DESCRIPTION("Broadcom PHY driver");
30MODULE_AUTHOR("Maciej W. Rozycki");
31MODULE_LICENSE("GPL");
32
33static int bcm54210e_config_init(struct phy_device *phydev)
34{
35 int val;
36
37 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
38 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
39 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
40 bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, val);
41
42 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
43 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
44 bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
45
46 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) {
47 val = phy_read(phydev, MII_CTRL1000);
48 val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
49 phy_write(phydev, MII_CTRL1000, val);
50 }
51
52 return 0;
53}
54
55static int bcm54612e_config_init(struct phy_device *phydev)
56{
57 /* Clear TX internal delay unless requested. */
58 if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
59 (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
60 /* Disable TXD to GTXCLK clock delay (default set) */
61 /* Bit 9 is the only field in shadow register 00011 */
62 bcm_phy_write_shadow(phydev, 0x03, 0);
63 }
64
65 /* Clear RX internal delay unless requested. */
66 if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
67 (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
68 u16 reg;
69
70 reg = bcm54xx_auxctl_read(phydev,
71 MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
72 /* Disable RXD to RXC delay (default set) */
73 reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
74 /* Clear shadow selector field */
75 reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
76 bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
77 MII_BCM54XX_AUXCTL_MISC_WREN | reg);
78 }
79
80 return 0;
81}
82
83static int bcm5481x_config(struct phy_device *phydev)
84{
85 int rc, val;
86
87 /* handling PHY's internal RX clock delay */
88 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
89 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
90 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
91 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
92 /* Disable RGMII RXC-RXD skew */
93 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
94 }
95 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
96 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
97 /* Enable RGMII RXC-RXD skew */
98 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
99 }
100 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
101 val);
102 if (rc < 0)
103 return rc;
104
105 /* handling PHY's internal TX clock delay */
106 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
107 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
108 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
109 /* Disable internal TX clock delay */
110 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
111 }
112 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
113 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
114 /* Enable internal TX clock delay */
115 val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN;
116 }
117 rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
118 if (rc < 0)
119 return rc;
120
121 return 0;
122}
123
124/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
125static int bcm50610_a0_workaround(struct phy_device *phydev)
126{
127 int err;
128
129 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
130 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
131 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
132 if (err < 0)
133 return err;
134
135 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
136 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
137 if (err < 0)
138 return err;
139
140 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
141 MII_BCM54XX_EXP_EXP75_VDACCTRL);
142 if (err < 0)
143 return err;
144
145 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
146 MII_BCM54XX_EXP_EXP96_MYST);
147 if (err < 0)
148 return err;
149
150 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
151 MII_BCM54XX_EXP_EXP97_MYST);
152
153 return err;
154}
155
156static int bcm54xx_phydsp_config(struct phy_device *phydev)
157{
158 int err, err2;
159
160 /* Enable the SMDSP clock */
161 err = bcm54xx_auxctl_write(phydev,
162 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
163 MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
164 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
165 if (err < 0)
166 return err;
167
168 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
169 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
170 /* Clear bit 9 to fix a phy interop issue. */
171 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
172 MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
173 if (err < 0)
174 goto error;
175
176 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
177 err = bcm50610_a0_workaround(phydev);
178 if (err < 0)
179 goto error;
180 }
181 }
182
183 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
184 int val;
185
186 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
187 if (val < 0)
188 goto error;
189
190 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
191 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
192 }
193
194error:
195 /* Disable the SMDSP clock */
196 err2 = bcm54xx_auxctl_write(phydev,
197 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
198 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
199
200 /* Return the first error reported. */
201 return err ? err : err2;
202}
203
204static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
205{
206 u32 orig;
207 int val;
208 bool clk125en = true;
209
210 /* Abort if we are using an untested phy. */
211 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
212 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
213 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M)
214 return;
215
216 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
217 if (val < 0)
218 return;
219
220 orig = val;
221
222 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
223 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
224 BRCM_PHY_REV(phydev) >= 0x3) {
225 /*
226 * Here, bit 0 _disables_ CLK125 when set.
227 * This bit is set by default.
228 */
229 clk125en = false;
230 } else {
231 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
232 /* Here, bit 0 _enables_ CLK125 when set */
233 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
234 clk125en = false;
235 }
236 }
237
238 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
239 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
240 else
241 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
242
243 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY)
244 val |= BCM54XX_SHD_SCR3_TRDDAPD;
245
246 if (orig != val)
247 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
248
249 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
250 if (val < 0)
251 return;
252
253 orig = val;
254
255 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
256 val |= BCM54XX_SHD_APD_EN;
257 else
258 val &= ~BCM54XX_SHD_APD_EN;
259
260 if (orig != val)
261 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
262}
263
264static int bcm54xx_config_init(struct phy_device *phydev)
265{
266 int reg, err, val;
267
268 reg = phy_read(phydev, MII_BCM54XX_ECR);
269 if (reg < 0)
270 return reg;
271
272 /* Mask interrupts globally. */
273 reg |= MII_BCM54XX_ECR_IM;
274 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
275 if (err < 0)
276 return err;
277
278 /* Unmask events we are interested in. */
279 reg = ~(MII_BCM54XX_INT_DUPLEX |
280 MII_BCM54XX_INT_SPEED |
281 MII_BCM54XX_INT_LINK);
282 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
283 if (err < 0)
284 return err;
285
286 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
287 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
288 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
289 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
290
291 if ((phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) ||
292 (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) ||
293 (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
294 bcm54xx_adjust_rxrefclk(phydev);
295
296 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E) {
297 err = bcm54210e_config_init(phydev);
298 if (err)
299 return err;
300 } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54612E) {
301 err = bcm54612e_config_init(phydev);
302 if (err)
303 return err;
304 } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
305 /* For BCM54810, we need to disable BroadR-Reach function */
306 val = bcm_phy_read_exp(phydev,
307 BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
308 val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
309 err = bcm_phy_write_exp(phydev,
310 BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
311 val);
312 if (err < 0)
313 return err;
314 }
315
316 bcm54xx_phydsp_config(phydev);
317
318 return 0;
319}
320
321static int bcm5482_config_init(struct phy_device *phydev)
322{
323 int err, reg;
324
325 err = bcm54xx_config_init(phydev);
326
327 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
328 /*
329 * Enable secondary SerDes and its use as an LED source
330 */
331 reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_SSD);
332 bcm_phy_write_shadow(phydev, BCM5482_SHD_SSD,
333 reg |
334 BCM5482_SHD_SSD_LEDM |
335 BCM5482_SHD_SSD_EN);
336
337 /*
338 * Enable SGMII slave mode and auto-detection
339 */
340 reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD;
341 err = bcm_phy_read_exp(phydev, reg);
342 if (err < 0)
343 return err;
344 err = bcm_phy_write_exp(phydev, reg, err |
345 BCM5482_SSD_SGMII_SLAVE_EN |
346 BCM5482_SSD_SGMII_SLAVE_AD);
347 if (err < 0)
348 return err;
349
350 /*
351 * Disable secondary SerDes powerdown
352 */
353 reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD;
354 err = bcm_phy_read_exp(phydev, reg);
355 if (err < 0)
356 return err;
357 err = bcm_phy_write_exp(phydev, reg,
358 err & ~BCM5482_SSD_1000BX_CTL_PWRDOWN);
359 if (err < 0)
360 return err;
361
362 /*
363 * Select 1000BASE-X register set (primary SerDes)
364 */
365 reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_MODE);
366 bcm_phy_write_shadow(phydev, BCM5482_SHD_MODE,
367 reg | BCM5482_SHD_MODE_1000BX);
368
369 /*
370 * LED1=ACTIVITYLED, LED3=LINKSPD[2]
371 * (Use LED1 as secondary SerDes ACTIVITY LED)
372 */
373 bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1,
374 BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
375 BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
376
377 /*
378 * Auto-negotiation doesn't seem to work quite right
379 * in this mode, so we disable it and force it to the
380 * right speed/duplex setting. Only 'link status'
381 * is important.
382 */
383 phydev->autoneg = AUTONEG_DISABLE;
384 phydev->speed = SPEED_1000;
385 phydev->duplex = DUPLEX_FULL;
386 }
387
388 return err;
389}
390
391static int bcm5482_read_status(struct phy_device *phydev)
392{
393 int err;
394
395 err = genphy_read_status(phydev);
396
397 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
398 /*
399 * Only link status matters for 1000Base-X mode, so force
400 * 1000 Mbit/s full-duplex status
401 */
402 if (phydev->link) {
403 phydev->speed = SPEED_1000;
404 phydev->duplex = DUPLEX_FULL;
405 }
406 }
407
408 return err;
409}
410
411static int bcm5481_config_aneg(struct phy_device *phydev)
412{
413 struct device_node *np = phydev->mdio.dev.of_node;
414 int ret;
415
416 /* Aneg firsly. */
417 ret = genphy_config_aneg(phydev);
418
419 /* Then we can set up the delay. */
420 bcm5481x_config(phydev);
421
422 if (of_property_read_bool(np, "enet-phy-lane-swap")) {
423 /* Lane Swap - Undocumented register...magic! */
424 ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
425 0x11B);
426 if (ret < 0)
427 return ret;
428 }
429
430 return ret;
431}
432
433static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
434{
435 int val;
436
437 val = phy_read(phydev, reg);
438 if (val < 0)
439 return val;
440
441 return phy_write(phydev, reg, val | set);
442}
443
444static int brcm_fet_config_init(struct phy_device *phydev)
445{
446 int reg, err, err2, brcmtest;
447
448 /* Reset the PHY to bring it to a known state. */
449 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
450 if (err < 0)
451 return err;
452
453 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
454 if (reg < 0)
455 return reg;
456
457 /* Unmask events we are interested in and mask interrupts globally. */
458 reg = MII_BRCM_FET_IR_DUPLEX_EN |
459 MII_BRCM_FET_IR_SPEED_EN |
460 MII_BRCM_FET_IR_LINK_EN |
461 MII_BRCM_FET_IR_ENABLE |
462 MII_BRCM_FET_IR_MASK;
463
464 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
465 if (err < 0)
466 return err;
467
468 /* Enable shadow register access */
469 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
470 if (brcmtest < 0)
471 return brcmtest;
472
473 reg = brcmtest | MII_BRCM_FET_BT_SRE;
474
475 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
476 if (err < 0)
477 return err;
478
479 /* Set the LED mode */
480 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
481 if (reg < 0) {
482 err = reg;
483 goto done;
484 }
485
486 reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
487 reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
488
489 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
490 if (err < 0)
491 goto done;
492
493 /* Enable auto MDIX */
494 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
495 MII_BRCM_FET_SHDW_MC_FAME);
496 if (err < 0)
497 goto done;
498
499 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
500 /* Enable auto power down */
501 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
502 MII_BRCM_FET_SHDW_AS2_APDE);
503 }
504
505done:
506 /* Disable shadow register access */
507 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
508 if (!err)
509 err = err2;
510
511 return err;
512}
513
514static int brcm_fet_ack_interrupt(struct phy_device *phydev)
515{
516 int reg;
517
518 /* Clear pending interrupts. */
519 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
520 if (reg < 0)
521 return reg;
522
523 return 0;
524}
525
526static int brcm_fet_config_intr(struct phy_device *phydev)
527{
528 int reg, err;
529
530 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
531 if (reg < 0)
532 return reg;
533
534 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
535 reg &= ~MII_BRCM_FET_IR_MASK;
536 else
537 reg |= MII_BRCM_FET_IR_MASK;
538
539 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
540 return err;
541}
542
543struct bcm53xx_phy_priv {
544 u64 *stats;
545};
546
547static int bcm53xx_phy_probe(struct phy_device *phydev)
548{
549 struct bcm53xx_phy_priv *priv;
550
551 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
552 if (!priv)
553 return -ENOMEM;
554
555 phydev->priv = priv;
556
557 priv->stats = devm_kcalloc(&phydev->mdio.dev,
558 bcm_phy_get_sset_count(phydev), sizeof(u64),
559 GFP_KERNEL);
560 if (!priv->stats)
561 return -ENOMEM;
562
563 return 0;
564}
565
566static void bcm53xx_phy_get_stats(struct phy_device *phydev,
567 struct ethtool_stats *stats, u64 *data)
568{
569 struct bcm53xx_phy_priv *priv = phydev->priv;
570
571 bcm_phy_get_stats(phydev, priv->stats, stats, data);
572}
573
574static struct phy_driver broadcom_drivers[] = {
575{
576 .phy_id = PHY_ID_BCM5411,
577 .phy_id_mask = 0xfffffff0,
578 .name = "Broadcom BCM5411",
579 .features = PHY_GBIT_FEATURES,
580 .flags = PHY_HAS_INTERRUPT,
581 .config_init = bcm54xx_config_init,
582 .ack_interrupt = bcm_phy_ack_intr,
583 .config_intr = bcm_phy_config_intr,
584}, {
585 .phy_id = PHY_ID_BCM5421,
586 .phy_id_mask = 0xfffffff0,
587 .name = "Broadcom BCM5421",
588 .features = PHY_GBIT_FEATURES,
589 .flags = PHY_HAS_INTERRUPT,
590 .config_init = bcm54xx_config_init,
591 .ack_interrupt = bcm_phy_ack_intr,
592 .config_intr = bcm_phy_config_intr,
593}, {
594 .phy_id = PHY_ID_BCM54210E,
595 .phy_id_mask = 0xfffffff0,
596 .name = "Broadcom BCM54210E",
597 .features = PHY_GBIT_FEATURES,
598 .flags = PHY_HAS_INTERRUPT,
599 .config_init = bcm54xx_config_init,
600 .ack_interrupt = bcm_phy_ack_intr,
601 .config_intr = bcm_phy_config_intr,
602}, {
603 .phy_id = PHY_ID_BCM5461,
604 .phy_id_mask = 0xfffffff0,
605 .name = "Broadcom BCM5461",
606 .features = PHY_GBIT_FEATURES,
607 .flags = PHY_HAS_INTERRUPT,
608 .config_init = bcm54xx_config_init,
609 .ack_interrupt = bcm_phy_ack_intr,
610 .config_intr = bcm_phy_config_intr,
611}, {
612 .phy_id = PHY_ID_BCM54612E,
613 .phy_id_mask = 0xfffffff0,
614 .name = "Broadcom BCM54612E",
615 .features = PHY_GBIT_FEATURES,
616 .flags = PHY_HAS_INTERRUPT,
617 .config_init = bcm54xx_config_init,
618 .ack_interrupt = bcm_phy_ack_intr,
619 .config_intr = bcm_phy_config_intr,
620}, {
621 .phy_id = PHY_ID_BCM54616S,
622 .phy_id_mask = 0xfffffff0,
623 .name = "Broadcom BCM54616S",
624 .features = PHY_GBIT_FEATURES,
625 .flags = PHY_HAS_INTERRUPT,
626 .config_init = bcm54xx_config_init,
627 .ack_interrupt = bcm_phy_ack_intr,
628 .config_intr = bcm_phy_config_intr,
629}, {
630 .phy_id = PHY_ID_BCM5464,
631 .phy_id_mask = 0xfffffff0,
632 .name = "Broadcom BCM5464",
633 .features = PHY_GBIT_FEATURES,
634 .flags = PHY_HAS_INTERRUPT,
635 .config_init = bcm54xx_config_init,
636 .ack_interrupt = bcm_phy_ack_intr,
637 .config_intr = bcm_phy_config_intr,
638}, {
639 .phy_id = PHY_ID_BCM5481,
640 .phy_id_mask = 0xfffffff0,
641 .name = "Broadcom BCM5481",
642 .features = PHY_GBIT_FEATURES,
643 .flags = PHY_HAS_INTERRUPT,
644 .config_init = bcm54xx_config_init,
645 .config_aneg = bcm5481_config_aneg,
646 .ack_interrupt = bcm_phy_ack_intr,
647 .config_intr = bcm_phy_config_intr,
648}, {
649 .phy_id = PHY_ID_BCM54810,
650 .phy_id_mask = 0xfffffff0,
651 .name = "Broadcom BCM54810",
652 .features = PHY_GBIT_FEATURES,
653 .flags = PHY_HAS_INTERRUPT,
654 .config_init = bcm54xx_config_init,
655 .config_aneg = bcm5481_config_aneg,
656 .ack_interrupt = bcm_phy_ack_intr,
657 .config_intr = bcm_phy_config_intr,
658}, {
659 .phy_id = PHY_ID_BCM5482,
660 .phy_id_mask = 0xfffffff0,
661 .name = "Broadcom BCM5482",
662 .features = PHY_GBIT_FEATURES,
663 .flags = PHY_HAS_INTERRUPT,
664 .config_init = bcm5482_config_init,
665 .read_status = bcm5482_read_status,
666 .ack_interrupt = bcm_phy_ack_intr,
667 .config_intr = bcm_phy_config_intr,
668}, {
669 .phy_id = PHY_ID_BCM50610,
670 .phy_id_mask = 0xfffffff0,
671 .name = "Broadcom BCM50610",
672 .features = PHY_GBIT_FEATURES,
673 .flags = PHY_HAS_INTERRUPT,
674 .config_init = bcm54xx_config_init,
675 .ack_interrupt = bcm_phy_ack_intr,
676 .config_intr = bcm_phy_config_intr,
677}, {
678 .phy_id = PHY_ID_BCM50610M,
679 .phy_id_mask = 0xfffffff0,
680 .name = "Broadcom BCM50610M",
681 .features = PHY_GBIT_FEATURES,
682 .flags = PHY_HAS_INTERRUPT,
683 .config_init = bcm54xx_config_init,
684 .ack_interrupt = bcm_phy_ack_intr,
685 .config_intr = bcm_phy_config_intr,
686}, {
687 .phy_id = PHY_ID_BCM57780,
688 .phy_id_mask = 0xfffffff0,
689 .name = "Broadcom BCM57780",
690 .features = PHY_GBIT_FEATURES,
691 .flags = PHY_HAS_INTERRUPT,
692 .config_init = bcm54xx_config_init,
693 .ack_interrupt = bcm_phy_ack_intr,
694 .config_intr = bcm_phy_config_intr,
695}, {
696 .phy_id = PHY_ID_BCMAC131,
697 .phy_id_mask = 0xfffffff0,
698 .name = "Broadcom BCMAC131",
699 .features = PHY_BASIC_FEATURES,
700 .flags = PHY_HAS_INTERRUPT,
701 .config_init = brcm_fet_config_init,
702 .ack_interrupt = brcm_fet_ack_interrupt,
703 .config_intr = brcm_fet_config_intr,
704}, {
705 .phy_id = PHY_ID_BCM5241,
706 .phy_id_mask = 0xfffffff0,
707 .name = "Broadcom BCM5241",
708 .features = PHY_BASIC_FEATURES,
709 .flags = PHY_HAS_INTERRUPT,
710 .config_init = brcm_fet_config_init,
711 .ack_interrupt = brcm_fet_ack_interrupt,
712 .config_intr = brcm_fet_config_intr,
713}, {
714 .phy_id = PHY_ID_BCM5395,
715 .phy_id_mask = 0xfffffff0,
716 .name = "Broadcom BCM5395",
717 .flags = PHY_IS_INTERNAL,
718 .features = PHY_GBIT_FEATURES,
719 .get_sset_count = bcm_phy_get_sset_count,
720 .get_strings = bcm_phy_get_strings,
721 .get_stats = bcm53xx_phy_get_stats,
722 .probe = bcm53xx_phy_probe,
723}, {
724 .phy_id = PHY_ID_BCM89610,
725 .phy_id_mask = 0xfffffff0,
726 .name = "Broadcom BCM89610",
727 .features = PHY_GBIT_FEATURES,
728 .flags = PHY_HAS_INTERRUPT,
729 .config_init = bcm54xx_config_init,
730 .ack_interrupt = bcm_phy_ack_intr,
731 .config_intr = bcm_phy_config_intr,
732} };
733
734module_phy_driver(broadcom_drivers);
735
736static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
737 { PHY_ID_BCM5411, 0xfffffff0 },
738 { PHY_ID_BCM5421, 0xfffffff0 },
739 { PHY_ID_BCM54210E, 0xfffffff0 },
740 { PHY_ID_BCM5461, 0xfffffff0 },
741 { PHY_ID_BCM54612E, 0xfffffff0 },
742 { PHY_ID_BCM54616S, 0xfffffff0 },
743 { PHY_ID_BCM5464, 0xfffffff0 },
744 { PHY_ID_BCM5481, 0xfffffff0 },
745 { PHY_ID_BCM54810, 0xfffffff0 },
746 { PHY_ID_BCM5482, 0xfffffff0 },
747 { PHY_ID_BCM50610, 0xfffffff0 },
748 { PHY_ID_BCM50610M, 0xfffffff0 },
749 { PHY_ID_BCM57780, 0xfffffff0 },
750 { PHY_ID_BCMAC131, 0xfffffff0 },
751 { PHY_ID_BCM5241, 0xfffffff0 },
752 { PHY_ID_BCM5395, 0xfffffff0 },
753 { PHY_ID_BCM89610, 0xfffffff0 },
754 { }
755};
756
757MODULE_DEVICE_TABLE(mdio, broadcom_tbl);