Loading...
1/*
2 * Copyright (c) 2013 Linaro Ltd.
3 * Copyright (c) 2013 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/sched.h>
10#include <linux/device.h>
11#include <linux/dmaengine.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/slab.h>
18#include <linux/spinlock.h>
19#include <linux/of_device.h>
20#include <linux/of.h>
21#include <linux/clk.h>
22#include <linux/of_dma.h>
23
24#include "virt-dma.h"
25
26#define DRIVER_NAME "k3-dma"
27#define DMA_ALIGN 3
28#define DMA_MAX_SIZE 0x1ffc
29
30#define INT_STAT 0x00
31#define INT_TC1 0x04
32#define INT_ERR1 0x0c
33#define INT_ERR2 0x10
34#define INT_TC1_MASK 0x18
35#define INT_ERR1_MASK 0x20
36#define INT_ERR2_MASK 0x24
37#define INT_TC1_RAW 0x600
38#define INT_ERR1_RAW 0x608
39#define INT_ERR2_RAW 0x610
40#define CH_PRI 0x688
41#define CH_STAT 0x690
42#define CX_CUR_CNT 0x704
43#define CX_LLI 0x800
44#define CX_CNT 0x810
45#define CX_SRC 0x814
46#define CX_DST 0x818
47#define CX_CFG 0x81c
48#define AXI_CFG 0x820
49#define AXI_CFG_DEFAULT 0x201201
50
51#define CX_LLI_CHAIN_EN 0x2
52#define CX_CFG_EN 0x1
53#define CX_CFG_MEM2PER (0x1 << 2)
54#define CX_CFG_PER2MEM (0x2 << 2)
55#define CX_CFG_SRCINCR (0x1 << 31)
56#define CX_CFG_DSTINCR (0x1 << 30)
57
58struct k3_desc_hw {
59 u32 lli;
60 u32 reserved[3];
61 u32 count;
62 u32 saddr;
63 u32 daddr;
64 u32 config;
65} __aligned(32);
66
67struct k3_dma_desc_sw {
68 struct virt_dma_desc vd;
69 dma_addr_t desc_hw_lli;
70 size_t desc_num;
71 size_t size;
72 struct k3_desc_hw desc_hw[0];
73};
74
75struct k3_dma_phy;
76
77struct k3_dma_chan {
78 u32 ccfg;
79 struct virt_dma_chan vc;
80 struct k3_dma_phy *phy;
81 struct list_head node;
82 enum dma_transfer_direction dir;
83 dma_addr_t dev_addr;
84 enum dma_status status;
85};
86
87struct k3_dma_phy {
88 u32 idx;
89 void __iomem *base;
90 struct k3_dma_chan *vchan;
91 struct k3_dma_desc_sw *ds_run;
92 struct k3_dma_desc_sw *ds_done;
93};
94
95struct k3_dma_dev {
96 struct dma_device slave;
97 void __iomem *base;
98 struct tasklet_struct task;
99 spinlock_t lock;
100 struct list_head chan_pending;
101 struct k3_dma_phy *phy;
102 struct k3_dma_chan *chans;
103 struct clk *clk;
104 u32 dma_channels;
105 u32 dma_requests;
106};
107
108#define to_k3_dma(dmadev) container_of(dmadev, struct k3_dma_dev, slave)
109
110static struct k3_dma_chan *to_k3_chan(struct dma_chan *chan)
111{
112 return container_of(chan, struct k3_dma_chan, vc.chan);
113}
114
115static void k3_dma_pause_dma(struct k3_dma_phy *phy, bool on)
116{
117 u32 val = 0;
118
119 if (on) {
120 val = readl_relaxed(phy->base + CX_CFG);
121 val |= CX_CFG_EN;
122 writel_relaxed(val, phy->base + CX_CFG);
123 } else {
124 val = readl_relaxed(phy->base + CX_CFG);
125 val &= ~CX_CFG_EN;
126 writel_relaxed(val, phy->base + CX_CFG);
127 }
128}
129
130static void k3_dma_terminate_chan(struct k3_dma_phy *phy, struct k3_dma_dev *d)
131{
132 u32 val = 0;
133
134 k3_dma_pause_dma(phy, false);
135
136 val = 0x1 << phy->idx;
137 writel_relaxed(val, d->base + INT_TC1_RAW);
138 writel_relaxed(val, d->base + INT_ERR1_RAW);
139 writel_relaxed(val, d->base + INT_ERR2_RAW);
140}
141
142static void k3_dma_set_desc(struct k3_dma_phy *phy, struct k3_desc_hw *hw)
143{
144 writel_relaxed(hw->lli, phy->base + CX_LLI);
145 writel_relaxed(hw->count, phy->base + CX_CNT);
146 writel_relaxed(hw->saddr, phy->base + CX_SRC);
147 writel_relaxed(hw->daddr, phy->base + CX_DST);
148 writel_relaxed(AXI_CFG_DEFAULT, phy->base + AXI_CFG);
149 writel_relaxed(hw->config, phy->base + CX_CFG);
150}
151
152static u32 k3_dma_get_curr_cnt(struct k3_dma_dev *d, struct k3_dma_phy *phy)
153{
154 u32 cnt = 0;
155
156 cnt = readl_relaxed(d->base + CX_CUR_CNT + phy->idx * 0x10);
157 cnt &= 0xffff;
158 return cnt;
159}
160
161static u32 k3_dma_get_curr_lli(struct k3_dma_phy *phy)
162{
163 return readl_relaxed(phy->base + CX_LLI);
164}
165
166static u32 k3_dma_get_chan_stat(struct k3_dma_dev *d)
167{
168 return readl_relaxed(d->base + CH_STAT);
169}
170
171static void k3_dma_enable_dma(struct k3_dma_dev *d, bool on)
172{
173 if (on) {
174 /* set same priority */
175 writel_relaxed(0x0, d->base + CH_PRI);
176
177 /* unmask irq */
178 writel_relaxed(0xffff, d->base + INT_TC1_MASK);
179 writel_relaxed(0xffff, d->base + INT_ERR1_MASK);
180 writel_relaxed(0xffff, d->base + INT_ERR2_MASK);
181 } else {
182 /* mask irq */
183 writel_relaxed(0x0, d->base + INT_TC1_MASK);
184 writel_relaxed(0x0, d->base + INT_ERR1_MASK);
185 writel_relaxed(0x0, d->base + INT_ERR2_MASK);
186 }
187}
188
189static irqreturn_t k3_dma_int_handler(int irq, void *dev_id)
190{
191 struct k3_dma_dev *d = (struct k3_dma_dev *)dev_id;
192 struct k3_dma_phy *p;
193 struct k3_dma_chan *c;
194 u32 stat = readl_relaxed(d->base + INT_STAT);
195 u32 tc1 = readl_relaxed(d->base + INT_TC1);
196 u32 err1 = readl_relaxed(d->base + INT_ERR1);
197 u32 err2 = readl_relaxed(d->base + INT_ERR2);
198 u32 i, irq_chan = 0;
199
200 while (stat) {
201 i = __ffs(stat);
202 stat &= (stat - 1);
203 if (likely(tc1 & BIT(i))) {
204 p = &d->phy[i];
205 c = p->vchan;
206 if (c) {
207 unsigned long flags;
208
209 spin_lock_irqsave(&c->vc.lock, flags);
210 vchan_cookie_complete(&p->ds_run->vd);
211 p->ds_done = p->ds_run;
212 spin_unlock_irqrestore(&c->vc.lock, flags);
213 }
214 irq_chan |= BIT(i);
215 }
216 if (unlikely((err1 & BIT(i)) || (err2 & BIT(i))))
217 dev_warn(d->slave.dev, "DMA ERR\n");
218 }
219
220 writel_relaxed(irq_chan, d->base + INT_TC1_RAW);
221 writel_relaxed(err1, d->base + INT_ERR1_RAW);
222 writel_relaxed(err2, d->base + INT_ERR2_RAW);
223
224 if (irq_chan) {
225 tasklet_schedule(&d->task);
226 return IRQ_HANDLED;
227 } else
228 return IRQ_NONE;
229}
230
231static int k3_dma_start_txd(struct k3_dma_chan *c)
232{
233 struct k3_dma_dev *d = to_k3_dma(c->vc.chan.device);
234 struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
235
236 if (!c->phy)
237 return -EAGAIN;
238
239 if (BIT(c->phy->idx) & k3_dma_get_chan_stat(d))
240 return -EAGAIN;
241
242 if (vd) {
243 struct k3_dma_desc_sw *ds =
244 container_of(vd, struct k3_dma_desc_sw, vd);
245 /*
246 * fetch and remove request from vc->desc_issued
247 * so vc->desc_issued only contains desc pending
248 */
249 list_del(&ds->vd.node);
250 c->phy->ds_run = ds;
251 c->phy->ds_done = NULL;
252 /* start dma */
253 k3_dma_set_desc(c->phy, &ds->desc_hw[0]);
254 return 0;
255 }
256 c->phy->ds_done = NULL;
257 c->phy->ds_run = NULL;
258 return -EAGAIN;
259}
260
261static void k3_dma_tasklet(unsigned long arg)
262{
263 struct k3_dma_dev *d = (struct k3_dma_dev *)arg;
264 struct k3_dma_phy *p;
265 struct k3_dma_chan *c, *cn;
266 unsigned pch, pch_alloc = 0;
267
268 /* check new dma request of running channel in vc->desc_issued */
269 list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
270 spin_lock_irq(&c->vc.lock);
271 p = c->phy;
272 if (p && p->ds_done) {
273 if (k3_dma_start_txd(c)) {
274 /* No current txd associated with this channel */
275 dev_dbg(d->slave.dev, "pchan %u: free\n", p->idx);
276 /* Mark this channel free */
277 c->phy = NULL;
278 p->vchan = NULL;
279 }
280 }
281 spin_unlock_irq(&c->vc.lock);
282 }
283
284 /* check new channel request in d->chan_pending */
285 spin_lock_irq(&d->lock);
286 for (pch = 0; pch < d->dma_channels; pch++) {
287 p = &d->phy[pch];
288
289 if (p->vchan == NULL && !list_empty(&d->chan_pending)) {
290 c = list_first_entry(&d->chan_pending,
291 struct k3_dma_chan, node);
292 /* remove from d->chan_pending */
293 list_del_init(&c->node);
294 pch_alloc |= 1 << pch;
295 /* Mark this channel allocated */
296 p->vchan = c;
297 c->phy = p;
298 dev_dbg(d->slave.dev, "pchan %u: alloc vchan %p\n", pch, &c->vc);
299 }
300 }
301 spin_unlock_irq(&d->lock);
302
303 for (pch = 0; pch < d->dma_channels; pch++) {
304 if (pch_alloc & (1 << pch)) {
305 p = &d->phy[pch];
306 c = p->vchan;
307 if (c) {
308 spin_lock_irq(&c->vc.lock);
309 k3_dma_start_txd(c);
310 spin_unlock_irq(&c->vc.lock);
311 }
312 }
313 }
314}
315
316static int k3_dma_alloc_chan_resources(struct dma_chan *chan)
317{
318 return 0;
319}
320
321static void k3_dma_free_chan_resources(struct dma_chan *chan)
322{
323 struct k3_dma_chan *c = to_k3_chan(chan);
324 struct k3_dma_dev *d = to_k3_dma(chan->device);
325 unsigned long flags;
326
327 spin_lock_irqsave(&d->lock, flags);
328 list_del_init(&c->node);
329 spin_unlock_irqrestore(&d->lock, flags);
330
331 vchan_free_chan_resources(&c->vc);
332 c->ccfg = 0;
333}
334
335static enum dma_status k3_dma_tx_status(struct dma_chan *chan,
336 dma_cookie_t cookie, struct dma_tx_state *state)
337{
338 struct k3_dma_chan *c = to_k3_chan(chan);
339 struct k3_dma_dev *d = to_k3_dma(chan->device);
340 struct k3_dma_phy *p;
341 struct virt_dma_desc *vd;
342 unsigned long flags;
343 enum dma_status ret;
344 size_t bytes = 0;
345
346 ret = dma_cookie_status(&c->vc.chan, cookie, state);
347 if (ret == DMA_COMPLETE)
348 return ret;
349
350 spin_lock_irqsave(&c->vc.lock, flags);
351 p = c->phy;
352 ret = c->status;
353
354 /*
355 * If the cookie is on our issue queue, then the residue is
356 * its total size.
357 */
358 vd = vchan_find_desc(&c->vc, cookie);
359 if (vd) {
360 bytes = container_of(vd, struct k3_dma_desc_sw, vd)->size;
361 } else if ((!p) || (!p->ds_run)) {
362 bytes = 0;
363 } else {
364 struct k3_dma_desc_sw *ds = p->ds_run;
365 u32 clli = 0, index = 0;
366
367 bytes = k3_dma_get_curr_cnt(d, p);
368 clli = k3_dma_get_curr_lli(p);
369 index = (clli - ds->desc_hw_lli) / sizeof(struct k3_desc_hw);
370 for (; index < ds->desc_num; index++) {
371 bytes += ds->desc_hw[index].count;
372 /* end of lli */
373 if (!ds->desc_hw[index].lli)
374 break;
375 }
376 }
377 spin_unlock_irqrestore(&c->vc.lock, flags);
378 dma_set_residue(state, bytes);
379 return ret;
380}
381
382static void k3_dma_issue_pending(struct dma_chan *chan)
383{
384 struct k3_dma_chan *c = to_k3_chan(chan);
385 struct k3_dma_dev *d = to_k3_dma(chan->device);
386 unsigned long flags;
387
388 spin_lock_irqsave(&c->vc.lock, flags);
389 /* add request to vc->desc_issued */
390 if (vchan_issue_pending(&c->vc)) {
391 spin_lock(&d->lock);
392 if (!c->phy) {
393 if (list_empty(&c->node)) {
394 /* if new channel, add chan_pending */
395 list_add_tail(&c->node, &d->chan_pending);
396 /* check in tasklet */
397 tasklet_schedule(&d->task);
398 dev_dbg(d->slave.dev, "vchan %p: issued\n", &c->vc);
399 }
400 }
401 spin_unlock(&d->lock);
402 } else
403 dev_dbg(d->slave.dev, "vchan %p: nothing to issue\n", &c->vc);
404 spin_unlock_irqrestore(&c->vc.lock, flags);
405}
406
407static void k3_dma_fill_desc(struct k3_dma_desc_sw *ds, dma_addr_t dst,
408 dma_addr_t src, size_t len, u32 num, u32 ccfg)
409{
410 if ((num + 1) < ds->desc_num)
411 ds->desc_hw[num].lli = ds->desc_hw_lli + (num + 1) *
412 sizeof(struct k3_desc_hw);
413 ds->desc_hw[num].lli |= CX_LLI_CHAIN_EN;
414 ds->desc_hw[num].count = len;
415 ds->desc_hw[num].saddr = src;
416 ds->desc_hw[num].daddr = dst;
417 ds->desc_hw[num].config = ccfg;
418}
419
420static struct dma_async_tx_descriptor *k3_dma_prep_memcpy(
421 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
422 size_t len, unsigned long flags)
423{
424 struct k3_dma_chan *c = to_k3_chan(chan);
425 struct k3_dma_desc_sw *ds;
426 size_t copy = 0;
427 int num = 0;
428
429 if (!len)
430 return NULL;
431
432 num = DIV_ROUND_UP(len, DMA_MAX_SIZE);
433 ds = kzalloc(sizeof(*ds) + num * sizeof(ds->desc_hw[0]), GFP_ATOMIC);
434 if (!ds) {
435 dev_dbg(chan->device->dev, "vchan %p: kzalloc fail\n", &c->vc);
436 return NULL;
437 }
438 ds->desc_hw_lli = __virt_to_phys((unsigned long)&ds->desc_hw[0]);
439 ds->size = len;
440 ds->desc_num = num;
441 num = 0;
442
443 if (!c->ccfg) {
444 /* default is memtomem, without calling device_control */
445 c->ccfg = CX_CFG_SRCINCR | CX_CFG_DSTINCR | CX_CFG_EN;
446 c->ccfg |= (0xf << 20) | (0xf << 24); /* burst = 16 */
447 c->ccfg |= (0x3 << 12) | (0x3 << 16); /* width = 64 bit */
448 }
449
450 do {
451 copy = min_t(size_t, len, DMA_MAX_SIZE);
452 k3_dma_fill_desc(ds, dst, src, copy, num++, c->ccfg);
453
454 if (c->dir == DMA_MEM_TO_DEV) {
455 src += copy;
456 } else if (c->dir == DMA_DEV_TO_MEM) {
457 dst += copy;
458 } else {
459 src += copy;
460 dst += copy;
461 }
462 len -= copy;
463 } while (len);
464
465 ds->desc_hw[num-1].lli = 0; /* end of link */
466 return vchan_tx_prep(&c->vc, &ds->vd, flags);
467}
468
469static struct dma_async_tx_descriptor *k3_dma_prep_slave_sg(
470 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sglen,
471 enum dma_transfer_direction dir, unsigned long flags, void *context)
472{
473 struct k3_dma_chan *c = to_k3_chan(chan);
474 struct k3_dma_desc_sw *ds;
475 size_t len, avail, total = 0;
476 struct scatterlist *sg;
477 dma_addr_t addr, src = 0, dst = 0;
478 int num = sglen, i;
479
480 if (sgl == NULL)
481 return NULL;
482
483 for_each_sg(sgl, sg, sglen, i) {
484 avail = sg_dma_len(sg);
485 if (avail > DMA_MAX_SIZE)
486 num += DIV_ROUND_UP(avail, DMA_MAX_SIZE) - 1;
487 }
488
489 ds = kzalloc(sizeof(*ds) + num * sizeof(ds->desc_hw[0]), GFP_ATOMIC);
490 if (!ds) {
491 dev_dbg(chan->device->dev, "vchan %p: kzalloc fail\n", &c->vc);
492 return NULL;
493 }
494 ds->desc_hw_lli = __virt_to_phys((unsigned long)&ds->desc_hw[0]);
495 ds->desc_num = num;
496 num = 0;
497
498 for_each_sg(sgl, sg, sglen, i) {
499 addr = sg_dma_address(sg);
500 avail = sg_dma_len(sg);
501 total += avail;
502
503 do {
504 len = min_t(size_t, avail, DMA_MAX_SIZE);
505
506 if (dir == DMA_MEM_TO_DEV) {
507 src = addr;
508 dst = c->dev_addr;
509 } else if (dir == DMA_DEV_TO_MEM) {
510 src = c->dev_addr;
511 dst = addr;
512 }
513
514 k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg);
515
516 addr += len;
517 avail -= len;
518 } while (avail);
519 }
520
521 ds->desc_hw[num-1].lli = 0; /* end of link */
522 ds->size = total;
523 return vchan_tx_prep(&c->vc, &ds->vd, flags);
524}
525
526static int k3_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
527 unsigned long arg)
528{
529 struct k3_dma_chan *c = to_k3_chan(chan);
530 struct k3_dma_dev *d = to_k3_dma(chan->device);
531 struct dma_slave_config *cfg = (void *)arg;
532 struct k3_dma_phy *p = c->phy;
533 unsigned long flags;
534 u32 maxburst = 0, val = 0;
535 enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
536 LIST_HEAD(head);
537
538 switch (cmd) {
539 case DMA_SLAVE_CONFIG:
540 if (cfg == NULL)
541 return -EINVAL;
542 c->dir = cfg->direction;
543 if (c->dir == DMA_DEV_TO_MEM) {
544 c->ccfg = CX_CFG_DSTINCR;
545 c->dev_addr = cfg->src_addr;
546 maxburst = cfg->src_maxburst;
547 width = cfg->src_addr_width;
548 } else if (c->dir == DMA_MEM_TO_DEV) {
549 c->ccfg = CX_CFG_SRCINCR;
550 c->dev_addr = cfg->dst_addr;
551 maxburst = cfg->dst_maxburst;
552 width = cfg->dst_addr_width;
553 }
554 switch (width) {
555 case DMA_SLAVE_BUSWIDTH_1_BYTE:
556 case DMA_SLAVE_BUSWIDTH_2_BYTES:
557 case DMA_SLAVE_BUSWIDTH_4_BYTES:
558 case DMA_SLAVE_BUSWIDTH_8_BYTES:
559 val = __ffs(width);
560 break;
561 default:
562 val = 3;
563 break;
564 }
565 c->ccfg |= (val << 12) | (val << 16);
566
567 if ((maxburst == 0) || (maxburst > 16))
568 val = 16;
569 else
570 val = maxburst - 1;
571 c->ccfg |= (val << 20) | (val << 24);
572 c->ccfg |= CX_CFG_MEM2PER | CX_CFG_EN;
573
574 /* specific request line */
575 c->ccfg |= c->vc.chan.chan_id << 4;
576 break;
577
578 case DMA_TERMINATE_ALL:
579 dev_dbg(d->slave.dev, "vchan %p: terminate all\n", &c->vc);
580
581 /* Prevent this channel being scheduled */
582 spin_lock(&d->lock);
583 list_del_init(&c->node);
584 spin_unlock(&d->lock);
585
586 /* Clear the tx descriptor lists */
587 spin_lock_irqsave(&c->vc.lock, flags);
588 vchan_get_all_descriptors(&c->vc, &head);
589 if (p) {
590 /* vchan is assigned to a pchan - stop the channel */
591 k3_dma_terminate_chan(p, d);
592 c->phy = NULL;
593 p->vchan = NULL;
594 p->ds_run = p->ds_done = NULL;
595 }
596 spin_unlock_irqrestore(&c->vc.lock, flags);
597 vchan_dma_desc_free_list(&c->vc, &head);
598 break;
599
600 case DMA_PAUSE:
601 dev_dbg(d->slave.dev, "vchan %p: pause\n", &c->vc);
602 if (c->status == DMA_IN_PROGRESS) {
603 c->status = DMA_PAUSED;
604 if (p) {
605 k3_dma_pause_dma(p, false);
606 } else {
607 spin_lock(&d->lock);
608 list_del_init(&c->node);
609 spin_unlock(&d->lock);
610 }
611 }
612 break;
613
614 case DMA_RESUME:
615 dev_dbg(d->slave.dev, "vchan %p: resume\n", &c->vc);
616 spin_lock_irqsave(&c->vc.lock, flags);
617 if (c->status == DMA_PAUSED) {
618 c->status = DMA_IN_PROGRESS;
619 if (p) {
620 k3_dma_pause_dma(p, true);
621 } else if (!list_empty(&c->vc.desc_issued)) {
622 spin_lock(&d->lock);
623 list_add_tail(&c->node, &d->chan_pending);
624 spin_unlock(&d->lock);
625 }
626 }
627 spin_unlock_irqrestore(&c->vc.lock, flags);
628 break;
629 default:
630 return -ENXIO;
631 }
632 return 0;
633}
634
635static void k3_dma_free_desc(struct virt_dma_desc *vd)
636{
637 struct k3_dma_desc_sw *ds =
638 container_of(vd, struct k3_dma_desc_sw, vd);
639
640 kfree(ds);
641}
642
643static struct of_device_id k3_pdma_dt_ids[] = {
644 { .compatible = "hisilicon,k3-dma-1.0", },
645 {}
646};
647MODULE_DEVICE_TABLE(of, k3_pdma_dt_ids);
648
649static struct dma_chan *k3_of_dma_simple_xlate(struct of_phandle_args *dma_spec,
650 struct of_dma *ofdma)
651{
652 struct k3_dma_dev *d = ofdma->of_dma_data;
653 unsigned int request = dma_spec->args[0];
654
655 if (request > d->dma_requests)
656 return NULL;
657
658 return dma_get_slave_channel(&(d->chans[request].vc.chan));
659}
660
661static int k3_dma_probe(struct platform_device *op)
662{
663 struct k3_dma_dev *d;
664 const struct of_device_id *of_id;
665 struct resource *iores;
666 int i, ret, irq = 0;
667
668 iores = platform_get_resource(op, IORESOURCE_MEM, 0);
669 if (!iores)
670 return -EINVAL;
671
672 d = devm_kzalloc(&op->dev, sizeof(*d), GFP_KERNEL);
673 if (!d)
674 return -ENOMEM;
675
676 d->base = devm_ioremap_resource(&op->dev, iores);
677 if (IS_ERR(d->base))
678 return PTR_ERR(d->base);
679
680 of_id = of_match_device(k3_pdma_dt_ids, &op->dev);
681 if (of_id) {
682 of_property_read_u32((&op->dev)->of_node,
683 "dma-channels", &d->dma_channels);
684 of_property_read_u32((&op->dev)->of_node,
685 "dma-requests", &d->dma_requests);
686 }
687
688 d->clk = devm_clk_get(&op->dev, NULL);
689 if (IS_ERR(d->clk)) {
690 dev_err(&op->dev, "no dma clk\n");
691 return PTR_ERR(d->clk);
692 }
693
694 irq = platform_get_irq(op, 0);
695 ret = devm_request_irq(&op->dev, irq,
696 k3_dma_int_handler, 0, DRIVER_NAME, d);
697 if (ret)
698 return ret;
699
700 /* init phy channel */
701 d->phy = devm_kzalloc(&op->dev,
702 d->dma_channels * sizeof(struct k3_dma_phy), GFP_KERNEL);
703 if (d->phy == NULL)
704 return -ENOMEM;
705
706 for (i = 0; i < d->dma_channels; i++) {
707 struct k3_dma_phy *p = &d->phy[i];
708
709 p->idx = i;
710 p->base = d->base + i * 0x40;
711 }
712
713 INIT_LIST_HEAD(&d->slave.channels);
714 dma_cap_set(DMA_SLAVE, d->slave.cap_mask);
715 dma_cap_set(DMA_MEMCPY, d->slave.cap_mask);
716 d->slave.dev = &op->dev;
717 d->slave.device_alloc_chan_resources = k3_dma_alloc_chan_resources;
718 d->slave.device_free_chan_resources = k3_dma_free_chan_resources;
719 d->slave.device_tx_status = k3_dma_tx_status;
720 d->slave.device_prep_dma_memcpy = k3_dma_prep_memcpy;
721 d->slave.device_prep_slave_sg = k3_dma_prep_slave_sg;
722 d->slave.device_issue_pending = k3_dma_issue_pending;
723 d->slave.device_control = k3_dma_control;
724 d->slave.copy_align = DMA_ALIGN;
725 d->slave.chancnt = d->dma_requests;
726
727 /* init virtual channel */
728 d->chans = devm_kzalloc(&op->dev,
729 d->dma_requests * sizeof(struct k3_dma_chan), GFP_KERNEL);
730 if (d->chans == NULL)
731 return -ENOMEM;
732
733 for (i = 0; i < d->dma_requests; i++) {
734 struct k3_dma_chan *c = &d->chans[i];
735
736 c->status = DMA_IN_PROGRESS;
737 INIT_LIST_HEAD(&c->node);
738 c->vc.desc_free = k3_dma_free_desc;
739 vchan_init(&c->vc, &d->slave);
740 }
741
742 /* Enable clock before accessing registers */
743 ret = clk_prepare_enable(d->clk);
744 if (ret < 0) {
745 dev_err(&op->dev, "clk_prepare_enable failed: %d\n", ret);
746 return ret;
747 }
748
749 k3_dma_enable_dma(d, true);
750
751 ret = dma_async_device_register(&d->slave);
752 if (ret)
753 return ret;
754
755 ret = of_dma_controller_register((&op->dev)->of_node,
756 k3_of_dma_simple_xlate, d);
757 if (ret)
758 goto of_dma_register_fail;
759
760 spin_lock_init(&d->lock);
761 INIT_LIST_HEAD(&d->chan_pending);
762 tasklet_init(&d->task, k3_dma_tasklet, (unsigned long)d);
763 platform_set_drvdata(op, d);
764 dev_info(&op->dev, "initialized\n");
765
766 return 0;
767
768of_dma_register_fail:
769 dma_async_device_unregister(&d->slave);
770 return ret;
771}
772
773static int k3_dma_remove(struct platform_device *op)
774{
775 struct k3_dma_chan *c, *cn;
776 struct k3_dma_dev *d = platform_get_drvdata(op);
777
778 dma_async_device_unregister(&d->slave);
779 of_dma_controller_free((&op->dev)->of_node);
780
781 list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
782 list_del(&c->vc.chan.device_node);
783 tasklet_kill(&c->vc.task);
784 }
785 tasklet_kill(&d->task);
786 clk_disable_unprepare(d->clk);
787 return 0;
788}
789
790static int k3_dma_suspend(struct device *dev)
791{
792 struct k3_dma_dev *d = dev_get_drvdata(dev);
793 u32 stat = 0;
794
795 stat = k3_dma_get_chan_stat(d);
796 if (stat) {
797 dev_warn(d->slave.dev,
798 "chan %d is running fail to suspend\n", stat);
799 return -1;
800 }
801 k3_dma_enable_dma(d, false);
802 clk_disable_unprepare(d->clk);
803 return 0;
804}
805
806static int k3_dma_resume(struct device *dev)
807{
808 struct k3_dma_dev *d = dev_get_drvdata(dev);
809 int ret = 0;
810
811 ret = clk_prepare_enable(d->clk);
812 if (ret < 0) {
813 dev_err(d->slave.dev, "clk_prepare_enable failed: %d\n", ret);
814 return ret;
815 }
816 k3_dma_enable_dma(d, true);
817 return 0;
818}
819
820static SIMPLE_DEV_PM_OPS(k3_dma_pmops, k3_dma_suspend, k3_dma_resume);
821
822static struct platform_driver k3_pdma_driver = {
823 .driver = {
824 .name = DRIVER_NAME,
825 .owner = THIS_MODULE,
826 .pm = &k3_dma_pmops,
827 .of_match_table = k3_pdma_dt_ids,
828 },
829 .probe = k3_dma_probe,
830 .remove = k3_dma_remove,
831};
832
833module_platform_driver(k3_pdma_driver);
834
835MODULE_DESCRIPTION("Hisilicon k3 DMA Driver");
836MODULE_ALIAS("platform:k3dma");
837MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (c) 2013 - 2015 Linaro Ltd.
3 * Copyright (c) 2013 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/sched.h>
10#include <linux/device.h>
11#include <linux/dma-mapping.h>
12#include <linux/dmapool.h>
13#include <linux/dmaengine.h>
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/slab.h>
20#include <linux/spinlock.h>
21#include <linux/of_device.h>
22#include <linux/of.h>
23#include <linux/clk.h>
24#include <linux/of_dma.h>
25
26#include "virt-dma.h"
27
28#define DRIVER_NAME "k3-dma"
29#define DMA_MAX_SIZE 0x1ffc
30#define DMA_CYCLIC_MAX_PERIOD 0x1000
31#define LLI_BLOCK_SIZE (4 * PAGE_SIZE)
32
33#define INT_STAT 0x00
34#define INT_TC1 0x04
35#define INT_TC2 0x08
36#define INT_ERR1 0x0c
37#define INT_ERR2 0x10
38#define INT_TC1_MASK 0x18
39#define INT_TC2_MASK 0x1c
40#define INT_ERR1_MASK 0x20
41#define INT_ERR2_MASK 0x24
42#define INT_TC1_RAW 0x600
43#define INT_TC2_RAW 0x608
44#define INT_ERR1_RAW 0x610
45#define INT_ERR2_RAW 0x618
46#define CH_PRI 0x688
47#define CH_STAT 0x690
48#define CX_CUR_CNT 0x704
49#define CX_LLI 0x800
50#define CX_CNT1 0x80c
51#define CX_CNT0 0x810
52#define CX_SRC 0x814
53#define CX_DST 0x818
54#define CX_CFG 0x81c
55#define AXI_CFG 0x820
56#define AXI_CFG_DEFAULT 0x201201
57
58#define CX_LLI_CHAIN_EN 0x2
59#define CX_CFG_EN 0x1
60#define CX_CFG_NODEIRQ BIT(1)
61#define CX_CFG_MEM2PER (0x1 << 2)
62#define CX_CFG_PER2MEM (0x2 << 2)
63#define CX_CFG_SRCINCR (0x1 << 31)
64#define CX_CFG_DSTINCR (0x1 << 30)
65
66struct k3_desc_hw {
67 u32 lli;
68 u32 reserved[3];
69 u32 count;
70 u32 saddr;
71 u32 daddr;
72 u32 config;
73} __aligned(32);
74
75struct k3_dma_desc_sw {
76 struct virt_dma_desc vd;
77 dma_addr_t desc_hw_lli;
78 size_t desc_num;
79 size_t size;
80 struct k3_desc_hw *desc_hw;
81};
82
83struct k3_dma_phy;
84
85struct k3_dma_chan {
86 u32 ccfg;
87 struct virt_dma_chan vc;
88 struct k3_dma_phy *phy;
89 struct list_head node;
90 enum dma_transfer_direction dir;
91 dma_addr_t dev_addr;
92 enum dma_status status;
93 bool cyclic;
94};
95
96struct k3_dma_phy {
97 u32 idx;
98 void __iomem *base;
99 struct k3_dma_chan *vchan;
100 struct k3_dma_desc_sw *ds_run;
101 struct k3_dma_desc_sw *ds_done;
102};
103
104struct k3_dma_dev {
105 struct dma_device slave;
106 void __iomem *base;
107 struct tasklet_struct task;
108 spinlock_t lock;
109 struct list_head chan_pending;
110 struct k3_dma_phy *phy;
111 struct k3_dma_chan *chans;
112 struct clk *clk;
113 struct dma_pool *pool;
114 u32 dma_channels;
115 u32 dma_requests;
116 unsigned int irq;
117};
118
119#define to_k3_dma(dmadev) container_of(dmadev, struct k3_dma_dev, slave)
120
121static struct k3_dma_chan *to_k3_chan(struct dma_chan *chan)
122{
123 return container_of(chan, struct k3_dma_chan, vc.chan);
124}
125
126static void k3_dma_pause_dma(struct k3_dma_phy *phy, bool on)
127{
128 u32 val = 0;
129
130 if (on) {
131 val = readl_relaxed(phy->base + CX_CFG);
132 val |= CX_CFG_EN;
133 writel_relaxed(val, phy->base + CX_CFG);
134 } else {
135 val = readl_relaxed(phy->base + CX_CFG);
136 val &= ~CX_CFG_EN;
137 writel_relaxed(val, phy->base + CX_CFG);
138 }
139}
140
141static void k3_dma_terminate_chan(struct k3_dma_phy *phy, struct k3_dma_dev *d)
142{
143 u32 val = 0;
144
145 k3_dma_pause_dma(phy, false);
146
147 val = 0x1 << phy->idx;
148 writel_relaxed(val, d->base + INT_TC1_RAW);
149 writel_relaxed(val, d->base + INT_TC2_RAW);
150 writel_relaxed(val, d->base + INT_ERR1_RAW);
151 writel_relaxed(val, d->base + INT_ERR2_RAW);
152}
153
154static void k3_dma_set_desc(struct k3_dma_phy *phy, struct k3_desc_hw *hw)
155{
156 writel_relaxed(hw->lli, phy->base + CX_LLI);
157 writel_relaxed(hw->count, phy->base + CX_CNT0);
158 writel_relaxed(hw->saddr, phy->base + CX_SRC);
159 writel_relaxed(hw->daddr, phy->base + CX_DST);
160 writel_relaxed(AXI_CFG_DEFAULT, phy->base + AXI_CFG);
161 writel_relaxed(hw->config, phy->base + CX_CFG);
162}
163
164static u32 k3_dma_get_curr_cnt(struct k3_dma_dev *d, struct k3_dma_phy *phy)
165{
166 u32 cnt = 0;
167
168 cnt = readl_relaxed(d->base + CX_CUR_CNT + phy->idx * 0x10);
169 cnt &= 0xffff;
170 return cnt;
171}
172
173static u32 k3_dma_get_curr_lli(struct k3_dma_phy *phy)
174{
175 return readl_relaxed(phy->base + CX_LLI);
176}
177
178static u32 k3_dma_get_chan_stat(struct k3_dma_dev *d)
179{
180 return readl_relaxed(d->base + CH_STAT);
181}
182
183static void k3_dma_enable_dma(struct k3_dma_dev *d, bool on)
184{
185 if (on) {
186 /* set same priority */
187 writel_relaxed(0x0, d->base + CH_PRI);
188
189 /* unmask irq */
190 writel_relaxed(0xffff, d->base + INT_TC1_MASK);
191 writel_relaxed(0xffff, d->base + INT_TC2_MASK);
192 writel_relaxed(0xffff, d->base + INT_ERR1_MASK);
193 writel_relaxed(0xffff, d->base + INT_ERR2_MASK);
194 } else {
195 /* mask irq */
196 writel_relaxed(0x0, d->base + INT_TC1_MASK);
197 writel_relaxed(0x0, d->base + INT_TC2_MASK);
198 writel_relaxed(0x0, d->base + INT_ERR1_MASK);
199 writel_relaxed(0x0, d->base + INT_ERR2_MASK);
200 }
201}
202
203static irqreturn_t k3_dma_int_handler(int irq, void *dev_id)
204{
205 struct k3_dma_dev *d = (struct k3_dma_dev *)dev_id;
206 struct k3_dma_phy *p;
207 struct k3_dma_chan *c;
208 u32 stat = readl_relaxed(d->base + INT_STAT);
209 u32 tc1 = readl_relaxed(d->base + INT_TC1);
210 u32 tc2 = readl_relaxed(d->base + INT_TC2);
211 u32 err1 = readl_relaxed(d->base + INT_ERR1);
212 u32 err2 = readl_relaxed(d->base + INT_ERR2);
213 u32 i, irq_chan = 0;
214
215 while (stat) {
216 i = __ffs(stat);
217 stat &= ~BIT(i);
218 if (likely(tc1 & BIT(i)) || (tc2 & BIT(i))) {
219 unsigned long flags;
220
221 p = &d->phy[i];
222 c = p->vchan;
223 if (c && (tc1 & BIT(i))) {
224 spin_lock_irqsave(&c->vc.lock, flags);
225 vchan_cookie_complete(&p->ds_run->vd);
226 p->ds_done = p->ds_run;
227 p->ds_run = NULL;
228 spin_unlock_irqrestore(&c->vc.lock, flags);
229 }
230 if (c && (tc2 & BIT(i))) {
231 spin_lock_irqsave(&c->vc.lock, flags);
232 if (p->ds_run != NULL)
233 vchan_cyclic_callback(&p->ds_run->vd);
234 spin_unlock_irqrestore(&c->vc.lock, flags);
235 }
236 irq_chan |= BIT(i);
237 }
238 if (unlikely((err1 & BIT(i)) || (err2 & BIT(i))))
239 dev_warn(d->slave.dev, "DMA ERR\n");
240 }
241
242 writel_relaxed(irq_chan, d->base + INT_TC1_RAW);
243 writel_relaxed(irq_chan, d->base + INT_TC2_RAW);
244 writel_relaxed(err1, d->base + INT_ERR1_RAW);
245 writel_relaxed(err2, d->base + INT_ERR2_RAW);
246
247 if (irq_chan)
248 tasklet_schedule(&d->task);
249
250 if (irq_chan || err1 || err2)
251 return IRQ_HANDLED;
252
253 return IRQ_NONE;
254}
255
256static int k3_dma_start_txd(struct k3_dma_chan *c)
257{
258 struct k3_dma_dev *d = to_k3_dma(c->vc.chan.device);
259 struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
260
261 if (!c->phy)
262 return -EAGAIN;
263
264 if (BIT(c->phy->idx) & k3_dma_get_chan_stat(d))
265 return -EAGAIN;
266
267 if (vd) {
268 struct k3_dma_desc_sw *ds =
269 container_of(vd, struct k3_dma_desc_sw, vd);
270 /*
271 * fetch and remove request from vc->desc_issued
272 * so vc->desc_issued only contains desc pending
273 */
274 list_del(&ds->vd.node);
275
276 c->phy->ds_run = ds;
277 c->phy->ds_done = NULL;
278 /* start dma */
279 k3_dma_set_desc(c->phy, &ds->desc_hw[0]);
280 return 0;
281 }
282 c->phy->ds_run = NULL;
283 c->phy->ds_done = NULL;
284 return -EAGAIN;
285}
286
287static void k3_dma_tasklet(unsigned long arg)
288{
289 struct k3_dma_dev *d = (struct k3_dma_dev *)arg;
290 struct k3_dma_phy *p;
291 struct k3_dma_chan *c, *cn;
292 unsigned pch, pch_alloc = 0;
293
294 /* check new dma request of running channel in vc->desc_issued */
295 list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
296 spin_lock_irq(&c->vc.lock);
297 p = c->phy;
298 if (p && p->ds_done) {
299 if (k3_dma_start_txd(c)) {
300 /* No current txd associated with this channel */
301 dev_dbg(d->slave.dev, "pchan %u: free\n", p->idx);
302 /* Mark this channel free */
303 c->phy = NULL;
304 p->vchan = NULL;
305 }
306 }
307 spin_unlock_irq(&c->vc.lock);
308 }
309
310 /* check new channel request in d->chan_pending */
311 spin_lock_irq(&d->lock);
312 for (pch = 0; pch < d->dma_channels; pch++) {
313 p = &d->phy[pch];
314
315 if (p->vchan == NULL && !list_empty(&d->chan_pending)) {
316 c = list_first_entry(&d->chan_pending,
317 struct k3_dma_chan, node);
318 /* remove from d->chan_pending */
319 list_del_init(&c->node);
320 pch_alloc |= 1 << pch;
321 /* Mark this channel allocated */
322 p->vchan = c;
323 c->phy = p;
324 dev_dbg(d->slave.dev, "pchan %u: alloc vchan %p\n", pch, &c->vc);
325 }
326 }
327 spin_unlock_irq(&d->lock);
328
329 for (pch = 0; pch < d->dma_channels; pch++) {
330 if (pch_alloc & (1 << pch)) {
331 p = &d->phy[pch];
332 c = p->vchan;
333 if (c) {
334 spin_lock_irq(&c->vc.lock);
335 k3_dma_start_txd(c);
336 spin_unlock_irq(&c->vc.lock);
337 }
338 }
339 }
340}
341
342static void k3_dma_free_chan_resources(struct dma_chan *chan)
343{
344 struct k3_dma_chan *c = to_k3_chan(chan);
345 struct k3_dma_dev *d = to_k3_dma(chan->device);
346 unsigned long flags;
347
348 spin_lock_irqsave(&d->lock, flags);
349 list_del_init(&c->node);
350 spin_unlock_irqrestore(&d->lock, flags);
351
352 vchan_free_chan_resources(&c->vc);
353 c->ccfg = 0;
354}
355
356static enum dma_status k3_dma_tx_status(struct dma_chan *chan,
357 dma_cookie_t cookie, struct dma_tx_state *state)
358{
359 struct k3_dma_chan *c = to_k3_chan(chan);
360 struct k3_dma_dev *d = to_k3_dma(chan->device);
361 struct k3_dma_phy *p;
362 struct virt_dma_desc *vd;
363 unsigned long flags;
364 enum dma_status ret;
365 size_t bytes = 0;
366
367 ret = dma_cookie_status(&c->vc.chan, cookie, state);
368 if (ret == DMA_COMPLETE)
369 return ret;
370
371 spin_lock_irqsave(&c->vc.lock, flags);
372 p = c->phy;
373 ret = c->status;
374
375 /*
376 * If the cookie is on our issue queue, then the residue is
377 * its total size.
378 */
379 vd = vchan_find_desc(&c->vc, cookie);
380 if (vd && !c->cyclic) {
381 bytes = container_of(vd, struct k3_dma_desc_sw, vd)->size;
382 } else if ((!p) || (!p->ds_run)) {
383 bytes = 0;
384 } else {
385 struct k3_dma_desc_sw *ds = p->ds_run;
386 u32 clli = 0, index = 0;
387
388 bytes = k3_dma_get_curr_cnt(d, p);
389 clli = k3_dma_get_curr_lli(p);
390 index = ((clli - ds->desc_hw_lli) /
391 sizeof(struct k3_desc_hw)) + 1;
392 for (; index < ds->desc_num; index++) {
393 bytes += ds->desc_hw[index].count;
394 /* end of lli */
395 if (!ds->desc_hw[index].lli)
396 break;
397 }
398 }
399 spin_unlock_irqrestore(&c->vc.lock, flags);
400 dma_set_residue(state, bytes);
401 return ret;
402}
403
404static void k3_dma_issue_pending(struct dma_chan *chan)
405{
406 struct k3_dma_chan *c = to_k3_chan(chan);
407 struct k3_dma_dev *d = to_k3_dma(chan->device);
408 unsigned long flags;
409
410 spin_lock_irqsave(&c->vc.lock, flags);
411 /* add request to vc->desc_issued */
412 if (vchan_issue_pending(&c->vc)) {
413 spin_lock(&d->lock);
414 if (!c->phy) {
415 if (list_empty(&c->node)) {
416 /* if new channel, add chan_pending */
417 list_add_tail(&c->node, &d->chan_pending);
418 /* check in tasklet */
419 tasklet_schedule(&d->task);
420 dev_dbg(d->slave.dev, "vchan %p: issued\n", &c->vc);
421 }
422 }
423 spin_unlock(&d->lock);
424 } else
425 dev_dbg(d->slave.dev, "vchan %p: nothing to issue\n", &c->vc);
426 spin_unlock_irqrestore(&c->vc.lock, flags);
427}
428
429static void k3_dma_fill_desc(struct k3_dma_desc_sw *ds, dma_addr_t dst,
430 dma_addr_t src, size_t len, u32 num, u32 ccfg)
431{
432 if (num != ds->desc_num - 1)
433 ds->desc_hw[num].lli = ds->desc_hw_lli + (num + 1) *
434 sizeof(struct k3_desc_hw);
435
436 ds->desc_hw[num].lli |= CX_LLI_CHAIN_EN;
437 ds->desc_hw[num].count = len;
438 ds->desc_hw[num].saddr = src;
439 ds->desc_hw[num].daddr = dst;
440 ds->desc_hw[num].config = ccfg;
441}
442
443static struct k3_dma_desc_sw *k3_dma_alloc_desc_resource(int num,
444 struct dma_chan *chan)
445{
446 struct k3_dma_chan *c = to_k3_chan(chan);
447 struct k3_dma_desc_sw *ds;
448 struct k3_dma_dev *d = to_k3_dma(chan->device);
449 int lli_limit = LLI_BLOCK_SIZE / sizeof(struct k3_desc_hw);
450
451 if (num > lli_limit) {
452 dev_dbg(chan->device->dev, "vch %p: sg num %d exceed max %d\n",
453 &c->vc, num, lli_limit);
454 return NULL;
455 }
456
457 ds = kzalloc(sizeof(*ds), GFP_NOWAIT);
458 if (!ds)
459 return NULL;
460
461 ds->desc_hw = dma_pool_zalloc(d->pool, GFP_NOWAIT, &ds->desc_hw_lli);
462 if (!ds->desc_hw) {
463 dev_dbg(chan->device->dev, "vch %p: dma alloc fail\n", &c->vc);
464 kfree(ds);
465 return NULL;
466 }
467 ds->desc_num = num;
468 return ds;
469}
470
471static struct dma_async_tx_descriptor *k3_dma_prep_memcpy(
472 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
473 size_t len, unsigned long flags)
474{
475 struct k3_dma_chan *c = to_k3_chan(chan);
476 struct k3_dma_desc_sw *ds;
477 size_t copy = 0;
478 int num = 0;
479
480 if (!len)
481 return NULL;
482
483 num = DIV_ROUND_UP(len, DMA_MAX_SIZE);
484
485 ds = k3_dma_alloc_desc_resource(num, chan);
486 if (!ds)
487 return NULL;
488
489 c->cyclic = 0;
490 ds->size = len;
491 num = 0;
492
493 if (!c->ccfg) {
494 /* default is memtomem, without calling device_config */
495 c->ccfg = CX_CFG_SRCINCR | CX_CFG_DSTINCR | CX_CFG_EN;
496 c->ccfg |= (0xf << 20) | (0xf << 24); /* burst = 16 */
497 c->ccfg |= (0x3 << 12) | (0x3 << 16); /* width = 64 bit */
498 }
499
500 do {
501 copy = min_t(size_t, len, DMA_MAX_SIZE);
502 k3_dma_fill_desc(ds, dst, src, copy, num++, c->ccfg);
503
504 if (c->dir == DMA_MEM_TO_DEV) {
505 src += copy;
506 } else if (c->dir == DMA_DEV_TO_MEM) {
507 dst += copy;
508 } else {
509 src += copy;
510 dst += copy;
511 }
512 len -= copy;
513 } while (len);
514
515 ds->desc_hw[num-1].lli = 0; /* end of link */
516 return vchan_tx_prep(&c->vc, &ds->vd, flags);
517}
518
519static struct dma_async_tx_descriptor *k3_dma_prep_slave_sg(
520 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sglen,
521 enum dma_transfer_direction dir, unsigned long flags, void *context)
522{
523 struct k3_dma_chan *c = to_k3_chan(chan);
524 struct k3_dma_desc_sw *ds;
525 size_t len, avail, total = 0;
526 struct scatterlist *sg;
527 dma_addr_t addr, src = 0, dst = 0;
528 int num = sglen, i;
529
530 if (sgl == NULL)
531 return NULL;
532
533 c->cyclic = 0;
534
535 for_each_sg(sgl, sg, sglen, i) {
536 avail = sg_dma_len(sg);
537 if (avail > DMA_MAX_SIZE)
538 num += DIV_ROUND_UP(avail, DMA_MAX_SIZE) - 1;
539 }
540
541 ds = k3_dma_alloc_desc_resource(num, chan);
542 if (!ds)
543 return NULL;
544 num = 0;
545
546 for_each_sg(sgl, sg, sglen, i) {
547 addr = sg_dma_address(sg);
548 avail = sg_dma_len(sg);
549 total += avail;
550
551 do {
552 len = min_t(size_t, avail, DMA_MAX_SIZE);
553
554 if (dir == DMA_MEM_TO_DEV) {
555 src = addr;
556 dst = c->dev_addr;
557 } else if (dir == DMA_DEV_TO_MEM) {
558 src = c->dev_addr;
559 dst = addr;
560 }
561
562 k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg);
563
564 addr += len;
565 avail -= len;
566 } while (avail);
567 }
568
569 ds->desc_hw[num-1].lli = 0; /* end of link */
570 ds->size = total;
571 return vchan_tx_prep(&c->vc, &ds->vd, flags);
572}
573
574static struct dma_async_tx_descriptor *
575k3_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
576 size_t buf_len, size_t period_len,
577 enum dma_transfer_direction dir,
578 unsigned long flags)
579{
580 struct k3_dma_chan *c = to_k3_chan(chan);
581 struct k3_dma_desc_sw *ds;
582 size_t len, avail, total = 0;
583 dma_addr_t addr, src = 0, dst = 0;
584 int num = 1, since = 0;
585 size_t modulo = DMA_CYCLIC_MAX_PERIOD;
586 u32 en_tc2 = 0;
587
588 dev_dbg(chan->device->dev, "%s: buf %pad, dst %pad, buf len %zu, period_len = %zu, dir %d\n",
589 __func__, &buf_addr, &to_k3_chan(chan)->dev_addr,
590 buf_len, period_len, (int)dir);
591
592 avail = buf_len;
593 if (avail > modulo)
594 num += DIV_ROUND_UP(avail, modulo) - 1;
595
596 ds = k3_dma_alloc_desc_resource(num, chan);
597 if (!ds)
598 return NULL;
599
600 c->cyclic = 1;
601 addr = buf_addr;
602 avail = buf_len;
603 total = avail;
604 num = 0;
605
606 if (period_len < modulo)
607 modulo = period_len;
608
609 do {
610 len = min_t(size_t, avail, modulo);
611
612 if (dir == DMA_MEM_TO_DEV) {
613 src = addr;
614 dst = c->dev_addr;
615 } else if (dir == DMA_DEV_TO_MEM) {
616 src = c->dev_addr;
617 dst = addr;
618 }
619 since += len;
620 if (since >= period_len) {
621 /* descriptor asks for TC2 interrupt on completion */
622 en_tc2 = CX_CFG_NODEIRQ;
623 since -= period_len;
624 } else
625 en_tc2 = 0;
626
627 k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg | en_tc2);
628
629 addr += len;
630 avail -= len;
631 } while (avail);
632
633 /* "Cyclic" == end of link points back to start of link */
634 ds->desc_hw[num - 1].lli |= ds->desc_hw_lli;
635
636 ds->size = total;
637
638 return vchan_tx_prep(&c->vc, &ds->vd, flags);
639}
640
641static int k3_dma_config(struct dma_chan *chan,
642 struct dma_slave_config *cfg)
643{
644 struct k3_dma_chan *c = to_k3_chan(chan);
645 u32 maxburst = 0, val = 0;
646 enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
647
648 if (cfg == NULL)
649 return -EINVAL;
650 c->dir = cfg->direction;
651 if (c->dir == DMA_DEV_TO_MEM) {
652 c->ccfg = CX_CFG_DSTINCR;
653 c->dev_addr = cfg->src_addr;
654 maxburst = cfg->src_maxburst;
655 width = cfg->src_addr_width;
656 } else if (c->dir == DMA_MEM_TO_DEV) {
657 c->ccfg = CX_CFG_SRCINCR;
658 c->dev_addr = cfg->dst_addr;
659 maxburst = cfg->dst_maxburst;
660 width = cfg->dst_addr_width;
661 }
662 switch (width) {
663 case DMA_SLAVE_BUSWIDTH_1_BYTE:
664 case DMA_SLAVE_BUSWIDTH_2_BYTES:
665 case DMA_SLAVE_BUSWIDTH_4_BYTES:
666 case DMA_SLAVE_BUSWIDTH_8_BYTES:
667 val = __ffs(width);
668 break;
669 default:
670 val = 3;
671 break;
672 }
673 c->ccfg |= (val << 12) | (val << 16);
674
675 if ((maxburst == 0) || (maxburst > 16))
676 val = 15;
677 else
678 val = maxburst - 1;
679 c->ccfg |= (val << 20) | (val << 24);
680 c->ccfg |= CX_CFG_MEM2PER | CX_CFG_EN;
681
682 /* specific request line */
683 c->ccfg |= c->vc.chan.chan_id << 4;
684
685 return 0;
686}
687
688static void k3_dma_free_desc(struct virt_dma_desc *vd)
689{
690 struct k3_dma_desc_sw *ds =
691 container_of(vd, struct k3_dma_desc_sw, vd);
692 struct k3_dma_dev *d = to_k3_dma(vd->tx.chan->device);
693
694 dma_pool_free(d->pool, ds->desc_hw, ds->desc_hw_lli);
695 kfree(ds);
696}
697
698static int k3_dma_terminate_all(struct dma_chan *chan)
699{
700 struct k3_dma_chan *c = to_k3_chan(chan);
701 struct k3_dma_dev *d = to_k3_dma(chan->device);
702 struct k3_dma_phy *p = c->phy;
703 unsigned long flags;
704 LIST_HEAD(head);
705
706 dev_dbg(d->slave.dev, "vchan %p: terminate all\n", &c->vc);
707
708 /* Prevent this channel being scheduled */
709 spin_lock(&d->lock);
710 list_del_init(&c->node);
711 spin_unlock(&d->lock);
712
713 /* Clear the tx descriptor lists */
714 spin_lock_irqsave(&c->vc.lock, flags);
715 vchan_get_all_descriptors(&c->vc, &head);
716 if (p) {
717 /* vchan is assigned to a pchan - stop the channel */
718 k3_dma_terminate_chan(p, d);
719 c->phy = NULL;
720 p->vchan = NULL;
721 if (p->ds_run) {
722 vchan_terminate_vdesc(&p->ds_run->vd);
723 p->ds_run = NULL;
724 }
725 p->ds_done = NULL;
726 }
727 spin_unlock_irqrestore(&c->vc.lock, flags);
728 vchan_dma_desc_free_list(&c->vc, &head);
729
730 return 0;
731}
732
733static void k3_dma_synchronize(struct dma_chan *chan)
734{
735 struct k3_dma_chan *c = to_k3_chan(chan);
736
737 vchan_synchronize(&c->vc);
738}
739
740static int k3_dma_transfer_pause(struct dma_chan *chan)
741{
742 struct k3_dma_chan *c = to_k3_chan(chan);
743 struct k3_dma_dev *d = to_k3_dma(chan->device);
744 struct k3_dma_phy *p = c->phy;
745
746 dev_dbg(d->slave.dev, "vchan %p: pause\n", &c->vc);
747 if (c->status == DMA_IN_PROGRESS) {
748 c->status = DMA_PAUSED;
749 if (p) {
750 k3_dma_pause_dma(p, false);
751 } else {
752 spin_lock(&d->lock);
753 list_del_init(&c->node);
754 spin_unlock(&d->lock);
755 }
756 }
757
758 return 0;
759}
760
761static int k3_dma_transfer_resume(struct dma_chan *chan)
762{
763 struct k3_dma_chan *c = to_k3_chan(chan);
764 struct k3_dma_dev *d = to_k3_dma(chan->device);
765 struct k3_dma_phy *p = c->phy;
766 unsigned long flags;
767
768 dev_dbg(d->slave.dev, "vchan %p: resume\n", &c->vc);
769 spin_lock_irqsave(&c->vc.lock, flags);
770 if (c->status == DMA_PAUSED) {
771 c->status = DMA_IN_PROGRESS;
772 if (p) {
773 k3_dma_pause_dma(p, true);
774 } else if (!list_empty(&c->vc.desc_issued)) {
775 spin_lock(&d->lock);
776 list_add_tail(&c->node, &d->chan_pending);
777 spin_unlock(&d->lock);
778 }
779 }
780 spin_unlock_irqrestore(&c->vc.lock, flags);
781
782 return 0;
783}
784
785static const struct of_device_id k3_pdma_dt_ids[] = {
786 { .compatible = "hisilicon,k3-dma-1.0", },
787 {}
788};
789MODULE_DEVICE_TABLE(of, k3_pdma_dt_ids);
790
791static struct dma_chan *k3_of_dma_simple_xlate(struct of_phandle_args *dma_spec,
792 struct of_dma *ofdma)
793{
794 struct k3_dma_dev *d = ofdma->of_dma_data;
795 unsigned int request = dma_spec->args[0];
796
797 if (request > d->dma_requests)
798 return NULL;
799
800 return dma_get_slave_channel(&(d->chans[request].vc.chan));
801}
802
803static int k3_dma_probe(struct platform_device *op)
804{
805 struct k3_dma_dev *d;
806 const struct of_device_id *of_id;
807 struct resource *iores;
808 int i, ret, irq = 0;
809
810 iores = platform_get_resource(op, IORESOURCE_MEM, 0);
811 if (!iores)
812 return -EINVAL;
813
814 d = devm_kzalloc(&op->dev, sizeof(*d), GFP_KERNEL);
815 if (!d)
816 return -ENOMEM;
817
818 d->base = devm_ioremap_resource(&op->dev, iores);
819 if (IS_ERR(d->base))
820 return PTR_ERR(d->base);
821
822 of_id = of_match_device(k3_pdma_dt_ids, &op->dev);
823 if (of_id) {
824 of_property_read_u32((&op->dev)->of_node,
825 "dma-channels", &d->dma_channels);
826 of_property_read_u32((&op->dev)->of_node,
827 "dma-requests", &d->dma_requests);
828 }
829
830 d->clk = devm_clk_get(&op->dev, NULL);
831 if (IS_ERR(d->clk)) {
832 dev_err(&op->dev, "no dma clk\n");
833 return PTR_ERR(d->clk);
834 }
835
836 irq = platform_get_irq(op, 0);
837 ret = devm_request_irq(&op->dev, irq,
838 k3_dma_int_handler, 0, DRIVER_NAME, d);
839 if (ret)
840 return ret;
841
842 d->irq = irq;
843
844 /* A DMA memory pool for LLIs, align on 32-byte boundary */
845 d->pool = dmam_pool_create(DRIVER_NAME, &op->dev,
846 LLI_BLOCK_SIZE, 32, 0);
847 if (!d->pool)
848 return -ENOMEM;
849
850 /* init phy channel */
851 d->phy = devm_kzalloc(&op->dev,
852 d->dma_channels * sizeof(struct k3_dma_phy), GFP_KERNEL);
853 if (d->phy == NULL)
854 return -ENOMEM;
855
856 for (i = 0; i < d->dma_channels; i++) {
857 struct k3_dma_phy *p = &d->phy[i];
858
859 p->idx = i;
860 p->base = d->base + i * 0x40;
861 }
862
863 INIT_LIST_HEAD(&d->slave.channels);
864 dma_cap_set(DMA_SLAVE, d->slave.cap_mask);
865 dma_cap_set(DMA_MEMCPY, d->slave.cap_mask);
866 dma_cap_set(DMA_CYCLIC, d->slave.cap_mask);
867 d->slave.dev = &op->dev;
868 d->slave.device_free_chan_resources = k3_dma_free_chan_resources;
869 d->slave.device_tx_status = k3_dma_tx_status;
870 d->slave.device_prep_dma_memcpy = k3_dma_prep_memcpy;
871 d->slave.device_prep_slave_sg = k3_dma_prep_slave_sg;
872 d->slave.device_prep_dma_cyclic = k3_dma_prep_dma_cyclic;
873 d->slave.device_issue_pending = k3_dma_issue_pending;
874 d->slave.device_config = k3_dma_config;
875 d->slave.device_pause = k3_dma_transfer_pause;
876 d->slave.device_resume = k3_dma_transfer_resume;
877 d->slave.device_terminate_all = k3_dma_terminate_all;
878 d->slave.device_synchronize = k3_dma_synchronize;
879 d->slave.copy_align = DMAENGINE_ALIGN_8_BYTES;
880
881 /* init virtual channel */
882 d->chans = devm_kzalloc(&op->dev,
883 d->dma_requests * sizeof(struct k3_dma_chan), GFP_KERNEL);
884 if (d->chans == NULL)
885 return -ENOMEM;
886
887 for (i = 0; i < d->dma_requests; i++) {
888 struct k3_dma_chan *c = &d->chans[i];
889
890 c->status = DMA_IN_PROGRESS;
891 INIT_LIST_HEAD(&c->node);
892 c->vc.desc_free = k3_dma_free_desc;
893 vchan_init(&c->vc, &d->slave);
894 }
895
896 /* Enable clock before accessing registers */
897 ret = clk_prepare_enable(d->clk);
898 if (ret < 0) {
899 dev_err(&op->dev, "clk_prepare_enable failed: %d\n", ret);
900 return ret;
901 }
902
903 k3_dma_enable_dma(d, true);
904
905 ret = dma_async_device_register(&d->slave);
906 if (ret)
907 goto dma_async_register_fail;
908
909 ret = of_dma_controller_register((&op->dev)->of_node,
910 k3_of_dma_simple_xlate, d);
911 if (ret)
912 goto of_dma_register_fail;
913
914 spin_lock_init(&d->lock);
915 INIT_LIST_HEAD(&d->chan_pending);
916 tasklet_init(&d->task, k3_dma_tasklet, (unsigned long)d);
917 platform_set_drvdata(op, d);
918 dev_info(&op->dev, "initialized\n");
919
920 return 0;
921
922of_dma_register_fail:
923 dma_async_device_unregister(&d->slave);
924dma_async_register_fail:
925 clk_disable_unprepare(d->clk);
926 return ret;
927}
928
929static int k3_dma_remove(struct platform_device *op)
930{
931 struct k3_dma_chan *c, *cn;
932 struct k3_dma_dev *d = platform_get_drvdata(op);
933
934 dma_async_device_unregister(&d->slave);
935 of_dma_controller_free((&op->dev)->of_node);
936
937 devm_free_irq(&op->dev, d->irq, d);
938
939 list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
940 list_del(&c->vc.chan.device_node);
941 tasklet_kill(&c->vc.task);
942 }
943 tasklet_kill(&d->task);
944 clk_disable_unprepare(d->clk);
945 return 0;
946}
947
948#ifdef CONFIG_PM_SLEEP
949static int k3_dma_suspend_dev(struct device *dev)
950{
951 struct k3_dma_dev *d = dev_get_drvdata(dev);
952 u32 stat = 0;
953
954 stat = k3_dma_get_chan_stat(d);
955 if (stat) {
956 dev_warn(d->slave.dev,
957 "chan %d is running fail to suspend\n", stat);
958 return -1;
959 }
960 k3_dma_enable_dma(d, false);
961 clk_disable_unprepare(d->clk);
962 return 0;
963}
964
965static int k3_dma_resume_dev(struct device *dev)
966{
967 struct k3_dma_dev *d = dev_get_drvdata(dev);
968 int ret = 0;
969
970 ret = clk_prepare_enable(d->clk);
971 if (ret < 0) {
972 dev_err(d->slave.dev, "clk_prepare_enable failed: %d\n", ret);
973 return ret;
974 }
975 k3_dma_enable_dma(d, true);
976 return 0;
977}
978#endif
979
980static SIMPLE_DEV_PM_OPS(k3_dma_pmops, k3_dma_suspend_dev, k3_dma_resume_dev);
981
982static struct platform_driver k3_pdma_driver = {
983 .driver = {
984 .name = DRIVER_NAME,
985 .pm = &k3_dma_pmops,
986 .of_match_table = k3_pdma_dt_ids,
987 },
988 .probe = k3_dma_probe,
989 .remove = k3_dma_remove,
990};
991
992module_platform_driver(k3_pdma_driver);
993
994MODULE_DESCRIPTION("Hisilicon k3 DMA Driver");
995MODULE_ALIAS("platform:k3dma");
996MODULE_LICENSE("GPL v2");