1/*
 2 * arch/sh/kernel/cpu/sh2a/clock-sh7206.c
 3 *
 4 * SH7206 support for the clock framework
 5 *
 6 *  Copyright (C) 2006  Yoshinori Sato
 7 *
 8 * Based on clock-sh4.c
 9 *  Copyright (C) 2005  Paul Mundt
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License.  See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/init.h>
16#include <linux/kernel.h>
17#include <asm/clock.h>
18#include <asm/freq.h>
19#include <asm/io.h>
20
21static const int pll1rate[]={1,2,3,4,6,8};
22static const int pfc_divisors[]={1,2,3,4,6,8,12};
23#define ifc_divisors pfc_divisors
24
25static unsigned int pll2_mult;
26
27static void master_clk_init(struct clk *clk)
28{
29	clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
30}
31
32static struct sh_clk_ops sh7206_master_clk_ops = {
33	.init		= master_clk_init,
34};
35
36static unsigned long module_clk_recalc(struct clk *clk)
37{
38	int idx = (__raw_readw(FREQCR) & 0x0007);
39	return clk->parent->rate / pfc_divisors[idx];
40}
41
42static struct sh_clk_ops sh7206_module_clk_ops = {
43	.recalc		= module_clk_recalc,
44};
45
46static unsigned long bus_clk_recalc(struct clk *clk)
47{
48	return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
49}
50
51static struct sh_clk_ops sh7206_bus_clk_ops = {
52	.recalc		= bus_clk_recalc,
53};
54
55static unsigned long cpu_clk_recalc(struct clk *clk)
56{
57	int idx = (__raw_readw(FREQCR) & 0x0007);
58	return clk->parent->rate / ifc_divisors[idx];
59}
60
61static struct sh_clk_ops sh7206_cpu_clk_ops = {
62	.recalc		= cpu_clk_recalc,
63};
64
65static struct sh_clk_ops *sh7206_clk_ops[] = {
66	&sh7206_master_clk_ops,
67	&sh7206_module_clk_ops,
68	&sh7206_bus_clk_ops,
69	&sh7206_cpu_clk_ops,
70};
71
72void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
73{
74	if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0))
75		pll2_mult = 1;
76	else if (test_mode_pin(MODE_PIN2 | MODE_PIN1))
77		pll2_mult = 2;
78	else if (test_mode_pin(MODE_PIN1))
79		pll2_mult = 4;
80
81	if (idx < ARRAY_SIZE(sh7206_clk_ops))
82		*ops = sh7206_clk_ops[idx];
83}

 1/*
 2 * arch/sh/kernel/cpu/sh2a/clock-sh7206.c
 3 *
 4 * SH7206 support for the clock framework
 5 *
 6 *  Copyright (C) 2006  Yoshinori Sato
 7 *
 8 * Based on clock-sh4.c
 9 *  Copyright (C) 2005  Paul Mundt
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License.  See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/init.h>
16#include <linux/kernel.h>
17#include <asm/clock.h>
18#include <asm/freq.h>
19#include <asm/io.h>
20
21static const int pll1rate[]={1,2,3,4,6,8};
22static const int pfc_divisors[]={1,2,3,4,6,8,12};
23#define ifc_divisors pfc_divisors
24
25static unsigned int pll2_mult;
26
27static void master_clk_init(struct clk *clk)
28{
29	clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
30}
31
32static struct sh_clk_ops sh7206_master_clk_ops = {
33	.init		= master_clk_init,
34};
35
36static unsigned long module_clk_recalc(struct clk *clk)
37{
38	int idx = (__raw_readw(FREQCR) & 0x0007);
39	return clk->parent->rate / pfc_divisors[idx];
40}
41
42static struct sh_clk_ops sh7206_module_clk_ops = {
43	.recalc		= module_clk_recalc,
44};
45
46static unsigned long bus_clk_recalc(struct clk *clk)
47{
48	return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
49}
50
51static struct sh_clk_ops sh7206_bus_clk_ops = {
52	.recalc		= bus_clk_recalc,
53};
54
55static unsigned long cpu_clk_recalc(struct clk *clk)
56{
57	int idx = (__raw_readw(FREQCR) & 0x0007);
58	return clk->parent->rate / ifc_divisors[idx];
59}
60
61static struct sh_clk_ops sh7206_cpu_clk_ops = {
62	.recalc		= cpu_clk_recalc,
63};
64
65static struct sh_clk_ops *sh7206_clk_ops[] = {
66	&sh7206_master_clk_ops,
67	&sh7206_module_clk_ops,
68	&sh7206_bus_clk_ops,
69	&sh7206_cpu_clk_ops,
70};
71
72void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
73{
74	if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0))
75		pll2_mult = 1;
76	else if (test_mode_pin(MODE_PIN2 | MODE_PIN1))
77		pll2_mult = 2;
78	else if (test_mode_pin(MODE_PIN1))
79		pll2_mult = 4;
80
81	if (idx < ARRAY_SIZE(sh7206_clk_ops))
82		*ops = sh7206_clk_ops[idx];
83}